Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the manufacturing method comprises the steps: providing a substrate which comprises a plurality of active regions isolated by a shallow trench isolation structure, and forming a plurality of initial bit line structures connected with first source and drain regions of the active regions on a first surface of the substrate; forming a plurality of first holes from the first surface between the adjacent initial bit line structures, wherein the first holes expose part of the side surface of the second source drain region of the active region and part of the side surface of the shallow trench isolation structure; filling a first contact structure in the first hole; a side wall protection layer is formed on the initial bit line structure, a bit line structure is obtained, and the width of the bit line structure is larger than that of the initial bit line structure; and forming a second contact structure correspondingly connected with the first contact structure to form the capacitor contact plug. The first contact structure is formed before the side wall protection layer is formed, so that timely discharge of byproducts is ensured, and effective connection between the capacitor contact plug and the active region is further ensured.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Capacitor contact structures are the core interconnection structures used in semiconductor structures to achieve device interconnection. During the fabrication of capacitor contact structures, poor contact between the active region and the capacitor contact structure can easily occur, reducing the yield of semiconductor structures. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising: A substrate is provided, the substrate including a plurality of active regions isolated by shallow trench isolation structures, a plurality of initial bit line structures being formed on a first surface of the substrate, the initial bit line structures being connected to a first source / drain region of the active regions; By removing a portion of the shallow trench isolation structure and a portion of the active region from the first surface between adjacent initial bit line structures, a plurality of first holes are obtained, the first holes exposing a portion of the side surface of the second source / drain region of the active region and a portion of the side surface of the shallow trench isolation structure. A first contact structure is filled into the first hole, and the first contact structure is connected to a portion of the side surface of the second source / drain region and a portion of the side surface of the shallow trench isolation structure. A sidewall protective layer is formed on the initial bit line structure to obtain a bit line structure, wherein the width of the bit line structure is greater than the width of the initial bit line structure. A second contact structure corresponding to the first contact structure is formed, and the second contact structure is connected to the corresponding first contact structure to form a capacitor contact plug.

[0006] According to some embodiments of this disclosure, removing a portion of the shallow trench isolation structure and a portion of the active region from the first surface between adjacent initial bitline structures to obtain a plurality of first holes includes: A protective layer is formed on the substrate, the protective layer covering the initial bit line structure and the first exposed surface of the substrate; The protective layer and the substrate are subjected to a first plasma etching process to obtain a plurality of first holes, wherein the first holes penetrate the protective layer. Before forming a sidewall protective layer on the initial bitline structure, the fabrication method further includes: Remove the protective layer.

[0007] According to some embodiments of this disclosure, the plasma used in the first plasma etching is mixed with a first gas, which is used to react with the partial sidewalls of the second source / drain region and the partial sidewalls of the shallow trench isolation structure to generate a protective structure.

[0008] According to some embodiments of this disclosure, the plasma is mixed with a second gas, which is used to increase the generation rate of the protective structure.

[0009] According to some embodiments of this disclosure, the plasma includes argon plasma; and / or The first gas includes C4F8; and / or The second gas includes CH2F2.

[0010] According to some embodiments of this disclosure, the plasma flow rate accounts for 50% to 90%, the first gas flow rate accounts for 5% to 35%, and the second gas flow rate accounts for 5% to 15%.

[0011] According to some embodiments of this disclosure, the angle between the plasma injection direction of the first plasma etching and the first direction is 0 to 1.5°, and the first direction is perpendicular to the first surface.

[0012] According to some embodiments of this disclosure, the first plasma etching etched in the first surface covers 50% to 90% of the first surface exposed between adjacent initial bit line structures.

[0013] According to some embodiments of this disclosure, before filling the first contact structure into the first hole, the manufacturing method further includes: A second plasma etching is performed on a portion of the side surface of the second source / drain region to remove the first oxide layer formed on the portion of the side surface of the second source / drain region, and a protective gas is introduced after the first oxide layer is removed to protect the exposed side surface of the second source / drain region.

[0014] According to some embodiments of this disclosure, the angle between the plasma injection direction of the second plasma etching and the first direction is 15° to 30°, and the first direction is perpendicular to the first surface; and / or, The second plasma etching employs argon plasma and hydrogen plasma; and / or, The energy of the second plasma etching is 50 eV to 100 eV.

[0015] According to some embodiments of this disclosure, filling the first contact structure within the first hole includes: A first contact layer is formed, which covers the initial bit line structure and fills the space between the first hole and the adjacent initial bit line structure. A portion of the first contact layer is removed to obtain the first contact structure, which is flush with the first surface.

[0016] According to some embodiments of this disclosure, forming a sidewall protective layer on the initial bitline structure includes: A first nitride layer, a second oxide layer, and a second nitride layer are sequentially formed on the sidewall of the initial bit line structure to obtain the bit line structure. The first nitride layer, the second oxide layer, and the second nitride layer constitute the sidewall protective layer. And / or, The sidewall protective layer covers part of the top surface of the first contact structure.

[0017] According to some embodiments of this disclosure, forming a second contact structure corresponding to the first contact structure includes: An isolation layer is formed, which fills the space between the bit line structures; A plurality of second holes are formed on the isolation layer, each second hole exposing the top surface of a first contact structure; The second contact structure is formed within the second hole.

[0018] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising: A substrate, the substrate including a plurality of active regions isolated by a shallow trench isolation structure, a plurality of bit line structures formed on a first surface of the substrate, the bit line structures being connected to a first source / drain region of the active regions; Multiple first holes are disposed on the first surface of the substrate, and the first holes expose a portion of the side surface of the second source / drain region of the active region and a portion of the side surface of the shallow trench isolation structure. Multiple first contact structures correspond one-to-one with multiple first holes. The first contact structure fills the corresponding first hole and is connected to the partial side surface of the second source / drain region and the partial side surface of the shallow trench isolation structure. Multiple second contact structures correspond one-to-one with multiple first contact structures, and the second contact structures are connected to the corresponding first contact structures to form capacitive contact plugs.

[0019] According to some embodiments of this disclosure, the bit line structure includes a sidewall protective layer that covers a portion of the top surface of the first contact structure.

[0020] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the capacitor contact plug is fabricated in two steps. Before forming the sidewall protection layer on the initial bit line structure, a first contact structure is formed to ensure sufficient space for the discharge of byproducts generated during the formation of the first hole. After the sidewall protection layer is formed, a second contact structure corresponding to and connected to the first contact structure is formed to constitute the capacitor contact plug, thereby ensuring effective electrical connection between the capacitor contact plug and the active region and improving the yield of the semiconductor structure.

[0021] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0023] Figure 1 This is a longitudinal section view of the storage node after the contact holes are formed in the related technology.

[0024] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0025] Figure 3 This is a longitudinal cross-sectional view of the substrate and initial bit line structure according to an exemplary embodiment.

[0026] Figure 4 This is a longitudinal section view showing the formation of a plurality of first holes according to an exemplary embodiment.

[0027] Figure 5 This is a longitudinal sectional view showing the formation of the first contact structure according to an exemplary embodiment.

[0028] Figure 6 This is a longitudinal sectional view showing the formation of the sidewall protective layer according to an exemplary embodiment.

[0029] Figure 7 This is a longitudinal cross-sectional view showing the formation of the second contact layer according to an exemplary embodiment.

[0030] Figure 8This is a longitudinal sectional view showing the formation of the second contact structure according to an exemplary embodiment.

[0031] Figure 9 This is a longitudinal sectional view showing the formation of the landing pad according to an exemplary embodiment.

[0032] Figure 10 This is a flowchart illustrating step S200, which involves forming a plurality of first holes, according to an exemplary embodiment.

[0033] Figure 11 This is a longitudinal cross-sectional view showing the formation of a protective layer according to an exemplary embodiment.

[0034] Figure 12 This is a longitudinal cross-sectional view of the protective layer and substrate after a first plasma etching, according to an exemplary embodiment.

[0035] Figure 13 This is a flowchart illustrating step S300, which involves filling the first contact structure into the first hole, according to an exemplary embodiment.

[0036] Figure 14 This is a longitudinal cross-sectional view showing the formation of the first contact layer according to an exemplary embodiment.

[0037] Figure 15 This is a flowchart illustrating step S500, which involves forming a second contact structure corresponding to the first contact structure, according to an exemplary embodiment.

[0038] Figure 16 This is a longitudinal cross-sectional view showing the formation of the isolation layer according to an exemplary embodiment.

[0039] Figure 17 This is a longitudinal sectional view showing the formation of a plurality of second holes according to an exemplary embodiment.

[0040] Figure 18 This is a flowchart illustrating a method for fabricating a semiconductor structure according to another exemplary embodiment.

[0041] Figure label: A, First width; B, Second width; L, Third width; α, Angle between the plasma injection direction of the first plasma etching and the first direction; 10. Storage node contact holes; 100, Substrate; 110, Active region; 1110, First source / drain region; 1120, Second source / drain region; 120, Shallow trench isolation structure; 130, First surface; 140, First via; 200, Initial bit line structure; 200', Bit line structure; 210, Polysilicon layer; 220, Metal nitride layer; 230, First metal layer; 240, First dielectric layer; 250, Sidewall protection layer; 2530, First nitride layer; 2520, Second oxide layer; 2510, Second nitride layer; 300, Capacitor contact plug; 310, First contact structure; 310', First contact layer; 320, Second contact structure; 320', Second contact layer; 400, Protective layer; 500, Protective structure; 600, Isolation layer; 610, Second hole; 700, Landing pad; 710, Ohmic layer; 720, Anti-diffusion layer; 730, Second metal layer; 740, Second dielectric layer. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] Capacitive contact structures are core interconnecting structures in semiconductor structures used to achieve device interconnection. Among the related technologies for fabricating capacitive contact structures, such as... Figure 1 As shown, the substrate 100 includes multiple active areas 110 (AA) isolated by a shallow trench isolation structure 120 (STI). Multiple bit line structures 200' connected to the first source / drain regions 1110 are formed on the first surface 130 of the substrate 100. Each bit line structure 200' includes a polysilicon layer 210, a metal nitride layer 220, a first metal layer 230, a first dielectric layer 240 stacked in the y-axis direction, and a sidewall protection layer 250 conformally covering the outer side of each of the aforementioned layers. The sidewall protection layer 250 includes a multilayer structure consisting of a first nitride layer 2530, a second oxide layer 2520, and a second nitride layer 2510 sequentially disposed along a direction close to the first dielectric layer 240, such that the spacing between adjacent bit line structures 200' in the x-axis direction (e.g., ) Figure 1The first width A) shown is relatively small, while the depth of the space between each bit line structure 200' is large. The large aspect ratio makes it difficult to remove byproducts (fluorides, polymer fragments, etc.) generated by etching when forming the memory node contact hole 10 on the first surface 130 between the bit line structures 200'. The byproducts accumulate in the exposed second source / drain region 1120, resulting in poor contact between the capacitor contact plug 300 and the active region 110 when forming the capacitor contact plug 300 in the memory node contact hole 10. This leads to electrical failure problems such as leakage, increased signal transmission loss, and decreased charge retention capability of memory cells, reducing the yield of the semiconductor structure.

[0044] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. By fabricating the capacitor contact plug in two steps, a first contact structure is formed before forming the sidewall protective layer on the initial bit line structure, ensuring sufficient space for byproducts to be discharged. After the sidewall protective layer is formed, a second contact structure corresponding to and connected to the first contact structure is formed to constitute the capacitor contact plug. This ensures effective electrical connection between the capacitor contact plug and the active region, thereby improving the conductivity of the semiconductor structure.

[0045] In one exemplary embodiment, a method for fabricating a semiconductor structure is provided, with reference to... Figure 2 As shown, the method for fabricating a semiconductor structure includes: S100. A substrate is provided, the substrate including a plurality of active regions isolated by a shallow trench isolation structure, a plurality of initial bit line structures are formed on a first surface of the substrate, and the initial bit line structures are connected to the first source and drain regions of the active regions.

[0046] In this step, such as Figure 3 As shown, the substrate 100 includes a plurality of active regions 110 isolated by a shallow trench isolation structure 120, and a plurality of initial bit line structures 200 are disposed at intervals on the substrate 100. The initial bit line structures 200 are connected to the first source / drain regions 1110 of the active regions 110. The initial bit line structure 200 includes a polysilicon layer 210, a metal nitride layer 220, a first metal layer 230 and a first dielectric layer 240 stacked together. The first dielectric layer 240 also covers the sidewalls of the polysilicon layer 210, the metal nitride layer 220 and the first metal layer 230 and the substrate 100 between the initial bit line structures 200.

[0047] For example, the substrate 100 is made of silicon (Si), silicon germanium (SiGe), etc., the shallow trench isolation structure 120 is made of silicon dioxide (SiO2), the metal nitride layer 220 is made of metal nitride, such as titanium nitride, the first metal layer 230 is made of metal materials such as tungsten (W) and titanium (Ti), and the first dielectric layer 240 is made of materials such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0048] S200. Remove a portion of the shallow trench isolation structure and a portion of the active region from the first surface between adjacent initial bit line structures to obtain a plurality of first holes. The first holes expose a portion of the side surface of the second source / drain region of the active region and a portion of the side surface of the shallow trench isolation structure.

[0049] In this step, such as Figure 4 As shown, a portion of the shallow trench isolation structure 120 and a portion of the active region 110 are removed from the first surface 130 between adjacent initial bit line structures 200 to obtain a plurality of first holes 140. The first holes 140 are etched, for example, by ion beam spraying (IBS), using plasmas such as argon plasma or helium plasma. Since there is no sidewall protective layer 250 to block the etching of the first holes 140, the third width L of the first holes 140 can be set to be greater than, for example, Figure 1 The storage node contact hole 10 in the related technology shown has a first width A. In addition, the depth-to-width ratio is small and the space between adjacent initial bit line structures 200 is large, so by-products are easy to discharge and will not accumulate. The first hole 140 exposes part of the side of the second source-drain region 1120 of the active region 110 and part of the side of the shallow trench isolation structure 120. The first source-drain region 1110 is the drain region and the second source-drain region 1120 is the source region.

[0050] S300, A first contact structure is filled into the first hole, and the first contact structure is connected to a portion of the side surface of the second source / drain region and a portion of the side surface of the shallow trench isolation structure.

[0051] In this step, such as Figure 5As shown, a first contact structure 310 is formed within the first hole 140, such that the first contact structure 310 is connected to both the second source / drain region 1120 and the shallow trench isolation structure 120. The material of the first contact structure 310 is, for example, polysilicon. Exemplarily, the first contact structure 310 can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., and is not limited here.

[0052] S400. A sidewall protective layer is formed on the initial bit line structure to obtain the bit line structure, wherein the width of the bit line structure is greater than the width of the initial bit line structure.

[0053] In this step, such as Figure 6 As shown, after the first contact structure 310 is formed, a sidewall protective layer 250 is formed on the initial bit line structure 200 to obtain the bit line structure 200'. The sidewall protective layer 250 covers the initial bit line structure 200 and can also cover the first surface 130 of the substrate 100 and the first contact structure 310.

[0054] S500, A second contact structure corresponding to the first contact structure is formed, and the second contact structure is connected to the corresponding first contact structure to form a capacitor contact plug.

[0055] In this step, such as Figure 7 , Figure 8 and Figure 17 As shown, after the sidewall protective layer 250 is formed, a second contact layer 320' connected to each first contact structure 310 is formed in each second hole 610. The second contact layer 320' also covers the top of the bit line structure 200'. The material of the second contact layer 320' is, for example, polysilicon. Exemplarily, the sidewall protective layer 250 covering the first contact structure 310 and the first surface 130 can be completely removed before the second contact structure 320 is formed, or only the sidewall protective layer 250 at the location where it needs to be connected to the first contact structure 310 can be removed.

[0056] In one embodiment, such as Figure 7 and Figure 8 As shown, after the second contact layer 320' is formed, a portion of the second contact layer 320' located on top of the bit line structure 200' and in the second hole 610 is removed to obtain a plurality of second contact structures 320. Each second contact structure 320 is connected to each first contact structure 310 to form a capacitor contact plug 300.

[0057] like Figure 9 As shown, after forming the capacitor contact plug 300, an ohmic layer 710, an anti-diffusion layer 720, a second metal layer 730, and a second dielectric layer 740 are sequentially formed on the capacitor contact plug 300. The second metal layer 730 fills the space enclosed by the anti-diffusion layer 720 and covers the top surface of the bit line structure 200'. The second dielectric layer 740 covers the top surface of the second metal layer 730, resulting in the landing pad 700. Exemplarily, the material of the ohmic layer 710 is a metal silicide, the material of the anti-diffusion layer 720 is a metal nitride, the material of the second metal layer 730 is a metal such as tungsten (W) or titanium (Ti), and the material of the second dielectric layer 740 is, for example, silicon nitride (SiN) or silicon carbonitride (SiCN).

[0058] In this embodiment, the capacitor contact plug 300 is fabricated in two steps. Before forming the sidewall protection layer 250 on the initial bit line structure 200, the first contact structure 310 is formed first to ensure sufficient space for by-products to be discharged. After the sidewall protection layer 250 is formed, the second contact structure 320, which is connected to the first contact structure 310, is formed to constitute the capacitor contact plug 300. This ensures effective electrical connection between the capacitor contact plug 300 and the active region 110 and improves the conductivity of the semiconductor structure.

[0059] In one embodiment, such as Figure 10 As shown, in step S200, a portion of the shallow trench isolation structure and a portion of the active region are removed from the first surface between adjacent initial bit line structures to obtain multiple first holes, including: S210. A protective layer is formed on the substrate, the protective layer covering the initial bit line structure and the first surface of the substrate exposed.

[0060] In this step, such as Figure 11 As shown, before forming the first hole 140, a protective layer 400 is first formed on the substrate 100. The material of the protective layer 400 is, for example, silicon dioxide. The protective layer 400 can protect other structures from damage when the first hole 140 is formed subsequently. The protective layer 400 is formed, for example, by atomic layer deposition. Two or more gaseous precursors are alternately pulsed into the reaction chamber, and a self-limiting surface chemical reaction occurs on the surface of the initial bit line structure 200 and on the first surface 130 of the substrate 100 between adjacent initial bit line structures 200. Since only one atomic-level thin film is deposited for each pulse, it has the advantage of precise thickness control. S220. Perform a first plasma etching on the protective layer and the substrate to obtain multiple first holes, with each first hole penetrating the protective layer.

[0061] In this step, such as Figure 12As shown, the protective layer 400 and the substrate 100 are subjected to first plasma etching by ion beam bombardment to obtain a plurality of first holes 140. When etching to form the first holes 140, the space between adjacent initial bit line structures 200 covered by the protective layer 400 has a second width B, which is greater than the first width A in related technologies, so that the etching by-products can be easily discharged.

[0062] Before forming a sidewall protective layer on the initial bitline structure, the semiconductor structure fabrication method also includes: Remove the protective layer.

[0063] In this step, such as Figure 5 As shown, before forming the sidewall protective layer 250, the protective layer 400 is removed, exposing the first dielectric layer 240 for connection with the sidewall protective layer 250.

[0064] In this embodiment, before the first hole 140 is formed by ion beam bombardment, a protective layer 400 is first formed to protect other structures and prevent them from being bombarded by sputtered ions. After the first contact structure 310 is formed and before the sidewall protective layer 250 is formed, the protective layer 400 is removed to ensure that the initial bit line structure 200 is not damaged and to avoid affecting the performance of the semiconductor structure.

[0065] In some embodiments, continue to refer to Figure 12 The plasma used in the first plasma etching process contains a first gas mixed in with it. This first gas reacts with a portion of the sidewalls of the second source / drain region 1120 exposed by plasma bombardment, as well as a portion of the sidewalls of the shallow trench isolation structure 120, to generate a protective structure 500. The plasma etching process is highly directional (making the direction easy to control), while the reaction of the first gas is non-directional. The first gas moves along the direction of the plasma to the first surface 130, where it reacts chemically with the materials of the active region 110 and the shallow trench isolation structure 120. The resulting protective structure 500 covers the sidewalls of the first hole 140. However, because the bottom wall of the first hole 140 is constantly bombarded by plasma, the protective structure 500 does not cover the bottom wall of the first hole 140.

[0066] For example, the direction of the first plasma etching can be changed by adjusting the concentration of the plasma in the first plasma etching; the first gas is, for example, C4F8 (octafluorocyclobutane).

[0067] In this embodiment, by mixing a first gas into the plasma used for the first plasma etching, the protective structure 500 generated by the reaction of the first gas with the substrate 100 during the etching process of forming the first hole 140 can protect the sidewall of the first hole 140 from being over-etched, ensuring the integrity of other structures near the first hole 140, while also ensuring etching efficiency.

[0068] In some embodiments, the plasma is also mixed with a second gas, which is used to increase the generation rate of the protective structure. The second gas is, for example, CH2F2 (difluoromethane).

[0069] In this embodiment, by mixing a second gas into the plasma, the generation rate of the protective structure is increased, thereby further enhancing the protective effect of the protective structure.

[0070] In some embodiments, the plasma includes argon plasma; and / or, the first gas includes C4F8; and / or, the second gas includes CH2F2.

[0071] In this embodiment, C4F8 is selected as the first gas and CH2F2 as the second gas, resulting in a dense and stable protective structure that improves the protection effect on the sidewall of the first hole.

[0072] In some embodiments, during the first plasma etching, the plasma flow rate accounts for 50% to 90%, the first gas flow rate accounts for 5% to 35%, and the second gas flow rate accounts for 5% to 15%; in one embodiment, the plasma flow rate accounts for 75%, the first gas flow rate accounts for 20%, and the second gas flow rate accounts for 5%; in another embodiment, the plasma flow rate accounts for 60%, the first gas flow rate accounts for 30%, and the second gas flow rate accounts for 10%.

[0073] In this embodiment, by setting the above-mentioned flow rate ratio, the density and energy of the ion beam can be stabilized, ensuring a more uniform etching rate, and also ensuring that by-products are discharged in a timely manner to avoid their accumulation, thereby improving the yield of semiconductor structure fabrication.

[0074] In some embodiments, such as Figure 12 As shown, the first direction is, for example, Figure 12 In the y-axis direction, the angle α between the plasma injection direction of the first plasma etching and the first direction is 0 to 1.5°, for example: 0°, 0.5°, 1.2°, 1.45°, 1.5°, etc.

[0075] In this embodiment, by setting the angle α between the plasma injection direction of the first plasma etching and the first direction to 0 to 1.5°, which is nearly perpendicular to the first surface 130°, it is suitable for etching structures with high aspect ratios, avoids damage to non-target areas, and improves etching efficiency.

[0076] In some embodiments, continue to refer to Figure 12As shown, the etched area of ​​the first plasma etching on the first surface 130 accounts for 50% to 90% of the first surface 130 exposed between adjacent initial bit line structures 200, for example, 60%, 75%, 88%, 90%, etc.

[0077] In this embodiment, the etching efficiency is ensured by limiting the effective range of the first plasma etching.

[0078] In some embodiments, before filling the first contact structure into the first hole in step S300, the fabrication method further includes: A second plasma etching is performed on a portion of the side surface of the second source / drain region to remove the first oxide layer formed on the portion of the side surface of the second source / drain region, and a protective gas is introduced after the first oxide layer is removed to protect the exposed side surface of the second source / drain region.

[0079] In this step, such as Figure 4 , Figure 5 and Figure 12 As shown, after the first hole 140 is etched and the protective structure 500 is removed, the second source / drain region 1120 is exposed through the first hole 140. Since the material of the second source / drain region 1120 includes silicon, the exposed silicon in the second source / drain region 1120 will be oxidized to form a first oxide layer, which will affect the connection between the second source / drain region 1120 and the first contact structure 310. By performing a second plasma etching on a portion of the side of the second source / drain region 1120, the formed first oxide layer can be removed. After removal, a protective gas is introduced to prevent the second source / drain region 1120 from being oxidized again, and the first contact structure 310 is formed again. The protective gas is, for example, nitrogen.

[0080] In this embodiment, the first oxide layer is removed by second plasma etching, and oxygen is dispelled by protective gas, thus ensuring effective electrical connection between the first contact structure 310 and the second source / drain region 1120.

[0081] In some embodiments, continue to refer to Figure 11 The angle between the plasma injection direction of the second plasma etching and the first direction is 15° to 30°. The first direction is, for example, the y-axis direction in the figure. The angle between the plasma injection direction of the second plasma etching and the first direction is, for example, 15°, 20°, 28.8°, 30°, etc.; and / or, the plasma used for the second plasma etching includes argon plasma and hydrogen plasma; and / or, the energy of the second plasma etching is 50eV to 100eV, for example, 50eV, 66eV, 85eV, 100eV, etc.

[0082] In this embodiment, by setting the incident direction and energy range of the second plasma etching, it is ensured that only the first oxide layer is removed without damaging the second source / drain region. By setting the etching to use a mixed argon and hydrogen plasma, the argon plasma provides directional and controllable physical bombardment to ensure the directionality of the etching, while the hydrogen plasma provides mild reduction and chemical assistance, does not generate highly corrosive free radicals, and does not over-etch.

[0083] In some embodiments, such as Figure 13 As shown, filling the first contact structure into the first hole in step S300 includes: S310. A first contact layer is formed, which covers the initial bit line structure and fills the space between the first hole and the adjacent initial bit line structure.

[0084] In this step, refer to Figure 14 As shown, after the first hole 140 is formed, the first contact layer 310' is filled in the space between adjacent initial bit line structures 200, and the first contact layer 310' also covers the initial bit line structure 200.

[0085] S320. Remove part of the first contact layer to obtain the first contact structure, which is flush with the first surface.

[0086] In this step, such as Figure 5 As shown, a portion of the first contact layer 310' is removed to obtain the first contact structure 310, which is flush with the first surface 130. For example, the first dielectric layer 240 on the first surface 130 is used as an etching stop layer to remove a portion of the first contact layer 310', so that the first contact structure 310 is flush with the first surface 130. Alternatively, the etching time can be controlled to make the first contact structure 310 flush with the first surface 130.

[0087] In this embodiment, by first forming the first contact layer 310' and then removing part of it to obtain the first contact structure 310, the first contact layer 310' can be fully compacted in the filling space. This ensures not only the full connection between the first contact structure 310 and the second source / drain region 1120, but also the compactness and absence of voids in the first contact structure 310, thereby improving the conductivity stability of the first contact structure 310.

[0088] In some embodiments, forming a sidewall protective layer on the initial bitline structure in step S400 includes: A first nitride layer, a second oxide layer, and a second nitride layer are sequentially formed on the sidewall of the initial bit line structure to obtain the bit line structure. The first nitride layer, the second oxide layer, and the second nitride layer constitute a sidewall protective layer; and / or, the sidewall protective layer covers part of the top surface of the first contact structure.

[0089] In this step, such as Figure 6 and Figure 7 As shown, a first nitride layer 2530, a second oxide layer 2520, and a second nitride layer 2510 are sequentially formed on the sidewall of the initial bit line structure 200 to obtain the bit line structure 200'. Since the first contact structure 310 is formed before the sidewall protective layer 250 is formed, the sidewall protective layer 250 can cover part of the top surface of the first contact structure 310.

[0090] In this embodiment, after forming the first contact structure 310, a first nitride layer 2530, a second oxide layer 2520, and a second nitride layer 2510 are formed sequentially to obtain a bit line structure 200'. The bit line structure 200' does not affect the discharge of byproducts during the etching process, thus ensuring the performance of the semiconductor structure.

[0091] In some embodiments, such as Figure 15 As shown, the formation of the second contact structure corresponding to the first contact structure in step S500 includes: S510, Form an isolation layer that fills the space between bitline structures.

[0092] In this step, refer to Figure 16 As shown, after forming the sidewall protective layer 250, an isolation layer 600 is first filled in the space between adjacent bit line structures 200'. The material of the isolation layer 600 is, for example, silicon dioxide.

[0093] S520. Multiple second holes are formed on the isolation layer, each second hole exposing the top surface of a first contact structure.

[0094] In this step, such as Figure 17 As shown, a plurality of second holes 610 are formed on the isolation layer 600 at positions corresponding to each of the first contact structures 310, and the second holes 610 expose the top surface of the corresponding first contact structure 310. For example, a mask layer can be provided, and the isolation layer 600 can be patterned using the mask layer as a mask to form a plurality of second holes 610; when the second nitride layer 2510 covering the first contact structure 310 is not removed, the second nitride layer 2510 needs to be etched after etching the isolation layer 600 to expose the top surface of the first contact structure 310.

[0095] S530, A second contact structure is formed in the second hole.

[0096] In this step, such as Figure 7 and Figure 8As shown, a second contact layer 320' is filled into the second hole 610, and the second contact layer 320' also covers the top of the bit line structure 200'. Then, the part of the second contact layer 320' located on the top of the bit line structure 200' and in the second hole 610 is removed to obtain a plurality of second contact structures 320, so that the second contact structures 320 are connected to each of the first contact structures 310 to form a capacitor contact plug 300.

[0097] In this embodiment, the formation of the isolation layer 600 and the formation of the second hole 610 in the isolation layer 600 provide a basis for forming the capacitive contact plug 300.

[0098] In one exemplary embodiment, this disclosure provides a method for fabricating a semiconductor structure, such as... Figure 18 As shown, it includes: S1. A substrate is provided, the substrate including multiple active regions isolated by shallow trench isolation structures, and multiple initial bit line structures are formed on a first surface of the substrate, the initial bit line structures being connected to the first source and drain regions of the active regions. S2. A protective layer is formed on the substrate, the protective layer covering the initial bit line structure and the first surface of the substrate exposed; S3. Perform a first plasma etching on the protective layer and the substrate to obtain multiple first holes. The first holes penetrate the protective layer and expose part of the side surface of the second source / drain region of the active region and part of the side surface of the shallow trench isolation structure. The plasma used for the first plasma etching is a mixture of a first gas and a second gas. The plasma includes argon plasma, the first gas includes C4F8, and the second gas includes CH2F2. S4. Perform a second plasma etching on a portion of the side surface of the second source / drain region to remove the first oxide layer formed on the portion of the side surface of the second source / drain region, and after removing the first oxide layer, introduce a protective gas to protect the exposed side surface of the second source / drain region; the plasma used for the second plasma etching includes argon plasma and hydrogen plasma. S5. Form a first contact layer. The first contact layer covers the initial bit line structure and fills the space between the first hole and the adjacent initial bit line structure. Remove part of the first contact layer to obtain a first contact structure. The first contact structure is flush with the first surface and is connected to part of the side surface of the second source / drain region and part of the side surface of the shallow trench isolation structure. S6. A first nitride layer, a second oxide layer, and a second nitride layer are sequentially formed on the sidewall of the initial bit line structure to obtain the bit line structure. The first nitride layer, the second oxide layer, and the second nitride layer constitute the sidewall protective layer. The width of the bit line structure is greater than the width of the initial bit line structure. S7. Form an isolation layer that fills the space between bit line structures; form a plurality of second holes on the isolation layer, each second hole exposing the top surface of a first contact structure; form a second contact structure in the second hole, the second contact structure being connected to the corresponding first contact structure to form a capacitor contact plug.

[0099] In this embodiment, the capacitor contact plug 300 is fabricated in two steps. Before forming the sidewall protection layer 250 on the initial bit line structure 200, the first hole 140 and the first contact structure 310 are formed by first plasma etching. The plasma used in the first plasma etching is mixed with a first gas and a second gas. During the etching process to form the first hole 140, the first gas reacts with the substrate 100 to form a protective structure 500, which can protect the sidewall of the first hole 140 from being over-etched. The second gas can increase the formation rate of the protective structure 500, ensuring the integrity of other structures near the first hole 140, while ensuring sufficient space for by-products to be discharged. After the sidewall protection layer 250 is formed, a second contact structure 320 corresponding to and connected to the first contact structure 310 is formed to constitute the capacitor contact plug 300, ensuring effective electrical connection between the capacitor contact plug 300 and the active region 110, and improving the conductivity of the semiconductor structure.

[0100] An exemplary embodiment of this disclosure provides a semiconductor structure that can be fabricated using the semiconductor structure fabrication method described in the above embodiments.

[0101] like Figure 8 and Figure 9 As shown, the semiconductor structure includes a substrate 100, a plurality of first vias 140, a plurality of first contact structures 310, and a plurality of second contact structures 320. The substrate 100 includes a plurality of active regions 110 isolated by shallow trench isolation structures 120. A plurality of bit line structures 200' are formed on the first surface 130 of the substrate 100, and the bit line structures 200' are connected to the first source / drain regions 1110 of the active regions 110. The plurality of first vias 140 are disposed on the first surface 130 of the substrate 100, and the first vias 140 expose the active regions 110. Partial side surfaces of the second source / drain region 1120 and partial side surfaces of the shallow trench isolation structure 120; a plurality of first contact structures 310 correspond one-to-one with a plurality of first holes 140, the first contact structures 310 fill the corresponding first holes 140 and are connected to a portion of the side surfaces of the second source / drain region 1120 and a portion of the side surfaces of the shallow trench isolation structure 120; a plurality of second contact structures 320 correspond one-to-one with a plurality of first contact structures 310, the second contact structures 320 are connected to the corresponding first contact structures 310 to form a capacitor contact plug 300.

[0102] Bit line structure 200' includes a stacked polysilicon layer 210, a metal nitride layer 220, a first metal layer 230, and a first dielectric layer 240. The first dielectric layer 240 also covers the sidewalls of the polysilicon layer 210, the metal nitride layer 220, and the first metal layer 230. Bit line structure 200' also includes a sidewall protection layer 250, which conformally covers the polysilicon layer 210, the metal nitride layer 220, the first metal layer 230, and the first dielectric layer 240. The sidewall protection layer 250 includes a first nitride layer 2530, a second oxide layer 2520, and a second nitride layer 2510 arranged sequentially from the inside to the outside.

[0103] The semiconductor structure also includes a landing pad 700, which includes an ohmic layer 710, an anti-diffusion layer 720, a second metal layer 730, and a second dielectric layer 740 sequentially formed on the capacitor contact plug 300. The second metal layer 730 fills the space enclosed by the anti-diffusion layer 720 and covers the top surface of the bit line structure 200'. The second dielectric layer 740 covers the top surface of the second metal layer 730.

[0104] For example, the substrate 100 is made of silicon (Si), silicon germanium (SiGe), etc., the shallow trench isolation structure 120 and the second oxide layer 2520 are made of silicon dioxide (SiO2), the metal nitride layer 220 and the anti-diffusion layer 720 are made of metal nitride, the first metal layer 230 and the second metal layer 730 are made of metal materials such as tungsten (W) and titanium (Ti), the first dielectric layer 240, the second dielectric layer 740, the first nitride layer 2530 and the second nitride layer 2510 are made of materials such as silicon nitride (SiN) or silicon carbonitride (SiCN), the capacitor contact plug 300 is made of materials such as polysilicon, and the ohmic layer 710 is made of metal silicide.

[0105] In this embodiment, by dividing the capacitor contact plug 300 into a first contact structure 310 and a second contact structure 320 corresponding to and connected to the first contact structure 310, an effective electrical connection between the capacitor contact plug 300 and the active region 110 is ensured, thereby improving the conductivity of the semiconductor structure.

[0106] In some embodiments, reference Figures 7 to 9 As shown, the bit line structure 200' includes a sidewall protective layer 250, which covers a portion of the top surface of the first contact structure 310.

[0107] In this embodiment, by setting a portion of the top surface of the first contact structure 310 to be covered by the sidewall protective layer 250, that is, in the second direction, the width of the first contact structure 310 is greater than the distance between the sidewall protective layers 250 of two adjacent bit line structures 200'. For example, the second direction is... Figure 6In the x-axis direction, the stability of the connection between the first contact structure 310 and the substrate 100 is ensured.

[0108] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0109] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure. In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0110] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0111] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0112] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, the substrate including a plurality of active regions isolated by shallow trench isolation structures, a plurality of initial bit line structures being formed on a first surface of the substrate, the initial bit line structures being connected to a first source / drain region of the active regions; By removing a portion of the shallow trench isolation structure and a portion of the active region from the first surface between adjacent initial bit line structures, a plurality of first holes are obtained, the first holes exposing a portion of the side surface of the second source / drain region of the active region and a portion of the side surface of the shallow trench isolation structure. A first contact structure is filled into the first hole, and the first contact structure is connected to a portion of the side surface of the second source / drain region and a portion of the side surface of the shallow trench isolation structure. A sidewall protective layer is formed on the initial bit line structure to obtain a bit line structure, wherein the width of the bit line structure is greater than the width of the initial bit line structure. A second contact structure is formed corresponding to the first contact structure, and the second contact structure is connected to the corresponding first contact structure to form a capacitor contact plug.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The process of removing a portion of the shallow trench isolation structure and a portion of the active region from the first surface between adjacent initial bit line structures yields a plurality of first holes, including: A protective layer is formed on the substrate, the protective layer covering the initial bit line structure and the first surface of the substrate exposed; The protective layer and the substrate are subjected to a first plasma etching process to obtain a plurality of first holes, wherein the first holes penetrate the protective layer. Before forming a sidewall protective layer on the initial bitline structure, the fabrication method further includes: Remove the protective layer.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The plasma used in the first plasma etching process contains a first gas mixed in with it. The first gas reacts with a portion of the sidewalls of the second source / drain region and a portion of the sidewalls of the shallow trench isolation structure to generate a protective structure.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The plasma contains a second gas, which is used to increase the generation rate of the protective structure.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The plasma includes argon plasma; and / or The first gas includes C4F8; and / or The second gas includes CH2F2.

6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The plasma flow rate accounts for 50% to 90%, the first gas flow rate accounts for 5% to 35%, and the second gas flow rate accounts for 5% to 15%.

7. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The angle between the plasma injection direction of the first plasma etching and the first direction is 0 to 1.5°, and the first direction is perpendicular to the first surface.

8. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The first plasma etching etched a region on the first surface that covers 50% to 90% of the first surface exposed between adjacent initial bit line structures.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before filling the first contact structure into the first hole, the manufacturing method further includes: A second plasma etching is performed on a portion of the side surface of the second source / drain region to remove the first oxide layer formed on the portion of the side surface of the second source / drain region, and a protective gas is introduced after the first oxide layer is removed to protect the exposed side surface of the second source / drain region.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The angle between the plasma injection direction of the second plasma etching and the first direction is 15° to 30°, and the first direction is perpendicular to the first surface; and / or, The second plasma etching employs argon plasma and hydrogen plasma; and / or, The energy of the second plasma etching is 50 eV to 100 eV.

11. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The step of filling the first contact structure into the first hole includes: A first contact layer is formed, which covers the initial bit line structure and fills the space between the first hole and the adjacent initial bit line structure. A portion of the first contact layer is removed to obtain the first contact structure, which is flush with the first surface.

12. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a sidewall protective layer on the initial bitline structure includes: A first nitride layer, a second oxide layer, and a second nitride layer are sequentially formed on the sidewall of the initial bit line structure to obtain the bit line structure. The first nitride layer, the second oxide layer, and the second nitride layer constitute the sidewall protective layer. And / or, The sidewall protective layer covers part of the top surface of the first contact structure.

13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the second contact structure corresponding to the first contact structure includes: An isolation layer is formed, which fills the space between the bit line structures; A plurality of second holes are formed on the isolation layer, each second hole exposing the top surface of a first contact structure; The second contact structure is formed within the second hole.

14. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate, the substrate including a plurality of active regions isolated by a shallow trench isolation structure, a plurality of bit line structures formed on a first surface of the substrate, the bit line structures being connected to a first source / drain region of the active regions; Multiple first holes are disposed on the first surface of the substrate, and the first holes expose a portion of the side surface of the second source / drain region of the active region and a portion of the side surface of the shallow trench isolation structure. Multiple first contact structures correspond one-to-one with multiple first holes. The first contact structure fills the corresponding first hole and is connected to the partial side surface of the second source / drain region and the partial side surface of the shallow trench isolation structure. Multiple second contact structures correspond one-to-one with multiple first contact structures, and the second contact structures are connected to the corresponding first contact structures to form capacitive contact plugs.

15. The semiconductor structure according to claim 14, characterized in that, The bit line structure includes a sidewall protective layer that covers a portion of the top surface of the first contact structure.

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