Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a first channel structure; a first air layer surrounding a side surface of the first channel structure; a first bit line contacting a side surface of the first channel structure; a first word line contacting a lower portion of the first channel structure; a storage node having one end portion contacting an upper portion of the first channel structure; a second channel structure contacting an upper portion of the storage node; a second air layer configured to surround a side surface of the second channel structure; a second bit line contacting a side surface of the second channel structure; and a second word line contacting an upper portion of the second channel structure. The first bit line extends in a direction perpendicular to a direction in which the first channel structure extends. The second word line extends in a direction perpendicular to a direction in which the second channel structure extends.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0165691, filed on November 19, 2024, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this patent document. Technical Field

[0003] The technology and embodiments disclosed in this patent document generally relate to a semiconductor device, and more specifically, to a semiconductor device including a memory cell. Background Technology

[0004] Since miniaturization and higher integration of semiconductor devices have become major issues, memory cells included in semiconductor devices can be formed with three-dimensional (3D) patterns. Miniaturized memory cells with three-dimensional (3D) patterns can be equipped with configurations that improve the operating characteristics of the memory cells. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a semiconductor memory device that includes two transistors and has a higher degree of integration.

[0006] Various embodiments of this disclosure relate to a semiconductor memory device configured to be less affected by parasitic capacitance.

[0007] According to embodiments of this disclosure, a semiconductor device may include: a first channel structure; a first air layer configured to surround a side surface of the first channel structure; a first bit line configured to contact the side surface of the first channel structure; a first word line configured to contact a lower portion of the first channel structure; a memory node having an end portion contacting an upper portion of the first channel structure; a second channel structure configured to contact the upper portion of the memory node; a second air layer configured to surround a side surface of the second channel structure; a second bit line configured to contact a side surface of the second channel structure; and a second word line configured to contact the upper portion of the second channel structure. The first bit line extends in a direction perpendicular to the direction in which the first channel structure extends, and the second word line extends in a direction perpendicular to the direction in which the second channel structure extends.

[0008] In some other implementations, the direction in which the first line extends is perpendicular to the direction in which the second line extends.

[0009] In some other embodiments, the first air layer may include a first vertical extension disposed between two adjacent first lines.

[0010] In some other embodiments, the second air layer may include a second vertical extension disposed between two adjacent second bit lines.

[0011] In some other embodiments, the first channel structure may include: a first gate having a columnar shape extending in a vertical direction; a first gate insulating layer configured to surround a side surface and a bottom surface of the first gate; and a first channel region configured to surround the first gate insulating layer. The second channel structure may include: a second gate having a columnar shape extending in a vertical direction; a second gate insulating layer configured to surround a side surface and a bottom surface of the second gate; and a second channel region configured to surround the second gate insulating layer.

[0012] In some other embodiments, the semiconductor device may further include a peripheral region disposed below the first word line.

[0013] In some other embodiments, the first air layer may include a first gap-filling region disposed in the first vertical extension.

[0014] In some other embodiments, the second air layer may include a second gap-filling region disposed in the second vertical extension.

[0015] In some other embodiments, the first air layer may include a first residual sacrificial layer configured to contact the sidewall of the first channel structure.

[0016] In some other embodiments, the second air layer may include a second residual sacrificial layer configured to contact the sidewalls of the second channel structure.

[0017] In some other embodiments, the first air layer may be disposed between the first digit line and the first letter line, and configured as part of the sidewall surrounding the first channel structure.

[0018] In some other embodiments, a second air layer may be disposed between the second bit line and the second word line, and configured as part of the sidewall surrounding the second channel structure.

[0019] According to another embodiment of this disclosure, a semiconductor device may include: a plurality of first word lines, each first word line being configured to extend along a first direction; a plurality of first channel structures, each of the plurality of first channel structures being configured to contact the upper portion of the plurality of first word lines and extend along a second direction perpendicular to the first direction; a plurality of first bit lines, each of the plurality of first bit lines having a common contact contacting the side surfaces of the first channel structures arranged parallel to each other along a third direction; a first air layer disposed between the plurality of first channel structures; a plurality of memory nodes, each of the plurality of memory nodes being configured to contact the upper portion of the plurality of first channel structures; a plurality of second channel structures, each of the plurality of second channel structures being configured to contact the plurality of memory nodes and extend along a second direction; a plurality of second bit lines, each of the plurality of second bit lines having a common contact contacting the side surfaces of the second channel structures arranged parallel to each other along a third direction; a second air layer disposed between the plurality of second channel structures; and a plurality of second word lines, each of the plurality of second word lines being configured to contact the upper portion of the second channel structures arranged parallel to each other along the first direction.

[0020] In some other embodiments, a first air layer may surround a portion of the side surface of a plurality of first channel structures; and a second air layer may surround a portion of the side surface of the second channel structure.

[0021] In some other embodiments, a plurality of first word lines may be arranged repeatedly along a third direction; and a plurality of second word lines may be arranged repeatedly along a third direction.

[0022] In some other embodiments, each of the plurality of first channel structures may include: a first gate having a columnar shape extending in a vertical direction; a first gate insulating layer configured to surround a side surface and a bottom surface of the first gate; and a first channel region configured to surround the first gate insulating layer. Each of the plurality of second channel structures includes: a second gate having a columnar shape extending in a vertical direction; a second gate insulating layer configured to surround a side surface and a bottom surface of the second gate; and a second channel region configured to surround the second gate insulating layer.

[0023] In some other embodiments, at least a portion of the first air layer may be disposed below a plurality of first position lines; and at least a portion of the second air layer may be disposed below a plurality of second position lines.

[0024] In some other embodiments, the first air layer may include a plurality of first vertical extensions, each first vertical extension being disposed between two adjacent first lines among a plurality of first lines and extending in a third direction, and the second air layer may include a plurality of second vertical extensions, each second vertical extension being disposed between two adjacent second lines among a plurality of second lines and extending in a third direction.

[0025] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device may include: forming a first word line on a substrate; forming a first bit line over the first word line; forming a first channel structure such that a bottom surface of the first channel structure contacts the first word line and a side surface of the first channel structure contacts the first bit line; forming a first air layer to surround the side surface of the first channel structure; forming a memory node to contact the top surface of the first channel structure; forming a second bit line over the memory node; forming a second channel structure such that a bottom surface of the second channel structure contacts the memory node and a side surface of the second channel structure contacts the second bit line; and forming a second air layer to surround the side surface of the second channel structure.

[0026] It should be understood that the foregoing general description and the following detailed description of this disclosure are illustrative and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0027] The foregoing and other features, as well as the advantages of this disclosure, will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0028] Figure 1 This is a schematic perspective view illustrating a portion of a memory cell array of a semiconductor device based on some embodiments of the present disclosure.

[0029] Figure 2 This is a circuit diagram illustrating an example of an equivalent circuit of a memory cell of a semiconductor device based on some embodiments of the present disclosure.

[0030] Figure 3A This is a plan view as seen from the second direction D2, showing a portion of a memory cell array based on some embodiments of this disclosure.

[0031] Figure 3B This illustrates some embodiments based on this disclosure. Figure 3A A cross-sectional view of an example memory cell taken by the first tangent.

[0032] Figure 3C This illustrates some embodiments based on this disclosure. Figure 3A A cross-sectional view of an example memory cell taken by the second tangent.

[0033] Figure 4A This is a plan view as seen from the second direction D2, showing a portion of a memory cell array based on some other embodiments of this disclosure.

[0034] Figure 4B This illustrates some other embodiments based on this disclosure. Figure 4A A cross-sectional view of an example memory cell taken by the third tangent.

[0035] Figure 4C This illustrates some other embodiments based on this disclosure. Figure 4A A cross-sectional view of an example memory cell taken by the fourth tangent.

[0036] Figures 5A to 26C This is a view illustrating examples of methods for manufacturing semiconductor devices based on some embodiments of this disclosure. Detailed Implementation

[0037] Embodiments of this disclosure provide implementations and examples of semiconductor devices including memory cells that can be used in configurations to substantially solve one or more technical or engineering problems and mitigate limitations or drawbacks encountered in some other semiconductor devices. Some embodiments of this disclosure relate to a semiconductor memory device including two transistors and having higher integration density. Some embodiments of this disclosure relate to a semiconductor memory configured to be less affected by parasitic capacitance. Recognizing the above-mentioned problems, this disclosure can provide semiconductor devices with three-dimensional (3D) channels to improve integration density. This disclosure can provide semiconductor devices having at least one transistor operating as a memory element, resulting in a simplified manufacturing process. This disclosure can provide semiconductor devices including an air layer, thereby reducing signal distortion caused by parasitic capacitance.

[0038] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, all drawings will use the same reference numerals to refer to the same or similar parts. Although the present disclosure is readily adaptable to various modifications and substitutions, specific embodiments are shown by way of example in the drawings. However, the present disclosure should not be construed as limiting itself to the embodiments set forth herein.

[0039] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that this disclosure is not limited to the specific embodiments, but includes various modifications, equivalents, and / or substitutions of the embodiments. Embodiments of this disclosure can provide various effects that can be directly or indirectly recognized by this disclosure.

[0040] In the following description, detailed descriptions of the relevant known configurations or functions will be omitted to avoid confusing the subject.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, as used in this specification, the terms “comprising,” “including,” “containing,” and / or “including” specify the presence of stated constituent elements, steps, operations, and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations, and / or components. The term “and / or” may include a combination of multiple items or any one of multiple items.

[0042] In the following description, a semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic perspective view illustrating an example of a portion 1 of a memory cell array of a semiconductor device based on some embodiments of the present disclosure.

[0044] refer to Figure 1 The memory cell array may include memory cells (MCs), and each memory cell (MC) may include a first transistor TR1, a memory node SN, and a second transistor TR2.

[0045] The first transistor TR1 and the second transistor TR2 can be arranged in a vertical direction, and the first transistor TR1 and the second transistor TR2 can be connected to the memory node SN.

[0046] The first transistor TR1 may include a first channel structure CS1, a first bit line BL1, and a first word line WL1.

[0047] The first character line WL1 can extend along the first direction D1. A plurality of first channel structures CS1, which are repeatedly arranged along the first direction D1, can be disposed on the first character line WL1.

[0048] Multiple first channel structures CS1 arranged repeatedly along the first direction D1 can be connected to a first word line WL1.

[0049] The first channel structure CS1 may extend along the second direction D2 and may include multiple layers. For example, the first channel structure CS1 may include a first gate, a first gate insulating layer, and a first channel region.

[0050] The first channel structure CS1 can be connected to the first word line WL1 through the first channel region.

[0051] The first line BL1 can extend along the third direction D3. The first line BL1 can contact the side surface of the first channel region included in the first channel structure CS1.

[0052] The first line BL1 extending along the third direction D3 can make common contact (e.g., contact each, forming a common contact) with the side surfaces of a plurality of first channel structures CS1 repeatedly arranged along the third direction D3. Specifically, the first line BL1 can extend along the direction D3 perpendicular to the direction D2 in which the first channel structures CS1 extend.

[0053] The memory node SN can be a region connected to the first channel structure CS1 and the second channel structure CS2. The memory node SN can contact the lower part of the second channel region included in the second channel structure CS2 and the upper part of the first gate included in the first channel structure CS1.

[0054] The second channel structure CS2 can be connected to the upper part of the storage node SN.

[0055] The second channel structure CS2 may extend along the second direction D2 and may include multiple layers. For example, the second channel structure CS2 may include a second gate, a second gate insulating layer, and a second channel region.

[0056] The second bit line BL2 can be connected to the side surface of the second channel structure CS2.

[0057] The second bit line BL2 can extend along the third direction D3. The second bit line BL2 can be connected to the side surface of the second channel region included in the second channel structure CS2.

[0058] The second bit line BL2 extending along the third direction D3 can be connected to the side surface of a plurality of second channel structures CS2 that are repeatedly arranged along the third direction D3.

[0059] The second word line WL2 can be connected to the upper part of the second channel structure CS2. The second word line WL2 can be connected to the upper part of the second gate included in the second channel structure CS2. The second word line WL2 can extend along a direction D1 perpendicular to direction D2.

[0060] Multiple second channel structures CS2 arranged repeatedly along the first direction D1 can be connected to a second word line WL2.

[0061] Figure 2 This is a circuit diagram illustrating an example of an equivalent circuit of a memory cell of a semiconductor device based on some embodiments of the present disclosure.

[0062] exist Figure 2 The diagram shows the connection between the first transistor TR1, the storage node SN, and the second transistor TR2.

[0063] The following will refer to Figure 1 and Figure 2The structure and operation method of a storage unit based on some embodiments of the present disclosure are described.

[0064] The second transistor TR2 may include a second word line WL2 and a second bit line BL2. Furthermore, the second transistor TR2 may include a second gate, a second gate insulating layer, and a second channel region.

[0065] In some embodiments, the second gate may be connected to the second word line WL2, and one side of the second channel region may be connected to the second bit line BL2.

[0066] The other side of the second channel region can be connected to the memory node SN. The memory node SN can be located between the first transistor TR1 and the second transistor TR2, and can be a region of the second channel region included in the second transistor TR2 connected to the region of the first gate included in the first transistor TR1.

[0067] The first transistor TR1 may include a first word line WL1 and a first bit line BL1. Furthermore, the first transistor TR1 may include a first gate, a first gate insulating layer, and a first channel region.

[0068] In some embodiments, the first gate may be connected to the memory node SN. Furthermore, the first word line WL1 may be connected to one side of the first channel region, while the first bit line BL1 may be connected to the other side of the first channel region.

[0069] The semiconductor device, including the first transistor TR1 and the second transistor TR2, can be operated as a storage device.

[0070] When an activation signal is provided to the second gate via the second word line WL2, the second transistor TR2 can be turned on. When the second transistor TR2 is turned on, the amount of charge stored in the memory node SN may change due to the voltage supplied to the second bit line BL2. At this time, the type of data to be stored in the memory node SN can be determined based on the voltage supplied to the second bit line BL2. This operation can be referred to as a write operation.

[0071] The voltage output from the first transistor TR1 can be changed according to the charge stored in the storage node SN.

[0072] When any voltage is supplied to the first word line WL1 and the first bit line BL1 is in a pre-charge state, the pre-charge voltage of the first bit line BL1 can vary depending on the voltage supplied by the first word line WL1 when a charge with an active voltage is stored in the storage node SN.

[0073] On the other hand, when such charge with an activation level voltage is not stored in the storage node SN, the precharge voltage of the first word line BL1 may not vary depending on the voltage provided by the first word line WL1.

[0074] Therefore, the type of data stored in the storage node SN can be determined by detecting the voltage change of the first line BL1. This operation can be referred to as a read operation.

[0075] One storage node SN can correspond to one storage cell. By selectively operating the first transistor TR1 and the second transistor TR2, different types of data can be stored or retrieved in the corresponding storage cell.

[0076] Parasitic capacitance may occur between the memory node SN and the first word line WL1 adjacent to the memory node SN, and parasitic capacitance may occur between the memory node SN and the first bit line BL1 adjacent to the memory node SN. Furthermore, parasitic capacitance may occur between the memory node SN and the second word line WL2 adjacent to the memory node SN, and parasitic capacitance may occur between the memory node SN and the second bit line BL2 adjacent to the memory node SN.

[0077] Due to parasitic capacitance, a voltage drop may occur at the storage node SN. For example, a voltage change at storage node SN may occur due to a voltage change on the first word line WL1 or the second word line WL2. As a result, the voltage change may also increase as the parasitic capacitance increases.

[0078] When a voltage drop occurs in a storage node (SN), the sensing margin of the semiconductor device may decrease, leading to a deterioration in the operating characteristics of the storage element.

[0079] Therefore, a structure may be needed to reduce the parasitic capacitance between the storage node SN and the adjacent first word line WL1, the parasitic capacitance between the storage node SN and the adjacent first bit line BL1, the parasitic capacitance between the storage node SN and the second word line WL2, and the parasitic capacitance between the storage node SN and the second bit line BL2.

[0080] Figure 3A This is a plan view as seen from the second direction D2, showing a portion of a memory cell array based on some embodiments of this disclosure.

[0081] Figure 3B This illustrates some embodiments based on this disclosure. Figure 3A A cross-sectional view of an example memory cell intercepted by the first tangent line A1-A1′.

[0082] Figure 3C This illustrates some embodiments based on this disclosure. Figure 3AA cross-sectional view of an example memory cell intercepted by the second tangent line B1-B1′.

[0083] In some embodiments, the first tangent A1-A1′ may be a tangent extending along a third direction D3. Furthermore, the second tangent B1-B1′ may be a tangent extending along a first direction D1.

[0084] In the following text, reference will be made to Figure 3A , Figure 3B and Figure 3C The structure of a semiconductor device based on some embodiments of this disclosure is described.

[0085] refer to Figures 3A to 3C Semiconductor devices based on some embodiments of this disclosure may include a first word line 110 disposed on the peripheral region PERI.

[0086] The Peripheral Area (PERI) can be a region that provides multiple transistors and multiple control circuits. The transistors and control circuits included in the PERI can be connected to the memory cells located above the PERI via at least one vertical contact.

[0087] The structure in which the peripheral area PERI is located below the storage cell can be called a peripheral-under-cell (PUC) structure.

[0088] The first word line 110 may extend along a first direction D1. The first word line 110 may include multiple layers. For example, the first word line 110 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0089] The first word line 110 may be surrounded by a first insulating layer 120, and a plurality of adjacent first word lines 110 may be electrically isolated from each other through the first insulating layer 120. The first insulating layer 120 may include an insulating material such as silicon nitride.

[0090] The first air layer 130 may be disposed above the first insulating layer 120. The first air layer 130 may be a region that includes air.

[0091] The first air layer 130 may open at least a portion of the side surface of the first channel structure 160.

[0092] refer to Figure 3C The first air layer 130 may include a first vertical extension V1 disposed between two adjacent first lines 150 and extending along a third direction D3.

[0093] Furthermore, the first air layer 130 may include a first gap-filling region 131 disposed within the first vertical extension V1. The first gap-filling region 131 may extend along a third direction D3.

[0094] The first gap-filling region 131 may include silicon oxide manufactured by a spin-on dielectric (SOD) process.

[0095] By forming a first air layer 130 that includes air, the parasitic capacitance that may occur between the storage node 170 and the first word line 110 can be reduced.

[0096] Furthermore, the parasitic capacitance that may occur between the first first line 150 can be reduced by including the first vertical extension V1 in the first air layer 130.

[0097] The second insulating layer 140 may be disposed above the first air layer 130. The second insulating layer 140 may surround the side surfaces of the first channel structure 160, the first bit line 150, and the storage node 170.

[0098] In some embodiments, the second insulating layer 140 may include an insulating material such as silicon nitride.

[0099] The second insulating layer 140 may include, for example, a lower end portion 140a (hereinafter referred to as the "lower end portion of the second insulating layer"), a middle end portion 140b (hereinafter referred to as the "middle end portion of the second insulating layer"), and an upper end portion 140c (hereinafter referred to as the "upper end portion of the second insulating layer").

[0100] The lower end 140a, the middle end 140b, and the upper end 140c of the second insulating layer may comprise the same or different insulating materials. When the second insulating layer 140 is provided, the first first line 150, the first channel structure 160, and the storage node 170 that are adjacent to each other may be electrically isolated from each other.

[0101] The first line 150 may be disposed in the second insulating layer 140 and may extend in the third direction D3. Each first line 150 may include multiple layers. For example, the first line 150 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0102] The first line 150 may contact the side surface of the first channel structure 160. The first line 150 may be formed to surround at least a portion of the side surface of the first channel structure 160. The first line 150 may contact the first channel region 163 included in the first channel structure 160.

[0103] The first channel structure 160 may include a first gate 161 formed as a column extending along a second direction D2, a first gate insulating layer 162 surrounding the bottom surface and side surface of the first gate 161, and a first channel region 163 formed as surrounding the first gate insulating layer 162.

[0104] The first gate 161 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof. The first gate 161 may be formed to include a side surface extending along the second direction D2. For example, the first gate 161 may be formed as a cylinder or a polygonal cylinder.

[0105] The first gate insulating layer 162 may include an insulating material such as silicon oxide.

[0106] The first channel region 163 may be disposed on the bottom surface and side surface of the first gate insulating layer 162. The first channel region 163 may include, for example, an oxide semiconductor material.

[0107] Oxide semiconductor materials may include, for example, indium gallium zinc oxide (IGZO).

[0108] According to another embodiment, the first channel region 163 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0109] The first channel region 163, which includes an oxide semiconductor material, can have low leakage current characteristics.

[0110] Storage node 170 can be surrounded by a second insulating layer 140.

[0111] Storage node 170 may include, for example, metal, metal nitride, polysilicon, combinations thereof, and / or multiple layers thereof. Storage node 170 may electrically connect a first channel structure 160 and a second channel structure 250 to each other.

[0112] A third insulating layer 210 may be disposed on top of the storage node 170. The third insulating layer 210 may include an insulating material such as silicon nitride.

[0113] The second air layer 220 can be disposed above the third insulating layer 210. The second air layer 220 can be a region that includes air.

[0114] The second air layer 220 can open at least a portion of the side surface of the second channel structure 250.

[0115] refer to Figure 3C The second air layer 220 may include a second vertical extension V2 disposed between two adjacent second bit lines 240 and extending along a third direction D3.

[0116] Furthermore, the second air layer 220 may include a second gap-filling region 221 disposed within the second vertical extension V2. The second gap-filling region 221 may extend along a third direction D3.

[0117] The second gap-filling region 221 may include silicon oxide manufactured by a spin-on dielectric (SOD) process.

[0118] By forming a second air layer 220 that includes air, parasitic capacitance that may occur between storage node 170 and second bit line 240 or between storage node 170 and second word line 260 can be reduced.

[0119] Furthermore, the parasitic capacitance that may occur between the second bit lines 240 can be reduced by the second vertical extension V2 included in the second air layer 220.

[0120] The fourth insulating layer 230 may be disposed above the second air layer 220. The fourth insulating layer 230 may surround the side surfaces of the second channel structure 250, the second bit line 240, and the second word line 260.

[0121] In some embodiments, the fourth insulating layer 230 may include an insulating material such as silicon nitride.

[0122] The fourth insulating layer 230 may include, for example, a lower end 230a (hereinafter referred to as the "lower end of the fourth insulating layer"), a middle end 230b (hereinafter referred to as the "middle end of the fourth insulating layer"), and an upper end 230c (hereinafter referred to as the "upper end of the fourth insulating layer").

[0123] The lower end 230a, the middle end 230b, and the upper end 230c of the fourth insulating layer may contain the same insulating material or different insulating materials.

[0124] When the fourth insulating layer 230 is provided, the second bit line 240, the second channel structure 250 and the second word line 260 that are adjacent to each other can be electrically isolated from each other.

[0125] The second bit line 240 may be disposed in the second insulating layer 140 and may extend in the third direction D3. Each second bit line 240 may include multiple layers. For example, the second bit line 240 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0126] The second bit line 240 may contact the side surface of the second channel structure 250. The second bit line 240 may be formed to surround at least a portion of the side surface of the second channel structure 250. The second bit line 240 may contact the second channel region 253 included in the second channel structure 240.

[0127] The second channel structure 250 may include a second gate 251 formed as a column extending along the second direction D2, a second gate insulating layer 252 formed to surround the bottom surface and side surface of the second gate 251, and a second channel region 253 formed to surround the second gate insulating layer 252.

[0128] The second gate 251 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof. The second gate 251 may be formed to include a side surface extending along the second direction D2. For example, the second gate 251 may have a cylindrical or polygonal cylindrical shape.

[0129] The second gate insulating layer 252 may include an insulating material such as silicon oxide.

[0130] The second channel region 253 can be disposed on the side surface and the bottom surface of the second gate insulating layer 252. The second channel region 253 may include, for example, an oxide semiconductor material.

[0131] Oxide semiconductor materials may include, for example, indium gallium zinc oxide (IGZO).

[0132] According to another embodiment, the second channel region 253 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), etc.

[0133] The second channel region 253, which includes an oxide semiconductor material, can have low leakage current characteristics.

[0134] One or more second word lines 260 may be disposed on the second channel structure 250. More specifically, the second word lines 260 may be connected to a second gate 251 included in the second channel structure 250.

[0135] The second word line 260 may extend along the first direction D1. The second word line 260 may include multiple layers. For example, the second word line 260 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof. Multiple adjacent second word lines 260 may be electrically isolated from each other by a fourth insulating layer 230.

[0136] Figure 4A This is a plan view as seen from the second direction D2, showing a portion of a memory cell array based on some other embodiments of this disclosure.

[0137] Figure 4B This illustrates some other embodiments based on this disclosure. Figure 4A A cross-sectional view of an example memory cell taken by the third tangent.

[0138] Figure 4CThis illustrates some other embodiments based on this disclosure. Figure 4A A cross-sectional view of an example memory cell taken by the fourth tangent.

[0139] According to an embodiment, the third tangent A2-A2′ may be a tangent extending along a third direction D3. Furthermore, the fourth tangent B2-B2′ may be a tangent extending along a first direction D1.

[0140] In the following text, reference will be made to Figure 4A , Figure 4B and Figure 4C The structure of a semiconductor device according to an embodiment of the present disclosure is described.

[0141] In addition to the first residual sacrificial layer 132 disposed in the first air layer 130 and the second residual sacrificial layer 222 disposed in the second air layer 220, such as Figures 4A to 4C The remaining internal structure of the semiconductor device shown is similar to that of the reference. Figures 3A to 3C The internal structures of the semiconductor devices described are basically the same; therefore, for the sake of brevity, redundant descriptions will be omitted. The following description will focus on the residual sacrificial layers 132 and 222. Figures 4A to 4C The semiconductor device shown.

[0142] The first residual sacrificial layer 132 is disposed within the first air layer 130 and may surround at least a portion of the side surface of the first channel structure 160.

[0143] The first residual sacrificial layer 132 may surround the sidewall of the first channel region 163 included in the first channel structure 160. The first residual sacrificial layer 132 may be formed to contact the sidewall of the first channel structure 160.

[0144] The first residual sacrificial layer 132 may include a carbon-containing material, such as spin-coated carbon (SOC).

[0145] When the first air layer 130 is formed by plasma process, the first residual sacrificial layer 132 can be formed by selectively removing the spin-coated carbon (SOC) layer.

[0146] In this case, the plasma process can be carried out using a gas including at least one of oxygen, nitrogen, or hydrogen (e.g., oxygen (O2), nitrogen (N2), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), or methane (CH4)).

[0147] For example, if an O2 plasma process is performed, oxygen radicals (O*) can combine with the carbon in the sacrificial layer, resulting in the formation of CO or CO2. The generated CO or CO2 can be discharged to the outside through the first vertical extension V1, allowing the sacrificial layer pattern to be removed and a first air layer 130 to be formed.

[0148] At this point, information regarding whether to retain the sacrificial layer pattern can be adjusted by controlling the execution time and temperature of the plasma process or the gas used in the plasma process.

[0149] The second residual sacrificial layer 222 may be disposed within the second air layer 220 and may surround at least a portion of the side surface of the second channel structure 250. The second residual sacrificial layer 222 may be formed to contact the sidewall of the second channel structure 250.

[0150] The second residual sacrificial layer 222 may surround the sidewall of the second channel region 253 included in the second channel structure 250.

[0151] The second residual sacrificial layer 222 may include a carbon-containing material, such as spin-coated carbon (SOC).

[0152] When the second air layer 220 is formed by plasma process, the second residual sacrificial layer 222 can be formed by selectively removing the spin-coated carbon (SOC) layer. The manufacturing process of the second residual sacrificial layer 222 is basically the same as that of the first residual sacrificial layer 132. Therefore, for the sake of brevity, the repeated description of it will be omitted.

[0153] In the following text, reference will be made to Figures 5A to 26C A method for manufacturing a semiconductor device according to embodiments of the present disclosure is described.

[0154] Figures 5A to 5C This is a view illustrating an example of a method for manufacturing a first word line of a semiconductor device according to an embodiment of the present disclosure.

[0155] Figure 5A This is a plan view when viewed from the second direction D2, illustrating a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0156] Figure 5B It shows along Figure 5A The cross-sectional view of an example memory cell array cut by the fifth tangent A3-A3′ is shown.

[0157] Figure 5C It shows along Figure 5A The cross-sectional view of an example memory cell array cut by the sixth tangent B3-B3′ is shown.

[0158] Figures 5A to 5C This is a view illustrating an example of a method for forming a first sacrificial layer above the first word line.

[0159] refer to Figures 5A to 5CA first insulating layer 120 may be formed on the first word line 110, and a first sacrificial layer 130a may be formed on the first insulating layer 120.

[0160] Although not shown in the figure, the first word line 110 can be formed on a substrate suitable for semiconductor processing.

[0161] For example, the substrate can be formed of a silicon-containing semiconductor material. The substrate may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof.

[0162] The substrate may also include other semiconductor materials, such as germanium. The substrate may include group III / V semiconductor substrates, for example, compound semiconductor substrates, such as gallium arsenide (GaAs).

[0163] The substrate may include a silicon-on-insulator (SOI) substrate.

[0164] In another embodiment, the substrate may include a peripheral circuit region (not shown) located at its lower portion.

[0165] The first character line 110 can extend along the first direction D1.

[0166] The first word line 110 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0167] The first insulating layer 120 may overlap with the first word line 110 formed on the substrate. The first insulating layer 120 may include silicon nitride.

[0168] The first sacrificial layer 130a can be formed to overlap the entire upper portion of the first insulating layer 120. The region where the first sacrificial layer 130a is formed can be the region used as the first air layer 130 by a plasma process.

[0169] The first sacrificial layer 130a may include a carbon-containing material. For example, the first sacrificial layer 130a may include spin-coated carbon (SOC).

[0170] Figures 6A to 6C This is a view illustrating an example of a method for forming the lower end of the second insulating layer and the first prepositioning line over the first sacrificial layer 130a.

[0171] Figure 6A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0172] Figure 6B It shows along Figure 6A The example cross-sectional view of the memory cell array shown is intercepted by the seventh tangent A4-A4′.

[0173] Figure 6C It shows along Figure 6A The cross-sectional view of an example memory cell array cut by the eighth tangent B4-B4′ is shown.

[0174] refer to Figures 6A to 6C The lower end portion 140a of the second insulating layer can be formed on the first sacrificial layer 130a, and the first prepositioning line 150a can be formed in the lower end portion 140a of the second insulating layer.

[0175] The lower end portion 140a of the second insulating layer may include a region comprising silicon nitride. Alternatively, the lower end portion 140a of the second insulating layer may be a region included within the second insulating layer 140.

[0176] The first prepositioning line 150a can be formed by etching a portion of the lower end 140a of the second insulating layer and depositing a conductive material. The first prepositioning line 150a may include a metal, a metal nitride, polysilicon, a combination thereof, or multiple layers thereof.

[0177] Figures 7A to 7C This is a view illustrating an example of a method for forming the first channel hole 160a.

[0178] Figure 7A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0179] Figure 7B It shows along Figure 7A The example cross-sectional view of the memory cell array shown is taken by the ninth tangent A5-A5′.

[0180] Figure 7C It shows along Figure 7A The cross-sectional view of an example memory cell array cut by the tenth tangent B5-B5′ is shown.

[0181] refer to Figures 7A to 7C One or more first channel holes 160a can penetrate at least a portion of the first prepositioning line 150a, the lower end of the second insulating layer 140a, the first sacrificial layer 130a, and the first insulating layer 120.

[0182] Each first channel hole 160a can be formed as a column extending along the second direction D2, such that the first channel region 163 included in the first channel structure 160 has a channel-all-around (CAA) structure.

[0183] refer to Figure 7A A first channel hole 160a can be formed in the first line 150. Furthermore, refer to... Figure 7B and Figure 7C The first channel hole 160a can be formed such that at least a portion of the first letter line 110 is open.

[0184] The first channel region 163 can be connected to the first word line 110 by opening at least a portion of the first word line 110. The first channel hole 160a can be selectively formed by an etching process.

[0185] Figures 8A to 8C This is a view illustrating an example of a method for forming a first pre-gate 161a, a first pre-gate insulating layer 162a, and a first pre-channel region 163a within a first channel via 160a.

[0186] Figure 8A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0187] Figure 8B It shows along Figure 8A The cross-sectional view of an example memory cell array cut by the eleventh sectional line A6-A6′ is shown.

[0188] Figure 8C It shows along Figure 8A The cross-sectional view of an example memory cell array shown is taken by the twelfth tangent B6-B6′.

[0189] refer to Figures 8A to 8C A first pre-channel region 163a, a first pre-gate insulating layer 162a, and a first pre-gate 161a can be sequentially formed within the first channel hole 160a.

[0190] The first pre-channel region 163a may include an oxide semiconductor material, and the oxide semiconductor material may include, for example, indium gallium zinc oxide (IGZO).

[0191] The first pre-groove region 163a can be formed to surround the bottom surface and side surface of the first groove hole 160a. The bottom surface of the first pre-groove region 163a can contact the first letter line 110, and a portion of the side surface of the first pre-groove region 163a can contact the first letter line 150.

[0192] A first pre-gate insulating layer 162a may be formed over the first pre-channel region 163a. ​​The first pre-gate insulating layer 162a may include an insulating material such as silicon oxide.

[0193] The first pre-gate 161a may be formed on the first pre-gate insulating layer 162a. The first pre-gate 161a may include a metal, a metal nitride, polysilicon, a combination thereof, or a multilayer thereof.

[0194] Figures 9A to 9C This is a view illustrating an example of a method for forming the first channel structure 160.

[0195] Figure 9A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0196] Figure 9B It shows along Figure 9A The cross-sectional view of an example memory cell array cut by the thirteenth tangent A7-A7′ is shown.

[0197] Figure 9C It shows along Figure 9A The cross-sectional view of an example memory cell array cut by the fourteenth tangent B7-B7′ is shown.

[0198] refer to Figures 9A to 9C The first channel structure 160 can be formed by selectively removing some regions of the first pre-channel region 163a, the first pre-gate insulating layer 162a, and the first pre-gate 161a.

[0199] The plurality of first gates 161 can be electrically isolated from each other by selectively removing some regions of the first pre-channel region 163a, the first pre-gate insulating layer 162a, and the first pre-gate 161a. In addition, the plurality of first channel regions 163 arranged adjacent to each other along the first direction D1 can be electrically isolated from each other.

[0200] On the other hand, a plurality of first channel regions 163 arranged adjacent to each other along the third direction D3 can be electrically connected to each other via the first line 150 (e.g., forming a common contact).

[0201] Figures 10A to 10C This is a view illustrating an example of a method for forming the second insulating layer 140.

[0202] Figure 10A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0203] Figure 10B It shows along Figure 10A The cross-sectional view of an example memory cell array shown is taken by the fifteenth tangent A8-A8′.

[0204] Figure 10C It shows along Figure 10A The cross-sectional view of an example memory cell array shown is taken by the sixteenth tangent B8-B8′.

[0205] refer to Figures 10A to 10CAn insulating layer may be additionally deposited on the first channel structure 160 to form a second insulating layer intermediate end 140b. The second insulating layer intermediate end 140b may include an insulating material such as silicon nitride.

[0206] The middle end 140b of the second insulating layer may be a region included in the second insulating layer 140 formed later.

[0207] Figures 11A to 11C This is a view showing an example of a method for forming the first vertical hole V1a.

[0208] Figure 11A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0209] Figure 11B It shows along Figure 11A The cross-sectional view of an example memory cell array cut by the seventeenth tangent A9-A9′ is shown.

[0210] Figure 11C It shows along Figure 11A The cross-sectional view of an example memory cell array shown is taken by the eighteenth tangent B9-B9′.

[0211] refer to Figures 11A to 11C Each first vertical hole V1a can be a region obtained by etching the middle end 140b and the lower end 140a of the second insulating layer, and can be a region connected to the first sacrificial layer 130a. The first vertical hole V1a can be formed by selectively etching the region between adjacent first lines 150. The first vertical hole V1a can extend along a third direction D3.

[0212] Figures 12A to 12C This is a view illustrating an example of a method for forming the first air layer 130.

[0213] Figure 12A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0214] Figure 12B It shows along Figure 12A The cross-sectional view of an example memory cell array shown is taken by the nineteenth tangent A10-A10′.

[0215] Figure 12C It shows along Figure 12A The cross-sectional view of an example memory cell array shown is taken by the 20th tangent B10-B10′.

[0216] refer to Figures 12A to 12CThe process of removing the first sacrificial layer 130a and forming the first air layer 130 by means of plasma process is shown.

[0217] Plasma processes can be carried out using gases including at least one of oxygen, nitrogen, or hydrogen (e.g., O2, N2, H2, CO, CO2, or CH4).

[0218] The sacrificial layer (first sacrificial layer 130a) and the plasma can react with each other, and the gas produced by this reaction can be discharged to the outside through the first vertical extension V1. The first air layer 130 can be formed in the region where the first sacrificial layer 130a is removed.

[0219] In some embodiments, the shape of the residual sacrificial layer in contact with the sidewall of the first channel region 163 can be adjusted by controlling the execution time and temperature of the plasma process or the gas used for the plasma process.

[0220] For example, when the first sacrificial layer 130a is completely removed by plasma processing, no residual sacrificial layer is left in the first air layer 130, as in Figure 3A , Figure 3B and Figure 3C As in the embodiments.

[0221] On the other hand, when the plasma process is performed such that a portion of the first sacrificial layer 130a is retained, the first residual sacrificial layer 132 can be retained in the first air layer 130, as in Figure 4A , Figure 4B and Figure 4C As in the embodiments.

[0222] Figures 13A to 13C This is a view illustrating an example of a method for forming the first pre-gap filling region 131a.

[0223] Figure 13A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0224] Figure 13B It shows along Figure 13A The cross-sectional view of an example memory cell array cut by the 21st tangent A11-A11′ is shown.

[0225] Figure 13C It shows along Figure 13A The cross-sectional view of an example memory cell array cut by the 22nd tangent B11-B11′ is shown.

[0226] refer to Figures 13A to 13CThe first pre-gap filling region 131a can be formed on the second insulating layer 140 by the SOD (spin-on dielectric) process.

[0227] The first pre-gap filling region 131a may include an insulating material such as silicon oxide.

[0228] In some embodiments, the first pre-gap filling region 131a may extend from the upper part of the middle end 140b of the second insulating layer to the depth of the first vertical extension V1 up to the first line 150.

[0229] When the first pre-gap filling region 131a extends to the depth of the first first line 150, the first pre-gap filling region 131a can serve as an insulating layer between adjacent first first lines 150. The first pre-gap filling region 131a extending between adjacent first first lines 150 can reduce the parasitic capacitance that occurs between the first first lines 150.

[0230] Figures 14A to 14C This is a view illustrating an example of a method for forming the first gap-filling region 131.

[0231] Figure 14A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0232] Figure 14B It shows along Figure 14A The cross-sectional view of an example memory cell array shown is taken by the 23rd tangent A12-A12′.

[0233] Figure 14C It shows along Figure 14A The cross-sectional view of an example memory cell array shown is taken by the 24th tangent B12-B12′.

[0234] refer to Figures 14A to 14C The first gap filling region 131 can be formed by removing a portion of the first pre-gap filling region 131a and a portion of the middle end 140b of the second insulating layer.

[0235] Figures 15A to 15C This is a view illustrating an example of a method for forming one or more storage nodes 170.

[0236] Figure 15A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0237] Figure 15B It shows along Figure 15AThe cross-sectional view of an example memory cell array cut by the 25th tangent A13-A13′ is shown.

[0238] Figure 15C It shows along Figure 15A The cross-sectional view of an example memory cell array shown is taken by the 26th tangent B13-B13′.

[0239] refer to Figures 15A to 15C Each memory node 170 can be formed on the first gate 161 included in the first channel structure 160.

[0240] Storage node 170 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0241] In some embodiments, the upper end portion 140c of the second insulating layer may be additionally formed on the first channel structure 160, and the storage node 170 may be formed within the upper end portion 140c of the second insulating layer.

[0242] The upper end portion 140c of the second insulating layer may be a region included in the second insulating layer 140.

[0243] Selective etching is performed on some areas of the upper end 140c of the second insulating layer to define the area where the memory node 170 will be formed.

[0244] Figures 16A to 16C This is a view illustrating an example of a method for forming a second sacrificial layer 220a above storage node 170.

[0245] Figure 16A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0246] Figure 16B It shows along Figure 16A The cross-sectional view of an example memory cell array shown is taken by the 27th tangent A14-A14′.

[0247] Figure 16C It shows along Figure 16A The cross-sectional view of an example memory cell array shown is taken by the 28th tangent B14-B14′.

[0248] refer to Figures 16A to 16C A third insulating layer 210 can be formed on top of the storage node 170, and a second sacrificial layer 220a can be formed on top of the third insulating layer 210.

[0249] The third insulating layer 210 may include silicon nitride or the like, and the second sacrificial layer 220a may include a carbon-containing material. For example, the second sacrificial layer 220a may include spin-coated carbon (SOC).

[0250] Figures 17A to 17C This is a view illustrating an example of a method for forming a lower end portion 230a of a fourth insulating layer and a second prepositioning line 240a over a second sacrificial layer 220a.

[0251] Figure 17A This is a plan view as viewed from the second direction D2, showing an example plan view of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0252] Figure 17B It shows along Figure 17A The cross-sectional view of an example memory cell array shown is taken by the 29th tangent A15-A15′.

[0253] Figure 17C It shows along Figure 17A The cross-sectional view of an example memory cell array shown is taken by the 30th tangent B15-B15′.

[0254] refer to Figures 17A to 17C The lower end portion 230a of the fourth insulating layer can be formed on the second sacrificial layer 220a, and the second prepositioning line (240a) can be formed in the lower end portion 230a of the fourth insulating layer.

[0255] The lower end portion 230a of the fourth insulating layer may be a region including silicon nitride, and may then be a region included in the fourth insulating layer 230.

[0256] The second prepositioning line 240a can be formed by etching a portion of the lower end 230a of the fourth insulating layer and depositing a conductive material. The second prepositioning line 240a may include a metal, a metal nitride, polysilicon, a combination thereof, or multiple layers thereof.

[0257] Figures 18A to 18C This is a view showing an example of a method for forming the second channel hole 250a.

[0258] Figure 18A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0259] Figure 18B It shows along Figure 18A The cross-sectional view of an example memory cell array shown is taken by the 31st tangent A16-A16′.

[0260] Figure 18C It shows along Figure 18AThe cross-sectional view of an example memory cell array shown is taken by the 32nd tangent B16-B16′.

[0261] refer to Figures 18A to 18C The second channel hole 250a can penetrate at least a portion of the second prepositioning line 240a, the lower end of the second insulating layer 230a, the second sacrificial layer 220a, and the third insulating layer 210.

[0262] Each second channel hole 250a can be formed as a column extending along the second direction D2, such that the second channel region 253 included in the second channel structure 250 has a channel full-around (CAA) structure.

[0263] refer to Figure 18A A second channel hole 250a can be formed in the second bit line 240. Furthermore, refer to... Figure 18B and Figure 18C The second channel hole 250a can be formed such that at least a portion of the storage node 170 is open.

[0264] The second channel region 253 can be connected to the memory node 170 by opening at least a portion of the memory node 170. The second channel via 250a can be selectively formed by an etching process.

[0265] Figures 19A to 19C This is a view illustrating an example of a method for forming a second pre-gate 251a, a second pre-gate insulating layer 252a, and a second pre-channel region 253a within a second channel via 250a.

[0266] Figure 19A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0267] Figure 19B It shows along Figure 19A The cross-sectional view of an example memory cell array shown is taken by the 33rd tangent A17-A17′.

[0268] Figure 19C It shows along Figure 19A The cross-sectional view of an example memory cell array shown is taken by the 34th tangent B17-B17′.

[0269] refer to Figures 19A to 19C A second pre-channel region 253a, a second pre-gate insulating layer 252a, and a second pre-gate 251a can be sequentially formed within the second channel hole 250a.

[0270] The second pre-channel region 253a may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0271] The second pre-channel region 253a can be formed to surround the bottom surface and side surface of the second channel hole 250a. The bottom surface of the second pre-channel region 253a can contact the storage node 170, and a portion of the side surface of the second pre-channel region 253a can contact the second bit line 240.

[0272] A second pre-gate insulating layer 252a may be formed over the second pre-channel region 253a. The second pre-gate insulating layer 252a may include an insulating material such as silicon oxide.

[0273] The second pregate 251a may be formed on the second pregate insulating layer 252a. The second pregate 251a may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0274] Figures 20A to 20C This is a view showing an example of a method for forming the second channel structure 250.

[0275] Figure 20A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0276] Figure 20B It shows along Figure 20A The cross-sectional view of an example memory cell array cut by the 35th tangent A18-A18′ is shown.

[0277] Figure 20C It shows along Figure 20A The cross-sectional view of an example memory cell array shown is taken by the 36th tangent B18-B18′.

[0278] refer to Figures 20A to 20C The first channel structure 250 can be formed by selectively removing a portion of the second pre-channel region 253a, the second pre-gate insulating layer 252a, and the second pre-gate 251a.

[0279] The plurality of second gates 251 can be electrically isolated from each other by selectively removing a portion of the second pre-channel region 253a, the second pre-gate insulating layer 252a, and the second pre-gate 251a. Furthermore, the plurality of second channel regions 253 arranged adjacent to each other along the first direction D1 can be electrically isolated from each other.

[0280] On the other hand, a plurality of second channel regions 253 arranged adjacent to each other along the third direction D3 can be electrically connected to each other via the second bit line 240.

[0281] Figures 21A to 21C This is a view illustrating an example of a method for forming the fourth insulating layer 230.

[0282] Figure 21A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0283] Figure 21B It shows along Figure 21A The cross-sectional view of an example memory cell array shown is taken by the 37th tangent A19-A19′.

[0284] Figure 21C It shows along Figure 21A The cross-sectional view of an example memory cell array shown is taken by the 38th tangent B19-B19′.

[0285] refer to Figures 21A to 21C An insulating layer may be additionally deposited on the second channel structure 250 to form a fourth insulating layer intermediate end 230b. The fourth insulating layer intermediate end 230b may include an insulating material such as silicon nitride. The fourth insulating layer intermediate end 230b may be a region included in the fourth insulating layer 230 formed later.

[0286] Figures 22A to 22C This is a view showing an example of a method for forming one or more second vertical holes V2a.

[0287] Figure 22A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0288] Figure 22B It shows along Figure 22A The cross-sectional view of an example memory cell array shown is taken by the 39th tangent A20-A20′.

[0289] Figure 22C It shows along Figure 22A The cross-sectional view of an example memory cell array cut by the 40th tangent B20-B20′ is shown.

[0290] refer to Figures 22A to 22C Each second vertical aperture V2a can be a region obtained by etching the middle end 230b and the lower end 230a of the fourth insulating layer, and can be a region connected to the second sacrificial layer 220a. The second vertical aperture V2a can be formed by selectively etching the region between adjacent second bit lines 240. The second vertical aperture V2a can extend along a third direction D3.

[0291] Figures 23A to 23C This is a view illustrating an example of a method for forming the second air layer 220.

[0292] Figure 23A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0293] Figure 23B It shows along Figure 23A The cross-sectional view of an example memory cell array cut by the 41st tangent A21-A21′ is shown.

[0294] Figure 23C It shows along Figure 23A The cross-sectional view of an example memory cell array cut by the 42nd tangent B21-B21′ is shown.

[0295] refer to Figures 23A to 23C The process of removing the second sacrificial layer 220a and forming the second air layer 220 by means of plasma process is shown.

[0296] Plasma processes can be carried out using gases including at least one of oxygen, nitrogen, or hydrogen (e.g., O2, N2, H2, CO, CO2, or CH4).

[0297] The sacrificial layer and the plasma can react with each other, and the gas produced by this reaction can be discharged to the outside through the second vertical extension V2. A second air layer 220 can be formed in the region where the second sacrificial layer 220a is removed.

[0298] In some embodiments, the shape of the residual sacrificial layer in contact with the sidewall of the second channel region 253 can be adjusted by controlling the execution time and temperature of the plasma process or the gas used in the plasma process.

[0299] For example, when the second sacrificial layer 220a is completely removed by plasma processing, no residual sacrificial layer is left in the second air layer 220, as in Figure 3A , Figure 3B and Figure 3C As in the embodiments.

[0300] On the other hand, when the plasma process is performed such that a portion of the second sacrificial layer 220a is retained, the second residual sacrificial layer 222 can be retained within the second air layer 220, as in Figure 4A , Figure 4B and Figure 4C As in the embodiments.

[0301] Figures 24A to 24C This is a view illustrating an example of a method for forming the second pre-gap filling region 221a.

[0302] Figure 24AThis is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0303] Figure 24B It shows along Figure 24A The cross-sectional view of an example memory cell array shown is taken by the 43rd tangent A22-A22′.

[0304] Figure 24C It shows along Figure 24A The cross-sectional view of an example memory cell array cut by the 44th tangent B22-B22′ is shown.

[0305] refer to Figures 24A to 24C A second pre-gap filling region 221a can be formed on the middle end 230b of the fourth insulating layer by the SOD (spin-on dielectric) process.

[0306] The second pre-gap filling region 221a may include an insulating material such as silicon oxide.

[0307] In some embodiments, the second pre-gap filling region 221a may extend from the upper part of the middle end 230b of the fourth insulating layer to the depth of the second vertical extension V2 up to the second bit line 240.

[0308] When the second pre-gap fill region 221a extends to the depth of the second bit line 240, the second pre-gap fill region 221a can serve as an insulating layer between adjacent second bit lines 240. The second pre-gap fill region 221a extending between adjacent second bit lines 240 can reduce the parasitic capacitance that occurs between the second bit lines 240.

[0309] Figures 25A to 25C This is a view showing an example of a method for forming the second gap-filling region 221.

[0310] Figure 25A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0311] Figure 25B It shows along Figure 25A The cross-sectional view of an example memory cell array cut by the 45th tangent A23-A23′ is shown.

[0312] Figure 25C It shows along Figure 25A The cross-sectional view of an example memory cell array shown is taken by the 46th tangent B23-B23′.

[0313] refer to Figures 25A to 25CThe second gap filling region 221 can be formed by removing a portion of the second pre-gap filling region 221a and a portion of the middle end 230b of the fourth insulating layer.

[0314] Figures 26A to 26C This is a view showing an example of a method for forming one or more second word lines 260.

[0315] Figure 26A This is a plan view when viewed from the second direction D2, illustrating an example of a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0316] Figure 26B It shows along Figure 26A The cross-sectional view of an example memory cell array shown is taken by the 47th tangent A24-A24′.

[0317] Figure 26C It shows along Figure 26A The cross-sectional view of an example memory cell array shown is taken by the 48th tangent B24-B24′.

[0318] refer to Figures 26A to 26C The second word line 260 can be formed on the second gate 251 included in the second channel structure 250.

[0319] The second word line 260 may include metal, metal nitride, polysilicon, combinations thereof, or multiple layers thereof.

[0320] In some embodiments, the upper end portion 230c of the fourth insulating layer may be additionally formed on the second channel structure 250, and the second letter line 260 may be formed within the upper end portion 230c of the fourth insulating layer.

[0321] Selective etching is performed on some areas of the upper end 230c of the fourth insulating layer to define the area where the second word line 260 will be formed.

[0322] The fourth insulating layer 230 may be a region including the lower end 230a, the middle end 230b, and the upper end 230c of the fourth insulating layer.

[0323] The second character line 260 can be formed to extend along the first direction D1.

[0324] The second line 260 may be publicly connected (e.g., connected in a public manner to form a public contact) to a plurality of second channel structures 250 that are adjacent to each other along the second direction.

[0325] Furthermore, according to an embodiment, a peripheral region PERI can also be formed below the first word line 110 and the first insulating layer 120. In this case, the peripheral region PERI can be a region in which multiple transistors and multiple control circuits are provided.

[0326] As is apparent from the above description, semiconductor devices based on some embodiments of the present disclosure include three-dimensional (3D) channels to improve integration.

[0327] Semiconductor devices based on some embodiments of this disclosure include at least one transistor that operates as a storage element, thereby resulting in a simplified manufacturing process.

[0328] Furthermore, semiconductor devices based on some embodiments of this disclosure may include an air layer to reduce signal distortion caused by parasitic capacitance.

[0329] The embodiments disclosed herein can provide various effects that can be directly or indirectly recognized through the patent documents mentioned above.

[0330] Those skilled in the art will understand that this disclosure may be practiced in other specific ways than those set forth herein. Furthermore, claims not expressly set forth in the appended claims may be offered as a combination of embodiments or included as new claims by subsequent amendments after the filing of the application.

[0331] Although several illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be conceived based on what is described and / or shown in this patent document.

Claims

1. A semiconductor device, comprising: First channel structure; A first air layer surrounds the side surface of the first channel structure; The first bit line contacts the side surface of the first channel structure; The first character line contacts the lower part of the first channel structure; A storage node having an end portion that contacts the upper portion of the first channel structure; A second channel structure is in contact with the upper part of the storage node; A second air layer surrounds the side surface of the second channel structure; The second bit line contacts the side surface of the second channel structure; as well as The second letter line contacts the upper part of the second channel structure; in: The first bit line extends along a first perpendicular direction that is perpendicular to the direction in which the first channel structure extends; and The second letter extends along a second vertical direction that is perpendicular to the direction in which the second channel structure extends.

2. The semiconductor device according to claim 1, wherein, The direction in which the first bit line extends is perpendicular to the direction in which the second word line extends.

3. The semiconductor device according to claim 1, wherein, The first air layer includes a first vertical extension disposed between two adjacent first lines.

4. The semiconductor device according to claim 1, wherein, The second air layer includes a second vertical extension disposed between two adjacent second bit lines.

5. The semiconductor device according to claim 1, in, The first channel structure includes: A first gate, the first gate having a cylindrical shape extending along the first vertical direction; A first gate insulating layer, the first gate insulating layer surrounding the side surface and bottom surface of the first gate; and The first channel region surrounds the first gate insulating layer, and The second channel structure includes: The second gate has a columnar shape extending along the second vertical direction; A second gate insulating layer, the second gate insulating layer surrounding the side surface and bottom surface of the second gate; and The second channel region surrounds the second gate insulating layer.

6. The semiconductor device according to claim 1 further includes a peripheral region, the peripheral region being disposed below the first word line.

7. The semiconductor device according to claim 3, wherein, The first air layer includes a first gap-filling region disposed in the first vertical extension.

8. The semiconductor device according to claim 4, wherein, The second air layer includes a second gap-filling region disposed in the second vertical extension.

9. The semiconductor device according to claim 1, wherein, The first air layer includes a first residual sacrificial layer configured to contact the sidewall of the first channel structure.

10. The semiconductor device according to claim 1, wherein, The second air layer includes a second residual sacrificial layer configured to contact the sidewall of the second channel structure.

11. The semiconductor device according to claim 1, wherein, The first air layer is disposed between the first bit line and the first word line, and surrounds a portion of the sidewall of the first channel structure.

12. The semiconductor device according to claim 1, wherein, The second air layer is disposed between the second bit line and the second word line, and surrounds a portion of the sidewall of the second channel structure.

13. A semiconductor device, comprising: Multiple first-character lines, each extending along a first direction; A plurality of first channel structures, the plurality of first channel structures respectively contacting the upper part of the plurality of first letter lines and extending along a second direction perpendicular to the first direction; A plurality of first first lines, the plurality of first first lines having a common contact element that contacts the side surfaces of the first channel structures arranged parallel to each other along a third direction; A first air layer is disposed between the plurality of first channel structures; Multiple storage nodes, each of which contacts the upper part of the multiple first channel structures; A plurality of second channel structures, wherein the plurality of second channel structures respectively contact the plurality of storage nodes and extend along the second direction; A plurality of second bit lines, the plurality of second bit lines having a common contact element that contacts the side surfaces of the second channel structures arranged parallel to each other along the third direction; A second air layer is disposed between the plurality of second channel structures; as well as A plurality of second letter lines, the plurality of second letter lines respectively contacting the upper part of the plurality of second channel structures arranged parallel to each other along the first direction.

14. The semiconductor device according to claim 13, wherein, The first air layer surrounds a portion of the side surface of the plurality of first channel structures; and The second air layer surrounds a portion of the side surface of the plurality of second channel structures.

15. The semiconductor device according to claim 13, wherein, The plurality of first character lines are repeatedly arranged along the third direction; and The plurality of second digit lines are repeatedly arranged along the third direction.

16. The semiconductor device according to claim 13, in, Each of the plurality of first channel structures includes: A first gate, the first gate having a cylindrical shape extending in a vertical direction; A first gate insulating layer, the first gate insulating layer surrounding the side surface and bottom surface of the first gate; and The first channel region surrounds the first gate insulating layer, and Each of the plurality of second channel structures includes: A second gate, the second gate having a cylindrical shape extending along the vertical direction; A second gate insulating layer, the second gate insulating layer surrounding the side surface and bottom surface of the second gate; and The second channel region surrounds the second gate insulating layer.

17. The semiconductor device according to claim 13, wherein, At least a portion of the first air layer is disposed below the plurality of first lines; and At least a portion of the second air layer is disposed below the plurality of second bit lines.

18. The semiconductor device according to claim 13, in, The first air layer includes a plurality of first vertical extensions, each first vertical extension being disposed between two adjacent first lines among the plurality of first lines and extending along the third direction. The second air layer includes a plurality of second vertical extensions, each of which is disposed between two adjacent second bit lines among the plurality of second bit lines and extends along the third direction.

19. A method for manufacturing a semiconductor device, the method comprising: The first word line is formed on the substrate; The first line is formed above the first character line; A first channel structure is formed such that the bottom surface of the first channel structure contacts the first character line and the side surface of the first channel structure contacts the first bit line. A first air layer is formed to surround the side surface of the first channel structure; A storage node is formed to contact the top surface of the first channel structure; A second bit line is formed on the storage node; A second channel structure is formed such that the bottom surface of the second channel structure contacts the memory node and the side surface of the second channel structure contacts the second bit line; as well as A second air layer is formed to surround the side surface of the second channel structure.

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