Preparation method of storage structure and storage structure

Abstract

The invention discloses a preparation method of a storage structure and the storage structure. The preparation method comprises the following steps: forming a stacking structure on a substrate structure; the stacked structure comprises a plurality of stacked bodies and isolation structures located between the stacked bodies, and each stacked body comprises a bit line, a storage laminated layer and a first mask layer which are arranged in a stacked mode; carrying out planarization processing on the stack structure to remove the first mask layer and expose the storage stack layer; then, forming a mask covering layer covering the stacked structure; removing the storage lamination layer and the isolation structure in the word line contact region to form a first groove; and forming the first dielectric layer filling the first groove, and then removing the remaining mask covering layer, so that the process window is expanded, and the electrical performance and yield of the storage structure are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a memory structure and the memory structure itself. Background Technology

[0002] Three-dimensional (3D) memory includes a memory array located in the memory area and peripheral devices located in the peripheral area for controlling signals traveling to and from the memory array. For example, three-dimensional phase change random access memory (3D PCM) can store information by utilizing the reversible phase transition of materials between amorphous and crystalline states, and has advantages such as high stability, low power consumption, high storage density, and compatibility with traditional CMOS processes.

[0003] However, the electrical performance and yield of three-dimensional phase-change memory in related technologies still need to be further improved. Summary of the Invention

[0004] To address the problems of existing technologies, this application provides a method for fabricating a storage structure and a storage structure itself. The technical solution is as follows: On the one hand, a method for fabricating a storage structure is provided, including: A stacked structure is formed on a substrate structure; the stacked structure includes a plurality of stacked bodies spaced apart in a first direction and an isolation structure located between the stacked bodies, each of the stacked bodies including a bit line, a memory stack and a first mask layer stacked along a second direction; the second direction is perpendicular to the substrate structure, and the first direction is perpendicular to the second direction; The stacked structure is planarized to remove the first mask layer and expose the storage stack. After the planarization process, a mask cover layer is formed to cover the stacked structure; Remove the storage stack and the isolation structure within the word line contact area to form a first groove; A first dielectric layer is formed to fill the first groove, and after the first dielectric layer is formed, the remaining mask cover layer is removed.

[0005] In some embodiments, the memory stack includes a first electrode layer, a gate layer, a second electrode layer, a phase change layer, and a third electrode layer stacked along the second direction; the planarization process of the stacked structure to remove the first mask layer and expose the memory stack includes: The stacked structure is planarized, and the process stops at removing the third electrode layer of a predetermined thickness.

[0006] In some embodiments, the preset thickness does not exceed 20 Å in the second direction.

[0007] In some embodiments, removing the remaining mask cover layer includes: planarizing the remaining mask cover layer and stopping at the top surface of the third electrode layer.

[0008] In some embodiments, the thickness of the mask covering layer in the second direction is less than the thickness of the first mask layer in the second direction.

[0009] In some embodiments, the thickness of the mask covering layer in the second direction is no greater than 150 Å.

[0010] In some embodiments, the method further includes: removing the memory stack and the isolation structure in the upper conductor contact area while removing the memory stack and the isolation structure in the word line contact area, forming a second groove.

[0011] In some implementations, removing the storage stack and the isolation structure within the word line contact area and the upper conductor contact area includes: The mask overlay is patterned to form a patterned mask overlay. Using the patterned mask overlay as a mask, the exposed storage stack and the isolation structure are etched away to form the first groove and the second groove.

[0012] In some embodiments, the substrate structure includes a word line overlap structure located within the word line contact area; after removing the remaining mask overlay, the method further includes: In the word line contact area, a first contact structure is formed that penetrates the first dielectric layer and is connected to the word line overlapping structure; A word line layer is formed, which covers the first contact structure, the first dielectric layer, and the remaining memory stack; The word line layer, the first contact structure, and the remaining memory stack are etched along the second direction to form a memory cell array and word lines extending along the first direction.

[0013] On the one hand, a storage structure is provided, which is obtained by using any of the storage structure preparation methods described above.

[0014] In some implementations, the storage structure includes any one of phase-change memory, select-only memory, dynamic random access memory, and flash memory.

[0015] In this embodiment, after forming a stacked structure on the substrate, the stacked structure is first planarized to remove the first mask layer of each stack, exposing the memory stack beneath the first mask layer. Next, a mask overlay layer is formed covering the stacked structure. Then, the memory stack and isolation structure within the word line contact area are removed to form a first groove. A first dielectric layer is then formed to fill the first groove, and the remaining mask overlay layer is removed after forming the first dielectric layer. During this fabrication process, since neither the memory region nor the peripheral region is opened when the first mask layer is removed, there is no load effect during the removal process. Furthermore, because the thickness of the remaining mask overlay layer is much lower than the total thickness of the first mask layer and the mask overlay layer, the remaining mask overlay layer can be removed in a shorter time, thus avoiding the load effect caused by prolonged mask polishing, expanding the process window, and thereby improving the electrical performance and yield of the fabricated memory structure. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a plan view of the storage structure provided in the embodiments of this application; Figures 2 to 6 This is a structural cross-sectional view of the fabrication process of a three-dimensional phase change memory provided in one embodiment; Figure 7 This is a schematic flowchart of a method for preparing a storage structure according to an embodiment of this application; Figures 8 to 13 This is a cross-sectional view of the structure during the preparation process of the storage structure provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0021] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0022] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0023] Figure 1 The diagram shows a plan view of a storage structure including storage area 110 and peripheral area 120. The peripheral area 120 is located on the periphery of storage area 110 and can be located on one or more sides of storage area 110 (such as two sides, three sides, or all four sides).

[0024] For ease of description, the first direction can be defined as... Figure 1 The first direction, viewed from left to right, can also be referred to as the X direction in this embodiment. The third direction is defined as the direction that is on the same plane as the first direction and intersects it; this third direction can also be referred to as the Y direction in this embodiment. Figure 1 As shown in the figure, the third direction, namely the Y direction, can be orthogonal to the first direction, namely the X direction.

[0025] The storage area 110 may include an array area 111 in which phase change memory cells are arranged in an array. Each phase change memory cell is arranged at the intersection of a corresponding bit line (BL) and word line (WL). The bit lines may be spaced apart in the X direction and extend in the Y direction, and the word lines may be spaced apart in the Y direction and extend in the X direction.

[0026] The storage area 110 also includes a word line contact area 112 (also known as WLCT) located in the middle of the storage area 110 along the word line extension direction (i.e., the X direction), where word line contacts that extend the word lines outward can be formed in the word line contact area 112.

[0027] The peripheral area 120 may include peripheral circuitry for operating the phase-change memory cells within the array area 111. This operation may include selection, writing, erasing, reading, programming, etc. The peripheral area 120 typically includes an upper-layer conductor contact area 121, which can form upper-layer conductor contacts for operating the peripheral circuitry. Compared to the critical dimension of the word line contact area 112 in the X direction, the critical dimension of the upper-layer conductor contact area 121 in the X direction is typically relatively smaller; that is, the critical dimension of the word line contact area 112 in the X direction is larger than the critical dimension of the upper-layer conductor contact area 121 in the X direction. For example, the critical dimension of the word line contact area 112 in the X direction may be 40 μm, while the critical dimension of the upper-layer conductor contact area 121 in the X direction may only be 2 μm.

[0028] In the fabrication of three-dimensional memory structures, planarization processes such as chemical mechanical polishing are typically performed to simultaneously planarize the memory region 110 and the peripheral region 120. Because the critical dimension of the word line contact region 112 in the X direction is larger than that of the upper-layer conductor contact region 121 in the X direction, some structural defects are introduced during the fabrication of the three-dimensional memory structure, affecting the final electrical performance and yield of the memory. The following section uses a three-dimensional phase-change memory structure as an example, combined with... Figures 2 to 6 This is to illustrate the structural defects introduced during the fabrication of three-dimensional phase change memory structures.

[0029] like Figure 2 As shown, a first stacked structure 220 is formed on the first substrate structure 210.

[0030] The first stacked structure 220 includes a plurality of first stacked bodies 221 spaced apart in a first direction, i.e., the X direction, and a first isolation structure 222 located between the first stacked bodies 221. Each first stacked body 221 includes a bit line 2211, a first memory stack 2212, and a hard mask layer 2213 stacked along a second direction. The second direction is perpendicular to the first substrate structure 210, and the first direction, i.e., the X direction, is perpendicular to the second direction. In this embodiment, the second direction can also be referred to as the Z direction, such as... Figure 2 As shown in the diagram, a hard mask layer 2213 defines the pattern of bit line 2211, which covers the top electrode of the underlying first memory stack 2212.

[0031] Next, as Figure 3 As shown, a hard mask overlay layer 310 is formed over the first stacked structure 220. It can be understood that the hard mask overlay layer 310 is formed on the hard mask layer 2213 and the first isolation structure 222.

[0032] Next, as Figure 4 As shown, the hard mask cover layer 310, the first stack 221 and the first isolation structure 222 in the word line contact area 112 are removed by etching process, and the hard mask cover layer 310, the first stack 221 and the first isolation structure 222 in the upper conductor contact area 121 are also removed.

[0033] Next, as Figure 5 As shown, a dielectric filling layer 510 is formed in the word line contact area 112 and the upper conductor contact area 121. It can be understood that the dielectric filling layer 510 includes a first dielectric filling layer 511 located in the word line contact area 112 and a second dielectric filling layer 512 located in the upper conductor contact area 121.

[0034] Next, as Figure 6 As shown, the remaining hard mask capping layer 310 and hard mask layer 2213 are removed using a chemical mechanical polishing (CMP) process. It can be understood that the total thickness of the hard mask to be removed in the Z direction is the sum of the thicknesses of hard mask layer 2213 and hard mask capping layer 310. For example, if the thickness of hard mask layer 2213 in the Z direction is 260 Å and the thickness of hard mask capping layer 310 in the Z direction is 150 Å, then in… Figure 6 The steps shown require the removal of a total 410 Å thick hard mask in a single grinding process, which takes a considerable amount of time (at least 110 s) to allow the second dielectric filling layer 512 within the upper conductor contact region 121, which has a critically small size in the X direction, to appear as shown. Figure 6The deep butterfly-shaped indentation 601 shown in the figure has a significant load effect, resulting in a structural defect in the memory structure. Furthermore, the deep butterfly-shaped defect 601 will cause the upper part of the subsequently formed upper-layer conductor contact to be missing, leading to a decrease in the electrical performance and yield of the memory structure.

[0035] To avoid the occurrence of the aforementioned butterfly defect 601, one approach is to reduce... Figure 6 The grinding time of chemical mechanical polishing in the steps shown is limited, but this method will result in insufficient removal of the hard mask on the phase change memory cell in the array region 111, leaving residues. This will lead to the failure of subsequent phase change memory cell opening, reducing the electrical performance and yield of the memory structure.

[0036] Therefore, embodiments of this application provide a method for preparing a storage structure, such as... Figure 7 The diagram shown is a flowchart illustrating a method for fabricating a storage structure according to an embodiment of this application. The method includes: In step S701, a stacked structure is formed on the substrate structure. The stacked structure includes a plurality of stacked bodies spaced apart in a first direction and an isolation structure located between the stacked bodies. Each stacked body includes a bit line, a storage stack, and a first mask layer stacked along a second direction.

[0037] Wherein, the second direction is perpendicular to the substrate structure, and the first direction is perpendicular to the second direction.

[0038] Bit lines are spaced apart in a first direction and extend along a third direction intersecting the first direction, wherein a second direction is perpendicular to both the first and third directions. A first mask layer defines the pattern of the bit lines.

[0039] In step S703, the stacked structure is planarized to remove the first mask layer and expose the storage stack.

[0040] In step S705, after the planarization process, a mask cover layer is formed to cover the stacked structure.

[0041] In step S707, the storage stack and the isolation structure within the word line contact area are removed to form a first groove.

[0042] Specifically, the first groove can expose the portion of the substrate structure located in the word line contact area.

[0043] In some embodiments, while removing the memory stack and the isolation structure in the word line contact area, the memory stack and the isolation structure in the upper conductor contact area may also be removed to form a second groove.

[0044] For example, the opening size of the first groove in the first direction may be larger than the opening size of the second groove in the first direction.

[0045] In step S709, a first dielectric layer is formed to fill the first groove, and after the first dielectric layer is formed, the remaining mask covering layer is removed.

[0046] In the above-described fabrication method of this application embodiment, after forming a stacked structure on the substrate structure, the stacked structure is first planarized to remove the first mask layer of each stack, exposing the memory stack below the first mask layer. Since the memory area and the peripheral area are not opened at this time, there is no load effect in this removal process. Afterwards, since the thickness of the remaining mask cover layer in the Z direction (e.g., 150 Å as mentioned above) is much lower than the total thickness of the first mask layer and the mask cover layer (e.g., 150 Å + 260 Å = 410 Å as mentioned above), the remaining mask cover layer can be removed in a shorter time. For example, the grinding time to remove the 150 Å thick mask cover layer is about 40 seconds, thereby avoiding the load effect caused by long-term mask grinding, expanding the process window, and thus improving the electrical performance and yield of the fabricated memory structure.

[0047] In some implementations, the storage structure in the embodiments of this application may include any one of phase-change memory structure, select-only memory structure, dynamic random access memory structure, and flash memory structure.

[0048] The following uses phase-change memory structure as an example, combined with... Figures 8 to 13 The preparation method of the storage structure provided in the embodiments of this application will be described in detail, wherein, Figures 8 to 13 This is a cross-sectional view of the storage structure during its fabrication process.

[0049] like Figure 8 As shown, a stacked structure 820 is formed on the substrate structure 810.

[0050] In practical applications, the substrate structure 810 may include a substrate 811, a second dielectric layer 812 formed on the substrate 811, and a third dielectric layer 813 formed on the second dielectric layer 812. An interconnect line 814 is formed in the second dielectric layer 812, and an overlap structure 815 is formed in the third dielectric layer 813 that penetrates the third dielectric layer 813 and contacts the interconnect line 814.

[0051] For example, substrate 811 can be a bulk semiconductor or a silicon on insulator (SOI) substrate, which can be doped (e.g., doped with p-type or n-type dopant) or undoped. The SOI substrate is a semiconductor material layer formed on an insulating layer, which can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, disposed on a silicon substrate or a glass substrate. In specific implementations, the semiconductor material of the substrate can include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide.

[0052] Interconnect 814 includes at least a first interconnect 8141, a second interconnect 8142, and a third interconnect 8143. The first interconnect 8141 is used to electrically connect word lines via a lap structure 815, the second interconnect 8142 is used to electrically connect upper-layer conductors via the lap structure 815, and the third interconnect 8143 is used to electrically connect bit lines via the lap structure 815. For ease of distinction, the lap structure 815 contacting the first interconnect 8141 can be referred to as the word line lap structure, the lap structure 815 contacting the second interconnect 8142 can be referred to as the upper-layer conductor lap structure, and the lap structure 815 contacting the third interconnect 8143 can be referred to as the bit line lap structure.

[0053] The interconnect 814 may be formed of a conductive material, such as copper or aluminum. The lap structure 815 may be formed of a conductive material, such as tungsten, tantalum, tantalum nitride, or titanium nitride.

[0054] The materials forming the second dielectric layer 812 and the third dielectric layer 813 may include oxides or nitrides, such as silicon oxide or silicon nitride.

[0055] For example, the substrate structure 810 may also include a barrier layer 816 located between the second dielectric layer 812 and the third dielectric layer 813. The overlapping structure 815 penetrates the third dielectric layer 813 and the barrier layer 816 and contacts the interconnect 814. The barrier layer 816 can be used to protect the morphology of the interconnect 814 formed on the second dielectric layer 812 from being damaged, which is beneficial to ensuring the quality of the phase change memory.

[0056] The stack structure 820 includes a plurality of stack bodies 821 and an isolation structure 822. The plurality of stack bodies 821 are spaced apart in the X direction and extend in the Y direction. The isolation structure 822 fills the gaps between adjacent stack bodies 821. Each stack body 821 includes a bit line 8211, a storage stack 8212 and a first mask layer 8213 stacked in the Z direction. The upper surface of the isolation structure 822 is flush with the upper surface of the stack body 821.

[0057] Bit line 8211 is used to transmit corresponding control signals to the coupled phase-change memory cell.

[0058] The storage stack 8212 may include at least a phase change layer, a gating layer, and multiple electrode layers stacked in the Z direction, for example, reference Figure 8 The storage stack 8212 may include a first electrode layer 8212a, a gate layer 8212b, a second electrode layer 8212c, a phase change layer 8212d, and a third electrode layer 8212e, which are stacked sequentially along the Z direction. This storage stack 8212 can be used to form phase change memory cells coupled to bit lines 8211. Each phase change memory cell can store one or more data bits, and can be written to or read from by changing the voltage applied to the corresponding gate layer.

[0059] In some examples, the storage stack 8212 may further include multiple adhesion layers, which may include a first adhesion layer between the bit line 8211 and the first electrode layer 8212a, a second adhesion layer between the second electrode layer 8212c and the phase change layer 8212d, and a third adhesion layer between the phase change layer 8212d and the third electrode layer 8212e. The multiple adhesion layers can be used to enhance the adhesion of the electrode layers, reduce the probability of electrode layer peeling in subsequent processes, and also reduce material diffusion in the electrode layers. The materials of the multiple adhesion layers may include silicon tungsten nitride (WSiN) and / or silicon titanium nitride (TiSiN).

[0060] In some examples, the stack 821 may further include a sidewall protection layer covering the sidewalls of the stack 821 to protect the memory stack 8212 within the stack 821 in subsequent processes. The material of the sidewall protection layer may include, but is not limited to, silicon nitride, silicon oxide, etc. In some examples, the stack 821 may further include an interface layer located between the sidewall protection layer and a portion of the sidewalls of the stack 821, covering the sidewalls of the phase change layer 8212d and the sidewalls of the third electrode layer 8212e. The material of the interface layer may include at least one of titanium nitride, tantalum nitride, silicon nitride, silicon oxynitride, etc., and may be a single-layer thin film or a multilayer thin film stack structure. This interface layer can prevent the outward diffusion of elements in the phase change layer 8212d and prevent external elements from diffusing into the phase change layer 8212d.

[0061] The first mask layer 8213 defines the pattern of the bit line 8211. The material of the first mask layer 8213 may include, but is not limited to, silicon nitride.

[0062] In some embodiments, forming a stacked structure 820 on the substrate structure 810 may include: Provide such as Figure 8 The substrate structure shown is 810.

[0063] Next, a bit line material layer, a storage material stack, and a first mask material layer are sequentially stacked along the Z direction on the substrate structure 810.

[0064] The bit line material layer is used to form bit lines 8211. The conductive material of the bit line material layer may include one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides.

[0065] A storage material stack is used to form a storage stack 8212. The storage material stack may include a phase change material layer, a gating material layer, and multiple electrode material layers stacked in the Z direction. The multiple electrode material layers may be formed of a conductive material, which may include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The conductive materials of the multiple electrode material layers may be the same or different.

[0066] The phase change material layer can be made of chalcogenides, such as germanium. antimony Tellurium (Ge Sb Te, GST) material or indium antimony Tellurium (In) Sb Te, IST) materials, etc., specifically, for example, the material of the phase change memory material layer can be , , or And so on. The material of the gating material layer can include any suitable bidirectional threshold switch (OTS) material, such as... , , or The first mask material layer is used to form the first mask layer 8213.

[0067] In some examples, the storage material stack may also include multiple layers of adhesive material for forming multiple adhesive layers.

[0068] In specific implementation, one or more thin film deposition processes can be used to deposit the first conductive line material layer, the storage material stack, and the first mask material layer. For example, one or more of the following processes can be used: chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0069] Next, the first mask material layer is patterned to form a first mask layer 8213, which may have a plurality of mask openings that expose portions of the storage material stack, the plurality of mask openings being spaced apart in the X direction and extending along the Y direction.

[0070] Next, based on the first mask layer 8213, multiple isolation structures are formed that penetrate the storage material stack and the first conductive line material layer, and the storage material stack, bit line material layer and the first mask material layer between adjacent isolation structures form a stack.

[0071] Specifically, multiple mask openings can be used to sequentially penetrate the memory material stack and the bit line material layer, thereby forming the bit line material layer into a bit line extending along the Y direction and the memory material stack into a memory stack extending along the Y direction in the same etching step, thus obtaining multiple stacks 821. Next, the trenches between two adjacent stacks 821 are filled with an isolation material, which can be a dielectric material, such as silicon oxide, and can be filled using one or more thin film deposition processes. Afterward, a planarization process such as chemical mechanical polishing can be used to planarize the trenches so that the upper surface of the isolation material is flush with the upper surface of the stack 821, exposing the upper surface of the stack 821, resulting in an isolation structure 822 located between adjacent stacks 821.

[0072] In some examples, before filling the trench between two adjacent stacks 821 with the insulating material, a sidewall protective layer may be deposited on the sidewall of the stack 821 with the trench exposed. After depositing the sidewall protective layer, the remaining gap between the two adjacent stacks 821 is filled with the insulating material to form an isolation structure 822 located between the adjacent stacks 821.

[0073] The above-described embodiments provide a process basis for subsequent processes by forming a stacked structure on the substrate structure.

[0074] Next, see Figure 9 The stack structure 820 is planarized to remove the first mask layer 8213 in the stack structure 820 and expose the storage stack 8212.

[0075] Specifically, planarization processes such as chemical mechanical polishing can be used to planarize the stacked structure 820 until the top surface of the storage stack 8212 is exposed.

[0076] For example, the storage stack 8212 is as follows Figure 8 The structure shown includes a first electrode layer 8212a, a gate layer 8212b, a second electrode layer 8212c, a phase change layer 8212d, and a third electrode layer 8212e stacked along the z-direction.

[0077] To improve the connectivity of the third electrode layer 8212e, the planarization process of the stacked structure 820 to remove the first mask layer 8213 and expose the memory stack 8212 may include: planarizing the stacked structure 820 and stopping at removing the third electrode layer 8212e of a predetermined thickness. This allows the surface of the remaining third electrode layer 8212e to have better flatness, which helps to provide better electrical connectivity. Moreover, since the memory area and the peripheral area are not opened at this step, there is no load effect, and the subsequent polishing time can be reduced. This is beneficial to further expand the process window and improve the yield and electrical performance of the memory structure.

[0078] Understandably, the aforementioned preset thickness is less than the thickness of the third electrode layer 8212e in the Z direction. For example, the preset thickness in the Z direction does not exceed 20 Å, so as to improve the flatness of the remaining third electrode layer while avoiding excessive loss of electrode material.

[0079] Next, see Figure 10 After the planarization process described above, a mask cover layer 1010 is formed that covers the stacked structure 820.

[0080] Understandably, the mask cover layer 1010 is formed on the exposed surface of the storage stack 8212 and the surface of the isolation structure 822. Specifically, the mask cover layer 1010 is formed on the surface of the third electrode 8212e and the surface of the isolation structure 822.

[0081] The material of the mask capping layer 1010 can be a hard mask material such as silicon nitride. The mask capping layer 1010 can be deposited using one or more thin film deposition processes, such as one or a combination of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0082] For example, the thickness of the mask cover layer 1010 in the Z direction is less than the thickness of the first mask layer 8213 in the Z direction. This avoids the load effect caused by excessive grinding time when removing the mask cover layer 1010 due to excessive thickness while providing masking function. This is beneficial to improving the yield and electrical performance of the storage structure.

[0083] Preferably, the thickness of the mask covering layer 1010 in the Z direction is no greater than 150 Å. For example, the thickness of the mask covering layer 1010 in the Z direction can be 150 Å, while the thickness of the first mask layer 8213 in the Z direction can be 260 Å.

[0084] Next, see Figure 11 Remove the storage stack 8212 and isolation structure 822 in the word line contact area 112 to form the first groove 1110.

[0085] Understandably, when the storage stack 8212 and isolation structure 822 within the word line contact area 112 are removed, a portion of the mask cover layer 1010 located in the word line contact area 112 will also be removed.

[0086] Specifically, a portion of the mask cover layer 1010 located in the word line contact area 112, as well as the storage stack 8212 and isolation structure 822 located below the portion of the mask cover layer 1010, can be etched to remove them in sequence, forming a first groove 1110 on the upper surface of the exposed substrate structure 810.

[0087] In some implementations, such as Figure 11 As shown, while removing the storage stack 8212 and isolation structure 822 in the word line contact area 112, the storage stack 8212 and isolation structure 822 in the upper conductor contact area 121 can also be removed to form a second groove 1120.

[0088] Understandably, when removing the storage stack 8212 and isolation structure 822 within the upper conductor contact area 121, a portion of the mask cover layer 1010 located in the upper conductor contact area 121 will also be removed. Specifically, the second groove can expose the upper surface of the substrate structure 810, and typically the opening size of the first groove 1110 in the X direction is larger than the opening size of the second groove 1120 in the X direction.

[0089] In some embodiments, removing the storage stack 8212 and isolation structure 822 within the word line contact area 112 and the upper conductor contact area 121 may include: The mask cover layer 1010 is patterned to form a patterned mask cover layer 1130; Next, using the patterned mask cover layer 1130 as a mask, the exposed storage stack 8212 and isolation structure 822 are etched away to form the first groove 1110 and the second groove 1120, thereby opening the word line contact area 112 and the upper conductor contact area 121 at the same time, providing a process basis for the subsequent formation of conductive contacts.

[0090] Specifically, the patterned mask cover layer 1130 may include a first opening and a second opening. The first opening defines the position of the word line contact area 112, and the second opening defines the position of the upper layer conductor contact area 121. The exposed memory stack 8212 and isolation structure 822 can be etched along the first and second openings of the patterned mask cover layer 1130, such that both the first and second openings extend toward the substrate structure 810 and stop at the surface of the substrate structure 810. A first groove 1110 is formed in the word line contact area 112 corresponding to the first opening, and a second groove 1120 is formed in the upper layer conductor contact area 121 corresponding to the second opening.

[0091] The etching process can be either dry etching or wet etching.

[0092] Understandably, after etching to form the first groove 1110 and the second groove 1120, the patterned mask cover layer 1130 becomes the remaining mask cover layer, and the remaining mask cover layer covers the remaining memory stack 8212, which will be formed into a phase change memory cell in subsequent processes.

[0093] The above-described implementation method opens two key contact windows—the word line contact area and the upper conductor contact area—simultaneously through the same etching process, which helps to improve the fabrication efficiency of the memory structure and increase the throughput of the production line.

[0094] Next, see Figure 12 A first dielectric layer 1210 is formed to fill the first groove 1110 and the second groove 1120.

[0095] Specifically, a first dielectric material can be deposited in the first groove 1110, which fills the first groove 1110 and overflows to cover the upper surface of the remaining mask cover layer 1010. Then, the excess first dielectric material is removed by a process such as chemical mechanical polishing, so that the upper surface of the remaining first dielectric material is flush with the upper surface of the remaining mask cover layer 1010 to form the first dielectric layer 1210.

[0096] The first dielectric material used to form the first dielectric layer 1210 may include oxides, such as silicon oxide.

[0097] Understandably, when the word line contact area 112 and the upper conductor contact area 121 open simultaneously, that is, when the first groove 1110 is formed and the second groove 1120 is also formed, the first dielectric layer 1210 is also filled in the second groove 1120, such as... Figure 12 As shown, the first dielectric layer 1210 includes a first portion dielectric layer 1211 located in the first groove 1110 and a second portion dielectric layer 1212 located in the second groove 1120.

[0098] Next, see Figure 13 After the first dielectric layer 1210 is formed, the remaining mask cover layer 1010 is removed.

[0099] Specifically, after forming the first dielectric layer 1210, the remaining mask cover layer 1010 can be planarized until the top surface of the third electrode 8212e is exposed, so that the mask cover layer 1010 located on the remaining memory stack 8212 is completely removed. Since only the thickness of the mask cover layer 1010 needs to be removed in this process, it can be completed in a shorter grinding time. The grinding time is reduced, and while effectively exposing the remaining memory stack 8212 to provide a process basis for the subsequent formation of phase change memory cells, the loading effect is avoided, the process window of the phase change memory is expanded, and the yield and electrical performance of the memory structure are improved.

[0100] In some embodiments, after removing the remaining mask overlay 1010, the method may further include etching the remaining memory stack 8212 to form a memory cell array, and forming word lines intersecting the bit lines 8211 on the memory cell array. Specifically, this may include: In the word line contact area 112, a first contact structure is formed that penetrates the first dielectric layer 1210 and is connected to the word line overlap structure; then, a word line layer is formed that covers the first contact structure, the first dielectric layer 1210 and the remaining memory stack 8212; then, the word line layer, the first contact structure and the remaining memory stack 8212 are etched along the Z direction to form a memory cell array and word lines extending along the X direction.

[0101] The word line layer is used to form word lines after being patterned. The conductive material of the word line layer can include one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides. The word line layer can be deposited using one or more thin-film deposition processes.

[0102] In a specific implementation, an etching mask material layer can first be formed on the word line layer. Based on the preset pattern of the word lines, multiple openings exposing the word line layer are formed in the etching mask material layer. These multiple openings extend along the X direction and are spaced apart along the Y direction. Next, the word line layer, the first contact structure, and the remaining memory stack are etched along the multiple openings in the Z direction, and the etching stops on the bit line 8211. Thus, while keeping the bit line 8211 intact, the remaining memory stack is formed into a columnar array of memory cells perpendicular to the surface of the substrate structure, the word line layer is formed into word lines extending along the X direction and spaced apart along the Y direction, and the first contact structure is formed into word line contacts.

[0103] Understandably, the aforementioned storage cell array includes multiple storage cells, which may include any one of phase-change storage cells, select-only storage cells, dynamic random access storage cells, and flash memory cells.

[0104] In some examples, upper-layer conductor contacts can be formed in the upper conductor contact area 121 simultaneously with the formation of the memory cell array and word lines. Specifically, while forming a first contact structure that penetrates the first dielectric layer 1210 and connects to the word line overlap structure in the word line contact area 112, a second contact structure that penetrates the first dielectric layer 1210 and connects to the upper conductor overlap structure can be formed in the upper conductor contact area 121. The word line layer formed subsequently can cover the first contact structure, the second contact structure, the first dielectric layer 1210, and the remaining memory stack 8212. While etching the word line layer, the first contact structure, and the remaining memory stack 8212 along the Z direction, the second contact structure is also etched, so that the second contact structure is formed as an upper conductor contact, thereby improving the fabrication efficiency of the memory structure.

[0105] In the above embodiments, by significantly reducing the grinding time, it is possible to effectively avoid deep butterfly-shaped depressions in the first dielectric layer of the upper conductor contact area, thereby effectively avoiding the upper part of the upper conductor contact, and improving the yield and electrical performance of the memory structure.

[0106] This application also provides a storage structure prepared based on any of the foregoing methods, which may be a phase change memory structure.

[0107] It should be noted that the storage structure embodiments provided in this application and the storage structure preparation method embodiments belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0108] The preparation method and storage structure of the storage structure provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating a storage structure, characterized in that, include: A stacked structure is formed on a substrate structure; the stacked structure includes a plurality of stack bodies spaced apart in a first direction and an isolation structure located between the stack bodies, each of the stack bodies including a bit line, a memory stack and a first mask layer stacked along a second direction; The second direction is perpendicular to the substrate structure, and the first direction is perpendicular to the second direction; The stacked structure is planarized to remove the first mask layer and expose the storage stack. After the planarization process, a mask cover layer is formed to cover the stacked structure; Remove the storage stack and the isolation structure within the word line contact area to form a first groove; A first dielectric layer is formed to fill the first groove, and after the first dielectric layer is formed, the remaining mask cover layer is removed.

2. The preparation method according to claim 1, characterized in that, The memory stack includes a first electrode layer, a gate layer, a second electrode layer, a phase change layer, and a third electrode layer stacked along the second direction; the planarization process of the stacked structure to remove the first mask layer and expose the memory stack includes: The stacked structure is planarized, and the process stops at removing the third electrode layer of a predetermined thickness.

3. The preparation method according to claim 2, characterized in that, The preset thickness does not exceed 20 Å in the second direction.

4. The preparation method according to claim 2, characterized in that, The removal of the remaining mask cover layer includes: planarizing the remaining mask cover layer and stopping at the top surface of the third electrode layer.

5. The preparation method according to claim 1, characterized in that, The thickness of the mask covering layer in the second direction is less than the thickness of the first mask layer in the second direction.

6. The preparation method according to claim 5, characterized in that, The thickness of the mask covering layer in the second direction is no greater than 150 Å.

7. The preparation method according to claim 1, characterized in that, Also includes: While removing the memory stack and the isolation structure in the word line contact area, the memory stack and the isolation structure in the upper conductor contact area are also removed to form a second groove.

8. The preparation method according to claim 7, characterized in that, Removing the storage stack and the isolation structure within the word line contact area and the upper conductor contact area includes: The mask overlay is patterned to form a patterned mask overlay. Using the patterned mask overlay as a mask, the exposed storage stack and the isolation structure are etched away to form the first groove and the second groove.

9. The preparation method according to claim 1, characterized in that, The substrate structure includes a word line overlap structure located within the word line contact area; After removing the remaining mask cover layer, the method further includes: In the word line contact area, a first contact structure is formed that penetrates the first dielectric layer and is connected to the word line overlapping structure; A word line layer is formed, which covers the first contact structure, the first dielectric layer, and the remaining memory stack; The word line layer, the first contact structure, and the remaining memory stack are etched along the second direction to form a memory cell array and word lines extending along the first direction.

10. A storage structure, characterized in that, Prepared according to the method for preparing the storage structure according to any one of claims 1 to 9.

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