High-voltage low-resistance lateral double-diffused metal oxide semiconductor device and manufacturing method thereof

Abstract

The invention provides a high-voltage low-resistance lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof. The device comprises a semiconductor substrate which is provided with a second conductive type epitaxial layer; a drift region and a second conductive type body region; a gate structure; a source region and a drain region; a field oxide layer is arranged on the surface of the drift region and located on one side of the gate structure. According to the manufacturing method, a thermal oxidation process for forming a deep trench isolation oxide layer is utilized, and meanwhile, a field oxide layer is grown on the surface of a drift region. The field oxide layer is introduced to replace a traditional STI structure, electric field concentration at the STI groove corner of the drift region is eliminated, the concentration of the drift region is allowed to be improved, and therefore the breakdown voltage is improved, and meanwhile the on-resistance is reduced; meanwhile, the DTI thermal process is utilized to synchronously form the field oxide layer, additional process thermal budget is not increased, and the manufacturing cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device and its manufacturing method. Background Technology

[0002] With the rapid development of power electronic systems towards higher frequencies and greater integration, laterally diffused metal-oxide-semiconductor (LDMOS) devices, as core components of power integrated circuits, directly affect the system's energy efficiency and reliability. Modern applications place stringent "high voltage and low resistance" requirements on LDMOS devices, meaning that the device's breakdown voltage (BV) must meet high-voltage operating conditions, such as a breakdown voltage ≥120V, while simultaneously minimizing the on-resistance (Rsp) to reduce conduction losses to the greatest extent possible.

[0003] However, traditional LDMOS devices are limited by the theoretical limits of silicon materials, facing severe performance bottlenecks in high-voltage applications. To improve the breakdown voltage, the length of the drift region is usually increased, but this leads to a sharp increase in on-resistance; at the same time, the concentration of the electric field on the device surface under high voltage can easily cause premature breakdown.

[0004] To address the issue of surface electric field concentration, the mainstream solution in the industry is to employ shallow trench isolation (STI) structures. While STI structures can alleviate surface electric field concentration with a slight increase in on-resistance, their inherent structural characteristics introduce new problems. Specifically, STI structures introduce trench corners at the bottom of the STI along the drift region path, resulting in new electric field concentration points at these locations. This electric field concentration at the trench corners limits further optimization of the trade-off between breakdown voltage (BV) and on-resistance (Rsp) in high-voltage LDMOS devices, making it difficult to simultaneously achieve higher breakdown voltage and lower resistance, leaving room for performance improvement. Furthermore, introducing additional structures to optimize the electric field often requires complex process steps, leading to a significant increase in process thermal budget and increasing manufacturing difficulty and cost.

[0005] Therefore, a new device structure and process method are needed that can effectively alleviate the electric field concentration in the drift region while taking into account the control of the process thermal budget, thereby obtaining better BV-Rsp performance. Summary of the Invention

[0006] This application provides a high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device and its manufacturing method, in order to solve the technical problems of electric field concentration at the bottom slot corner of the drift region STI in conventional STI structure LDMOS devices, which limits the optimization of the trade-off relationship between device breakdown voltage and on-resistance, and the increase in process thermal budget caused by the additional introduction of oxide structure.

[0007] This application provides a high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device, comprising:

[0008] A semiconductor substrate having an epitaxial layer of a second conductivity type;

[0009] The drift region and the second conductivity type body region are located within the second conductivity type epitaxial layer;

[0010] A gate structure, located on the surface of a semiconductor substrate, includes a gate dielectric layer and a gate conductive layer;

[0011] The first conductivity type heavily doped region includes the source region located in the second conductivity type bulk region and the drain region located in the drift region;

[0012] The surface of the drift region is provided with a field oxide layer, which is located on one side of the gate structure.

[0013] Preferably, the device further includes a heavily doped region of a second conductivity type, which is disposed within the second conductivity type body region as a body contact region.

[0014] Preferably, the field oxide layer is a localized silicon oxide structure.

[0015] Preferably, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0016] Preferably, the gate conductive layer covers the gate dielectric layer and partially extends to cover the surface of the field oxide layer.

[0017] Preferably, a first conductivity type buried layer is further provided between the semiconductor substrate and the second conductivity type epitaxial layer.

[0018] Preferably, the second conductivity type epitaxial layer further comprises a deep first conductivity type well region and a first conductivity type well region; the deep first conductivity type well region is located in the second conductivity type epitaxial layer, and the bottom of the deep first conductivity type well region is in contact with the first conductivity type buried layer; the first conductivity type well region is located above the deep first conductivity type well region; and the first conductivity type heavily doped region is located within the first conductivity type well region.

[0019] Preferably, a second conductive type buried layer is provided below the drift region.

[0020] Preferably, the surface of the semiconductor substrate is further provided with a shallow trench isolation structure.

[0021] Preferably, a deep trench isolation structure is also provided within the semiconductor substrate.

[0022] Preferably, the deep trench isolation structure includes a deep trench, and the depth of the deep trench is greater than the depth of the first conductivity type buried layer disposed in the semiconductor substrate.

[0023] Preferably, the deep trench isolation structure includes a deep trench isolation oxide layer formed on the inner wall of the deep trench.

[0024] Preferably, the field oxide layer and the deep trench isolation oxide layer are formed by the same thermal oxidation process.

[0025] Preferably, the deep trench isolation structure further includes a deep trench isolation conductive layer filled inside the deep trench.

[0026] Preferably, the gate dielectric layer is made of silicon dioxide.

[0027] Preferably, the material of the gate conductive layer is polycrystalline silicon.

[0028] This application also provides a method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device, comprising the following steps:

[0029] Step 1: Provide a semiconductor substrate, form a second conductivity type epitaxial layer on the semiconductor substrate, and form a deep first conductivity type well region and a shallow trench isolation structure in the second conductivity type epitaxial layer;

[0030] Step 2: Sequentially deposit a barrier layer and a hard mask layer on the surface where Step 1 was completed;

[0031] Step 3: Open windows and etch the barrier layer and hard mask layer in the deep trench isolation region, and then etch the semiconductor substrate and the epitaxial layer of the second conductivity type to form a deep trench;

[0032] Step 4: Etch away the barrier layer and hard mask layer in the localized oxide area of ​​silicon to expose the silicon surface;

[0033] Step 5: Perform a thermal oxidation process to form a deep trench isolation oxide layer on the inner wall of the deep trench, and simultaneously grow a field oxide layer at the location where the silicon surface is exposed in the local oxidation area of ​​silicon using this thermal oxidation process.

[0034] Step 6: Remove the remaining hard mask layer and blocking layer;

[0035] Step 7: Perform ion implantation to form a drift region, a second conductivity type body region, and a first conductivity type trap region;

[0036] Step 8: Form a gate dielectric layer on the surface, deposit conductive material, and etch to form a gate conductive layer and a deep trench isolation conductive layer filled in the deep trench;

[0037] Step 9: Perform source / drain ion implantation to form a heavily doped region of the first conductivity type.

[0038] Preferably, in step one, a buried layer of a first conductivity type is also formed in the semiconductor substrate.

[0039] Preferably, in step one, the process of forming a second conductivity type epitaxial layer and a deep first conductivity type well region includes: growing a first second conductivity type epitaxial layer on a semiconductor substrate.

[0040] Preferably, in step one, the process of forming the second conductivity type epitaxial layer and the deep first conductivity type well region further includes: performing ion implantation on the first second conductivity type epitaxial layer to form the deep first conductivity type well region.

[0041] Preferably, in step one, the process of forming the second conductivity type epitaxial layer and the deep first conductivity type well region further includes: continuing to grow a second second conductivity type epitaxial layer on the first second conductivity type epitaxial layer, wherein the first second conductivity type epitaxial layer and the second second conductivity type epitaxial layer together constitute the second conductivity type epitaxial layer.

[0042] Preferably, in step two, the material of the barrier layer is silicon dioxide.

[0043] Preferably, in step two, the material of the hard mask layer is silicon nitride.

[0044] Preferably, in step three, the depth of the deep trench is greater than the depth of the first conductivity type buried layer disposed in the semiconductor substrate.

[0045] Preferably, in step five, the oxidative growth of the field oxide layer is achieved by means of the thermal oxidation process of the deep trench isolation oxide layer.

[0046] Preferably, in step five, the two ends of the field oxide layer are shaped like bird beaks.

[0047] Preferably, in step five, the field oxide layer is a silicon localized oxide structure.

[0048] Preferably, in step seven, a second conductive type buried layer corresponding to the position of the drift region in the depth direction is also formed.

[0049] Preferably, in step seven, the formation process of the drift region and the second conductive type buried layer includes: simultaneously injecting the drift region and the second conductive type buried layer using a high-energy injection process.

[0050] Preferably, in step eight, the gate dielectric layer is formed by a thermal oxidation process.

[0051] Preferably, in step eight, the conductive material is polycrystalline silicon, the gate conductive layer is gate polycrystalline silicon, and the deep trench isolation conductive layer is deep trench isolation polycrystalline silicon.

[0052] Preferably, step nine further includes implanting to form a heavily doped region of a second conductivity type, the heavily doped region of the second conductivity type being located within a body region of the second conductivity type.

[0053] As described above, the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0054] This application replaces the traditional STI structure with a field oxide layer (e.g., a LOCOS structure), utilizing its gentle, beak-like morphology to eliminate electric field concentration at the STI trench corners of the drift region, thereby optimizing the electric field distribution on the device surface. This allows for higher doping concentrations in the drift region without premature breakdown, significantly reducing on-resistance while increasing breakdown voltage and improving the BV-Rsp tradeoff of high-voltage LDMOS devices. Furthermore, the fabrication method of this application utilizes the thermal oxidation process required to form the deep trench isolation oxide layer to simultaneously grow the field oxide layer on the drift region surface, achieving process reuse. This method not only avoids increasing the process thermal budget due to the introduction of an additional LOCOS process and reduces the thermal impact on bulk impurity distribution, but also simplifies the process flow and reduces manufacturing costs. Attached Figure Description

[0055] Figure 1 The diagram shows a process flow diagram of the manufacturing method of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention.

[0056] Figure 2 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after the formation of the epitaxial layer and shallow trench isolation structure.

[0057] Figure 3 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after the formation of a deep trench.

[0058] Figure 4 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after the formation of a localized silicon oxide region.

[0059] Figure 5 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after the formation of the field oxide layer and the removal of the mask layer.

[0060] Figure 6 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after ion implantation to form each well region.

[0061] Figure 7 The diagram shows a cross-sectional structure of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention after the formation of the gate structure and deep trench filling.

[0062] Figure 8The diagram shown is a cross-sectional view of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention.

[0063] Figure 9 The diagram shows a comparison of the drain current-gate voltage characteristics of the high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device of the present invention and a conventional device.

[0064] Figure 10 The diagram shows a comparison of the breakdown voltage characteristics of the high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device of the present invention and a conventional device. Detailed Implementation

[0065] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] The embodiments of this application provide a high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device. Please refer to [link / reference]. Figure 8 , Figure 8 A cross-sectional view of the device after it has been manufactured is shown.

[0067] The device includes: a semiconductor substrate having a second conductivity type epitaxial layer 102; a drift region 109 and a second conductivity type body region 110 located within the second conductivity type epitaxial layer 102; a gate structure located on the surface of the semiconductor substrate, including a gate dielectric layer 112 and a gate conductive layer 113; a first conductivity type heavily doped region 115, including a source region located within the second conductivity type body region 110 and a drain region located within the drift region 109; a field oxide layer 107 is provided on the surface of the drift region 109, and the field oxide layer 107 is located on one side of the gate structure.

[0068] In some embodiments, the semiconductor substrate material may be selected from elemental semiconductors, including crystalline silicon, polycrystalline silicon, amorphous silicon, diamond, or germanium; compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), aluminum arsenide (AlAs), or aluminum antimonide (AlSb); or alloy semiconductors, including silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). The semiconductor substrate may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a silicon-on-glass substrate. The semiconductor substrate may have any crystal orientation, such as (100), (110), or (111) crystal orientations, and may contain various doping configurations, such as P-type substrates or N-type substrates.

[0069] In some embodiments, the device further includes a heavily doped region 116 of a second conductivity type, which is disposed within the second conductivity type body region 110 as a body contact region. By providing a high concentration of the heavily doped region 116 of the second conductivity type, a low-impedance ohmic contact can be provided for the second conductivity type body region 110, thereby effectively fixing the body potential. This potential fixing effect can suppress the turn-on of parasitic bipolar transistors (BJTs) inside the device, prevent latch-up due to parasitic effects, and thus improve the reliability of the device under high voltage and high current operating conditions.

[0070] In some embodiments, the field oxide layer 107 is a localized silicon oxide (LOCOS) structure. This LOCOS structure typically has a beak-like morphology that tapers gradually at both ends and is thicker in the central region. Compared to shallow trench isolation (STI) structures with steeply vertical sidewalls, the field oxide layer 107 exhibits a smoother transition in geometry on the surface of the drift region 109. This smooth structure effectively mitigates the surface electric field, eliminating significant electric field concentration points like those at the bottom trench corners of STI structures. This electric field optimization allows for higher doping concentrations in the drift region 109 without reducing the breakdown voltage (BV), thereby directly reducing the on-resistance (Rsp) and significantly improving the BV-Rsp tradeoff characteristics of high-voltage devices.

[0071] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type. For example, for an N-type LDMOS, the first conductivity type dopant can be selected from group V elements such as phosphorus (P), arsenic (As), and antimony (Sb); the second conductivity type dopant can be selected from group III elements such as boron (B), boron difluoride (BF2), and indium (In). This embodiment uses an N-type first conductivity type and a P-type second conductivity type as an example for illustration.

[0072] In some embodiments, the gate conductive layer 113 covers the gate dielectric layer 112 and partially extends to cover the surface of the field oxide layer 107. The portion of the gate conductive layer 113 extending above the field oxide layer 107 actually forms a field plate structure. When the device is in a blocking state (reverse bias), this field plate structure can help deplete the charge on the surface of the drift region 109, further reducing the electric field peak at the gate edge and the surface of the drift region, and improving the device's breakdown voltage capability.

[0073] In some embodiments, a first conductivity type buried layer 101 is further provided between the semiconductor substrate and the second conductivity type epitaxial layer 102. The first conductivity type buried layer 101 is typically formed by a high-dose ion implantation process, serving as a low-resistivity layer of the device to help reduce parasitic resistance, or as an isolation layer to suppress substrate current.

[0074] In some embodiments, the second conductivity type epitaxial layer 102 further comprises a deep first conductivity type well region 103 and a first conductivity type well region 111; the deep first conductivity type well region 103 is located in the second conductivity type epitaxial layer 102, and the bottom of the deep first conductivity type well region 103 contacts the first conductivity type buried layer 101; the first conductivity type well region 111 is located above the deep first conductivity type well region 103; and the first conductivity type heavily doped region 115 is located within the first conductivity type well region 111. This vertically connected well structure (first conductivity type well region 111 - deep first conductivity type well region 103 - first conductivity type buried layer 101 - first conductivity type heavily doped region 115) provides a low-resistance path for current, or can be used to form a fully isolated island-like region, enabling LDMOS devices to be flexibly integrated into complex analog / mixed-signal circuits.

[0075] In some embodiments, a second conductivity type buried layer 108 is further provided below the drift region 109. The second conductivity type buried layer 108, together with the upper drift region 109 and the lower semiconductor substrate or epitaxial layer, constitutes a dual surface electric field reduction structure. This structure enhances the depletion capability of the drift region 109 by introducing an additional PN junction, allowing the doping concentration of the drift region 109 to be further increased while maintaining a high breakdown voltage, thereby significantly reducing the on-resistance.

[0076] In some embodiments, a shallow trench isolation structure 104 is further provided on the surface of the semiconductor substrate. The formation of the shallow trench isolation structure 104 typically involves photolithography, trench etching, dielectric deposition, and planarization processes. Its filling material is typically silicon oxide formed by high-density plasma chemical vapor deposition (HDP-CVD), which has good isolation properties and is used to define the active area.

[0077] In some embodiments, a deep trench isolation structure is also provided within the semiconductor substrate. The deep trench isolation structure (DTI) typically has a greater depth than the shallow trench isolation structure 104, and is used to form a deep isolation ring around high-voltage devices to prevent high-voltage signals from interfering with adjacent low-voltage logic circuits, thereby achieving noise isolation under high integration.

[0078] In some embodiments, the deep trench isolation structure includes a deep trench 106a, and the depth of the deep trench 106a is greater than the depth of the first conductivity type buried layer 101 disposed in the semiconductor substrate. When the deep trench 106a penetrates the first conductivity type buried layer 101 in the depth direction, it can completely cut off the lateral parasitic current path, eliminate the latch-up risk between buried layers of different potentials, and provide complete dielectric isolation.

[0079] In some embodiments, the deep trench isolation structure includes a deep trench isolation oxide layer 106 formed on the inner wall of the deep trench 106a. The deep trench isolation oxide layer 106 serves as a liner oxide layer, and its quality directly affects the isolation and withstand voltage characteristics of the deep trench.

[0080] In some embodiments, the field oxide layer 107 and the deep trench isolation oxide layer 106 are formed through the same thermal oxidation process. This is a core innovation of this application. In conventional processes, LOCOS and DTI typically require separate thermal processes, leading to an increase in the overall thermal budget and making it prone to re-diffusion of impurities. This embodiment uses the long-duration, high-temperature thermal process required for the growth of the deep trench isolation oxide layer 106 simultaneously for the growth of the field oxide layer 107 (LOCOS) on the surface of the drift region. This not only saves process steps and costs, but more importantly, it significantly reduces the process thermal budget, enabling more precise control over the doping distribution in the bulk region, drift region, etc.

[0081] In some embodiments, the deep trench isolation structure further includes a deep trench isolation conductive layer 114 filled within the deep trench 106a. The material of the deep trench isolation conductive layer 114 may include undoped polycrystalline silicon, in-situ doped polycrystalline silicon, amorphous silicon, or metallic materials such as tungsten (W), aluminum (Al), and copper (Cu). Polycrystalline silicon is often used as a filler material to reduce stress because its coefficient of thermal expansion is similar to that of a silicon substrate.

[0082] In some embodiments, the gate dielectric layer 112 is made of silicon dioxide. Alternatively, the gate dielectric layer 112 may also be made of silicon oxynitride (SiON), silicon nitride (SiN), or a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), strontium titanate (SrTiO3), and combinations thereof. Using a high-k material increases the physical thickness while maintaining a low equivalent oxide thickness (EOT), thereby reducing gate leakage current.

[0083] In some embodiments, the gate conductive layer 113 is made of polycrystalline silicon. Besides polycrystalline silicon, the gate conductive layer 113 can also be made of metal, metal alloy, metal silicide, or a combination thereof. For example, materials may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi2), etc. Using a metal gate can reduce gate resistance and eliminate the polycrystalline silicon depletion effect.

[0084] To further verify the beneficial effects of the high-voltage, low-resistance LDMOS device provided in the embodiments of this application, the inventors compared and evaluated the LDMOS device with the LOCOS structure proposed in this application with the traditional LDMOS device with the STI structure (shallow trenches filled with silicon dioxide and having steep sidewalls) based on the TCAD simulation tool.

[0085] Please refer to Figure 9 , Figure 9 This paper presents a comparison curve of the drain current (Id) - gate voltage (Vg) characteristics of a LOCOS structure LDMOS device (green curve) according to an embodiment of this application and a conventional STI structure LDMOS device (red curve). Figure 9 It can be seen that, under the same gate voltage drive, the device in this embodiment can provide a larger drain current. Data from the on-resistance calculated using the Id-Vg curve shows that the specific on-resistance (Rsp) of a traditional STI structure LDMOS device is approximately 173.3 mΩ / mm², while the Rsp of the high-voltage, low-resistance LDMOS device proposed in this embodiment is reduced to approximately 163 mΩ / mm². This result indicates that by introducing a field oxide layer 107 (LOCOS) to replace the traditional STI structure, the electric field concentration at the STI trench corner is eliminated, allowing for an appropriate increase in the doping concentration of the drift region 109 during design. This successfully reduces the on-resistance by approximately 6% without sacrificing the breakdown voltage, significantly reducing the device's conduction losses.

[0086] Please refer to Figure 10 , Figure 10The graph shows a comparison of the breakdown voltage (BV) characteristics of the LOCOS structure LDMOS device (green curve) of this application embodiment and the conventional STI structure LDMOS device (red curve). The horizontal axis represents the drain voltage, and the vertical axis represents the drain current. As shown, the conventional STI structure LDMOS device experiences avalanche breakdown at approximately 149.3V, with a sharp increase in leakage current; while the device of this application embodiment only breaks down at approximately 152.7V. This indicates that the breakdown voltage (BV) of the device of this application embodiment is improved by approximately 2.3%. This improvement in breakdown voltage is mainly attributed to the gentle bird's beak-like morphology of the field oxide layer 107, which optimizes the electric field distribution on the surface of the drift region and avoids the premature breakdown problem caused by the sharp corners at the bottom of the conventional STI structure.

[0087] comprehensive Figure 9 and Figure 10 The data shows that the scheme of forming LOCOS structure synchronously through the DTI thermal process in this application embodiment effectively breaks the mutual constraint between breakdown voltage (BV) and on-resistance (Rsp) in traditional LDMOS devices without increasing the additional process thermal budget, thereby improving the overall performance of the device.

[0088] This application also provides a method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device. Figure 1 This is a schematic diagram of the manufacturing process. Figures 2 to 8 This is a schematic cross-sectional view of the device structure corresponding to each step of the manufacturing method.

[0089] The method includes the following steps:

[0090] Step 1: Provide a semiconductor substrate, form a second conductivity type epitaxial layer 102 on the semiconductor substrate, and form a deep first conductivity type well region 103 and a shallow trench isolation structure 104 in the second conductivity type epitaxial layer 102. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of the cross-sectional structure after completing step one.

[0091] In some embodiments, a first conductivity type buried layer 101 is also formed in the semiconductor substrate. The first conductivity type buried layer 101 can be formed by an ion implantation process, for example, implanting arsenic (As) or antimony (Sb) ions, followed by high-temperature annealing.

[0092] In some embodiments, the process of forming a second conductivity type epitaxial layer 102 and a deep first conductivity type well region 103 includes: growing a first second conductivity type epitaxial layer 102a on a semiconductor substrate ( Figure 2(Not separately marked, but part of 102). Epitaxial growth can be performed using reduced pressure chemical vapor deposition (LPCVD) or ultra-high vacuum chemical vapor deposition (UHV-CVD), using silane (SiH4), dichlorosilane (DCS), or trichlorosilane (TCS) as precursor gases to grow single-crystal silicon layers via vapor phase epitaxy.

[0093] In some embodiments, the process of forming the second conductivity type epitaxial layer 102 and the deep first conductivity type well region 103 further includes: performing ion implantation on the first second conductivity type epitaxial layer 102a to form the deep first conductivity type well region 103. By inserting an ion implantation step in the middle of epitaxial growth, the doping concentration and location of the buried layer can be precisely controlled. Due to the thin layer thickness, the pre-buried deep well can be achieved without extremely high energy implantation equipment.

[0094] In some embodiments, the process of forming the second conductivity type epitaxial layer 102 and the deep first conductivity type well region 103 further includes: continuing to grow a second second conductivity type epitaxial layer 102b on the first second conductivity type epitaxial layer 102a. Figure 2 (Not separately indicated, but together with 102a, it constitutes 102), consisting of a first second conductivity type epitaxial layer 102a and a second second conductivity type epitaxial layer 102b. This multi-segment epitaxial process allows for the construction of complex vertical doped profiles within the device. After epitaxy is completed, the shallow trench isolation structure 104 is fabricated, typically including: forming a pad oxide layer on the surface by thermal oxidation; depositing a silicon nitride mask layer; defining the active region by photolithography; forming trenches by dry etching of the silicon substrate; filling the trenches by high-density plasma (HDP) deposition of silicon dioxide; and removing excess silicon oxide and planarizing the surface by chemical mechanical polishing (CMP).

[0095] Step 2: Sequentially deposit barrier layer 105a and hard mask layer 105b on the surface where Step 1 was completed. Please refer to [reference needed]. Figure 3 , Figure 3 The structure after depositing a barrier layer and a hard mask layer, and after opening and etching in the deep trench isolation region, is shown. In some embodiments, the barrier layer 105a is made of silicon dioxide. This layer can be grown by a thermal oxidation process or deposited by a tetraethoxysilane (TEOS)-based CVD process to buffer the stress of the subsequent silicon nitride layer.

[0096] In some embodiments, the hard mask layer 105b is made of silicon nitride. The silicon nitride layer can be formed by reacting dichlorosilane and ammonia using an LPCVD process, or deposited using a PECVD process. Silicon nitride serves as an antioxidant mask for subsequent thermal oxidation processes and a hard mask for deep trench etching.

[0097] Step 3: Window and etch the barrier layer 105a and hard mask layer 105b in the deep trench isolation region, then etch the semiconductor substrate and the second conductivity type epitaxial layer 102 to form the deep trench 106a. Please refer to [link / reference needed]. Figure 3 The etching of the barrier layer 105a and the hard mask layer 105b can be performed using reactive ion etching (RIE) with fluorine-containing gases (such as CF4, CHF3). Subsequent silicon substrate etching to form the deep trench 106a typically employs deep reactive ion etching (DRIE) techniques, such as the Bosch process, which alternates between sulfur hexafluoride (SF6) plasma etching and octafluorocyclobutane (C4F8) polymer deposition passivation to form trenches with high aspect ratios and vertical sidewalls in the silicon substrate. In some embodiments, the depth of the deep trench 106a is greater than the depth of the first conductivity type buried layer 101 disposed in the semiconductor substrate.

[0098] Step 4: Etch away the barrier layer 105a and hard mask layer 105b in the localized silicon oxide region to expose the silicon surface. Please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the cross-sectional structure after etching to expose the localized oxide region of silicon. This step typically involves defining the LOCOS region using photolithography, removing the silicon nitride hard mask layer 105b using anisotropic dry etching, and removing the barrier layer 105a using wet etching (such as diluted hydrofluoric acid) or dry etching, thereby exposing the silicon surface that needs to be thermally oxidized.

[0099] Step 5: Perform a thermal oxidation process to form a deep trench isolation oxide layer 106 on the inner wall of the deep trench 106a. Simultaneously, using this thermal oxidation process, a field oxide layer 107 is grown at the location where the silicon surface is exposed in the localized silicon oxidation region. After this step, the hard mask layer and barrier layer are removed.

[0100] In some embodiments, the oxidation growth of the field oxide layer 107 is achieved via a thermal oxidation process of the deep trench isolation oxide layer 106. The thermal oxidation process is typically carried out in a high-temperature furnace tube, purged with oxygen or water vapor (H2O). Within the deep trench 106a, oxygen reacts with silicon to form the pad oxide layer 106; simultaneously, in the LOCOS window region, oxygen reacts with the exposed silicon surface to grow a thicker field oxide layer 107. In some embodiments, the field oxide layer 107 has beak-shaped ends. This is due to the lateral diffusion of the oxidant below the edge of the silicon nitride hard mask layer; this gradient beak morphology helps to mitigate electric field concentration. In some embodiments, the field oxide layer 107 is a localized oxidation of silicon (LOCOS) structure.

[0101] Step 6: Remove the remaining hard mask layer 105b and barrier layer 105a. Please refer to... Figure 5 , Figure 5This is a schematic diagram of the cross-sectional structure after removing the hard mask layer and the barrier layer. The hard mask layer 105b (silicon nitride) can be removed by wet stripping with a hot phosphoric acid solution, and the barrier layer 105a (silicon dioxide) can be removed by a dilute hydrofluoric acid solution. Figure 5 The structure after thermal oxidation and removal of the hard mask is shown, at which point the deep trench isolation oxide layer 106 and the field oxide layer 107 have been formed simultaneously.

[0102] Step 7: Perform ion implantation to form the drift region 109, the second conductivity type body region 110, and the first conductivity type well region 111. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of the cross-sectional structure after ion implantation to form each well region.

[0103] In some embodiments, a second conductive type buried layer 108 is also formed, corresponding to the position of the drift region 109 in the depth direction.

[0104] In some embodiments, the formation process of the drift region 109 and the second conductivity type buried layer 108 includes simultaneously implanting the drift region 109 and the second conductivity type buried layer 108 using a high-energy implantation process. For example, under the same photomask, by adjusting the implantation energy, impurity peaks are formed at different depths, thereby simultaneously constructing the shallow drift region 109 and the deep buried layer 108. The second conductivity type body region 110 is typically implanted with boron or boron difluoride, and the implantation angle needs to be precisely controlled to prevent channeling effects. These implantation steps determine the device's threshold voltage, breakdown voltage, and on-resistance.

[0105] Step 8: Form a gate dielectric layer 112 on the surface, deposit conductive material, and etch to form a gate conductive layer 113 and a deep trench isolation conductive layer 114 filling the deep trench. Please refer to... Figure 7 , Figure 7 A schematic diagram of the cross-sectional structure after the gate and deep trench filling are formed.

[0106] In some embodiments, the gate dielectric layer 112 is formed by a thermal oxidation process. This step can be performed in a dry oxygen atmosphere to obtain a high-quality interface. Alternatively, the gate dielectric layer 112 can also be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The material of the gate dielectric layer 112 can include silicon dioxide, silicon oxynitride (SiON), silicon nitride (SiN), or high-k dielectric materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), strontium titanate (SrTiO3), and combinations thereof. Using high-k materials can increase the physical thickness while maintaining a low equivalent oxide thickness (EOT), thereby reducing gate leakage current.

[0107] In some embodiments, the conductive material is polycrystalline silicon, the gate conductive layer 113 is gate polycrystalline silicon, and the deep trench isolation conductive layer 114 is deep trench isolation polycrystalline silicon. Polycrystalline silicon deposition is typically performed using a low-pressure chemical vapor deposition (LPCVD) process, and N-type or P-type impurities can be introduced through in-situ doping or subsequent ion implantation to reduce resistivity. Besides polycrystalline silicon, the conductive material can also be made of metals, metal alloys, metal silicides, or combinations thereof. For example, materials may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi2), etc. These metallic materials can be formed using processes such as physical vapor deposition (PVD) or metal-organic chemical vapor deposition (MOCVD). Subsequently, the gate pattern is defined and the filling at the top of the deep trench is etched back using photolithography and anisotropic dry etching (e.g., using Cl2 / HBr gas plasma). A portion of the gate conductive layer 113 is formed on the field oxide layer 107 as a field plate to optimize the surface electric field.

[0108] Step 9: Perform source / drain ion implantation to form the first conductivity type heavily doped region 115. Please refer to [link / reference needed]. Figure 8 , Figure 8 To complete all front-end processes and the cross-sectional structure diagram after source and drain implantation, this step can simultaneously form a first conductivity type heavily doped region 115 on the first conductivity type well region 111, body region 110, and drift region 109.

[0109] In some embodiments, implantation is further included to form a heavily doped region 116 of a second conductivity type, the heavily doped region 116 being located within a body region 110 of a second conductivity type. Source-drain implantation typically employs high-dose, low-energy implantation, followed by a rapid thermal annealing (RTA) process to activate impurities and repair lattice damage.

[0110] Finally, the device's electrodes are brought out using conventional back-end processing (BEOL). Specifically, an interlayer dielectric (ILD) is first deposited. The material of this interlayer dielectric can include silicon oxide, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), undoped silicon glass (USG), silicon fluoride glass (FSG), spin-coated glass (SOG), or low-k dielectric materials, such as carbon-doped silicon oxide or porous silicon oxide. The interlayer dielectric can be formed using plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), subatmospheric pressure chemical vapor deposition (SACVD), or spin-coating. After deposition, the surface of the dielectric layer is typically planarized using chemical mechanical planarization (CMP) or reflow processes.

[0111] Next, contact holes are formed in the interlayer dielectric layer using photolithography and anisotropic dry etching processes (e.g., using fluorocarbon gases), exposing the surfaces of the source, drain, and gate electrodes. Before filling the contact holes, one or more barrier / adhesion layers are typically deposited. Materials can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof, and the formation method can be physical vapor deposition (PVD) or atomic layer deposition (ALD). Subsequently, conductive plug material is filled into the contact holes. The material is typically tungsten (W), but can also be copper (Cu), aluminum (Al), cobalt (Co), or alloys thereof. The filling process often employs chemical vapor deposition (CVD) or electrochemical plating (ECP). After filling, excess metal on the surface is removed using a CMP process.

[0112] Finally, a metal interconnect layer is formed. The material for the metal interconnect layer can be selected from aluminum (Al), aluminum-copper alloy (AlCu), aluminum-silicon-copper alloy (AlSiCu), copper (Cu), gold (Au), or tungsten (W). For aluminum-based interconnects, sputtering is typically used to deposit the metal layer, followed by reactive ion etching (RIE) to form the circuit pattern. For copper-based interconnects, single-damascene or dual-damascene processes are used, including barrier layer deposition, copper seed layer deposition, copper electroplating, and CMP planarization. Through the above interconnect structure, the source region, drain region, and gate conductive layer 113 are led out to external pads, completing the final packaging connection of the device.

[0113] To further verify the beneficial effects of the high-voltage, low-resistance LDMOS device provided in the embodiments of this application, the inventors compared and evaluated the LDMOS device with the LOCOS structure proposed in this application with the traditional LDMOS device with the STI structure (shallow trenches filled with silicon dioxide and having steep sidewalls) based on the TCAD simulation tool.

[0114] Please refer to Figure 9 , Figure 9 This paper presents a comparison curve of the drain current (Id) - gate voltage (Vg) characteristics of a LOCOS structure LDMOS device (green curve) according to an embodiment of this application and a conventional STI structure LDMOS device (red curve). Figure 9It can be seen that, under the same gate voltage drive, the device in this embodiment can provide a larger drain current. Data from the on-resistance calculated using the Id-Vg curve shows that the specific on-resistance (Rsp) of a traditional STI structure LDMOS device is approximately 173.3 mΩ / mm², while the Rsp of the high-voltage, low-resistance LDMOS device proposed in this embodiment is reduced to approximately 163 mΩ / mm². This result indicates that by introducing a field oxide layer 107 (LOCOS) to replace the traditional STI structure, the electric field concentration at the STI trench corner is eliminated, allowing for an appropriate increase in the doping concentration of the drift region 109 during design. This successfully reduces the on-resistance by approximately 6% without sacrificing the breakdown voltage, significantly reducing the device's conduction losses.

[0115] Please refer to Figure 10 , Figure 10 The graph shows a comparison of the breakdown voltage (BV) characteristics of the LOCOS structure LDMOS device (green curve) of this application embodiment and the conventional STI structure LDMOS device (red curve). The horizontal axis represents the drain voltage, and the vertical axis represents the drain current. As shown, the conventional STI structure LDMOS device experiences avalanche breakdown at approximately 149.3V, with a sharp increase in leakage current; while the device of this application embodiment only breaks down at approximately 152.7V. This indicates that the breakdown voltage (BV) of the device of this application embodiment is improved by approximately 2.3%. This improvement in breakdown voltage is mainly attributed to the gentle bird's beak-like morphology of the field oxide layer 107, which optimizes the electric field distribution on the surface of the drift region and avoids the premature breakdown problem caused by the sharp corners at the bottom of the conventional STI structure.

[0116] comprehensive Figure 9 and Figure 10 The data shows that the scheme of forming LOCOS structure synchronously through the DTI thermal process in this application embodiment effectively breaks the mutual constraint between breakdown voltage (BV) and on-resistance (Rsp) in traditional LDMOS devices without increasing the additional process thermal budget, thereby improving the overall performance of the device.

[0117] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device, comprising: Semiconductor substrate having an epitaxial layer (102) of a second conductivity type. The drift region (109) and the second conductivity type body region (110) are located within the second conductivity type epitaxial layer (102); A gate structure, located on the surface of the semiconductor substrate, includes a gate dielectric layer (112) and a gate conductive layer (113). The first conductivity type heavily doped region (115) includes a source region located in the second conductivity type body region (110) and a drain region located in the drift region (109); The feature is that the surface of the drift region (109) is provided with a field oxide layer (107), and the field oxide layer (107) is located on one side of the gate structure.

2. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The device further includes a second conductivity type heavily doped region (116), which is disposed within the second conductivity type body region (110) as a body contact region.

3. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The field oxide layer (107) is a localized silicon oxide (LOCOS) structure.

4. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

5. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The gate conductive layer (113) covers the gate dielectric layer (112) and extends partially to cover the surface of the field oxide layer (107).

6. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: A first conductivity type buried layer (101) is further provided between the semiconductor substrate and the second conductivity type epitaxial layer (102).

7. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 6, characterized in that: The second conductivity type epitaxial layer (102) is further provided with a deep first conductivity type well region (103) and a first conductivity type well region (111); the deep first conductivity type well region (103) is located in the second conductivity type epitaxial layer (102), and the bottom of the deep first conductivity type well region (103) is in contact with the first conductivity type buried layer (101); the first conductivity type well region (111) is located above the deep first conductivity type well region (103); and the first conductivity type heavily doped region (115) is located in the first conductivity type well region (111).

8. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: A second conductive type buried layer (108) is also provided below the drift region (109).

9. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The surface of the semiconductor substrate is also provided with a shallow trench isolation structure (104).

10. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The semiconductor substrate also has a deep trench isolation structure.

11. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 10, characterized in that: The deep trench isolation structure includes a deep trench (106a), and the depth of the deep trench (106a) is greater than the depth of the first conductivity type buried layer (101) disposed in the semiconductor substrate.

12. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 10, characterized in that: The deep trench isolation structure includes a deep trench isolation oxide layer (106) formed on the inner wall of the deep trench (106a).

13. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 12, characterized in that: The field oxide layer (107) and the deep trench isolation oxide layer (106) are formed by the same thermal oxidation process.

14. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 10, characterized in that: The deep trench isolation structure also includes a deep trench isolation conductive layer (114) filled inside the deep trench (106a).

15. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The gate dielectric layer (112) is made of silicon dioxide.

16. The high-voltage, low-resistance lateral double-diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The material of the gate conductive layer (113) is polycrystalline silicon.

17. A method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device, characterized in that, include: Step 1: Provide a semiconductor substrate, form a second conductivity type epitaxial layer (102) on the semiconductor substrate, and form a deep first conductivity type well region (103) and a shallow trench isolation structure (104) in the second conductivity type epitaxial layer (102). Step 2: Sequentially deposit a barrier layer (105a) and a hard mask layer (105b) on the surface where Step 1 was completed. Step 3: Open windows and etch the barrier layer (105a) and the hard mask layer (105b) in the deep trench isolation region, and then etch the semiconductor substrate and the second conductivity type epitaxial layer (102) to form a deep trench (106a). Step 4: Etch away the barrier layer (105a) and the hard mask layer (105b) in the localized silicon oxide region to expose the silicon surface; Step 5: Perform a thermal oxidation process to form a deep trench isolation oxide layer (106) on the inner wall of the deep trench (106a), and simultaneously grow a field oxide layer (107) at the location where the silicon surface is exposed in the local oxidation area of ​​the silicon using the thermal oxidation process. Step 6: Remove the remaining hard mask layer (105b) and the barrier layer (105a). Step 7: Perform ion implantation to form a drift region (109), a second conductivity type body region (110), and a first conductivity type trap region (111). Step 8: Form a gate dielectric layer (112) on the surface, deposit conductive material, and etch to form a gate conductive layer (113) and a deep trench isolation conductive layer (114) filled in the deep trench. Step 9: Perform source / drain ion implantation to form a heavily doped region (115) of the first conductivity type.

18. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step one, a first conductivity type buried layer (101) is also formed in the semiconductor substrate.

19. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step one, the process of forming the second conductivity type epitaxial layer (102) and the deep first conductivity type well region (103) includes: growing a first second conductivity type epitaxial layer (102a) on the semiconductor substrate.

20. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 19, characterized in that: In step one, the process of forming the second conductivity type epitaxial layer (102) and the deep first conductivity type well region (103) further includes: performing ion implantation on the first second conductivity type epitaxial layer (102a) to form the deep first conductivity type well region (103).

21. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 20, characterized in that: In step one, the process of forming the second conductivity type epitaxial layer (102) and the deep first conductivity type well region (103) further includes: growing a second second conductivity type epitaxial layer (102b) on the first second conductivity type epitaxial layer (102a), wherein the first second conductivity type epitaxial layer (102a) and the second second conductivity type epitaxial layer (102b) together constitute the second conductivity type epitaxial layer (102).

22. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step two, the material of the barrier layer (105a) is silicon dioxide.

23. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step two, the material of the hard mask layer (105b) is silicon nitride.

24. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step three, the depth of the deep trench (106a) is greater than the depth of the first conductivity type buried layer (101) disposed in the semiconductor substrate.

25. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step five, the oxidative growth of the field oxide layer (107) is achieved by means of the thermal oxidation process of the deep trench isolation oxide layer (106).

26. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step five, the two ends of the field oxide layer (107) are shaped like bird beaks.

27. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step five, the field oxide layer (107) is a localized silicon oxide (LOCOS) structure.

28. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step seven, a second conductive type buried layer (108) is also formed, which corresponds to the position of the drift region (109) in the depth direction.

29. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 28, characterized in that: In step seven, the formation process of the drift region (109) and the second conductive type buried layer (108) includes: simultaneously injecting the drift region (109) and the second conductive type buried layer (108) using a high-energy injection process.

30. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step eight, the gate dielectric layer (112) is formed by a thermal oxidation process.

31. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: In step eight, the conductive material is polycrystalline silicon, the gate conductive layer (113) is gate polycrystalline silicon, and the deep trench isolation conductive layer (114) is deep trench isolation polycrystalline silicon.

32. The method for manufacturing a high-voltage, low-resistivity lateral double-diffused metal-oxide-semiconductor device according to claim 17, characterized in that: Step nine further includes implanting to form a second conductivity type heavily doped region (116), which is located within the second conductivity type body region (110).

Images