Thin film transistor and preparation method thereof, memory and memory reading method
By adjusting the contact area and overlap area of the thin-film transistors, the asymmetry of the transistors in the 2T0C memory cell was achieved, the crosstalk current problem was solved, the read margin and the number of memory cells were improved, and the read power consumption was reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUZHOU UNIV
- Filing Date
- 2026-01-08
- Publication Date
- 2026-05-19
AI Technical Summary
The lack of a gating control transistor in the existing 2T0C memory cell read transistors leads to crosstalk current interference during the read process, compressing the read margin of the memory and limiting the cell expansion capability of the memory array.
By adjusting the contact area and overlap area between the metal electrodes and the channel of the thin-film transistor, the contact resistance and threshold voltage are changed, making the transistor asymmetrical in different current directions. The electrode connection method of the second transistor is configured to suppress crosstalk current, and the read current is increased through a specific electrical connection method.
It significantly improves read margin during the read process, increases the number of array storage cells, and reduces power consumption during read operations.
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Figure CN122069759A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electrical components technology, and in particular to a thin-film transistor and its fabrication method, a memory and its read-out method. Background Technology
[0002] The revolutionary development of IoT, AI, and cloud computing technologies has driven a geometrical increase in data volume, posing a severe challenge to storage systems in terms of data storage and processing performance. Against the backdrop of high-density, high-performance storage demands, embedded DRAM (eDRAM), with its potential in high-density storage, is gradually challenging the technological dominance of SRAM. The exploration of eDRAM as a replacement for SRAM aims to develop two typical cell architectures: first, the traditional 1T1C structure based on one transistor and one capacitor (1T1C architecture); and second, a gain cell structure adapted to CMOS processes. However, the 1T1C architecture is limited by its complex capacitor manufacturing process and destructive read mechanisms, while the gain cell based on CMOS processes suffers from rapid data loss due to high leakage current.
[0003] Based on this, thin-film transistors (TFTs), due to their unique structure and electrical properties, have been widely used in display driving, flexible electronics, and 3D integration. Especially in the field of memory technology, TFTs have become a key component for constructing high-density, low-power memory cells. Vertical thin-film transistors, in particular, possess low leakage current characteristics and stackable manufacturing capabilities, which can extend memory data retention time, reduce memory power consumption, and increase memory density through 3D integration technology, thus demonstrating significant advantages in 2T0C (two transistors without capacitors) gain cell architectures.
[0004] However, although gain cell memory arrays based on the 2T0C architecture have advantages in terms of density and process integration, during the read process, the lack of gating control transistors can lead to crosstalk current interference in unselected rows or columns, which in turn reduces the read margin of the memory and directly limits the cell expansion capability of the memory array. Summary of the Invention
[0005] This invention provides a thin-film transistor and its fabrication method, a memory and a memory reading method, solving the problem of how to suppress crosstalk current during reading in a thin-film transistor of a 2TOC memory cell read transistor.
[0006] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a thin-film transistor is provided, comprising: An insulating substrate layer, a first metal layer, a passivation layer, and a second metal layer are sequentially stacked. The third electrode at least partially covers the second metal layer and extends through the second metal layer to the gate formed by the first metal layer; A channel layer is disposed on the surface of the side where the third electrode extension is located, and is in contact with the first metal layer, the passivation layer and the second metal layer; The first metal layer constitutes the first electrode of the thin-film transistor, and the second metal layer constitutes the second electrode of the thin-film transistor; Wherein, the contact area between the first metal layer and the channel layer is the first contact area; the contact area between the second metal layer and the channel layer is the second contact area; the area of the third electrode projected onto the cross-sectional direction of the first metal layer is the first overlapping area, and the area of the third electrode projected onto the cross-sectional direction of the second metal layer is the second overlapping area; by configuring the first contact area, the second contact area, the first overlapping area, and the second overlapping area, the thin-film transistor is made to have a configurable contact resistance and threshold voltage in a first current direction or a second current direction; the first current direction is current flowing from the first electrode to the second electrode, and the second current direction is current flowing from the second electrode to the first electrode.
[0007] In a second aspect, a method for fabricating a thin-film transistor is provided, comprising: supply Insulating substrate layer and cleaning; In the A first metal layer is formed on the insulating substrate layer; A passivation layer is formed on the first metal layer; A second metal layer is formed on the passivation layer; A hole structure penetrating the first metal layer is formed on the second metal layer; wherein the first depth of the hole structure in the first metal layer is different from the second depth in the second metal layer, such that the first contact area and the second contact area are not equal; A channel layer is deposited on the second metal layer in at least a portion of the inner wall of the hole structure and the opening of the hole structure; A gate dielectric layer is formed on the channel layer; a gate electrode layer is formed on the gate dielectric layer to form a gate electrode; wherein the extension of the gate electrode within the via structure is configured such that the first overlapping area and the second overlapping area are not equal.
[0008] Thirdly, a memory is provided, comprising: Storage array; the storage array includes multiple storage units; each storage unit includes: The first transistor is configured to write data, with its gate connected to the write word line and its first source / drain connected to the write bit line. The second transistor is configured to read data, and its gate is connected to the second source / drain of the first transistor to form a memory node. Its first electrode and second electrode are respectively connected to the read word line and the read bit line. Wherein, the second transistor is a thin-film transistor as described in the first aspect; the second transistor is configured such that: between its electrode connected to the read word line and the electrode connected to the read bit line, the threshold voltage in the direction opposite to the read current direction is greater than the threshold voltage in the read current direction; Data is stored in the form of charge on the third electrode of the second transistor, i.e., the storage node.
[0009] Fourthly, a method for reading from a memory is provided, wherein the memory is as described in the third aspect, comprising: Pre-charging is implemented by configuring the voltage of both the word line and the bit line to the first voltage. The voltage of the read word line connected to the selected memory cell is pulled down from the first voltage to the second voltage, while the voltage of the read word line connected to the unselected memory cell is kept at the first voltage, wherein the first voltage is higher than the second voltage; The stored data is read by sensing the voltage change of the read bit line connected to the selected storage cell using a read decision device. Wherein, the threshold voltage of the second transistor in the direction of the read current is lower than the threshold voltage in the direction opposite to the read current, so that the crosstalk current flowing through the second transistor in the unselected memory cell is suppressed.
[0010] The thin-film transistor and its fabrication method, and the memory and its read-out method of this application, (1) change the contact resistance by adjusting the contact area between the metal electrode and the channel of the vertical thin-film transistor and the overlap area between the metal electrode and the third electrode; or change the effective width of the contact barrier by adjusting the overlap area between the metal electrode and the third electrode, thereby adjusting the threshold voltage of the transistor. Furthermore, when the same level is applied to the third electrode, the turn-on threshold voltages in different current directions are not equal, that is, the output transfer characteristics I of the transistor current in different directions are different. DS -V DS It has asymmetry. (2) When the thin film transistor is used as the cell read transistor of the gain unit memory, a specific electrical connection configuration is proposed to connect it with the array read word line and read bit line. This can significantly increase the pull-down current during the reading process, suppress the array read crosstalk current, significantly improve the read margin of the read bit line, and thus improve the reading speed. At the same time, it can also increase the number of array memory cells, reduce the power supply voltage of the read array, and thus reduce the power consumption of the read operation. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of this application; Figure 2 This is a schematic diagram of the output characteristic curve of a vertical source-drain asymmetric thin-film transistor according to an embodiment of this application; Figure 3 This is a schematic diagram of the transfer characteristic curve of a vertical source-drain asymmetric thin-film transistor according to an embodiment of this application; Figure 4 This is a schematic flowchart of a method for fabricating a thin-film transistor according to an embodiment of this application; Figure 5 This is a schematic diagram of a storage unit of the memory provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the memory array provided in this application embodiment, showing the electrical connection between the read bit lines and the read decision unit. Figure 8 This is a schematic diagram of a storage array according to an embodiment of this application, in which the read bit lines are electrically connected to the switch network and the switch network is electrically connected to the read decision unit; Figure 9 This is a schematic flowchart of a memory reading method provided in an embodiment of this application; Figure 10 This application provides a schematic diagram of a gain unit storage array structure composed of 2T0C storage cells and a read operation. Figure 11 This is a schematic diagram illustrating the effect of the storage array provided in this application on suppressing crosstalk current; Figure 12 This is a schematic diagram illustrating the effect of the storage array provided in the embodiments of this application on increasing the number of array storage units.
[0012] Figure label: Thin-film transistor 10, insulating substrate layer 101, Si insulating substrate 1010, An insulating substrate 1011, a first metal layer 102, a passivation layer 103, a second metal layer 104, a channel layer 105, a third electrode 106, a gate dielectric layer 1060, a gate electrode layer 1061, an interlayer dielectric layer 107, a memory cell 20, a memory array 21, a first transistor 201, a second transistor 202, a write word line 203, a first write word line 2031, an m-th write word line 203m, a write bit line 204, a first write bit line 2041, an n-th write bit line 204n, a read word line 205, a first read word line 2051, an m-th read word line 205m, a read bit line 206, a first read bit line 2061, and an n-th read bit line 206n. Detailed Implementation
[0013] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.
[0014] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0015] The steps described in this application and the flowcharts in the accompanying drawings are not necessarily to be strictly followed according to the step numbers; the execution order of the steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.
[0016] The crosstalk current phenomenon during the reading process of 2T0C memory cells is fundamentally due to the fact that the source and drain currents of the thin-film transistors in the 2T0C memory cell read transistors are symmetrical. The contact resistance characteristics of the source and drain electrodes, the electrode configuration, and the correspondence between them and the direction of the read current flowing through the source and drain electrodes are not clear. Therefore, it is impossible to effectively suppress the crosstalk current during the reading of the memory array.
[0017] This specification provides a thin-film transistor and its fabrication method, a memory and a memory read-out method, which will be described in detail below with reference to the accompanying drawings and preferred embodiments.
[0018] Please see Figure 1 This application provides a thin-film transistor, comprising: It includes an insulating substrate layer 101, a first metal layer 102, a passivation layer 103, and a second metal layer 104 that are sequentially stacked. The third electrode 106 at least partially covers the second metal layer 104 and extends through the second metal layer 104 to the gate formed by the first metal layer 102. The channel layer 105 is disposed on the surface of the side where the extension of the third electrode 106 is located, and is in contact with the first metal layer 102, the passivation layer 103 and the second metal layer 104. The first metal layer 102 constitutes the first electrode of the thin-film transistor, and the second metal layer 104 constitutes the second electrode of the thin-film transistor. Wherein, the contact area between the first metal layer 102 and the channel layer 105 is the first contact area; the contact area between the second metal layer 104 and the channel layer 105 is the second contact area; the area of the third electrode 106 projected onto the cross-sectional direction of the first metal layer 102 is the first overlapping area, and the area of the third electrode 106 projected onto the cross-sectional direction of the second metal layer 104 is the second overlapping area; by configuring the first contact area, the second contact area, the first overlapping area, and the second overlapping area, the thin-film transistor is made to have a configurable contact resistance and threshold voltage in a first current direction or a second current direction; the first current direction is current flowing from the first electrode to the second electrode, and the second current direction is current flowing from the second electrode to the first electrode.
[0019] Furthermore, the contact resistance of the thin-film transistor can be changed by adjusting the first contact area, the second contact area, the first overlapping area, and the second overlapping area.
[0020] Specifically, the contact resistance formed between the first metal layer 102 and the channel layer 105 is the first contact resistance; the contact resistance formed between the second metal layer 104 and the channel layer 105 is the second contact resistance. The first contact resistance can be reduced by increasing the first contact area, thereby increasing the number of carrier injection paths and improving the carrier injection efficiency. Conversely, the first contact resistance can be increased by decreasing the first contact area. Similarly, the second contact resistance can be reduced by increasing the second contact area, or increased by decreasing the second contact area.
[0021] Turn-on current refers to the conduction current between the first electrode and the second electrode when the transistor is turned on.
[0022] When the turn-on current of the thin-film transistor is in the first current direction, increasing the first overlapping area increases the channel range formed by the first electrode, providing an additional current path and thus reducing the first contact resistance; decreasing the second overlapping area increases the injection barrier at the second electrode, weakening carrier injection and thus increasing the second contact resistance. When the turn-on current of the thin-film transistor is in the second current direction, decreasing the first overlapping area increases the injection barrier at the first electrode, weakening carrier injection and thus increasing the first contact resistance; increasing the second overlapping area increases the channel range formed by the second electrode, providing an additional current path and thus reducing the second contact resistance.
[0023] Furthermore, by adjusting the first overlapping area and the second overlapping area, the effective width of the contact barrier of the thin-film transistor is changed, thereby regulating the threshold voltage of the thin-film transistor.
[0024] Specifically, the contact barrier between the first metal layer 102 and the channel layer 105 is a first contact barrier; the contact barrier between the second metal layer 104 and the channel layer 105 is a second contact barrier.
[0025] When the turn-on current of the thin-film transistor is in the first current direction, the turn-on threshold voltage of the transistor along the first current direction can be reduced by making the effective width of the second contact barrier lower than the effective width of the first contact barrier; conversely, the turn-on threshold voltage of the thin-film transistor along the first current direction can be increased.
[0026] The effective width of the first contact barrier can be increased by reducing the first overlapping area; the effective width of the second contact barrier can be decreased by increasing the second overlapping area.
[0027] When the turn-on current of the thin-film transistor is in the second current direction, the turn-on threshold voltage of the transistor along the second current direction is reduced by making the effective width of the second contact barrier higher than the effective width of the first contact barrier; conversely, the turn-on threshold voltage of the thin-film transistor along the second current direction is increased by making the effective width of the second contact barrier lower than the effective width of the first contact barrier.
[0028] The effective width of the first contact barrier can be reduced by increasing the first overlapping area; or the effective width of the second contact barrier can be increased by reducing the second overlapping area.
[0029] In some possible implementations, the first contact area is configured to be larger than the second contact area, and the first overlapping area is larger than the second overlapping area, such that the first contact resistance between the first metal layer 102 and the channel layer 105 is smaller than the second contact resistance between the second metal layer 104 and the channel layer 105; and the threshold voltage in the first current direction is larger than the threshold voltage in the second current direction.
[0030] In some possible implementations, the first contact area is configured to be smaller than the second contact area, and the first overlap area is smaller than the second overlap area, such that the second contact resistance between the second electrode and the channel layer is smaller than the first contact resistance between the first electrode and the channel layer; and the threshold voltage in the second current direction is greater than the threshold voltage in the first current direction.
[0031] For example, Figure 2 The output response curve of the thin-film transistor 10 is shown. When the same voltage level is applied to the third electrode 106, the thin-film transistor has different threshold voltages for different current directions. Taking an n-type device as an example, if the current is in the second current direction, the effective width of the second contact barrier of the transistor can be made larger than the effective width of the first contact barrier by adjusting the first and second overlapping areas. This results in a smaller threshold voltage in the second current direction and a larger threshold voltage in the first current direction. Similarly, if the current is in the first current direction, the effective width of the second contact barrier of the transistor can be made smaller than the effective width of the first contact barrier by adjusting the first and second overlapping areas. This results in a smaller threshold voltage in the first current direction and a larger threshold voltage in the second current direction. hour, The output response is negative. hour, The output response is biased towards positive; it should be understood that this trend should be completely reversed in p-type devices.
[0032] Figure 3 The transfer characteristic curves of the thin-film transistor 10 are shown. For example... Figure 3 As shown, when voltages of equal magnitude but different directions are applied between the first and second electrodes of the transistor... When ), the The transfer characteristics and responses are different.
[0033] Compared to traditional vertical thin-film transistors, where the source and drain electrodes have equal contact areas with the channel and equal overlap areas with the third electrode, the thin-film transistor 10 in this embodiment is a vertical source-drain asymmetric thin-film transistor structure. The contact resistance can be changed by adjusting the contact area between the metal electrode and the channel and the overlap area between the metal electrode and the third electrode. The effective width of the contact barrier can also be changed by adjusting the overlap area between the metal electrode and the third electrode, thereby controlling the threshold voltage of the transistor.
[0034] Furthermore, when the same voltage level is applied to the third electrode, the turn-on threshold voltage is not equal in different current directions, i.e., the output characteristics of the transistor in different current directions. It has asymmetry and transfer properties. Furthermore, they are different. Therefore, by using thin-film transistors as read transistors in the gain unit, the read current can be significantly increased during the read process, while suppressing crosstalk current, achieving a larger read margin, increasing the number of array memory cells, and reducing read operation power consumption.
[0035] In some possible implementations, the thin-film transistor has the characteristic of being three-dimensionally stackable in multiple layers. Furthermore, the thin-film transistor has the characteristic of being compatible with low-temperature back-end processes.
[0036] In some possible implementations, the channel layer 105 is an amorphous oxide semiconductor material.
[0037] In some possible embodiments, the insulating substrate layer 101 includes a Si insulating substrate 1010 and a SiO2 insulating substrate 1011; the first metal layer 102 is located at the bottom; the second metal layer 104 is located between the channel layer 105 and the passivation layer 103; the passivation layer 103 is disposed between the first metal layer 102 and the second metal layer 104 to separate the first metal layer 102 and the second metal layer 104; the channel layer 105 is electrically contacted with the first metal layer 102 and the second metal layer 104 respectively; the third electrode 106 includes a gate dielectric layer 1060 and a gate electrode layer 1061.
[0038] Please see Figure 4 Corresponding to the above-described thin-film transistor embodiments, this application provides a method for fabricating the thin-film transistor, comprising: Step S401: Provide Insulating substrate layer and cleaning.
[0039] Specifically, The insulating substrate layer includes a Si insulating substrate 1010 and Insulating substrate 1011.
[0040] Step S402: In the A first metal layer is formed on the insulating substrate layer.
[0041] In specific operation, as described The lift-off region is defined on the insulating substrate using electron beam lithography, and the first metal layer is deposited using physical vapor deposition.
[0042] Step S403: Form a passivation layer on the first metal layer.
[0043] In specific operation, a physical vapor deposition passivation layer 103 is applied based on step S402.
[0044] Step S404: Form a second metal layer on the passivation layer.
[0045] In specific operation, the stripping region is defined by electron beam lithography based on step S403, and the second metal layer 104 is deposited by physical vapor deposition.
[0046] Step S405: Form a hole structure penetrating to the first metal layer on the second metal layer; wherein the first depth of the hole structure in the first metal layer is different from the second depth in the second metal layer, such that the first contact area and the second contact area are not equal.
[0047] In specific operation, based on step S404, the etching area is defined by electron beam lithography, and holes of different depths are etched by dry etching.
[0048] Step S406: Deposit a channel layer on the second metal layer in at least a portion of the inner wall of the hole structure and the opening of the hole structure.
[0049] In specific operation, the photomask resist is removed based on step S405, and the channel layer 105 is deposited on the surface and sidewalls of the hole by atomic layer deposition.
[0050] Step S407: A gate dielectric layer is formed on the channel layer; a gate electrode layer is formed on the gate dielectric layer to form a gate; wherein the extension portion of the gate within the via structure is configured such that the first overlapping area and the second overlapping area are not equal.
[0051] In specific operation, based on step S406, the photoresist is spin-coated and the etching area is defined by electron beam lithography. Wet etching is used for device isolation. Then the photoresist mask is removed. Atomic layer deposition is used to deposit the gate dielectric layer 1060 in the designated area on the inner wall and opening of the hole. Atomic layer deposition is used to deposit the gate electrode layer 1061 on the surface and sidewall of the hole. Wet etching is used for device isolation. Then the photoresist mask is removed.
[0052] By controlling different etching times, the first metal layer is etched to different depths to form a hole structure, thereby regulating the first contact area, the second contact area, the first overlapping area, and the second overlapping area, which in turn affects the contact resistance and the contact barrier.
[0053] The above-described method for fabricating thin-film transistors achieves the same technical effects as the above-described thin-film transistor embodiments, and will not be repeated here to avoid repetition.
[0054] See Figure 10 For a gain unit memory array composed of 2T0C memory cells, Figure 10 This diagram illustrates a gain-cell memory array structure composed of 2T0C memory cells and its read operation. As shown, reading occurs row by row. Since the 2T0C memory cell structure lacks transistors that function like switches, crosstalk current will exist on unselected rows connected to the same read bit line during reading. Existing gain-cell memory arrays composed of 2T0C memory cells cannot suppress this crosstalk current, resulting in reduced read margin and limited array size. For example, when reading the first row of data, the first row read word line 2051 is pulled down from VDD to GND, while other row read word lines remain at VDD. If the data stored in the memory cell is "1", meaning the voltage at the third electrode of the read transistor is high, the read transistor is in a conducting state, and a current flows through it. This current is referred to as the read current (Iread). Due to the read current, the read bit line 206n of this column will be discharged. Since the other unselected cells in the same column do not have switches controlling their on / off states, if the data stored in an unselected cell in the same column is also "1", a current opposite to the read current will flow through the read transistor of the unselected cell; this current is the crosstalk current (Ict). The effective read current is the difference between the read current and all crosstalk currents in the same column. The more "1"s stored in the same column, the larger the crosstalk current, and the smaller the effective read current, resulting in a reduced read margin. Furthermore, the same column cannot accommodate too many memory cells, directly limiting the array size.
[0055] To address the issue that crosstalk current limits read margin and array size when existing thin-film transistors are applied to gain-cell memories composed of 2T0C memory cells, this application provides a memory, corresponding to the aforementioned thin-film transistor embodiments, comprising: Storage array 21; the storage array includes a plurality of storage cells 20; each storage cell 20 includes: The first transistor 201 is configured to write data, with its gate connected to the write word line and its first source / drain connected to the write bit line. The second transistor 202 is configured to read data, its gate is connected to the second source / drain of the first transistor to form a memory node, and its first electrode and second electrode are respectively connected to the read word line and the read bit line; Wherein, the second transistor 202 is the aforementioned thin-film transistor 10; the second transistor 202 is configured such that the threshold voltage in the direction opposite to the read current direction between its electrode connected to the read word line and the electrode connected to the read bit line is greater than the threshold voltage in the read current direction. Data is stored in the form of charge on the third electrode of the second transistor, that is, the storage node (SN).
[0056] Specifically, Figure 5 Several possible 2T0C memory cells are shown. For example... Figure 5 As shown, the memory cell 20 includes a first transistor 201, a second transistor 202, a write word line 203, a write bit line 204, a read word line 205, and a read bit line 206. The first transistor 201 can be a thin-film transistor 10 or a conventional source-drain symmetrical thin-film transistor, and the second transistor 202 uses the thin-film transistor 10 described in the above embodiment. Taking the first transistor 201 as an example where it also uses a thin-film transistor 10, the third electrode of the first transistor 201 is electrically connected to the write word line 203; the first electrode of the first transistor 201 is electrically connected to the write bit line 204, and the second electrode is electrically connected to the third electrode of the second transistor 202.
[0057] Furthermore, the second transistor 202 is specifically configured as follows: Its first electrode is connected to the read character line, and its second electrode is connected to the read bit line; the first contact resistance is less than the second contact resistance, and the threshold voltage in the first current direction is greater than the threshold voltage in the second current direction; or: Its first electrode is connected to the read bit line, and its second electrode is connected to the read word line; the second contact resistance is less than the first contact resistance; the threshold voltage in the second current direction is greater than the threshold voltage in the first current direction.
[0058] In other words, (Configuration 1) allows the first contact resistance of the second transistor 202 to be less than the second contact resistance, and the threshold voltage in the first current direction to be greater than the threshold voltage in the second current direction; the first electrode of the second transistor 202 is electrically connected to the read word line, and the second electrode is electrically connected to the read bit line, i.e., the first metal layer of the second transistor 202 is electrically connected to the read word line, and the second metal layer is electrically connected to the read bit line. (Configuration 2) allows the second contact resistance of the second transistor 202 to be less than the first contact resistance, and the threshold voltage in the second current direction to be greater than the threshold voltage in the first current direction; the first electrode of the second transistor is electrically connected to the read bit line, and the second electrode is electrically connected to the read word line.
[0059] Furthermore, the second transistors in all the memory cells connected to the same read bit line or read word line have the same electrode connection configuration.
[0060] In some possible implementations, the switching of the first transistor is controlled via the write line.
[0061] It should be noted that in a single read operation, only one of the second transistors electrically connected to the same read bit line is selected to perform the read operation. That is, in a column of second transistors, only one cell is read at a time, and the current direction of the second transistor of the cell being read is opposite to the current direction of the other unread cells' second transistors.
[0062] The metal layers of the second transistors electrically connected to the same read bit line or read word line in the memory array 21 are the same metal layer. The second transistors of the memory cells in the memory array are configured in the same way, that is, all are configured as one, or all are configured as two.
[0063] For example, the storage array 21 consists of a first preset number of storage cells arranged sequentially along a first direction, a second preset number of storage cells arranged sequentially along a second direction, a first preset number of write bit lines and a first preset number of read bit lines along the first direction, and a second preset number of write word lines and a second preset number of read word lines along the second direction.
[0064] The read bit lines of the storage array are electrically connected to the read decision unit, or the read bit lines are electrically connected to the switch network and the switch network is electrically connected to the read decision unit. For example... Figure 7 This is a schematic diagram of an array where the read bit lines of the storage array are electrically connected to the read decision unit. Figure 8 This is a schematic diagram of a storage array where the read bit lines are electrically connected to the switch network and the switch network is electrically connected to the read decision unit.
[0065] In some possible implementations, when the read bit line is connected to the read circuit, the resistivity of the material used for the read bit line is greater than the resistivity of the material used for the read word line; when the read word line is connected to the read circuit, the resistivity of the material used for the read word line is greater than the resistivity of the material used for the read bit line.
[0066] Regarding the material requirements for word lines in a memory array, in the read word lines and read bit lines electrically connected by the two metal layers of the read transistor, the resistivity of the material used for the metal line connected to the read circuit is greater than the resistivity of the material used for the other metal line. That is, when a read bit line is connected to the read circuit, the resistivity of the material used for the read bit line is greater than that of the material used for the read word line; conversely, when a read word line is connected to the read circuit, the resistivity of the material used for the read word line is greater than that of the material used for the read bit line. This is because, during the read process, the parasitic resistance of the metal line connected to the read circuit has a relatively small impact on read performance.
[0067] Figure 6A schematic diagram of a possible actual structure of a memory cell 20 is shown. The actual structure of this memory cell includes two vertical thin-film transistors and an interlayer dielectric layer 107. A second transistor 202 is stacked with a first transistor 201, with the second transistor 202 located below the first transistor 201. The interlayer dielectric layer 107 fills the space between the second transistor 202 and the first transistor 201, separating them. The third electrode 106b of the second transistor 202 is electrically connected to the first metal layer 102a of the first transistor 201 through the interlayer dielectric layer 107. The read word line is electrically connected to the first metal layer 102b of the first transistor 201, and the read bit line is electrically connected to the second metal layer 104b of the second transistor 202. 103a is the passivation layer of the first transistor 201, 103b is the passivation layer of the second transistor 202; 104a is the second metal layer of the first transistor 201; and 106a is the third electrode of the first transistor 201.
[0068] Furthermore, such as Figure 10 As shown, the storage array 21 consists of n storage cells 20 arranged sequentially along the x-direction and m storage cells 20 arranged sequentially along the y-direction, for a total of n*m storage cells 20, as well as n write bit lines (2041-204n) and n read bit lines (2061-206n) along the x-direction, and m write word lines (2031-203m) and m read word lines (2051-205m) along the y-direction. The values of n and m can be the same or different; this embodiment does not impose any limitation on this.
[0069] It should be understood that the direction of the transistor's turn-on current determines how the contact area between the metal electrode of the second transistor and the channel, as well as the overlap area with the gate, are controlled. When the first electrode of the second transistor is electrically connected to the read word line and the second electrode is electrically connected to the read bit line, the first contact area, the second contact area, the first overlap area, and the second overlap area are adjusted to make the first contact resistance less than the second contact resistance, and the threshold voltage in the first current direction greater than the threshold voltage in the second current direction. When the first electrode of the second transistor is electrically connected to the read bit line and the second electrode is electrically connected to the read word line, the first contact area, the second contact area, the first overlap area, and the second overlap area are adjusted to make the second contact resistance less than the first contact resistance, and the threshold voltage in the second current direction greater than the threshold voltage in the first current direction. This configuration can fully utilize the suppression effect of the thin-film transistor 10 proposed in this application on crosstalk current during the read process.
[0070] It should be noted that the memory described in this application is effective for the read word line pull-down read scheme.
[0071] See Figure 9Corresponding to the above-described memory embodiments, this application provides a memory reading method, including: Step S901: Perform pre-charging, that is, configure the voltage of both the word line and the bit line to the first voltage.
[0072] Step S902: Pull down the voltage of the read word line connected to the selected memory cell from the first voltage to the second voltage, while keeping the voltage of the read word line connected to the unselected memory cell at the first voltage, wherein the first voltage is higher than the second voltage.
[0073] This step is the word line activation phase, where only one of the memory cells electrically connected to the same read bit line is selected to perform a read operation. The read word line electrically connected to the selected memory cell is configured with a second voltage, causing its second transistor to conduct; after conduction, an on-state current is formed between the first and second electrodes in the second transistor; the voltage of the unselected read word lines remains at the first voltage.
[0074] Step S903: Read the stored data by sensing the voltage change of the read bit line connected to the selected memory cell through the read decision device; Wherein, the threshold voltage of the second transistor in the direction of the read current is lower than the threshold voltage in the direction opposite to the read current, so that the crosstalk current flowing through the second transistor in the unselected memory cell is suppressed.
[0075] Furthermore, when the selected memory cell stores the first stored data, the second transistor in the on state generates a large read current, causing the read bit line voltage to be significantly lower than the first voltage, that is, generating a large read bit line voltage swing; when the selected memory cell stores the second stored data, the second transistor in the on state generates a small read current, resulting in a smaller read bit line voltage swing. The read decision unit is activated to sense the voltage swing of the read bit line; When the voltage swing of the read bit line is sensed to be greater than the first difference voltage, it is determined to be the first stored data; when the voltage swing of the read bit line is sensed to be less than the first difference voltage, it is determined to be the second stored data. The first voltage difference is less than the first voltage and greater than the second voltage.
[0076] Furthermore, the charge corresponding to the first stored data is greater than the charge corresponding to the second stored data. Specifically, the first stored data is a logic value of 1, and the second stored data is a logic value of 0.
[0077] Exemplary land, based on Figure 10 The read and write operations of a storage array consisting of 2T0C storage cells are explained.
[0078] For write operations: First, it should be noted that since the same row of memory cells 20 shares the same write word line 203 and the same column of memory cells 20 shares the same write bit line 204, data is written row by row. When no write operation is performed, the write word line 203 is at a voltage that turns off the first transistor, and the initial voltage of the write bit line 204 can be GND or VDD. During a write operation, firstly, according to the different data to be stored in different memory cells 20 in the same row, all write bit lines 2041-204n are set to different voltages; then, the write word line 203 of the data writing row is operated to turn on the first transistor 201 of all memory cells 20 in that row, so that different data are written to the memory nodes of different memory cells 20 in the same row simultaneously; finally, the write word line 203 of the data writing row is operated to turn off the first transistor 201 of all memory cells 20 in that row, and all write bit lines 2041-204n are restored to their initial voltages, and the data is stored in the memory node.
[0079] For read operations: First of all, it should be noted that since the same row storage cell 20 of the array shares the same read word line 205 and the same column storage cell 20 shares the same read bit line 206, data is read in units of rows or columns; when no read operation is performed, the read bit line 205 and the read word line 206 are at the same initial voltage VDD.
[0080] The following description is based on reading operations row by row. During a read operation, the read word line 205 of the data read row is first changed from the initial voltage VDD to the opposite voltage GND. The remaining read word lines of the storage array 21 maintain their initial voltages. All read bit lines 2061-206n of the storage array 21 are disconnected from the electrical connection maintaining the initial voltage VDD. If the data stored in the read memory cell 20 is sufficient to turn on the second transistor 202, a read current is generated. This read current flows from the read bit line 206 of the column containing the memory cell to the read word line 205 of the data read row. The read current discharges 206, causing the voltage of read line 206 to drop. As the voltage of read line 206 drops, if the data stored in a memory cell 20 that is not being read in the same column can also turn on the second transistor 202, crosstalk current will be generated. The current flows from the read word line 205 of the memory cell to the read line 206 of the column where the memory cell is located, so that the read line 206 of the column where the memory cell is located is charged by the crosstalk current. Finally, the data can be read based on the final voltage of the read line, or it can be read based on the effective read current obtained by subtracting the sum of the crosstalk currents in the column from the read current.
[0081] As can be seen from the read operation of storage array 21, the direction of crosstalk current is opposite to the direction of read current. The effect of crosstalk current on read operation is as follows: when reading data through the final voltage of read bit line 206, crosstalk current will affect the swing of read bit line voltage; when using current reading, crosstalk current will reduce the effective read current, both of which will ultimately affect read margin. Moreover, the larger the storage array 21 is (i.e., the more storage cells 20 there are), the larger the crosstalk current will be, thus the crosstalk current will also affect the array size.
[0082] During a read operation, if data is read based on the voltage of read line 206, different stored data will cause different voltage swings on read line 206, resulting in different final voltages. The difference between the maximum and minimum final voltages of read line 206 is the read margin. Suppressing crosstalk current allows for a larger voltage swing on read line 206, thus widening the difference between the maximum and minimum final voltages and improving the read margin. If data is read based on the effective read current, different stored data will have different read currents. The effective read current is the difference between the read current and all crosstalk currents caused by other non-read cells in the same row or column. The difference between the maximum and minimum effective read currents caused by different stored data is the read margin. Suppressing crosstalk current also widens the difference between the maximum and minimum effective read currents, thereby improving the read margin. Furthermore, suppressing crosstalk current allows for a further reduction in the VDD of the memory array. Therefore, using the thin-film transistors proposed in this application in the read transistors of the memory array can also directly reduce the power consumption of the read operation.
[0083] Since the thin-film transistor 10 has different output response and transfer characteristics depending on the direction of its turn-on current, and the direction of the crosstalk current is opposite to the direction of the read current, in the array design, it is only necessary to ensure that the direction of the turn-on current of the thin-film transistor 10 is in the direction of the smaller turn-on threshold voltage. Since the crosstalk current is in the opposite direction, that is, the direction of the turn-on current is in the direction of the larger turn-on threshold voltage, this design can achieve the effect of suppressing the crosstalk current.
[0084] Figure 11 The effect of thin-film transistor-based memory arrays on suppressing crosstalk current is shown. For example... Figure 11 As shown, the different transfer characteristics of the source and drain terminals with different current directions can be considered as having different equivalent thresholds for different current directions at the source and drain terminals. Figure 11 The equivalent threshold difference at the source and drain terminals in different current directions is visible. The larger the value, the smaller the crosstalk current on the array, and the crosstalk current is suppressed.
[0085] Figure 12This demonstrates the effect of thin-film transistor-based memory arrays on increasing the number of memory cells in the array. The array size is defined as the number of memory cells contained in the array. A certain read margin is necessary to ensure correct data retrieval. The larger the array, the greater the crosstalk current, and the smaller the read margin, making it difficult to guarantee correct data retrieval. Therefore, as... Figure 12 As shown, the suppression of crosstalk current allows for a further increase in array size.
[0086] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be used in other examples. It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.
Claims
1. A thin-film transistor, characterized in that, include: An insulating substrate layer, a first metal layer, a passivation layer, and a second metal layer are sequentially stacked. The third electrode at least partially covers the second metal layer and extends through the second metal layer to the gate formed by the first metal layer; A channel layer is disposed on the surface of the side where the third electrode extension is located, and is in contact with the first metal layer, the passivation layer and the second metal layer; The first metal layer constitutes the first electrode of the thin-film transistor, and the second metal layer constitutes the second electrode of the thin-film transistor; Wherein, the contact area between the first metal layer and the channel layer is the first contact area; the contact area between the second metal layer and the channel layer is the second contact area; the area of the third electrode projected onto the cross-sectional direction of the first metal layer is the first overlapping area, and the area of the third electrode projected onto the cross-sectional direction of the second metal layer is the second overlapping area; by configuring the first contact area, the second contact area, the first overlapping area, and the second overlapping area, the thin-film transistor is made to have a configurable contact resistance and threshold voltage in a first current direction or a second current direction; the first current direction is current flowing from the first electrode to the second electrode, and the second current direction is current flowing from the second electrode to the first electrode.
2. The thin-film transistor according to claim 1, characterized in that, The contact resistance is changed by adjusting the first contact area, the second contact area, the first overlapping area, and the second overlapping area.
3. The thin-film transistor according to claim 2, characterized in that, The contact resistance formed between the first metal layer and the channel layer is the first contact resistance; the contact resistance formed between the second metal layer and the channel layer is the second contact resistance. The first contact resistance is reduced by increasing the first contact area; or the first contact resistance is increased by decreasing the first contact area; or the second contact resistance is reduced by increasing the second contact area; or the second contact resistance is increased by decreasing the second contact area. Turn-on current refers to the conduction current between the first electrode and the second electrode when the transistor is turned on; When the turn-on current of the thin-film transistor is in the first current direction, the first contact resistance is reduced by increasing the first overlapping area; or the second contact resistance is increased by decreasing the second overlapping area. When the turn-on current of the thin-film transistor is in the second current direction, the first contact resistance is increased by reducing the first overlapping area; or the second contact resistance is decreased by increasing the second overlapping area.
4. The thin-film transistor according to claim 1, characterized in that, By adjusting the first and second overlapping areas, the effective width of the contact barrier of the thin-film transistor is changed, thereby regulating the threshold voltage of the thin-film transistor.
5. The thin-film transistor according to claim 4, characterized in that, The contact barrier between the first metal layer and the channel layer is a first contact barrier; the contact barrier between the second metal layer and the channel layer is a second contact barrier. When the turn-on current of the thin-film transistor is in the first current direction, the turn-on threshold voltage of the transistor along the first current direction is reduced by making the effective width of the second contact barrier lower than the effective width of the first contact barrier, or the turn-on threshold voltage of the thin-film transistor along the first current direction is increased by making the effective width of the second contact barrier higher than the effective width of the first contact barrier. The effective width of the first contact barrier is increased by reducing the first overlapping area; or the effective width of the second contact barrier is decreased by increasing the second overlapping area. When the turn-on current of the thin-film transistor is in the second current direction, the turn-on threshold voltage of the transistor along the second current direction is reduced by making the effective width of the second contact barrier higher than the effective width of the first contact barrier, or the turn-on threshold voltage of the thin-film transistor along the second current direction is increased by making the effective width of the second contact barrier lower than the effective width of the first contact barrier. The effective width of the first contact barrier is reduced by increasing the first overlapping area; or the effective width of the second contact barrier is increased by reducing the second overlapping area.
6. A method for fabricating a thin-film transistor, characterized in that, Fabricating a thin-film transistor as described in any one of claims 1-5, comprising: supply Insulating substrate layer and cleaning; In the A first metal layer is formed on the insulating substrate layer; A passivation layer is formed on the first metal layer; A second metal layer is formed on the passivation layer; A hole structure penetrating the first metal layer is formed on the second metal layer; wherein the first depth of the hole structure in the first metal layer is different from the second depth in the second metal layer, such that the first contact area and the second contact area are not equal; A channel layer is deposited on the second metal layer in at least a portion of the inner wall of the hole structure and the opening of the hole structure; A gate dielectric layer is formed on the channel layer; a gate electrode layer is formed on the gate dielectric layer to form a gate electrode; wherein the extension of the gate electrode within the via structure is configured such that the first overlapping area and the second overlapping area are not equal.
7. A memory, characterized in that, include: Storage array; The storage array includes multiple storage units; Each of the storage units includes: The first transistor is configured to write data, with its gate connected to the write word line and its first source / drain connected to the write bit line. The second transistor is configured to read data, and its gate is connected to the second source / drain of the first transistor to form a memory node. Its first electrode and second electrode are respectively connected to the read word line and the read bit line. Wherein, the second transistor is a thin-film transistor as described in any one of claims 1-5; the second transistor is configured such that: between its electrode connected to the read word line and the electrode connected to the read bit line, the threshold voltage in the direction opposite to the read current direction is greater than the threshold voltage in the read current direction; Data is stored in the form of charge on the third electrode of the second transistor, i.e., the storage node.
8. The memory according to claim 7, characterized in that, The second transistor is specifically configured as follows: Its first electrode is connected to the read character line, and its second electrode is connected to the read bit line; the first contact resistance is less than the second contact resistance, and the threshold voltage in the first current direction is greater than the threshold voltage in the second current direction; Alternatively: its first electrode is connected to the read bit line, and its second electrode is connected to the read word line; The second contact resistance is less than the first contact resistance; The threshold voltage in the second current direction is greater than the threshold voltage in the first current direction.
9. The memory according to claim 7, characterized in that, The second transistors in all the memory cells connected to the same read bit line or read word line have the same electrode connection configuration.
10. A method for reading a memory, characterized in that, The memory is the memory as described in any one of claims 7-9. include: Pre-charging is implemented by configuring the voltage of both the word line and the bit line to the first voltage. The voltage of the read word line connected to the selected memory cell is pulled down from the first voltage to the second voltage, while the voltage of the read word line connected to the unselected memory cell is kept at the first voltage, wherein the first voltage is higher than the second voltage; The stored data is read by sensing the voltage change of the read bit line connected to the selected storage cell using a read decision device. Wherein, the threshold voltage of the second transistor in the direction of the read current is lower than the threshold voltage in the direction opposite to the read current, so that the crosstalk current flowing through the second transistor in the unselected memory cell is suppressed.
11. The method for reading a memory according to claim 10, characterized in that, When the selected memory cell stores the first stored data, the second transistor in the on state generates a large read current, causing the read bit line voltage to be significantly lower than the first voltage, that is, generating a large read bit line voltage swing; when the selected memory cell stores the second stored data, the second transistor in the on state generates a small read current, resulting in a smaller read bit line voltage swing. The read decision unit is activated to sense the voltage swing of the read bit line; When the voltage swing of the read line is sensed to be greater than the first difference voltage, it is determined to be the first stored data; When the voltage swing of the read line is sensed to be less than the first difference voltage, it is determined to be the second stored data; The first voltage difference is less than the first voltage and greater than the second voltage.
12. The method for reading a memory according to claim 10, characterized in that, The charge corresponding to the first stored data is greater than the charge corresponding to the second stored data.
13. The method for reading a memory according to claim 12, characterized in that, The first stored data is a logical value of 1, and the second stored data is a logical value of 0.