Three-dimensional memory device with side integrated access

Abstract

A device includes a three-dimensional array of unit cells. Each of the unit cells includes: an access field effect transistor including a first horizontally extending semiconductor channel, a drain region, a first gate dielectric, and a first gate electrode; and a memory field effect transistor including a second horizontally extending semiconductor channel, a source region, a second gate dielectric, and a second gate electrode. The second gate dielectric includes a memory dielectric material having at least two programmable states. In one embodiment, a doped semiconductor material portion is located between a first horizontally extending semiconductor channel and a second horizontally extending semiconductor channel.

Description

[0001] Related applications

[0002] This application claims priority to the following: U.S. Provisional Application No. 63 / 656,950, filed June 6, 2024; U.S. Provisional Application No. 63 / 656,989, filed June 6, 2024; U.S. Non-Provisional Application No. 18 / 794,809, filed August 5, 2024; U.S. Non-Provisional Application No. 18 / 819,475, filed August 29, 2024; and U.S. Non-Provisional Application No. 18 / 819,569, filed August 29, 2024; the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more particularly to a three-dimensional memory device having a side-integrated access transistor and a method for manufacturing the same. Background Technology

[0004] NAND memory devices offer high memory cell density at a low cost per bit. However, as the number of layers in a NAND memory device increases, the length of the vertical channel increases, and the memory latency of the NAND memory device increases. Summary of the Invention

[0005] According to one aspect of this disclosure, a device structure includes a three-dimensional array of unit cells. Each unit cell includes: a access field-effect transistor (FET) including a first horizontally extending semiconductor channel, a drain region, a first gate dielectric, and a first gate electrode; and a memory field-effect transistor (FET) including a second horizontally extending semiconductor channel, a source region, a second gate dielectric, and a second gate electrode, wherein the second gate dielectric includes a memory dielectric material having at least two programmable states. In one embodiment, a portion of the doped semiconductor material is located between the first and second horizontally extending semiconductor channels.

[0006] According to another aspect of this disclosure, a method of forming a device structure includes: forming vertically alternating stacks of horizontally extending semiconductor rails and horizontally extending sacrificial rails, wherein each of the vertically alternating stacks extends laterally along a first horizontal direction, and the vertically alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches including uniform width portions and lateral protrusion portions; converting the proximal portions of the horizontally extending semiconductor rails into a three-dimensional array of doped semiconductor material portions by diffusing electro-doped material in the proximal portions of the lateral protrusion portions surrounding the lateral isolation trenches; and patterning the vertically alternating stacks, wherein the patterned portions of the vertically alternating stacks include a three-dimensional array of horizontally extending semiconductor rails, each of which contains a corresponding first horizontally extending semiconductor channel and a corresponding doped semiconductor material. The process includes: depositing a first gate dielectric material and a first gate electrode material around the first horizontally extended semiconductor channel; depositing a second gate dielectric material and a second gate electrode material around the second horizontally extended semiconductor channel; forming a one-dimensional array of bridge-around cavities such that each two-dimensional array of doped semiconductor material portions arranged along a direction perpendicular to the first horizontal direction is exposed to a corresponding bridge-around cavity in the bridge-around cavity; and isotropically etching the first gate electrode material and the second gate electrode material around the one-dimensional array of bridge-around cavities, wherein the remaining portion of the first gate electrode material constitutes a two-dimensional array of first word lines, and the remaining portion of the second gate electrode material constitutes a two-dimensional array of second word lines.

[0007] According to one aspect of this disclosure, a device structure includes a three-dimensional array of unit cells, the three-dimensional array of unit cells comprising a vertical stack of unit cells arranged along a vertical direction. Each unit cell includes: a field-effect transistor having a set of semiconductor material portions including a horizontally extending semiconductor channel; and a memory device having a first electrode electrically connected to a sidewall of the set of semiconductor material portions, a second electrode spaced apart from the field-effect transistor, and a memory layer located between the first electrode and the second electrode.

[0008] According to another aspect of this disclosure, a method of forming a device structure includes: forming a three-dimensional array of horizontally extending semiconductor rails extending laterally along a first horizontal direction on a substrate, wherein the three-dimensional array of horizontally extending semiconductor rails is structurally supported by a three-dimensional array of horizontally extending sacrificial rails; forming a first inter-rail cavity between first portions of vertically adjacent pairs of horizontally extending semiconductor rails by removing a first portion of each horizontally extending sacrificial rail; depositing a gate dielectric material and a gate electrode material around each first portion of the horizontally extending semiconductor rails; forming a second inter-rail cavity between vertically adjacent pairs of horizontally extending semiconductor rails by removing a second portion of each horizontally extending sacrificial rail; patterning the gate dielectric material and the gate electrode material into a three-dimensional array of gate dielectrics and a two-dimensional array of word lines; and replacing the second portions of the horizontally extending semiconductor rails with a three-dimensional array of instances of memory devices.

[0009] According to another aspect of this disclosure, a device structure comprising a three-dimensional array of unit cells is provided. Each unit cell includes: a access field-effect transistor including a first horizontally extending semiconductor channel, a first gate dielectric, and a first gate electrode; and a memory field-effect transistor including a second horizontally extending semiconductor channel, a second gate dielectric, and a second gate electrode, wherein the second gate dielectric includes a memory dielectric material having at least two programmable states.

[0010] According to another aspect of this disclosure, a method for forming a device structure is provided. The method includes: forming a three-dimensional array of horizontally extending semiconductor rails extending laterally along a first horizontal direction on a substrate, wherein the three-dimensional array of horizontally extending semiconductor rails is structurally supported by a three-dimensional array of horizontally extending sacrificial rails; forming a first inter-rail cavity between first portions of vertically adjacent pairs of horizontally extending semiconductor rails by removing a first portion of each horizontally extending sacrificial rail; depositing a first gate dielectric material and a first gate electrode material around each first portion of the horizontally extending semiconductor rails; forming a second inter-rail cavity between vertically adjacent pairs of horizontally extending semiconductor rails by removing a second portion of each horizontally extending sacrificial rail; patterning the first gate dielectric material and the first gate electrode material into a three-dimensional array of the first gate dielectric and a two-dimensional array of first word lines, wherein each first word line includes a corresponding row of first gate electrodes arranged along a second horizontal direction; and forming a second gate electrode around a second portion of each horizontally extending semiconductor rail. Attached Figure Description

[0011] for Figure 1A and Figure 40E All figures labeled with a combination of reference numerals and letter suffixes are categorized as follows: each figure with a reference numeral "A" is a vertical cross-sectional view; each figure with a reference numeral "B" is a horizontal cross-sectional view along the horizontal plane B-B' within the figures with the same reference numerals and letter suffixes "A"; each figure with a reference numeral "C" is a horizontal cross-sectional view along the horizontal plane C-C' within the figures with the same reference numerals and letter suffixes "A"; each figure with a reference numeral "D" is a vertical cross-sectional view along the vertical plane D-D' within the figures with the same reference numerals and letter suffixes "B" or "C"; and each figure with a reference numeral "E" is a vertical cross-sectional view along the vertical plane E-E' within the figures with the same reference numerals and letter suffixes "B" or "C". The vertical plane A-A' shown in the attached figure with the corresponding letter suffix "B", "C", "D" or "E" corresponds to the cutting plane of the vertical cross-sectional view of the attached figure with the same reference numeral and the letter suffix "A".

[0012] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E These are various views of a first exemplary structure following the formation of an etch stop structure and a vertical alternating sequence of sacrificial and semiconductor layers, according to a first embodiment of this disclosure.

[0013] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E These are various views of a first exemplary structure following the formation of the in-situ line trench and source trench according to a first embodiment of the present disclosure.

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E These are various views of a first exemplary structure after the formation of the sacrificial bitline trench fill structure and the sacrificial source trench fill structure, according to a first embodiment of the present disclosure.

[0015] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E These are various views of a first exemplary structure after the formation of a lateral isolation trench, according to a first embodiment of the present disclosure.

[0016] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E These are various views of a first exemplary structure following the formation of a sacrificial isolation trench filling structure, according to a first embodiment of this disclosure.

[0017] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E These are various views of a first exemplary structure following the formation of the first inter-track cavity and the first lateral isolation trench, according to a first embodiment of the present disclosure.

[0018] Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E These are various views of a first exemplary structure following the formation of a first gate dielectric material layer and a first gate electrode material layer, according to a first embodiment of the present disclosure.

[0019] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E These are various views of a first exemplary structure following the formation of a two-dimensional array of dielectric substrates according to a first embodiment of the present disclosure.

[0020] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E These are various views of a first exemplary structure after the first gate electrode material layer has been patterned into a first gate electrode material layer, according to a first embodiment of the present disclosure.

[0021] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E These are various views of a first exemplary structure after the first gate dielectric material layer has been patterned into a first gate dielectric layer, according to a first embodiment of the present disclosure.

[0022] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11EThese are various views of a first exemplary structure after the formation of an in-situ trench isolation structure according to a first embodiment of the present disclosure.

[0023] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E These are various views of a first exemplary structure after the formation of the sacrificial bitline structure according to a first embodiment of the present disclosure.

[0024] Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E These are various views of a first exemplary structure after the removal of the sacrificial source trench fill structure according to a first embodiment of the present disclosure.

[0025] Figure 14A , Figure 14B , Figure 14C , Figure 14D and Figure 14E These are various views of a first exemplary structure following the formation of the second inter-track cavity and the second lateral isolation trench, according to a first embodiment of this disclosure.

[0026] Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E These are various views of a first exemplary structure according to a first embodiment of the present disclosure, after the first gate dielectric layer is patterned into a three-dimensional array of gate dielectrics and after the first gate electrode material layer is patterned into a two-dimensional array of first word lines.

[0027] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E These are various views of a first exemplary structure following the deposition of a dielectric matrix material layer according to a first embodiment of the present disclosure.

[0028] Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E These are various views of a first exemplary structure following the patterning of a dielectric matrix material layer into a one-dimensional array of perforated dielectric matrices according to a first embodiment of the present disclosure.

[0029] Figure 18A , Figure 18B , Figure 18C , Figure 18D and Figure 18E These are various views of a first exemplary structure following the formation of a laterally recessed three-dimensional array according to a first embodiment of the present disclosure.

[0030] Figure 19A , Figure 19B , Figure 19C , Figure 19D and Figure 19E These are various views of a first exemplary structure following the formation of an in-situ via cavity according to a first embodiment of this disclosure.

[0031] Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20E These are various views of a first exemplary structure following the formation of the source and drain regions according to a first embodiment of the present disclosure.

[0032] Figure 21A , Figure 21B , Figure 21C , Figure 21D and Figure 21E These are various views of a first exemplary structure following the formation of a first conductive material layer and a sacrificial covering material layer, according to a first embodiment of the present disclosure.

[0033] Figure 22A , Figure 22B , Figure 22C , Figure 22D and Figure 22E These are various views of a first exemplary structure following the patterning of a sacrificial cover material layer into a three-dimensional array of sacrificial cover layers according to a first embodiment of this disclosure.

[0034] Figure 23A , Figure 23B , Figure 23C , Figure 23D and Figure 23E These are various views of a first exemplary structure following the patterning of a first conductive material layer into a three-dimensional array of first electrodes, according to a first embodiment of the present disclosure.

[0035] Figure 24A , Figure 24B , Figure 24C , Figure 24D and Figure 24E These are various views of a first exemplary structure following the formation of a memory material layer according to a first embodiment of the present disclosure.

[0036] Figure 25A , Figure 25B , Figure 25C , Figure 25D and Figure 25E These are various views of a first exemplary structure following the deposition of a second conductive material layer according to a first embodiment of the present disclosure.

[0037] Figure 26A , Figure 26B , Figure 26C , Figure 26D and Figure 26E These are various views of a first exemplary structure following the patterning of a second conductive material layer into a one-dimensional array of bit lines and conductive structures, according to a first embodiment of the present disclosure.

[0038] Figure 26F and Figure 26G These are corresponding vertical cross-sectional and top views of an alternative configuration of a first exemplary structure after patterning a second conductive material layer, according to a first embodiment of the present disclosure.

[0039] Figure 27A , Figure 27B , Figure 27C , Figure 27D and Figure 27E These are various views of a second exemplary structure following the formation of an in-situ trench isolation structure and the removal of a sacrificial source trench filling structure according to a second embodiment of this disclosure.

[0040] Figure 28A , Figure 28B , Figure 28C , Figure 28D and Figure 28E These are various views of a second exemplary structure following the formation of the second inter-track cavity and the second lateral isolation trench, according to a second embodiment of this disclosure.

[0041] Figure 29A , Figure 29B , Figure 29C , Figure 29D and Figure 29E These are various views of a second exemplary structure according to a second embodiment of the present disclosure, after the first gate dielectric layer is patterned into a three-dimensional array of gate dielectrics and after the first gate electrode material layer is patterned into a two-dimensional array of first word lines.

[0042] Figure 30A , Figure 30B , Figure 30C , Figure 30D and Figure 30E These are various views of a second exemplary structure according to a second embodiment of the present disclosure after changing the doping concentration of a second horizontally extended semiconductor channel within each semiconductor rail.

[0043] Figure 31A , Figure 31B , Figure 31C , Figure 31D and Figure 31E These are various views of a second exemplary structure following the formation of a second gate dielectric material layer according to a second embodiment of the present disclosure.

[0044] Figure 32A , Figure 32B , Figure 32C , Figure 32D and Figure 32E These are various views of a second exemplary structure following the deposition of a dielectric gate spacer material layer according to a second embodiment of the present disclosure.

[0045] Figure 33A , Figure 33B , Figure 33C , Figure 33D and Figure 33E These are various views of a second exemplary structure following the formation of a two-dimensional array of dielectric substrates according to a second embodiment of the present disclosure.

[0046] Figure 34A , Figure 34B , Figure 34C , Figure 34D and Figure 34E These are various views of a second exemplary structure following the formation of a dielectric gate spacer material layer and a gate cavity, according to a second embodiment of the present disclosure.

[0047] Figure 35A , Figure 35B , Figure 35C , Figure 35D and Figure 35E These are various views of a second exemplary structure according to a second embodiment of the present disclosure, after the formation of a second word line comprising a three-dimensional array of gate electrodes and the removal of physically exposed portions of a second gate dielectric material layer.

[0048] Figure 36A , Figure 36B , Figure 36C , Figure 36D and Figure 36E These are various views of a second exemplary structure following the formation of a source trench isolation structure according to a second embodiment of the present disclosure.

[0049] Figure 37A , Figure 37B , Figure 37C , Figure 37D and Figure 37E These are various views of a second exemplary structure following the formation of the in-situ via cavity and the source via cavity according to a second embodiment of this disclosure.

[0050] Figure 38A , Figure 38B , Figure 38C , Figure 38D and Figure 38E These are various views of a second exemplary structure following the formation of the source and drain regions according to a second embodiment of this disclosure.

[0051] Figure 39A , Figure 39B , Figure 39C , Figure 39D and Figure 39E These are various views of a second exemplary structure following the formation of the in-situ line and source line according to a second embodiment of this disclosure.

[0052] Figure 40A , Figure 40B , Figure 40C , Figure 40D and Figure 40E These are various views of alternative configurations of a second exemplary structure following the formation of the in-situ line and source structure according to a second embodiment of this disclosure.

[0053] Figure 41 This is a schematic circuit diagram of a first exemplary circuit that can be used to implement a three-dimensional memory device including the first exemplary structure.

[0054] Figure 42 This is a schematic circuit diagram of a second exemplary circuit that can be used to implement a three-dimensional memory device including the first exemplary structure.

[0055] Figure 43 This is a schematic circuit diagram of a third exemplary circuit that can be used to implement a three-dimensional memory device including the second exemplary structure.

[0056] Figure 44 This is a schematic circuit diagram of a fourth exemplary circuit that can be used to implement a three-dimensional memory device with an alternative configuration including the second exemplary structure.

[0057] Figure 45 This is a vertical cross-sectional view of a first semiconductor die containing an embodiment of the present disclosure of a three-dimensional memory array.

[0058] Figure 46 This is a vertical cross-sectional view of a second semiconductor containing an embodiment of the present disclosure of a three-dimensional memory array.

[0059] Figure 47 This is a vertical cross-sectional view of a third semiconductor die containing an embodiment of the present disclosure of a three-dimensional memory array.

[0060] Figure 48 This is a vertical cross-sectional view of a fourth semiconductor die containing an embodiment of the present disclosure of a three-dimensional memory array.

[0061] Figure 49 This is a vertical cross-sectional view of a fifth semiconductor die containing an embodiment of the present disclosure of a three-dimensional memory array.

[0062] Figure 50 This is a vertical cross-sectional view of a sixth semiconductor die containing an embodiment of the present disclosure of a three-dimensional memory array.

[0063] for Figure 51A and Figure 78G All figures labeled with a combination of reference numerals and letter suffixes are categorized as follows: each figure with a label including the letter suffix "A" is a vertical cross-sectional view; each figure with a label including the letter suffix "B" is a second vertical cross-sectional view; each figure with a label including the letter suffix "C" is a first horizontal cross-sectional view along horizontal plane C-C' within the figures with the same reference numerals and letter suffixes "A" or "B"; and each figure with a label including the letter suffix "D" is a horizontal cross-sectional view along horizontal plane D-D within the figures with the same reference numerals and letter suffixes "A" or "B". The second horizontal cross-sectional view; each drawing with a drawing label including the letter suffix "E" is a vertical cross-sectional view along the vertical plane E-E' within the drawing with the same drawing label and the letter suffix "C" or "D"; each drawing with a drawing label including the letter suffix "F" is a vertical cross-sectional view along the vertical plane F-F' within the drawing with the same drawing label and the letter suffix "C" or "D"; and each drawing with a drawing label including the letter suffix "G" is a vertical cross-sectional view along the vertical plane G-G' within the drawing with the same drawing label and the letter suffix "C" or "D". The vertical plane A-A' shown in the drawing with the corresponding letter suffix "C", "D", "E", "F" or "G" corresponds to the cutting plane of the first vertical cross-sectional view of the drawing with the same drawing label and the letter suffix "A". The vertical plane B-B' shown in the figure with the corresponding letter suffix "C", "D", "E", "F" or "G" corresponds to the cutting plane of the first vertical cross-sectional view of the figure with the same reference numeral and the letter suffix "B".

[0064] Figure 51A , Figure 51B , Figure 51C , Figure 51D , Figure 51E , Figure 51F and Figure 51G These are various views of a third exemplary structure following the formation of a lateral isolation trench including periodic lateral protrusions, according to a third embodiment of this disclosure.

[0065] Figure 52A , Figure 52B , Figure 52C , Figure 52D , Figure 52E , Figure 52F and Figure 52G These are various views of a third exemplary structure following the formation of a sacrificial isolation trench filling structure, according to a third embodiment of this disclosure.

[0066] Figure 53A , Figure 53B , Figure 53C , Figure 53D , Figure 53E , Figure 53F and Figure 53G These are various views of a third exemplary structure following the formation of a two-dimensional array of isotropic recesses and column cavities in a sacrificial isolation trench filling structure, according to a third embodiment of this disclosure.

[0067] Figure 54A , Figure 54B , Figure 54C , Figure 54D , Figure 54E , Figure 54F and Figure 54G These are various views of a third exemplary structure following the formation of a one-dimensional array of bridge-surrounding cavities according to a third embodiment of this disclosure.

[0068] Figure 55A , Figure 55B , Figure 55C , Figure 55D , Figure 55E , Figure 55F and Figure 55G These are various views of a third exemplary structure following the formation of a three-dimensional array of doped semiconductor material portions according to a third embodiment of this disclosure.

[0069] Figure 56A , Figure 56B , Figure 56C , Figure 56D , Figure 56E , Figure 56F and Figure 56G These are various views of a third exemplary structure following the formation of a one-dimensional array of sacrificial perforated wall structures, according to a third embodiment of this disclosure.

[0070] Figure 57A , Figure 57B , Figure 57C , Figure 57D , Figure 57E , Figure 57F and Figure 57GThese are various views of a third exemplary structure following the formation of the in-situ line trench and source trench according to a third embodiment of this disclosure.

[0071] Figure 58A , Figure 58B , Figure 58C , Figure 58D , Figure 58E , Figure 58F and Figure 58G These are various views of a third exemplary structure following the formation of the sacrificial bitline trench fill structure and the sacrificial source trench fill structure, according to a third embodiment of this disclosure.

[0072] Figure 59A , Figure 59B , Figure 59C , Figure 59D , Figure 59E , Figure 59F and Figure 59G These are various views of a third exemplary structure after the removal of the first portion of the sacrificial isolation trench fill structure and the sacrificial bit line trench fill structure, according to a third embodiment of this disclosure.

[0073] Figure 60A , Figure 60B , Figure 60C , Figure 60D , Figure 60E , Figure 60F and Figure 60G These are various views of a third exemplary structure following the formation of the first inter-track cavity, according to a third embodiment of this disclosure.

[0074] Figure 61A , Figure 61B , Figure 61C , Figure 61D , Figure 61E , Figure 61F and Figure 61G These are various views of a third exemplary structure following the formation of a first gate dielectric material layer and a continuous first gate electrode material layer, according to a third embodiment of this disclosure.

[0075] Figure 62A , Figure 62B , Figure 62C , Figure 62D , Figure 62E , Figure 62F and Figure 62G These are various views of a third exemplary structure following the formation of a two-dimensional array of a first dielectric substrate, according to a third embodiment of this disclosure.

[0076] Figure 63A , Figure 63B , Figure 63C , Figure 63D , Figure 63E , Figure 63F and Figure 63G These are various views of a third exemplary structure following the patterning of a continuous first gate electrode material layer according to a third embodiment of the present disclosure.

[0077] Figure 64A , Figure 64B , Figure 64C , Figure 64D , Figure 64E , Figure 64F and Figure 64G These are various views of a third exemplary structure after the formation of the in-situ trench isolation structure according to a third embodiment of this disclosure.

[0078] Figure 65A , Figure 65B , Figure 65C , Figure 65D , Figure 65E , Figure 65F and Figure 65G These are various views of a third exemplary structure following the formation of the second inter-track cavity, according to a third embodiment of this disclosure.

[0079] Figure 66A , Figure 66B , Figure 66C , Figure 66D , Figure 66E , Figure 66F and Figure 66G These are various views of a third exemplary structure following the formation of a second gate dielectric material layer and a continuous second gate electrode material layer, according to a third embodiment of this disclosure.

[0080] Figure 67A , Figure 67B , Figure 67C , Figure 67D , Figure 67E , Figure 67F and Figure 67G These are various views of a third exemplary structure following the formation of a second gate dielectric material layer and a continuous second gate electrode material layer, according to a third embodiment of this disclosure.

[0081] Figure 68A , Figure 68B , Figure 68C , Figure 68D , Figure 68E , Figure 68F and Figure 68G These are various views of a third exemplary structure following the formation of a two-dimensional array of a second dielectric substrate, according to a third embodiment of this disclosure.

[0082] Figure 69A , Figure 69B, Figure 69C , Figure 69D , Figure 69E , Figure 69F and Figure 69G These are various views of a third exemplary structure following the patterning of a continuous second gate electrode material layer according to a third embodiment of the present disclosure.

[0083] Figure 70A , Figure 70B , Figure 70C , Figure 70D , Figure 70E , Figure 70F and Figure 70G These are various views of a third exemplary structure following the formation of a source trench isolation structure according to a third embodiment of this disclosure.

[0084] Figure 71A , Figure 71B , Figure 71C , Figure 71D , Figure 71E , Figure 71F and Figure 71G These are various views of a third exemplary structure following the formation of the in-situ via cavity and the source via cavity according to a third embodiment of this disclosure.

[0085] Figure 72A , Figure 72B , Figure 72C , Figure 72D , Figure 72E , Figure 72F and Figure 72G These are various views of a third exemplary structure following the formation of the drain region, source region, vertical bit line, and vertical source line according to a third embodiment of this disclosure.

[0086] Figure 73A , Figure 73B , Figure 73C , Figure 73D , Figure 73E , Figure 73F and Figure 73G Various views of a third exemplary structure following the formation of a one-dimensional array of bridge-surround cavities by removing a one-dimensional array of sacrificial perforated wall structures, according to a third embodiment of this disclosure.

[0087] Figure 74A , Figure 74B , Figure 74C , Figure 74D , Figure 74E , Figure 74F and Figure 74G These are various views of a third exemplary structure following the formation of the tubular metal-semiconductor alloy region according to a third embodiment of this disclosure.

[0088] Figure 75A , Figure 75B , Figure 75C , Figure 75D , Figure 75E , Figure 75F and Figure 75G These are various views of a third exemplary structure according to a third embodiment of the present disclosure after the first gate dielectric layer, the first gate electrode material layer, the second gate dielectric layer, and the second gate electrode material layer have been recessed.

[0089] Figure 76A , Figure 76B , Figure 76C , Figure 76D , Figure 76E , Figure 76F and Figure 76G These are various views of a third exemplary structure following the formation of a one-dimensional array of perforated dielectric walls, according to a third embodiment of this disclosure.

[0090] Figure 77A , Figure 77B , Figure 77C , Figure 77D , Figure 77E , Figure 77F and Figure 77G These are various views of a first alternative configuration of a third exemplary structure according to a third embodiment of this disclosure.

[0091] Figure 78A , Figure 78B , Figure 78C , Figure 78D , Figure 78E , Figure 78F and Figure 78G These are various views of a second alternative configuration of a third exemplary structure according to a third embodiment of this disclosure. Detailed Implementation

[0092] As discussed above, embodiments of this disclosure relate to three-dimensional memory devices within laterally integrated access transistors and methods for fabricating the same, various aspects of which are described below. Embodiments of this disclosure can be used to form various multi-level memory structures, non-limiting examples of which include non-volatile memory arrays and volatile memory arrays that can be implemented as three-dimensional memory arrays. Each unit cell may include a combination of access transistors and impedance elements (such as capacitive or resistive elements), or may include a combination of access transistors and memory transistors.

[0093] The accompanying drawings are not drawn to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The same reference numerals denote the same or similar elements. Unless otherwise specified, elements having the same reference numerals are considered to have the same composition and the same function.

[0094] Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by those elements. As used herein, a first element positioned “on” a second element may be positioned on the outer side of a surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0095] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extension may be less than the extension of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0096] As used herein, the first and second surfaces are “vertically coincident” if the second surface overlies or lies beneath the first surface and a vertical or substantially vertical plane comprising the first and second surfaces is present. A substantially vertical plane is a plane extending in a straight line along an angle less than 5 degrees deviating from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0097] Generally speaking, a semiconductor package (or "package") refers to a single semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips bonded together, for example, by flip-chip bonding or chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit capable of independently executing external commands or reporting status. Typically, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of planes within it. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but some limitations may exist. When the die is a memory die (i.e., a die containing memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0098] refer to Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E This illustration depicts a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 2, which may be a semiconductor substrate, an insulating substrate, a conductive substrate, or a composite substrate comprising a stack of multiple layers. In some embodiments, the substrate 2 may include a single-crystal semiconductor substrate, such as a commercially available single-crystal silicon wafer. Preferably, but not necessarily, an etch stop structure 8 may be formed on the top surface of the substrate 2. The etch stop structure 8 may include at least one etch stop material layer and / or may include patterned discrete etch stop structures. Generally, any material layer and / or patterned material portion may be used as the etch stop structure 8. In some embodiments, the etch stop structure 8 may include a single-crystal carbon-doped silicon layer or a single-crystal nitrogen-doped silicon layer. In some other embodiments, the etch stop structure 8 may include at least one dielectric material layer, such as a silicon oxide layer, a silicon nitride layer, a silicon carbonitride layer, a silicon oxynitride layer, a dielectric metal oxide layer, or a combination thereof. Alternatively, the etch stop structure 8 includes a patterned dielectric material portion embedded in an upper portion of the substrate 2.

[0099] A vertically alternating sequence of sacrificial layers 20L and semiconductor layers 10L may be formed on the etch stop structure 8. In one embodiment, the sacrificial layers 20L and semiconductor layers 10L may include nanolayers comprising unpatterned layers having a thickness greater than 1 nm and less than 1 micrometer. Each sacrificial layer 20L includes a sacrificial material, and each semiconductor layer 10L includes a semiconductor material. The sacrificial material of the sacrificial layer 20L is a material that can be selectively removed subsequently relative to the material of the semiconductor layer 10L and relative to the material of the etch stop structure 8. For example, the semiconductor layer 10L may include silicon (such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon that can subsequently crystallize into polycrystalline silicon), and the sacrificial layer 20L may include a silicon-germanium compound semiconductor material (containing germanium atoms in the atomic percentage range of 10% to 40%), silicon nitride, organosilicon glass, or polymer material. Each semiconductor layer 10L may have a first thickness in the range of 10 nm to 200 nm (such as 20 nm to 100 nm), but smaller and larger first thicknesses may also be used. In one embodiment, semiconductor layer 10L may comprise single-crystal silicon epitaxially aligned with single-crystal semiconductor material within substrate 2, and sacrificial layer 20L may comprise a single-crystal silicon-germanium compound semiconductor layer epitaxially aligned with both the single-crystal silicon in semiconductor layer 10L and the single-crystal semiconductor material within substrate 2. In this case, the entire set of substrate 2, semiconductor layer 10L, and sacrificial layer 20L may be single-crystal and epitaxially aligned with each other. Each sacrificial layer 20L may have a second thickness in the range of 20 nm to 300 nm (e.g., 30 nm to 150 nm), but smaller and larger second thicknesses may also be used.

[0100] A vertical alternating sequence (20L, 10L) can be formed by an alternating sequence of deposition steps, each depositing a corresponding sacrificial layer 20L or a corresponding semiconductor layer 10L. For example, each semiconductor layer 10L can be deposited by a first type of chemical vapor deposition or atomic layer deposition process, and each sacrificial layer 20L can be deposited by a second type of chemical vapor deposition or atomic layer deposition process. The bottom layer of the vertical alternating sequence (20L, 10L) can be either a sacrificial layer 20L or a semiconductor layer 10L. The top layer of the vertical alternating sequence (20L, 10L) can be either a sacrificial layer 20L or a semiconductor layer 10L. (N+1) vertical alternating sequences (20L, 10L) can exist for the sacrificial layers 20L and the semiconductor layers 10L. The number N can be 2 to 2^3. 10 (such as 8 to 2) 8 Within the range of ), but fewer or more pairs can also be used. The three-dimensional array of unit cells UC is then formed within a volume of vertically alternating sequences (20L, 10L). Figure 1A , Figure 1B , Figure 1C , Figure 1Dand Figure 1E Each of the above schematically illustrates the volume of a unit cell UC. A three-dimensional array of unit cells UC includes a three-dimensional memory array. The three-dimensional array of unit cells UC may have a first periodicity along a first horizontal direction hd1, a second periodicity along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and a third periodicity along a vertical direction. The third periodicity may be equal to the sum of the first thickness and the second thickness.

[0101] refer to Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E A first photoresist layer (not shown) may be applied over a vertical alternating sequence (20L, 10L) and may be photolithographically patterned to form elongated openings extending laterally along a second horizontal direction hd2. The elongated openings may have a uniform width along a first horizontal direction hd1 and are formed at the boundaries of adjacent pairs of unit cells UC. A first anisotropic etching process may be performed to transfer the pattern of the openings in the first photoresist layer through the vertical alternating sequence (20L, 10L). Trenches (49, 99) extending laterally along the second horizontal direction hd2 may be formed. The total number of trenches (49, 99) may be L+1, where L is greater than or equal to 2. 6 Up to 2 18 The range is an integer, but smaller and larger numbers can also be used for integers L. The trenches (49, 99) can comprise a lateral alternation sequence of source trenches 49 (e.g., write-side trenches) and bit line trenches 99 (e.g., read-side trenches) alternating along the first horizontal direction hd1. Each of the source trenches 49 and bit line trenches 99 can have a corresponding uniform width along the first horizontal direction hd1, which can range from 50 nm to 600 nm (e.g., 100 nm to 400 nm), but smaller and larger widths can also be used. The center-to-center distance between adjacent pairs of trenches (49, 99) can be the same as the first periodicity of the three-dimensional array of the unit cell UC along the first horizontal direction hd1. The first periodicity can range from 200 nm to 10,000 nm (e.g., 400 nm to 1,000 nm), but smaller and larger sizes can also be used for the first periodicity. Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1EThe vertical alternating sequences (20L, 10L) formed at the processing step are divided into a one-dimensional array of vertical alternating sequences (20L, 10L) arranged along the first horizontal direction hd1, and laterally spaced from each other by the alternating sequences of source trench 49 and bit line trench 99. Each vertical alternating sequence (20L, 10L) of semiconductor layer 10L and sacrificial layer 20L may have a corresponding first flat sidewall perpendicular to the first horizontal direction hd1 and exposed to the corresponding bit line trench 99, and a corresponding second flat sidewall perpendicular to the first horizontal direction hd1 and exposed to the corresponding source trench 49. The first photoresist layer may then be removed, for example, by ashing.

[0102] refer to Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A first sacrificial filler material may be deposited in the source trench 49 and the bit line trench 99. The first sacrificial filler material may include carbon-based materials (such as amorphous carbon or diamond-like carbon), organosilicon glass, silicon oxide, silicon nitride, or polymer materials. Generally, the first sacrificial filler material differs from the material of the sacrificial layer 20L. Excess portions of the first sacrificial filler material can be removed from above a horizontal plane comprising the vertically alternating sequence (20L, 10L) by a planarization process that may utilize chemical mechanical polishing and / or dip etching. Each portion of the first sacrificial filler material filling the source trench 49 constitutes a sacrificial source trench filling structure 47. Each portion of the first sacrificial filler material filling the bit line trench 99 constitutes a sacrificial bit line trench filling structure 97.

[0103] refer to Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4EA second photoresist layer (not shown) may be applied over the alternating vertical sequence (20L, 10L) and the sacrificial trench fill structures (47, 97), and may be photolithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1. The elongated openings may have a uniform width along a second horizontal direction hd1 and may extend laterally along the first horizontal direction hd1 across the entire length of the one-dimensional array of the alternating vertical sequence (20L, 10L), or may extend laterally between corresponding adjacent pairs of sacrificial trench fill structures (47, 97). Generally, each elongated opening in the second photoresist layer may be formed at the boundary of adjacent pairs of unit cells UC spaced apart along the second horizontal direction. A second anisotropic etching process may be performed to transfer the pattern of the openings in the second photoresist layer through the alternating vertical sequence (20L, 10L). Lateral isolation trenches 59 extending laterally along the first horizontal direction hd1 may be formed. Each lateral isolation trench 59 may have a corresponding uniform width along the second horizontal direction hd2, which is less than the thickness of each sacrificial layer 20L. The uniform thickness of each lateral isolation trench 59 may be in the range of 10nm to 200nm (such as 20nm to 100nm), but smaller and larger widths may also be used. The total number of lateral isolation trenches 59 may be M+1, where M is in the range of 2... 6 Up to 2 20 The range is an integer, but smaller and larger quantities can also be used for integer M. The center-to-center distance between adjacent pairs of lateral isolation trenches 59 can be the same as the second periodicity of the three-dimensional array of the unit cell UC along the second horizontal direction hd2. The second periodicity can be in the range of 20 nm to 1,000 nm (such as 40 nm to 500 nm), but smaller and larger sizes can also be used for the second periodicity.

[0104] Each patterned portion of the semiconductor layer 10L includes a semiconductor rail 10. Each patterned portion of the sacrificial layer 20L includes a sacrificial rail 20. (As in...) Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2EThe one-dimensional array of vertically alternating sequences (20L, 10L) formed at the processing step is divided into a two-dimensional array of alternating stacks (20, 10) of semiconductor rails 10 and sacrificial rails 20. As used herein, a rail refers to an elongated structure that extends laterally along a length direction (such as a first horizontal direction hd1) and has a uniform width dimension along all width dimensions (such as a second horizontal direction hd1 and a vertical direction). In this case, each of the semiconductor rails 10 and sacrificial rails 20 may have a corresponding first width dimension along the second horizontal direction hd2 and may have a second width dimension along the vertical dimension. The lateral dimensions of the semiconductor rails 10 and sacrificial rails 20 along the second horizontal direction hd2 may range from 100 nm to 900 nm (such as 200 nm to 500 nm), but smaller and larger lateral dimensions may also be used.

[0105] A three-dimensional array of semiconductor rails 10 can be formed. The three-dimensional array of semiconductor rails 10 can be an L x M x (N+1) cubic three-dimensional array, wherein instances of unit cells UC are repeated L times along a first horizontal direction hd1, M times along a second horizontal direction hd2, and (N+1) times along the vertical direction. Each semiconductor rail in semiconductor rails 10 can have a corresponding rectangular parallelepiped shape. Each sacrificial rail in sacrificial rails 20 can have a corresponding rectangular parallelepiped shape. The second photoresist layer can then be removed, for example, by ashing.

[0106] Generally, a three-dimensional array of horizontally extending semiconductor rails 10 extending laterally along the first horizontal direction hd1 can be formed on the substrate 2. The three-dimensional array of horizontally extending semiconductor rails 10 can be structurally supported by a three-dimensional array of horizontally extending sacrificial rails 20.

[0107] refer to Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5EA second sacrificial filler material may be deposited in the lateral isolation trench 59. The second sacrificial filler material may include a different sacrificial filler material than the first sacrificial filler material. In one embodiment, the second sacrificial filler material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), organosilicon glass, silicon oxide, silicon nitride, or a polymer material. For example, the second sacrificial filler material may include silicon oxide. Generally, the second sacrificial filler material differs from the first sacrificial filler material of the sacrificial source trench filling structure 47 and the sacrificial bit line trench filling structure 97, and may be different from or the same as the material of the sacrificial layer 20L. Excess portions of the second sacrificial filler material can be removed from above a horizontal plane comprising the alternating stacks (20, 10) by a planarization process that may use chemical mechanical polishing and / or recess etching processes. The filling of each portion of the corresponding lateral isolation trench 59 with the second sacrificial filler material constitutes the sacrificial isolation trench filling structure 57. In an alternative embodiment, the sacrificial source trench filling structure 47 and the sacrificial bit line trench filling structure 97 may be formed after the formation of the sacrificial isolation trench filling structure 57. Therefore, Figures 2A to 2E as well as Figures 3A to 3E The steps shown can be in Figures 4A to 4E as well as Figures 5A to 5E The steps shown are executed afterward.

[0108] refer to Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E An etch mask layer (not illustrated), such as a photoresist layer, may be formed over the first exemplary structure and may be patterned to form openings over the region of the sacrificial bit line trench fill structure 97. A first selective material removal process may be performed to selectively remove the sacrificial bit line trench fill structure 97 relative to the materials of the semiconductor rail 10, the etch stop structure 8, the sacrificial isolation trench fill structure 57, and the etch stop structure 8. In an exemplary example, if the sacrificial bit line trench fill structure 97 comprises silicon nitride, a wet etching process using thermal phosphoric acid may be performed. If the sacrificial bit line trench fill structure 97 comprises a carbon-based material (such as amorphous carbon or diamond-like carbon), an ashing process may be used to remove the sacrificial bit line trench fill structure 97. Voids are formed in the volume of the bit line trench 99.

[0109] Subsequently, at least one second selective material removal process may be performed to remove a first portion of each horizontally extending sacrificial rail in the horizontally extending sacrificial rails 20, and to remove a first portion of each sacrificial isolation trench fill structure 57 near the gap within the volume of the bit line trench 99. A first lateral isolation trench 591 is formed in the volume from which the first portion of the sacrificial isolation trench fill structure 57 has been removed. By removing the first portion of each sacrificial isolation trench fill structure 57, the first lateral isolation trench 591 is formed between the first portions of laterally adjacent pairs of horizontally extending semiconductor rails 10. A first inter-rail cavity 291 is formed in the volume from which the first portion of the sacrificial rails 20 has been removed. By removing the first portion of each horizontally extending sacrificial rail in the horizontally extending sacrificial rails 20, the first inter-rail cavity 291 is formed between the first portions of vertically adjacent pairs of horizontally extending semiconductor rails 10.

[0110] When the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 comprise different materials, at least one second selective material removal process may include a set of two second selective material removal processes, each of which removes a corresponding material selected from the materials of the sacrificial isolation trench fill structure 57 and the sacrificial rail 20. In this case, the removal of material from the sacrificial isolation trench fill structure 57 may occur before or after the removal of material from the sacrificial rail 20. Alternatively, if the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 comprise the same sacrificial material, the removal of material from the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 may be performed simultaneously. Generally, the duration of each second selective material removal process in at least one second selective material removal process may be selected such that the length of each physically exposed surface of the first portion of each semiconductor rail 10 along the first horizontal direction hd1 is on the same order of magnitude as the size of the horizontally extending semiconductor channel of the access transistor to be subsequently formed. For example, the ratio of the length of each first portion of semiconductor rail 10 (i.e., the portion having physically exposed sidewalls, physically exposed top surface and physically exposed bottom surface) along the first horizontal direction hd1 to the length of the entire semiconductor rail 10 along the first horizontal direction may be in the range of 0.05 to 0.6 (such as 0.1 to 0.4), but smaller and larger ratios may also be used.

[0111] refer to Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7EA first gate dielectric material layer 60L is formed by conformal deposition or oxidation of the semiconductor rail 10. The first gate dielectric material layer 60L comprises a first gate dielectric material, such as silicon oxide or a dielectric metal oxide. The thickness of the first gate dielectric material layer 60L can be in the range of 2 nm to 20 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses can also be used.

[0112] A continuous first gate electrode material layer 68L may be conformally deposited on a first gate dielectric material layer 60L. The continuous first gate electrode material layer 68L includes a first gate electrode material, which may include any suitable conductive material. For example, the continuous first gate electrode material layer 68L may include at least one metal barrier layer (such as TiN, TaN, WN, or MoN) and a metal filler layer (such as W, Ti, Ta, Ru, or Mo). The continuous first gate electrode material layer 68L may be formed around each first portion of the horizontally extending semiconductor rail 10. The first gate electrode material of the continuous first gate electrode material layer 68L is deposited as a continuous material layer such that the lateral gaps between the first portions of laterally adjacent pairs of horizontally extending semiconductor rails 10 are filled with the first gate electrode material, while the vertical gaps between the first portions of vertically adjacent pairs of horizontally extending semiconductor rails 10 are not completely filled with the first gate electrode material. Therefore, after the deposition of the first gate electrode material of the continuous first gate electrode material layer 68L, a first lateral extension void 99 extending laterally along the second horizontal direction hd2 exists in the unfilled volume of the vertical gap between the first portions of adjacent pairs of semiconductor rails 10. Lateral extension voids 99' may exist within each bit line trench 99. The etch mask layer can then be removed, for example, by ashing.

[0113] refer to Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E A first dielectric filler material (such as silicon oxide) may be conformally deposited in the first lateral extension void 69, in the peripheral portion of the bit line trench 99, and on the horizontal extension of the continuous first gate electrode material layer 68L overlying the three-dimensional array of semiconductor rails 10. An isotropic recess etching process may be performed to remove portions of the first dielectric filler material from outside the volume of the first lateral extension void 69. The remaining portion of the first dielectric filler material filling the first lateral extension void 69 constitutes a two-dimensional array of first dielectric plates 62. Each first dielectric plate 62 is formed between corresponding vertically adjacent pairs of lateral extensions of the continuous first gate electrode material layer 68L extending laterally along the second horizontal direction hd2.

[0114] refer to Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E A first selective isotropic etching process can be performed to etch a portion of the continuous first gate electrode material layer 68L near or overlying the in-situ trench 99 of the semiconductor rail 10. The first selective isotropic etching process can selectively etch the first gate electrode material relative to the first gate dielectric material. For example, a wet etching process that selectively and isotropically etches the first gate electrode material relative to the first gate dielectric material can be used. The first selective isotropic etching process patterns the continuous first gate electrode material layers 68L into a one-dimensional array of first gate electrode material layers 68S laterally spaced along a first horizontal direction hd1. Each first gate electrode material layer 68S may surround a corresponding two-dimensional array of semiconductor rails 10. For example, each first gate electrode material layer 68S may have a rectangular array of vias through which the corresponding two-dimensional array of semiconductor rails 10 extends laterally along the first horizontal direction hd1, such as... Figure 9D As shown.

[0115] refer to Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E A second selective isotropic etching process can be performed to etch the portion of the first gate dielectric material layer 60L near or overlying the in-situ trench 99 of the first gate dielectric material layer 60L. The second selective isotropic etching process can selectively etch the first gate dielectric material relative to the materials of the semiconductor rails 10 and the first gate electrode material layer 68S. For example, a wet etching process (e.g., a diluted hydrofluoric acid etching process) can be used to selectively and isotropically etch the first gate dielectric material relative to the materials of the semiconductor rails 10 and the first gate electrode material layer 68S. The second selective isotropic etching process patterns the first gate dielectric material layer 60L into a one-dimensional array of first gate dielectric layers 60S laterally spaced along a first horizontal direction hd1. Each first gate dielectric layer 60S may surround a corresponding two-dimensional array of semiconductor rails 10 (e.g., each first gate dielectric layer 60S may have a rectangular array of vias, the corresponding two-dimensional array of semiconductor rails 10 extending laterally along the first horizontal direction hd1 through the rectangular array of vias, such as...). Figure 10D(As shown). Each first gate dielectric layer 60S includes a two-dimensional array of tubular portions having a corresponding rectangular vertical cross-sectional shape (in the case where the cutting plane is perpendicular to the first horizontal direction hd1) and vertical extensions at the ends of the two-dimensional array of tubular portions. If the first dielectric plate 62 comprises the same material as the first gate dielectric layer 60S (e.g., silicon oxide), the tip of the first dielectric plate 62 protruding beyond the end of the first gate electrode material layer 68S along the first horizontal direction hd1 may be thinned during the second selective isotropic etching process.

[0116] refer to Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E Dielectric filler material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in the bit line trench 99. Planarization processes such as chemical mechanical polishing may be performed to remove portions of the dielectric filler material from above a horizontal plane including the top surface of the sacrificial source trench filler structure 47. Each remaining portion of the filled bit line trench 99 with dielectric filler material constitutes a bit line trench isolation structure 94. In one embodiment, the top surface of the bit line trench isolation structure 94 may be formed within a horizontal plane including the top surface of the sacrificial source trench filler structure 47. Laterally alternating sequences of the bit line trench isolation structure 94 and the sacrificial source trench filler structure 47 may be arranged along a first horizontal direction hd1.

[0117] refer to Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E A photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to form a total of L x M openings over the bit line trench isolation structure 94. Each opening in the photoresist layer over the respective bit line trench isolation structure 94 may have area overlap in a plan view with a corresponding vertical stack of (N+1) semiconductor rails 10 and (N+1) interfaces between the bit line trench isolation structure 94. In one embodiment, each vertical stack of (N+1) semiconductor rails 10 includes a topmost semiconductor rail 10 serving as a dummy structure (i.e., a non-functional component) and N underlying semiconductor rails 10 located within a corresponding unit cell UC in a three-dimensional L x M x N array of unit cells.

[0118] An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the bit line trench isolation structure 94 and the first end segment of the semiconductor track 10. A bit line via cavity 95 extending vertically downward to the etch stop structure 8 (if present) can be formed through the bit line trench isolation structure 94. The photoresist layer can then be removed, for example, by ashing.

[0119] As discussed above, instances of the unit cell UC are repeated L times along the first horizontal direction hd1 and M times along the second horizontal direction hd2. Each bitline via cavity can be formed such that the sidewalls of the corresponding vertically stacked (N+1) semiconductor rails 10 are physically exposed to each bitline via cavity. In the presence of L / 2 bitline trench isolation structures 94, a 2 x M rectangular array of bitline via cavities can be formed through each bitline trench isolation structure 94. In the presence of (L / 2+1) bitline trench isolation structures 94, a 2 x M rectangular array of bitline via cavities can be formed through each bitline trench isolation structure 94 that is not the outermost bitline trench isolation structure 94, and a 1 x M rectangular array of bitline via cavities can be formed through each of the two outermost bitline trench isolation structures 94.

[0120] Sacrificial fill material may be deposited in the bit line via cavities, and planarization processes (such as chemical mechanical polishing or recessed etching) may be performed to remove the sacrificial fill material from above a horizontal plane including the topmost surface of the bit line trench isolation structure 94. The filling of each remaining portion of the corresponding bit line via cavity by the sacrificial fill material constitutes a sacrificial bit line structure 93. An L x M two-dimensional array of sacrificial bit line structures 93 may be formed. In exemplary examples, the sacrificial bit line structure 93 may comprise silicon nitride, a carbon-based material, a porous organosilicon glass, a polymer material, or a silicon-germanium compound semiconductor material. In some embodiments, the sacrificial bit line structure 93 may comprise the same material as the sacrificial source trench fill structure 47. Each sacrificial bit line structure 93 contacts the first sidewall of a corresponding vertically stacked (N+1) semiconductor rails 10. In some embodiments, the top portion of the sacrificial bit line structure 93 may be replaced with an etch-stop cap structure to provide protection during the subsequent replacement of a second portion of the semiconductor rails 10 with the memory device 200 described below.

[0121] In an alternative embodiment, if the etch stop structure 8 is omitted, the bit line via cavity 95 may extend vertically downwards to the substrate 2. In this case, the tip of the semiconductor rail 10 is not exposed in the bit line via cavity 95. The exposed portion of the substrate 2 is oxidized to form a semiconductor oxide (e.g., silicon oxide) dielectric etch stop structure at the bottom of the bit line via cavity 95. The width of the bit line via cavity 95 is then expanded by selective etching to expose the tip of the semiconductor rail 10. A sacrificial bit line structure 93 that contacts the tip of the semiconductor rail 10 is then formed in the bit line via cavity 95.

[0122] refer to Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E A third selective material removal process can be performed to selectively remove the sacrificial source trench fill structure 47 relative to the materials of the semiconductor rail 10, the sacrificial rail 20, and the sacrificial isolation trench fill structure 57. In some embodiments, a patterned etch mask layer (not shown) (such as a patterned photoresist layer) can be used to cover the sacrificial bit line structure 93 and prevent the sacrificial bit line structure 93 from being incidentally removed during the removal of the sacrificial source trench fill structure 47. Voids are formed in the source trench 49, i.e., in the volume from which the sacrificial source trench fill structure 47 has been removed.

[0123] refer to Figure 14A , Figure 14B , Figure 14C , Figure 14D and Figure 14E At least one fourth selective material removal process can be performed to remove a second portion (i.e., the remaining portion) of each horizontally extending sacrificial rail in the horizontally extending sacrificial rail 20, and to remove a second portion (i.e., the remaining portion) of each sacrificial isolation trench fill structure 57 near the gap within the volume of the source trench 49. A second lateral isolation trench 592 is formed in the volume from which the second portion of the sacrificial isolation trench fill structure 57 has been removed. By removing the second portion of each sacrificial isolation trench fill structure 57, the second lateral isolation trench 592 is formed between the second portions of laterally adjacent pairs of horizontally extending semiconductor rails 10. A second inter-rail cavity 292 is formed in the volume from which the second portion of the sacrificial rail 20 has been removed. By removing the second portion of each horizontally extending sacrificial rail in the horizontally extending sacrificial rail 20, the second inter-rail cavity 292 is formed between the second portions of vertically adjacent pairs of horizontally extending semiconductor rails 10.

[0124] When the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 comprise different materials, at least one fourth selective material removal process may include a set of two fourth selective material removal processes, each of which removes a corresponding material selected from the materials of the sacrificial isolation trench fill structure 57 and the sacrificial rail 20. In this case, the removal of material from the sacrificial isolation trench fill structure 57 may occur before or after the removal of material from the sacrificial rail 20. Alternatively, if the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 comprise the same sacrificial material, the removal of material from the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 may be performed simultaneously. Generally, the duration of each of the at least one second selective material removal process may be selected such that the entire remainder of the sacrificial isolation trench fill structure 57 and the sacrificial rail 20 is selectively removed relative to the first gate dielectric layer 60S and the semiconductor rail 10. Each semiconductor rail 10 includes a corresponding second portion having a pair of physically exposed sidewalls, a physically exposed top surface, a physically exposed bottom surface, and a physically exposed end surface perpendicular to the first horizontal direction hd1. A two-dimensional M x N array of semiconductor rails 10 laterally protrudes along the first horizontal direction hd1 through an opening in a vertical extension of each first gate dielectric layer 60S. An optional M x 1 array of the topmost semiconductor rail 10 overlays the M x N array of semiconductor rails 10, contacting the vertical extension of each topmost first gate dielectric layer 60U, but not extending through the opening in that vertical extension, as... Figure 14D As shown. The etched mask layer can then be removed, for example, by ashing.

[0125] refer to Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15EA first selective isotropic etching process, such as a first wet etching process, can be performed to selectively etch each vertical extension of the first gate dielectric layer 60S relative to the semiconductor rail 10. The remaining portion of each first gate dielectric layer 60S constitutes a corresponding M x N array of tubular gate dielectrics 60, which are also referred to as first gate dielectrics 60. The remaining portion of each topmost first gate dielectric layer 60S may also constitute a corresponding M x 1 array of additional gate dielectrics contacting the bottom portion of the M x 1 array of the topmost semiconductor rail 10. Each first gate dielectric layer 60S is divided into a corresponding two-dimensional M x N array of first gate dielectrics 60 and additional gate dielectrics. Thus, L first gate dielectric layers 60S are divided into a three-dimensional array of first gate dielectrics 60 with corresponding tubular configurations and a two-dimensional array of additional first gate dielectrics 60U with corresponding U-shaped configurations (which are non-tubular configurations), as shown below. Figure 15D As shown.

[0126] A second selective isotropic etching process, such as a second wet etching process, can be performed to selectively and isotropically recess the first gate electrode material layer 68S relative to the semiconductor rails 10. Optionally, the etching distance may be greater than the first gate electrode material layer 68S extending laterally along the first horizontal direction hd1 at the layer level of the first dielectric substrate 62. Thus, each first gate electrode material layer 68S can be divided into (N+2) discrete conductive material portions. Each of the N discrete conductive material portions patterned from each first gate electrode material layer 68S constitutes a first word line 68, which extends laterally along the second horizontal direction hd2 and laterally surrounds the semiconductor channels of the M semiconductor rails 10 arranged along the second horizontal direction hd2. Thus, each first word line 68 includes an assembly of M first gate electrodes adjacent to each other along the second horizontal direction hd2. The duration of the second selective isotropic etching process can be selected to optimize the gate length of the first word line 68, i.e., the first word line 68 extends laterally along a first horizontal direction hd1, which is the channel direction of the access transistor to be subsequently formed. Each of the first dielectric plates 62 may include a corresponding end surface physically exposed to a corresponding row of second inter-track cavities 292, and may include a corresponding physically exposed top surface segment and a corresponding physically exposed bottom surface segment. Each first gate dielectric 60 having a tubular configuration may include a corresponding set of physically exposed surface segments parallel to the first horizontal direction hd1.

[0127] The remaining portion of each first gate electrode material layer 68S constitutes a vertical stack of N first word lines 68, a bottom conductive strip contacting the bottom surface of the bottom dielectric plate 62, and a top conductive strip contacting the top surface of the top dielectric plate 62. The top semiconductor rail 10 within each vertical stack of (N+1) semiconductor rails 10 can act as a dummy structure and is not used as an active component of the L x M x N cubic three-dimensional array of unit cells. Each first gate electrode material layer 68S is divided into a corresponding vertical stack of N first word lines 68. Therefore, the L first gate electrode material layers 68S are divided into an L x N two-dimensional array of first word lines 68 extending laterally along the second horizontal direction hd2.

[0128] Generally, the first gate dielectric material and the first gate electrode material can be patterned into a three-dimensional array of first gate dielectrics 60 and a two-dimensional array of first word lines 68. Each of the L x M x N first gate dielectrics 60 in the L x M x N array of contact semiconductor rails 10 (excluding the L x M x 1 array of the topmost semiconductor rail 10) may include a corresponding tubular gate dielectric 60, which laterally surrounds a first portion of the corresponding horizontally extending semiconductor rail 10. Each first word line 68 includes M first gate electrodes that are merged along a second horizontal direction and surround a corresponding row of M tubular gate dielectrics 60 in a corresponding vertical cross-sectional view perpendicular to the first horizontal direction hd1, as shown below. Figure 15D As shown. Each tubular gate dielectric 60 includes a top dielectric portion 60T contacting the horizontal top surface of the corresponding horizontally extending semiconductor rail 10, a bottom dielectric portion 60B contacting the horizontal bottom surface of the corresponding horizontally extending semiconductor rail 10, and a pair of sidewall dielectric portions (60X, 60Y) contacting a pair of sidewalls of the corresponding horizontally extending semiconductor rail 10, as shown. Figure 15D As shown. Each of the top dielectric portion, the bottom dielectric portion, and the pair of sidewall dielectric portions is contacted by a first gate electrode, which is part of a corresponding first word line in the first word line 68.

[0129] refer to Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16EA dielectric matrix material layer 42L can be conformally deposited to fill the entire volume of the second lateral isolation trench 592 and the second inter-orbit cavity 292, as well as the peripheral portion of the source trench 49, without filling the central portion of the source trench 49. The dielectric matrix material layer 42L includes a dielectric filling material, such as undoped or doped silicate glass, and can be deposited using conformal deposition processes such as chemical vapor deposition or atomic layer deposition.

[0130] refer to Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E A recessed etching process can be performed to etch the dielectric matrix material layer 42L from around the unfilled volume of the source trench 49 and from above the topmost semiconductor rail 10. The dielectric matrix material layer 42L can be removed from within the volume of the source trench 49. The remaining portion of the dielectric matrix material layer 42L laterally surrounding the second portion of the semiconductor rail 10 constitutes a via dielectric matrix 42. Therefore, the dielectric matrix material layer 42L is patterned into a one-dimensional array of L via dielectric matrices 42 arranged along a first horizontal direction hd1. Each via dielectric matrix 42 within the one-dimensional array of via dielectric matrices 42 includes a corresponding two-dimensional M x N array of vias extending laterally along the first horizontal direction hd1. Each via dielectric matrix 42 is embedded in a corresponding two-dimensional M x N array of the semiconductor rail 10.

[0131] refer to Figure 18A , Figure 18B , Figure 18C , Figure 18D and Figure 18EA selective isotropic etching process can be performed to selectively and isotropically etch the semiconductor material of the semiconductor rail 10 relative to the materials of the through-hole dielectric matrix 42, the first gate dielectric 60, the bit line trench isolation structure 94, and the sacrificial bit line structure 93. For example, if the sacrificial rail 10 comprises silicon, a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH) can be performed to isotropically etch the second portion of the semiconductor rail 10. The duration of the selective isotropic etching process can be selected such that the remaining portion of each semiconductor rail 10 has sufficient channel length. For example, the lateral distance between the physically exposed sidewall of each remaining portion of the semiconductor rail 10 and the nearest sidewall of the first word line 68 can be in the range of 3 nm to 30 nm, but smaller and larger lateral distances can also be used. In one embodiment, the horizontal surface of the first word line 68 is not physically exposed. A lateral recess 19 is formed in the volume from which the second portion of the semiconductor rail 10 has been removed. Generally, a three-dimensional array of lateral recesses 19 can be formed by selectively etching a second portion of the horizontally extending semiconductor rails 10 relative to a one-dimensional array of the perforated dielectric substrate 42. If the etch stop structure 8 is omitted, the portion of the substrate 2 underlying the source trench 49 can also be etched.

[0132] refer to Figure 19A , Figure 19B , Figure 19C , Figure 19D and Figure 19E The sacrificial bitline structure 93 can be selectively removed relative to the bitline trench isolation structure 94 and the through-hole dielectric matrix 42 by performing a selective etching process, which may include an isotropic etching process (such as a wet etching process) or an anisotropic etching process. Alternatively, if the sacrificial bitline structure 93 comprises a carbon-based material, an ashing process may be used to remove the sacrificial bitline structure 93. Voids are formed in the volume of the bitline via cavity 95. Each semiconductor track in the semiconductor track 10 may include a first sidewall exposed in the corresponding bitline via cavity 95 and a second sidewall exposed in the corresponding lateral recess 19.

[0133] refer to Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20EOptional extension region doping processes can be performed to electrically dope the edge portions of the semiconductor rail 10 near the physically exposed sidewall surfaces of the semiconductor rail 10. For example, a vapor phase doping process or an outward diffusion process using a conformally deposited sacrificial doped silicate glass layer (such as a sacrificial phosphosilicate glass layer) can be used to convert the surface portions of the semiconductor rail 10 near the lateral recess 19 into source extension regions 13, and the surface portions of the semiconductor rail 10 near the in-situ via cavity 95 into drain extension regions 15. Each remaining portion of the semiconductor rail 10 that is not converted into source extension regions 13 or drain extension regions 15 constitutes a horizontally extending semiconductor channel 14. In one embodiment, the horizontally extending semiconductor channel 14 may have doping of a first conductivity type, and the source extension regions 13 and drain extension regions 15 may have doping of a second conductivity type opposite to the first conductivity type. The extension regions (13, 15) may include lightly doped regions of the second conductivity type (e.g., n-type). Alternatively, the formation of the source extension region 13 and the drain extension region 15 can be omitted.

[0134] A selective doping semiconductor deposition process can be performed to grow a doped semiconductor material with a second conductivity type of dopant on a first physically exposed semiconductor surface exposed to a lateral recess 19 from a first portion of a horizontally extending semiconductor track 10 and a second physically exposed semiconductor surface exposed to a bit line via cavity 95 from a second physically exposed semiconductor surface of the first portion of the horizontally extending semiconductor track 10. A selective semiconductor deposition process refers to a semiconductor deposition process that grows semiconductor material from physically exposed semiconductor surfaces while suppressing the growth of semiconductor material from dielectric surfaces. In an exemplary example, a chemical vapor deposition process using silane, dichlorosilane, or dichlorosilane as the reactant gas; hydrogen chloride as the reactant gas; and optional carrier gases (such as hydrogen, helium, and / or nitrogen) can be used to selectively grow doped silicon from the physically exposed surfaces of the semiconductor track 10. Dopant gases (such as arsine, phosphine, antimony, or diborane) can flow into the process chamber simultaneously or alternately with the reactant gases to dope the deposited semiconductor material with an electrical dopant of the second conductivity type. Source region 12 is formed on a first sidewall of semiconductor rail 10 located within lateral recess 19, and drain region 16 is formed on a second sidewall of semiconductor rail 10 located within bit line via cavity 95. Source region 12 and drain region 16 may include heavily doped regions of a second conductivity type, having a higher dopant concentration compared to optional extended regions (13, 15). Source region 12 has the same horizontal cross-sectional shape in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1 as the horizontal cross-sectional shape of lateral recess 19 and semiconductor rail 10 in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1. Drain region 16 has different horizontal cross-sectional shapes in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1, these different horizontal cross-sectional shapes varying according to the lateral distance from the nearest side semiconductor rail in semiconductor rail 10.

[0135] In one embodiment, the source region 12 is formed on a first physically exposed semiconductor surface of a first portion of a horizontally extending semiconductor track 10, such that the first physically exposed semiconductor surface is as shown in... Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4EThe processing step is formed within a small volume (i.e., the volume of the lateral recess 19) from which the second portion of the horizontally extending semiconductor track 10 has been removed. Each first portion of the horizontally extending semiconductor track 10 includes a corresponding second physically exposed semiconductor surface located on the opposite side of the corresponding first physically exposed semiconductor surface in the first physically exposed semiconductor surface. A selective semiconductor deposition process grows a drain region 16 on the second physically exposed semiconductor surface of the first portion of the horizontally extending semiconductor track 10. If the etch stop structure 8 is omitted, a doped semiconductor region of a second conductivity type is also formed on the exposed etched portion of the substrate 2.

[0136] A three-dimensional L x M x N array of access field-effect transistors 100 can be formed. Each access field-effect transistor 100 includes a set of semiconductor material portions (12, 13, 14, 15, 16) and a pair of opposing gate electrodes (which are portions of two word lines 68) located above and below the set of semiconductor material portions. The set of semiconductor material portions (12, 13, 14, 15, 16) includes a horizontally extending semiconductor channel 14, a source region 12, and a drain region 16, and can optionally include a source extension region 13 and a drain extension region 15. In one embodiment, the horizontally extending semiconductor channel 14 and the source region 12 have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the horizontally extending semiconductor channel 14 or the source region 12 and is perpendicular to the first horizontal direction hd1, regardless of the position of the vertical cutting plane of the respective vertical cross-sectional view. In one embodiment, the drain region 16 is located on the opposite side of the source region 12 relative to the horizontally extending channel region 14. In one embodiment, the drain region 16 has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction hd1, which varies according to the lateral distance from the horizontally extending semiconductor channel 14.

[0137] refer to Figure 21A , Figure 21B , Figure 21C , Figure 21D and Figure 21E A first conductive material layer 52L and a sacrificial cover material layer 53L can be conformally deposited. The first conductive material layer 52L comprises a highly conductive material, such as a metallic material. For example, the first conductive material layer 52L may include at least one metallic material, such as TiN, TaN, WN, MoN, W, Ru, and / or Mo. The first conductive material layer 52L can be deposited using a conformal deposition process such as chemical vapor deposition or atomic layer deposition. The thickness of the first conductive material layer 52L can range from 2 nm to 40 nm, but smaller and larger thicknesses are also possible.

[0138] The sacrificial cover material layer 53L comprises a material that can subsequently be used as an etch mask material for etching portions of the first conductive material layer 52L. The sacrificial cover material layer 53L may comprise silicon nitride or a dielectric metal oxide material. The sacrificial cover material layer 53L can be deposited using conformal deposition processes such as chemical vapor deposition or atomic layer deposition. The thickness of the sacrificial cover material layer 53L can range from 2 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0139] refer to Figure 22A , Figure 22B , Figure 22C , Figure 22D and Figure 22E An anisotropic etching process can be performed to remove the unmasked portion of the sacrificial cover material layer 53L from outside the volume of the lateral recess 19. The anisotropic etching process may have partially isotropic etching chemistry, such that the portion of the sacrificial cover material layer 53L located in the bit line via cavity 95 can be completely removed, or only a negligible residue of the sacrificial cover material layer 53L remains in the bit line via cavity 95. Each remaining portion of the sacrificial cover material layer 53L retained in the corresponding lateral recess of the lateral recess 19 constitutes a sacrificial cover material portion 53. A three-dimensional L x M x N array of sacrificial cover material portions 53 can be formed.

[0140] refer to Figure 23A , Figure 23B , Figure 23C , Figure 23D and Figure 23E A selective etching process can be performed to selectively etch the material of the first conductive material layer 52L relative to the material of the sacrificial cover material portion 53. For example, the selective etching process may include an isotropic wet etching process that selectively etches the metallic material of the first conductive material layer 52L relative to the material of the sacrificial cover material portion 53. The first conductive material layer 52L can be removed from inside the bit line via cavity 95 and from inside the source trench 49. In some embodiments, residual conductive material portions 52' may be retained on the physically exposed bottom surface of the bit line trench isolation structure 94. The remaining portion of the first conductive material layer 52L may constitute a three-dimensional L x M x N array of conductive material layers forming the first electrode 52 of the memory device 200 (described below) of an embodiment of the present disclosure. As used herein, memory device 200 refers to any volatile or non-volatile memory device capable of storing data. In a first embodiment, memory device 200 includes a capacitor or resistor. Preferably, the capacitor includes a ferroelectric capacitor that can store data based on the ferroelectric polarization direction of the memory material layer (e.g., the capacitor ferroelectric dielectric material).

[0141] In one embodiment, the three-dimensional L x M x N array of the first electrodes 52 can be completely formed within the volume of the three-dimensional L x M x N array of the lateral recess 19. In one embodiment, each first electrode 52 includes: an end conductive plate 52E, the end conductive plate being perpendicular to a first horizontal direction hd1; a top conductive plate 52T, the top conductive plate being adjacent to the top of the end conductive plate 52E and extending laterally along the first horizontal direction hd1; and a bottom conductive plate 52B, the bottom conductive plate being adjacent to the bottom of the end conductive plate 52E and extending laterally along the first horizontal direction hd1. In one embodiment, for each contact combination of a set of semiconductor material portions (12, 13, 14, 15, 16) and the first electrode 52, the top surface of the set of semiconductor material portions (12, 13, 14, 15, 16) and the top surface of the top conductive plate 52T are located in a first horizontal plane, and the bottom surface of the set of semiconductor material portions (12, 13, 14, 15, 16) and the bottom surface of the bottom conductive plate 52B are located in a second horizontal plane, as shown below. Figure 23A As shown.

[0142] exist Figure 23B In one embodiment shown, each first electrode 52 includes: an end conductive plate 52E, which is perpendicular to a first horizontal direction hd1; a first conductive sidewall plate 52X, which is adjacent to a first vertically extending edge of the end conductive plate 52E and extends laterally along the first horizontal direction hd1; and a second conductive sidewall plate 52Y, which is adjacent to a second vertically extending edge of the end conductive plate 52E and extends laterally along the first horizontal direction hd1. In one embodiment, for each contact combination of a set of semiconductor material portions (12, 13, 14, 15, 16) and the first electrode 52, the outer sidewall of the first sidewall of the set of semiconductor material portions (12, 13, 14, 15, 16) and the outer sidewall of the first conductive sidewall plate 52X are located in a first vertical plane parallel to the first horizontal direction hd1; and the outer sidewall of the second sidewall of the set of semiconductor material portions (12, 13, 14, 15, 16) and the outer sidewall of the second conductive sidewall plate 52Y are located in a second vertical plane parallel to the first horizontal direction hd1.

[0143] In one embodiment, for each contact combination of a set of semiconductor material portions (12, 13, 14, 15, 16) and a first electrode 52, the first electrode 52 has a vertical extension not greater than the vertical extension of a horizontally extending semiconductor channel 14 within the set of semiconductor material portions (12, 13, 14, 15, 16), and the first electrode 52 has a lateral extension not greater than the lateral extension of the horizontally extending semiconductor channel 14 along a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1. In one embodiment, the set of semiconductor material portions (12, 13, 14, 15, 16) includes a source region 12 in contact with the first electrode 52.

[0144] refer to Figure 24A , Figure 24B , Figure 24C , Figure 24D and Figure 24E At least one memory material layer 54 may be formed. Specifically, a continuous memory material layer may be conformally deposited on the physically exposed surface of the first exemplary structure. As used herein, “memory material” means any material or group of materials in which data may be stored. Memory materials may store information in the form of changes in the direction of ferroelectric polarization, changes in the amount of charge carriers (e.g., electrons) stored therein, or changes in the resistance of the material.

[0145] Generally, the memory material layer can be conformally deposited directly onto the physically exposed surface of the first electrode 52 as a continuous material layer. A photoresist layer 43 can be applied over the first exemplary structure and can be photolithographically patterned to cover the source trench 49 but not the bit line via cavity 95. The unmasked portions of the continuous memory material layer can be etched back and forth by performing an etch-back process. The remaining portions of the continuous memory material layer constitute memory material layers comprising two M x N arrays of memory layers 54. Each memory layer 54 includes a portion of the continuous memory material layer located within a corresponding lateral recess in the lateral recess 19. The photoresist layer 43 can then be removed, for example, by ashing.

[0146] In one embodiment, memory layer 54 comprises a ferroelectric dielectric material. In this case, memory device 200 includes non-volatile capacitors that provide variable capacitance depending on the direction of ferroelectric polarization within the ferroelectric dielectric material. Non-limiting examples of ferroelectric dielectric materials include titanate ferroelectric dielectric materials such as barium titanate, lead titanate, lead zirconate titanate, lanthanum lead zirconate titanate (PLZT), potassium niobate (KNbO3), sodium potassium niobate (KNN), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), and bismuth ferrite (BiFeO3). Other ferroelectric dielectric materials include strontium bismuth tantalate (SBT), polyvinylidene fluoride (PVDF) and its copolymers, zirconium oxide (ZrO2), hafnium oxide (HfO2), and their doped variants (such as zirconium-doped hafnium oxide (HZO), aluminum-doped hafnium oxide (HfAlO), and lanthanum-doped hafnium oxide (HfLaO)). Generally speaking, any suitable ferroelectric dielectric material can be used for memory layer 54.

[0147] In another embodiment, memory layer 54 includes a material that can provide a variable resistor having at least two programmable states offering different resistance values. In one embodiment, the memory material may include any material selected from: filamentary resistive dielectric materials, oxygen-vacancy-modulated resistive dielectric materials, phase-change materials, or polymeric materials exhibiting resistive switching properties. Non-limiting examples of filamentary resistive dielectric materials include tantalum oxide (TaO). x ), hafnium oxide (HfO) x Non-ferroelectric phases, such as titanium dioxide (TiO2), are examples. Non-limiting examples of oxygen vacancy-modulated resistive dielectric materials include strontium ruthenium ruthenium oxide (SrRuO3), lanthanum strontium manganese oxide (LaSrMnO3), and praseodymium calcium manganese oxide (PrCaMnO3). Non-limiting examples of phase change materials include chalcogenide semiconductor materials such as germanium antimony tellurium (Ge2Sb2Te5), antimony telluride (Sb2Te3), and gallium antimonide (GaSb). Non-limiting examples of polymer materials exhibiting resistive switching properties include polyvinyl alcohol (PVA), polyaniline (PANI), and poly(3,4-ethylenedioxythiophene)polystyrene sulfonic acid (PEDOT:PSS). Additionally, other materials used in resistive switching applications include binary metal oxides such as zinc oxide (ZnO) and nickel oxide (NiO), and composite oxides such as barium strontium titanate (BST) and lead zirconate titanate (PZT). Generally, any resistive memory material known in the art can be used as the material for memory layer 54. In this case, memory device 200 includes a variable resistor.

[0148] In another embodiment, memory layer 54 includes a charge storage material layer, such as silicon oxide, silicon nitride, silicon oxynitride, or dielectric metal oxide. These materials store charge (e.g., electrons) supplied from the source or drain of a corresponding access transistor 100. In this case, memory device 200 includes a capacitor for a volatile dynamic random access (DRAM) memory device, which includes an access transistor and a charge storage capacitor electrically connected to the source or drain (e.g., source 12) of access transistor 100.

[0149] refer to Figure 25A , Figure 25B , Figure 25C , Figure 25D and Figure 25E The second conductive material layer 98L may be deposited in the remaining volume of the lateral recess 19, in the source trench 49, in the bit line via cavity 95, and on the topmost surface of the through-hole dielectric matrix 42 and the bit line trench isolation structure 94. The second conductive material layer 98L may include at least one conductive material, such as a metal barrier material and a metal filler material. Exemplary metal barrier materials include TiN, TaN, WN, and / or MoN. Exemplary metal filler materials include W, Co, Ru, Mo, Ti, Ta, Cu, etc.

[0150] refer to Figure 26A , Figure 26B , Figure 26C , Figure 26D and Figure 26E The second conductive material layer 98L can be patterned into a one-dimensional array of vertical bit lines 98 and conductive structures 48A. Each conductive structure 48A includes a vertical conductive wall structure 48W filling a corresponding source trench 49 and at least one M x N array of conductive lateral protrusions projecting laterally into a corresponding lateral recess 19. Each conductive lateral protrusion within the conductive structure 48A constitutes a second electrode 48. Each volume of the unit cell UC may include a corresponding portion of the conductive wall structure 48W and a corresponding second electrode 48. Each conductive structure 48A located between a pair of two-dimensional M x N arrays of the access field-effect transistor 100 may include two M x N arrays of the second electrode 48.

[0151] Each adjacent combination of the first electrode 52, the memory layer 54, and the second electrode 48 constitutes a memory device 200. The memory layer 54 is located between the first electrode 52 and the second electrode 48. The memory layer 54 may surround the horizontally extending first electrode 52, and the second electrode 48 may surround the memory layer 54. The second electrode 48 is electrically connected to a vertical conductive wall structure 48W (e.g., a vertical write line). The first electrode 52 is connected to the source 12 of the access transistor 100. The drain region 16 of the access transistor 100 is electrically connected to a vertical bit line 98 (e.g., a vertical read line). In a first embodiment, the memory device 200 includes a two-terminal device, such as a ferroelectric capacitor, a charge storage capacitor, or a variable resistor. A three-dimensional L x M x N array of the two-terminal memory device 200 fills a three-dimensional array of lateral recesses 19. Each memory device 200 is electrically connected in series with a laterally adjacent access field-effect transistor in the three-dimensional array of the memory device and the access field-effect transistor 100.

[0152] Generally, a one-dimensional array of conductive structures 48A arranged along a first horizontal direction hd1 can be formed. Each conductive structure in the conductive structure 48A includes a corresponding conductive wall structure 48W extending laterally along a second horizontal direction hd2, and also includes a corresponding two-dimensional array of conductive lateral protrusions (i.e., second electrodes 48) in the unfilled volume of a corresponding two-dimensional array (which is a corresponding subset of the three-dimensional array of the lateral recess 19) that laterally protrudes from the conductive wall structure 48W along the first horizontal direction hd1 after the formation of the memory material layer. In one embodiment, each memory material layer in the memory material layer may include at least one M x N array of memory layers 54 interconnected with each other through vertically extending portions of the corresponding memory material layers. The second portion of the horizontally extending semiconductor rail 10 is replaced by a three-dimensional array of instances of memory devices 200. Each memory device 200 includes a first electrode 52, a second electrode 48, and a memory layer 54 located between the first electrode 52 and the second electrode 48.

[0153] exist Figure 26F and Figure 26G In an alternative configuration of the first embodiment shown, the vertical conductive wall structure 48W portion of the conductive structure 48A is replaced with a vertical write line 48WL embedded in the capacitor trench isolation structure 44C. The capacitor trench isolation structure 44C can be... Figures 11A to 11E The bitline trench isolation structure 94 in the steps shown is formed simultaneously. For example... Figures 12A to 12EAs shown, while forming the bit line cavity 95 through the bit line trench isolation structure 94, a capacitor via cavity can be formed through the capacitor trench isolation structure 44C. A second conductive material layer 98L can also be deposited into the capacitor via cavity and then patterned to form vertical bit lines 98 and vertical write lines 48WL, as described above relative to... Figures 26A to 26E As described. The vertical write line 48WL is similar to Figures 39A to 39E The vertical source line 46 is shown and will be described below with respect to the second embodiment.

[0154] Common Reference Figures 1A to 26G Furthermore, according to various embodiments of this disclosure, the device structure includes a three-dimensional array of unit cells, the three-dimensional array of unit cells comprising a vertical stack of unit cells UC arranged along a vertical direction (e.g., perpendicular to the top surface of the underlying substrate 2). Each unit cell UC includes: an access field-effect transistor 100 having a set of semiconductor material portions (12, 13, 14, 15, 16) including a horizontally extending semiconductor channel 14; and a memory device 200 having a first electrode 52 electrically connected to the sidewalls of the set of semiconductor material portions (12, 13, 14, 15, 16), a second electrode 48 spaced apart from the access field-effect transistor 100, and a memory layer 54 located between the first electrode 52 and the second electrode 48.

[0155] In one embodiment, the first electrode 52 physically contacts the sidewalls of the group of semiconductor material portions (12, 13, 14, 15, 16). In one embodiment, the first electrode 52 includes: an end conductive plate 52E, the end conductive plate being perpendicular to a first horizontal direction hd1; a top conductive plate 52T, the top conductive plate being adjacent to the top of the end conductive plate and extending laterally along the first horizontal direction hd1; and a bottom conductive plate 52B, the bottom conductive plate being adjacent to the bottom of the end conductive plate and extending laterally along the first horizontal direction hd1; a first conductive sidewall plate 52X, the first conductive sidewall plate being adjacent to a first vertically extending edge of the end conductive plate and extending laterally along the first horizontal direction hd1; and a second conductive sidewall plate 52Y, the second conductive sidewall plate being adjacent to a second vertically extending edge of the end conductive plate and extending laterally along the first horizontal direction hd1.

[0156] In one embodiment, the top surface of the set of semiconductor material portions (12, 13, 14, 15, 16) and the top surface of the top conductive plate 52T are located in a first horizontal plane; and the bottom surface of the set of semiconductor material portions (12, 13, 14, 15, 16) and the bottom surface of the bottom conductive plate 52B are located in a second horizontal plane. In one embodiment, the first sidewall of the set of semiconductor material portions (12, 13, 14, 15, 16) and the outer sidewall of the first conductive sidewall plate 52X are located in a first vertical plane parallel to the first horizontal direction hd1; and the second sidewall of the set of semiconductor material portions (12, 13, 14, 15, 16) and the outer sidewall of the second conductive sidewall plate 52Y are located in a second vertical plane parallel to the first horizontal direction hd1.

[0157] In one embodiment, the group of semiconductor material portions (12, 13, 14, 15, 16) further includes a source region 12 in contact with the first electrode 52, and a drain region 16 located on the opposite side of the horizontally extending channel 14 relative to the source region 12. In one embodiment, the horizontally extending semiconductor channel 14 and the source region 12 have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the horizontally extending semiconductor channel 14 or the source region 12 and is perpendicular to the first horizontal direction hd1, regardless of the position of the vertical cutting plane of the respective vertical cross-sectional view. In one embodiment, the drain region 16 has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction hd1 that varies according to the lateral distance from the horizontally extending semiconductor channel 14.

[0158] In one embodiment, the access field-effect transistor 100 further includes a tubular gate dielectric 60 that laterally surrounds the horizontally extending semiconductor channel 14 and extends laterally along a first horizontal direction hd1. In one embodiment, the access transistor 100 also includes a gate electrode that surrounds the tubular gate dielectric 60 in a vertical cross-sectional view perpendicular to the first horizontal direction hd1. The gate electrode includes a portion of a word line 68 that extends laterally along a second horizontal direction.

[0159] In one embodiment, the tubular gate dielectric 60 includes a top dielectric portion 60T that contacts a horizontal top surface of a horizontally extending semiconductor channel 14, a bottom dielectric portion 60B that contacts a horizontal bottom surface of a horizontally extending semiconductor channel 14, and a pair of sidewall dielectric portions (60X, 60Y) that contact a pair of sidewalls of a horizontally extending semiconductor channel 14; and each of the top dielectric portion, the bottom dielectric portion, and the pair of sidewall dielectric portions is contacted by a gate electrode (which is part of a word line 68).

[0160] In one embodiment, the vertical bit line 98 contacts the drain region 16 of the corresponding vertical stack in the vertical stack, and the vertical write lines (48W, 48WL) are electrically connected to the second electrode 48 of the corresponding vertical stack in the vertical stack.

[0161] In one embodiment, the three-dimensional array of the instances of the unit cells UC is arranged to provide: M rows of corresponding unit cells UC arranged along a second horizontal direction hd2, which is different from the first horizontal direction hd1; L columns of corresponding unit cells UC arranged along the first horizontal direction hd1; and vertical stacks of corresponding unit cells UC arranged along the vertical direction (i.e., a corresponding set of N unit cells).

[0162] In one embodiment, the device structure further includes a two-dimensional array of vertical bit lines 98 and vertical write lines (48W, 48WL). Each vertical bit line in the vertical bit lines 98 contacts a set of drain regions 16 located within a corresponding vertical stack in the vertical stack of the unit cell UC; each vertical write line in the vertical write lines (48W, 48WL) includes a vertical conductive wall structure 48W extending laterally along a second horizontal direction hd2; and each second electrode in the second electrodes 48 includes a conductive lateral protrusion projecting laterally from the conductive wall structure 48W along a first horizontal direction hd1.

[0163] In one embodiment, the memory device 200 is a ferroelectric capacitor, and the memory layer 54 comprises a ferroelectric dielectric material. In another embodiment, the memory device 200 is a charge storage capacitor, and the memory layer 54 comprises a charge storage dielectric material. In yet another embodiment, the memory device 200 is a variable resistor, and the memory layer 54 comprises a material selected from: filamentary resistive dielectric material; oxygen vacancy modulation resistive dielectric material; phase change material; or polymer material exhibiting resistive switching characteristics.

[0164] In one embodiment, the first electrode 52 has a vertical extension not greater than the vertical extension of the horizontally extending semiconductor channel 14; and the first electrode 52 has a lateral extension not greater than the lateral extension of the horizontally extending semiconductor channel 14 along a second horizontal direction hd2, the second horizontal direction hd2 being perpendicular to the first horizontal direction hd1.

[0165] refer to Figure 27A , Figure 27B , Figure 27C , Figure 27D and Figure 27E By omitting references Figures 12A to 12E The described processing steps and by executing the reference Figures 13A to 13E The described processing steps can be found from Figures 11A to 11EThe first exemplary structure shown derives a second exemplary structure according to a second embodiment of the present disclosure. Therefore, a bit-line trench isolation structure 94 is formed, and the sacrificial source trench fill structure 47 is removed.

[0166] refer to Figure 28A , Figure 28B , Figure 28C , Figure 28D and Figure 28E Executable reference Figures 14A to 14E The described processing steps form a second inter-track cavity 292 and a second lateral isolation trench 592. The second inter-track cavity 292 can be formed between vertically adjacent pairs of horizontally extending semiconductor tracks 10 by removing a second portion (i.e., the remaining portion) of each horizontally extending sacrificial track 20. The second lateral isolation trench 592 can be formed between laterally adjacent pairs of horizontally extending semiconductor tracks 10 by removing a second portion (i.e., the remaining portion) of each sacrificial isolation trench fill structure 57.

[0167] refer to Figure 29A , Figure 29B , Figure 29C , Figure 29D and Figure 29E Executable reference Figures 15A to 15E The described processing steps involve patterning a one-dimensional array of the first gate dielectric layer 60S into a three-dimensional array of the first gate dielectric 60, i.e., a three-dimensional L x M x N array of the first tubular gate dielectric 60, and patterning a one-dimensional array of the first gate electrode material layer 68S into a two-dimensional array of the first word lines 68, i.e., a two-dimensional L x N array of the first word lines 68. Each first word line 68 includes a corresponding row of first gate electrodes (i.e., M first gate electrodes merged together) arranged along a second horizontal direction hd2. Each first gate dielectric 60 has a first tubular configuration and laterally surrounds a first portion of a correspondingly horizontally extending semiconductor channel 14, and laterally extends along a first horizontal direction hd1. Each first gate electrode includes a corresponding portion of the first word line 68 laterally extending along the second horizontal direction hd2. Each first gate electrode surrounds a corresponding first tubular gate dielectric 60 in a vertical cross-sectional view perpendicular to the first horizontal direction hd1.

[0168] refer to Figure 30A , Figure 30B , Figure 30C , Figure 30D and Figure 30EOptionally, a doping process can be performed to electrically dope the second portion of the semiconductor rail 10 exposed to the combination of the second inter-rail cavity 292 and the second lateral isolation trench 592. For example, a vapor-phase doping process or an outward diffusion process using a conformally deposited sacrificial doped silicate glass layer (such as a sacrificial phosphosilicate or borosilicate glass layer) can be used to convert the second portion of the semiconductor rail 10 laterally surrounded by the combination of the second inter-rail cavity 292 and the second lateral isolation trench 592 into having the same characteristics as described in the reference. Figures 4A to 4E The described processing steps provide semiconductor channel portions of semiconductor rails 10 with different atomic concentrations of dopant. Each semiconductor rail 10 has a dopant concentration similar to that initially in the reference... Figures 4A to 4E The portion of electrically doped with the same atomic concentration provided at the described processing steps is referred herein as the first semiconductor channel 14 or the first horizontally extended semiconductor channel 14. The portion of each semiconductor track 10 having electrically doped with an atomic concentration modified by a conformal doping process is referred herein as the second semiconductor channel 34 or the second horizontally extended semiconductor channel 34.

[0169] In an exemplary example, the first horizontally extended semiconductor channel 14 may include doping of a first conductivity type and may include an atomic concentration of 1 x 10⁻⁶. 14 / cm 3 Up to 3 x 10 16 / cm 3 The first conductivity type of electrical dopant can be used within the range of [specific range], but smaller and larger atomic concentrations are also possible. The second horizontally extended semiconductor channel 34 may have doping of the first conductivity type and may include atomic concentrations in the range of 1 x 10[specific range] ... 15 / cm 3 Up to 3 x 10 17 / cm 3 The first type of electrical dopant can be used within the range of conductivity, but smaller and larger atomic concentrations can also be used. Therefore, the first horizontally extended semiconductor channel 14 can have a lower doping concentration compared to the second horizontally extended semiconductor channel 14.

[0170] Generally, a first horizontally extending semiconductor channel 14 exists within a first portion of each semiconductor rail 10 laterally surrounded by a corresponding first gate electrode (which includes a corresponding portion of a first word line 68), and a second horizontally extending semiconductor channel 34 exists within a second portion of each semiconductor rail 10 laterally surrounded by a combination of a second inter-rail cavity 292 and a second lateral isolation trench 592. The second horizontally extending semiconductor channel 34 contacts the first horizontally extending semiconductor channel 14 within each semiconductor rail 10. When a doping process is performed, the second horizontally extending semiconductor channel 34 and the first horizontally extending semiconductor channel 14 within each semiconductor rail 10 comprise the same semiconductor material but include electrically dopants of different atomic concentrations.

[0171] refer to Figures 30A to 30E The described doping process is optional and can therefore be omitted. When the doping process is omitted, the second horizontally extending semiconductor channel 34 and the first horizontally extending semiconductor channel 14 have the same material composition. In this case, the second horizontally extending semiconductor channel 34 and the first horizontally extending semiconductor channel 14 within each semiconductor rail 10 are composed of the same semiconductor material and therefore include the same type of electrical dopant with the same atomic concentration.

[0172] Generally speaking, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the first horizontally extending semiconductor channel 14 or the second horizontally extending semiconductor channel 34 and is perpendicular to the first horizontal direction hd1, regardless of the position of the vertical cutting plane of the corresponding vertical cross-sectional view. In other words, each semiconductor rail as a whole can have the same vertical cross-sectional shape in any vertical cross-sectional view that cuts through the semiconductor rail 10 and is perpendicular to the first horizontal direction hd1, regardless of the position of the vertical cutting plane of the corresponding cross-sectional view.

[0173] refer to Figure 31A , Figure 31B , Figure 31C , Figure 31D and Figure 31EA second gate dielectric material can be conformally deposited to form a second gate dielectric material layer 30L. For example, a chemical vapor deposition process or an atomic layer deposition process can be used to deposit the second gate dielectric material layer 30L. The thickness of the second gate dielectric material layer 30L can be in the range of 2 nm to 40 nm, but smaller and larger thicknesses can also be used. The second gate dielectric material layer 30L is deposited as a continuous material layer directly on the first sidewall of the two-dimensional L x N array of the first word line 68 perpendicular to the first horizontal direction hd1, directly on the physically exposed first sidewall, physically exposed top surface section and physically exposed bottom surface section of the two-dimensional L x N array of the first dielectric plate 62, and directly on the length sidewall, top surface, bottom surface and end surface of the second horizontally extending semiconductor channel 34 of the three-dimensional L x M x N array of the semiconductor rail 10. The second gate dielectric material layer 30L can be deposited in the second inter-rail cavity 292 and around the second portion of each horizontally extending semiconductor rail in the horizontally extending semiconductor rail 10.

[0174] According to one aspect of this disclosure, the second gate dielectric material comprises a ferroelectric or charge-trapping dielectric material having at least two programmable states. In one embodiment, the second gate dielectric material comprises or is substantially composed of the ferroelectric dielectric material described above. In one embodiment, the second gate dielectric material comprises a layer stack including a ferroelectric dielectric material layer and a non-ferroelectric dielectric material layer. In another embodiment, the second gate dielectric material comprises or is substantially composed of a charge-trapping dielectric material such as silicon nitride or silicon oxide, or a stack of silicon nitride and silicon oxide sublayers. In one embodiment, the second gate dielectric material layer 30L contacts the sidewall of the first gate electrode of each access field-effect transistor (which includes a first semiconductor channel 14, a first tubular gate dielectric 60, and a corresponding adjacent combination of a first gate electrode as part of a first word line 68) within a three-dimensional L x M x N array of access field-effect transistors.

[0175] refer to Figure 32A , Figure 32B , Figure 32C , Figure 32D and Figure 32EA dielectric gate spacer material (such as silicon nitride, silicon oxide, silicate glass, or dielectric metal oxide) can be conformally deposited to form a dielectric gate spacer material layer 35L. Therefore, the dielectric gate spacer material is deposited as a continuous material layer on the second gate dielectric material. The sum of the thickness of the second gate dielectric material layer 30L and the thickness of the dielectric gate spacer material layer 35L is greater than half the lateral spacing between adjacent pairs of semiconductor rails 10 spaced apart along the second horizontal direction hd2. Therefore, the dielectric gate spacer material fills the gap between the second portions of the second laterally adjacent pairs of the horizontally extending semiconductor rails 10.

[0176] According to one aspect of this disclosure, the dielectric gate spacer material of the dielectric gate spacer material layer 35L is deposited as a continuous material layer, such that the lateral gaps between the second portions of laterally adjacent pairs of horizontally extending semiconductor rails 10 are filled with dielectric gate spacer material, while the vertical gaps between the second portions of vertically adjacent pairs of horizontally extending semiconductor rails 10 are not completely filled with dielectric gate spacer material. Therefore, after the deposition of the dielectric gate spacer material of the dielectric gate spacer material layer 35L, a second laterally extending void 67 extending laterally along the second horizontal direction hd2 exists in the unfilled volume of the vertical gaps between the second portions of adjacent pairs of semiconductor rails 10. Laterally extending voids 49' may exist within each source trench 49.

[0177] refer to Figure 33A , Figure 33B , Figure 33C , Figure 33D and Figure 33E A two-dimensional L x N array of second dielectric plates 66 can be formed. The second dielectric plates 66 are formed between the lateral extensions of the dielectric gate spacer material layer 35L by conformally depositing a dielectric filler material and isotropically or anisotropically recessing the dielectric filler material. The remaining portion of the dielectric filler material constitutes the second dielectric plates 66. Specifically, a second dielectric filler material (such as silicon oxide or silicon carbonitride) different from the material of the dielectric gate spacer material layer 35L can be conformally deposited in the second lateral extension voids 67, deposited in the peripheral portion of the source trench 49, and deposited on the horizontal extension of the dielectric gate spacer material layer 35L overlying the three-dimensional array of semiconductor rails 10. An isotropic or anisotropic recess etching process can be performed to remove portions of the second dielectric filler material from outside the volume of the second lateral extension voids 67. The remaining portion of the second dielectric filler material filling the second lateral extension voids 67 constitutes the two-dimensional array of the second dielectric plates 66. Each second dielectric plate 66 is formed between the lateral extension portions of corresponding vertically adjacent pairs of dielectric gate spacer material layers 35L that extend laterally along the second horizontal direction hd2.

[0178] refer to Figure 34A , Figure 34B , Figure 34C , Figure 34D and Figure 34E A selective isotropic etching process can be performed to selectively recess the dielectric gate spacer material layer 35L with respect to the materials of the second dielectric substrate 66 and the second gate dielectric material layer 30L. The gate cavity 39 is formed by selectively and isotropically etching a first portion of the dielectric gate spacer material with respect to both the second gate dielectric material and the second dielectric substrate 66. For example, if the dielectric gate spacer material layer 35L comprises silicon nitride, a wet etching process using hot phosphoric acid can be performed to laterally recess the dielectric gate spacer material layer 35L with respect to the silicon oxide second dielectric substrate 66.

[0179] During the selective isotropic etching process, a second portion of the dielectric gate spacer material is not removed. Specifically, the duration of the selective isotropic etching process can be selected such that the remaining vertically extending portions of the dielectric gate spacer material layer 35L remain around each two-dimensional M x N array of semiconductor rails 10 and around each vertical stack of N second dielectric plates 66. Each remaining vertically extending portion of the dielectric gate spacer material layer 35L constitutes the dielectric gate spacer 35.

[0180] According to one aspect of this disclosure, the entirety of each sidewall of the second dielectric plate 66 perpendicular to the first horizontal direction hd1 and not directly exposed to the corresponding source trench 49 is contacted by a corresponding dielectric gate spacer 35. Each dielectric gate spacer 35 contacts the corresponding vertically stacked sidewalls of N second dielectric plates 66 and laterally surrounds a corresponding two-dimensional M x N array of the second horizontally extending semiconductor channel 34. Generally, the two-dimensional M x N array of semiconductor rails 10 extends laterally through the M x N array through the opening of the dielectric gate spacer 35.

[0181] Gate cavities 39 are formed within the combined volume of the second lateral isolation trench 592 and the second inter-rail cavity 292. A vertical stack of N gate cavities 39 is formed around each two-dimensional M x N array of semiconductor rails 10. In the second exemplary structure, the topmost semiconductor rail 10 (i.e., the L x M two-dimensional array of the topmost semiconductor rail 10) is not used to form a three-dimensional L x M x N array of unit cells UC, and the space laterally surrounding the topmost semiconductor rail 10 is not considered part of the vertical stack of gate cavities 39. Each gate cavity 39 laterally surrounds a corresponding one-dimensional array of M semiconductor rails 10 arranged along the second horizontal direction hd2.

[0182] refer to Figure 35A , Figure 35B , Figure 35C , Figure 35D and Figure 35E The second gate electrode material can be conformally deposited in the gate cavity 39, in the peripheral region of the source trench 49, and on the topmost semiconductor rail 10. The second gate electrode material can include any gate electrode material known in the art. For example, the second gate electrode material can include at least one metallic material, such as TiN, TaN, WN, MoN, W, Ru, and / or Mo. The entire volume of each gate cavity 39 can be filled with the second gate electrode material.

[0183] An isotropic recess etching process (such as a wet etching process) can be performed to selectively etch the second gate electrode material relative to the materials of the second gate dielectric material layer 30L and the second dielectric substrate 66. For example, a wet etching process can be performed to selectively etch a metal material relative to the dielectric material. The duration of the isotropic recess etching process can be selected such that the recessed surface of the remaining portion of the second gate electrode material is formed on the horizontal surface of the second dielectric substrate 66. The remaining portion of the second gate electrode material constitutes a second word line 38. Each second word line 38 may include an adjacent assembly of M second gate electrodes extending along a second horizontal direction hd2 and laterally surrounding a corresponding second horizontally extending semiconductor channel in a second horizontally extending semiconductor channel 34. A two-dimensional L x N array forming the second word lines 38 includes a three-dimensional L x M x N array of second gate electrodes for a three-dimensional L x M x N array of memory field-effect transistors 300.

[0184] Subsequently, a selective etching process can be performed to selectively remove physically exposed portions of the second gate dielectric material layer 30L relative to the materials of the semiconductor rail 10 and the second word line 38. Each remaining patterned portion of the second gate dielectric material layer 30L constitutes a second gate dielectric layer laterally surrounding a corresponding M x N array of the second horizontally extending semiconductor channel 34. A total of L second gate dielectric layers can be formed. Each portion of the second gate dielectric layer within the volume of a corresponding unit cell UC constitutes a second gate dielectric 30. Thus, each second gate dielectric layer may include a corresponding M x N array of second gate dielectrics 30. Each second gate dielectric 30 includes a tubular portion laterally surrounding the corresponding second horizontally extending semiconductor channel 34 and a vertically extending portion contacting the sidewall of the corresponding first gate electrode (which is part of the corresponding first word line 68). Each memory field-effect transistor 300 can store data bits by programming the ferroelectric polarization direction or by injecting charge carriers (e.g., electrons injected using Fowler-Nordheim tunneling or hot carrier injection) into the second gate dielectric material layer 30L.

[0185] As shown in Figure 35W, each second gate electrode 38 surrounds a corresponding second gate dielectric 30 in a vertical cross-sectional view perpendicular to the first horizontal direction hd1. The sidewall of each second gate dielectric 30 contacts the sidewall of the first gate electrode 38. In one embodiment, each interface between the sidewall of the second gate dielectric 30 and the sidewall of the corresponding first gate electrode (which is part of the first word line 68) is perpendicular to the first horizontal direction hd1. In one embodiment, each first gate dielectric 60 may contact a corresponding second gate dielectric 30. In one embodiment, each interface between the first gate dielectric 60 and the second gate dielectric 30 includes a horizontal surface segment and a vertical surface segment parallel to the first horizontal direction hd1.

[0186] In one embodiment, each second gate dielectric 30 includes a portion having a second tubular configuration and laterally surrounding a corresponding second horizontally extending semiconductor channel 34 and extending laterally along a first horizontal direction hd1. Two-dimensional M x N arrays of the second gate dielectrics 30 may be interconnected to form a second gate dielectric layer, which is a continuous material layer. L two-dimensional M x N arrays of the second gate dielectrics 30 comprise a three-dimensional L x M x N array of the second gate dielectrics 30. The L x M x N array of the unit cell UC comprises a three-dimensional memory array. Each second gate dielectric 30 within the three-dimensional memory array is a portion of a corresponding continuous gate dielectric layer (such as a second gate dielectric layer) that laterally extends along a second horizontal direction hd2 and contacts the first gate electrode of each access field-effect transistor within a corresponding row of unit cells UC. In one embodiment, each second gate dielectric 30 within the three-dimensional memory array is a portion of a corresponding continuous gate dielectric layer (such as a second gate dielectric layer) that contacts the first gate electrode of each access field-effect transistor within a corresponding vertical stack of unit cells UC.

[0187] In one embodiment, the two-dimensional array of second dielectric plates 66 may be arranged along a first horizontal direction hd1 and along a vertical direction. In one embodiment, each second dielectric plate 66 contacts the top surface of a corresponding lower second word line 38 including a first row (i.e., lower row) of second gate electrodes and contacts the bottom surface of a corresponding upper second word line 38 including a second row (i.e., upper row) of second gate electrodes. Dielectric gate spacers 35 are located between corresponding first word lines in the first word lines 68 and corresponding second word lines 38 (which include a corresponding row of second gate electrodes). Each dielectric gate spacer 35 may contact the sidewall of a corresponding row of second gate electrodes and may be laterally spaced from a corresponding row of second gate dielectrics 30 (which are adjacent to each other within the second gate dielectric layer) and a corresponding row of first gate electrodes (including portions of the first word lines 68) and a corresponding row of M first gate dielectrics 60.

[0188] In summary, the second gate electrode material can be deposited in the gate cavity 39 and can be isotropically recessed. The portion of the second gate electrode material filling the gate cavity 39 includes the second gate electrode (which includes a portion of the second word line 38). Therefore, the first portion of the dielectric gate spacer material can be replaced by the second gate electrode (which is a portion of the second word line 38). The second gate electrode (including a portion of the second word line 38) can be formed around the second portion of each horizontally extending semiconductor rail 10.

[0189] refer to Figure 36A , Figure 36B , Figure 36C , Figure 36D and Figure 36E Dielectric-filling material (such as undoped or doped silicate glass) may be deposited in the source trench 49. Planarization processes such as chemical mechanical polishing may be performed to remove portions of the dielectric-filling material from above a horizontal plane including the top surface of the bit line trench isolation structure 94. Each remaining portion of the source trench 49 filled with dielectric-filling material constitutes a source trench isolation structure 44. In one embodiment, the top surface of the source trench isolation structure 44 may be formed within a horizontal plane including the top surface of the bit line trench isolation structure 94. Laterally alternating sequences of source trench isolation structures 44 and bit line trench isolation structures 94 may be arranged along a first horizontal direction hd1.

[0190] refer to Figure 37A , Figure 37B , Figure 37C , Figure 37D and Figure 37E A photoresist layer (not shown) may be applied over the second exemplary structure and may be photolithographically patterned to form a total of (L+1) x M openings over the bit line trench isolation structure 94 and the source trench isolation structure 44. Each opening in the photoresist layer may have area overlap in a planar view with a corresponding vertical stack of (N+1) interfaces between the (N+1) semiconductor rails 10 and the bit line trench isolation structure 94 or the source trench isolation structure 44. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the bit line trench isolation structure 94 and the source trench isolation structure 44, as well as the end segments of the semiconductor rails 10. A bit line via cavity 95 may be formed through the bit line trench isolation structure 94, extending vertically downward to the etch stop structure 8 (or, if the etch stop structure is omitted, to the substrate 2). A source line via cavity 45 can be formed through the source trench isolation structure 44, extending vertically downward to the etch stop structure 8 (or, if the etch stop structure is omitted, to the substrate 2). The photoresist layer can then be removed, for example, by ashing.

[0191] refer to Figure 38A , Figure 38B , Figure 38C , Figure 38D and Figure 38EA conformal doping process can be performed to electrically dope the surface portion of the semiconductor track 10 near the physically exposed surface of the semiconductor track 10. For example, a vapor phase doping process or an outward diffusion process using a conformally deposited sacrificial doped silicate glass layer (such as a sacrificial borosilicate glass layer or a sacrificial phosphosilicate glass layer) can be used to convert the surface portion of the second horizontally extending semiconductor channel 34 near the source line via cavity 45 into a source extension region 33, and the surface portion of the first horizontally extending semiconductor channel 14 near the in-situ line via cavity 95 into a drain extension region 15. In one embodiment, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 may have doping of a first conductivity type, and the source extension region 33 and the drain extension region 15 may have doping of a second conductivity type opposite to the first conductivity type. Alternatively, the formation of the source extension region 33 and the drain extension region 15 may be omitted.

[0192] A selective semiconductor deposition process can be performed to grow a doped semiconductor material having a second conductivity type on a first physically exposed semiconductor surface exposed to a source line via cavity 45 from a first portion of the horizontally extending semiconductor track 10 and a second physically exposed semiconductor surface exposed to a bit line via cavity 95 from the first portion of the horizontally extending semiconductor track 10. The selective semiconductor deposition process at this step is comparable to that in the reference... Figures 20A to 20E The selective semiconductor deposition processes described are essentially the same.

[0193] Following the formation of the second gate electrode, a selective semiconductor deposition process grows a source region 32 on the sidewall of a second portion of the horizontally extending semiconductor rail 10 (i.e., the portion including the second horizontally extending semiconductor channel 34); and a drain region 16 on the sidewall of a first portion of the horizontally extending semiconductor rail 10 (i.e., the portion including the first horizontally extending semiconductor channel 14). In one embodiment, the source region 32 is formed on a first sidewall of the semiconductor rail 10 located within a source line via cavity 45, and the drain region 16 is formed on a second sidewall of the semiconductor rail 10 located within a bit line via cavity 95. The source region 32 has different horizontal cross-sectional shapes in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1, and these different horizontal cross-sectional shapes vary according to the lateral distance from the nearest side semiconductor rail in the semiconductor rail 10. The drain region 16 has different horizontal cross-sectional shapes in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1. These different horizontal cross-sectional shapes vary according to the lateral distance from the nearest semiconductor rail in the semiconductor rail 10.

[0194] A series connection between the access field-effect transistor 100 and the memory field-effect transistor 300 can be formed within each unit cell UC. The access field-effect transistor includes a first horizontally extending semiconductor channel 14, a first gate dielectric 60, a first gate electrode (which is part of a first word line 68), an optional drain extension region 15, and a drain region 16. The memory field-effect transistor includes a second horizontally extending semiconductor channel 34, a second gate dielectric 30 (which is part of a two-dimensional M x N array of continuous gate dielectric layers including the second gate dielectric 30), a second gate electrode (which is part of a second word line 38), an optional source extension region 33, and a source region 12 having the same material composition as the drain region 16. Each of the source region 32 and the drain region 16 has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction hd1, varying according to its lateral distance from the first horizontally extending semiconductor channel 14.

[0195] The second exemplary structure includes a three-dimensional L x M x N array of unit cells UC. The unit cells UC can be arranged to provide: rows of a corresponding set of M unit cells UC arranged along a second horizontal direction hd2, different from the first horizontal direction hd1; columns of a corresponding set of L unit cells UC arranged along the first horizontal direction hd1; and a vertical stack of a corresponding set of N unit cells UC arranged along a vertical direction. According to one aspect of this disclosure, the second gate dielectric 30 within each unit cell UC includes a memory dielectric material having at least two programmable states. The at least two programmable states can be selectively programmed based on the polarity and / or magnitude of an electrical bias of a semiconductor channel 34 extending across the second horizontal direction and a second gate electrode 38 (which is the portion of the second word line 38 located within the corresponding unit cell UC).

[0196] refer to Figure 39A , Figure 39B , Figure 39C , Figure 39D and Figure 39EAt least one conductive material layer may be deposited in the remaining volume of the bit line via cavity 95 and the source line via cavity 45. The at least one conductive material layer may comprise a combination of a metal barrier material and a metal filler material. Exemplary metal barrier materials include TiN, TaN, WN, and / or MoN. Exemplary metal filler materials include W, Co, Ru, Mo, Ti, Ta, Cu, etc. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surfaces of the bit line trench isolation structure 94 and the source trench isolation structure 44. The filling of each remaining portion of the corresponding source line via cavity 45 with the at least one conductive material constitutes a vertical source line 46. Each vertical source line 46 contacts a vertical stack of N source regions 32 and may contact an overlying dummy source region located on a dummy semiconductor track. An L x M array of vertical source lines 46 may be formed. The filling of each remaining portion of the corresponding bit line via cavity 95 with the at least one conductive material constitutes a bit line 98. Each bit line 98 contacts a vertically stacked N drain regions 16 and can also contact an overlying dummy drain region located on a dummy semiconductor track. An L x M array of bit lines 98 can be formed.

[0197] Generally, the two-dimensional array of vertical bit lines 98 can be configured such that each vertical bit line in the vertical bit lines 98 contacts a set of drain regions 16 located within the corresponding vertical stack of the unit cell UC. The two-dimensional array of vertical source lines 46 can be configured such that each vertical source line in the vertical source lines 46 contacts a set of source regions 32 located within the corresponding vertical stack of the unit cell UC.

[0198] refer to Figure 40A , Figure 40B , Figure 40C , Figure 40D and Figure 40E This illustrates an alternative configuration of a second exemplary structure according to a second embodiment of the present disclosure after the formation of bit line 98 and source structure 48S. The alternative configuration of the second exemplary structure can be derived from the second exemplary structure by replacing each array of vertical source lines 46 within the respective source trench 49 with a corresponding source structure 48S that contacts at least one two-dimensional array of source regions 32. Each source structure 48S located between two two-dimensional M x N arrays of semiconductor rail 20 may contact both two two-dimensional M x N arrays of source regions 32.

[0199] In another alternative implementation, located Figures 40A to 40E The laterally separated bit lines 98 in the illustrated laterally separated bit line cavity 95 can be replaced by a single bit line 98 located in the common bit line cavity 95 and contacting the drain regions (15, 16) of the laterally adjacent field-effect transistors, as shown. Figure 73A and Figure 73C As shown and described in more detail below.

[0200] Common Reference Figures 1A to 11E and Figures 27A to 40E Furthermore, according to a second embodiment of this disclosure, a device structure including a three-dimensional array of unit cells UC is provided. Each unit cell UC includes: an access field-effect transistor 100, which includes a first horizontally extending semiconductor channel 14, a first gate dielectric 60, and a first gate electrode (which is a portion of a first word line 68); and a memory field-effect transistor 300, which includes a second horizontally extending semiconductor channel 34, a second gate dielectric 30, and a second gate electrode 38 (which is a portion of a second word line 38 located within the corresponding unit cell UC), wherein the second gate dielectric 30 includes a memory dielectric material having at least two programmable states.

[0201] In one embodiment, the second horizontally extending semiconductor channel 34 contacts the first horizontally extending semiconductor channel 14. In one embodiment, the second horizontally extending semiconductor channel 34 and the first horizontally extending semiconductor channel 14 comprise the same semiconductor material, but include electrically conductive dopants of the same conductivity type with different atomic concentrations. In one embodiment, the second horizontally extending semiconductor channel 34 and the first horizontally extending semiconductor channel 14 have the same material composition.

[0202] In one embodiment, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the first horizontally extending semiconductor channel 14 or the second horizontally extending semiconductor channel 34 and is perpendicular to the first horizontal direction hd1, regardless of the position of the vertical cutting plane of the respective vertical cross-sectional view. In one embodiment, the access field-effect transistor 100 includes a drain region 16; and the memory field-effect transistor 300 includes a source region 32 having the same material composition as the drain region 16. In one embodiment, the drain region 16 has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction hd1 that varies according to the lateral distance from the first horizontally extending semiconductor channel 14.

[0203] In one embodiment, the sidewall of the second gate dielectric 30 contacts the sidewall of the first gate electrode (which is a portion of the first word line 68). In one embodiment, the interface between the sidewall of the second gate dielectric 30 and the sidewall of the first gate electrode (which is a portion of the first word line 68) is perpendicular to a first horizontal direction hd1. In one embodiment, the first gate dielectric 60 contacts the second gate dielectric 30. In one embodiment, the interface between the first gate dielectric 60 and the second gate dielectric 30 includes a horizontal surface segment and a vertical surface segment parallel to the first horizontal direction hd1. In one embodiment, the device structure includes a dielectric gate spacer 35 that contacts the sidewall of the second gate electrode 38 (which is a portion of the second word line 38 located within a corresponding unit cell UC) and is laterally spaced from the first gate electrode and the first gate dielectric 60 by the second gate dielectric 30.

[0204] In one embodiment, the first gate dielectric 60 has a first tubular configuration and laterally surrounds a first horizontally extending semiconductor channel 14, and extends laterally along a first horizontal direction hd1; and the second gate dielectric 30 includes a portion having a second tubular configuration and laterally surrounding a second horizontally extending semiconductor channel 34, and extending laterally along the first horizontal direction hd1. In one embodiment, the first gate electrode includes a portion of a first word line 68 extending laterally along a second horizontal direction; and the second gate electrode includes a portion of a second word line 38 extending laterally along a second horizontal direction hd2.

[0205] In one embodiment, a first gate electrode surrounds a first gate dielectric 60 in a first vertical cross-sectional view perpendicular to the first horizontal direction hd1; and a second gate electrode (which is the portion of the second word line 38 located within the corresponding unit cell UC) surrounds a second gate dielectric 30 in a second vertical cross-sectional view perpendicular to the first horizontal direction hd1.

[0206] In one embodiment, the three-dimensional array of unit cells UC is arranged to provide: rows of corresponding unit cells UC arranged along a second horizontal direction hd2, which is different from the first horizontal direction hd1; columns of corresponding unit cells UC arranged along the first horizontal direction hd1; and a vertical stack of corresponding unit cells UC arranged along a vertical direction. In one embodiment, each second gate dielectric 30 within the three-dimensional memory array is a portion of a corresponding continuous gate dielectric layer that extends laterally along the second horizontal direction hd2 and contacts the first gate electrode of each access field-effect transistor within a corresponding row of unit cells UC.

[0207] In one embodiment, the device structure further includes a two-dimensional array of vertical bit lines 98, wherein each vertical bit line of the vertical bit lines 98 contacts a set of drain regions 16 located within a corresponding vertical stack of the unit cell UC. In one embodiment, the device structure further includes a two-dimensional array of vertical source lines 46, wherein each vertical source line of the vertical source lines 46 contacts a set of source regions 32 located within a corresponding vertical stack of the unit cell UC.

[0208] In one embodiment, the device structure further includes a two-dimensional array of second dielectric plates 66 arranged along a first horizontal direction hd1 and along a vertical direction, wherein each second dielectric plate 66 contacts a top surface of a corresponding underlying second word line 38 including a first row of second gate electrodes and contacts a bottom surface of a corresponding overlay word line 68 including a second row of second gate electrodes. In one embodiment, the second gate dielectric 30 comprises a ferroelectric dielectric material. In another embodiment, the second gate dielectric 30 comprises a charge trapping dielectric material.

[0209] refer to Figure 41 A schematic circuit diagram of a first exemplary circuit is illustrated, which can be used to implement a three-dimensional memory device including a first exemplary structure, wherein the memory device 200 includes a charge storage (i.e., volatile) capacitor. The first exemplary circuit may include a first random access memory (RAM) device 501, which includes a three-dimensional array of integrated memory cells 480, such as a three-dimensional L x M x N array. Each unit cell UC in the first exemplary structure includes an integrated memory cell 480, which includes an access field-effect transistor 100 and a memory device 200. Each memory device 200 may be electrically accessed via an access field-effect transistor within a corresponding integrated memory cell 480 in the first exemplary structure. Each access field-effect transistor 100 is activated only when bit line 98 and word line 68 connected to the access field-effect transistor 100 are activated. In one embodiment, the first RAM device 501 includes a memory array region 550, which includes word line 68 and bit line 98. In an exemplary example, the first RAM device 501 may include a row decoder 560 connected to word line 68 and a sensing / programming circuit 570 connected to bit line 98. A column decoder 580 and a data buffer 590 may be connected to the sensing / programming circuit 570. The conductive structure 48A in the first exemplary structure may be electrically grounded.

[0210] refer to Figure 42A schematic circuit diagram of a second exemplary circuit is illustrated, which can be used to implement a three-dimensional memory device including the first exemplary structure, wherein the memory device 200 is a non-volatile memory device, such as a ferroelectric capacitor or a variable resistor. The second exemplary circuit may include a second random access memory (RAM) device 502, which includes a three-dimensional array of integrated memory cells 480 from the first exemplary structure, such as a three-dimensional L x M x N array. A fourth RAM device 502 can be derived from the first RAM device 503 by adding a write line 48A. The write line 48A is used for programming (i.e., writing) the memory device 200, while the bit line 98 is used for reading the memory device 200.

[0211] refer to Figure 43 A schematic circuit diagram of a third exemplary circuit is illustrated, which can be used to implement a three-dimensional memory device including a second exemplary structure, the second exemplary structure including a memory field-effect transistor 300. The third exemplary circuit may include a third random access memory (RAM) device 503, which includes a three-dimensional array of integrated memory cells 480' in the second exemplary structure, such as a three-dimensional L x M x N array. Each unit cell UC in the second exemplary structure includes an integrated memory cell 480', which includes an access field-effect transistor 100 and a memory field-effect transistor 300. Each memory field-effect transistor 300 may be electrically accessed via the access field-effect transistor 100 within the corresponding integrated memory cell 480'. Each access field-effect transistor 100 is activated only when the bit line 98 and the first word line 68 connected to the access field-effect transistor are activated. Each memory field-effect transistor 300 can be programmed by activating the access field-effect transistor within the same integrated memory cell 480' and by electrically biasing the corresponding second gate electrode (which is part of the corresponding second word line 38) and the corresponding vertical source line 46. In one embodiment, the third RAM device 503 includes a memory array region 550 that includes a first word line 68, a second word line 38, a bit line 98, and a vertical source line 46. In an exemplary example, the third RAM device 503 may include a row decoder 560 connected to the first word line 68 and the second word line 38, and a sensing / programming circuitry 570 connected to the bit line 98 and the vertical source line 46. Each pair of bit lines 98 and vertical source lines 46 connected to the vertical stack of N semiconductor rails 10 can be activated individually. A column decoder 580 and a data buffer 590 may be connected to the sensing / programming circuitry 570.

[0212] refer to Figure 44A schematic circuit diagram of a fourth exemplary circuit is illustrated, which can be used to implement a three-dimensional memory device including an alternative configuration of the second exemplary structure. The fourth exemplary circuit may include a fourth random access memory (RAM) device 504, which includes a three-dimensional array of integrated memory cells 480' in the second exemplary structure, such as a three-dimensional L x M x N array. The fourth RAM device 504 can be derived from the third RAM device 503 by replacing the vertical source lines 46 with source structures 48S, which has the same effect as electrically shorting all the vertical source lines 46. In this case, the source lines do not need to be driven individually.

[0213] The three-dimensional memory array of the embodiments disclosed herein can be located in various dies or bond assemblies. Figures 45 to 50 Non-limiting examples of die configurations of three-dimensional arrays of memory elements that can be used in various embodiments of this disclosure are illustrated.

[0214] refer to Figure 45 A three-dimensional memory array 550 may be disposed on a substrate 2 within a memory die 900. An upper metal interconnect structure 980 embedded within an upper dielectric material layer 960 may be formed on the three-dimensional array 550, and memory-side bonding pads 988 may be formed at the top layer of the upper dielectric material layer 960. A logic die 700 is provided, comprising a logic die substrate 702, control circuitry 720 including semiconductor devices configured to control the operation of the three-dimensional memory array 550, logic-side metal interconnect structures 780 embedded within the logic-side dielectric material layer 760, and logic-side bonding pads 788 electrically connected to a corresponding subset of the logic-side metal interconnect structures 780. The control circuitry 720 may include various CMOS circuits. The memory die 900 may be bonded to the logic die 700 via bonding between mating pairs of memory-side bonding pads 988 and logic-side bonding pads 788.

[0215] Generally, the memory die 900 and the logic die 700 can be bonded via metal-to-metal bonding between memory-side bonding pads 988 and logic-side bonding pads 788, or via solder-mediated bonding such as C4 bonding or microbump bonding. If metal-to-metal bonding is used, the memory-side bonding pad 988 directly contacts the logic-side bonding pad 788, and metal interdiffusion is initiated between the materials of the memory-side bonding pad 988 and the logic-side bonding pad 788. In this case, the outermost dielectric material layer in the upper dielectric material layer 960 can contact the outermost dielectric material layer in the logic-side dielectric material layer 760, and dielectric-to-dielectric bonding can be initiated between them. If C4 bonding or microbump bonding is used, a two-dimensional array of solder material portions can be interposed between the memory-side bonding pads 988 and the logic-side bonding pads 788, and can be bonded to both the memory-side bonding pads and the logic-side bonding pads. The gap between the outermost dielectric material layer in the upper dielectric material layer 960 and the outermost dielectric material layer in the logic side dielectric material layer 760 may be filled with a bottom filler material portion.

[0216] Memory dies 900 and logic dies 700 can be bonded via wafer-to-wafer bonding, die-to-die bonding, or die-to-wafer bonding. In the case of wafer-to-wafer bonding, a wafer comprising a two-dimensional array of memory dies 900 and another wafer comprising a two-dimensional array of logic dies 700 can be provided. Paired memory dies 900 and logic dies 700 can be bonded simultaneously by performing a metal-to-metal bonding process or a solder-mediated bonding process. In the case of die-to-die bonding, a single memory die 900 (as provided by monolithization of a wafer comprising a two-dimensional array of memory dies 900) can be bonded to a single logic die 700 (as provided by monolithization of a wafer comprising a two-dimensional array of logic dies 700). In the case of die-to-wafer bonding, memory die 900 may be bonded to a selected logic die 700 located on a wafer comprising a two-dimensional array of logic dies 700, or logic die 700 may be bonded to a selected memory die 900 located on a wafer comprising a two-dimensional array of memory dies 900.

[0217] refer to Figure 46 An example is shown of a second semiconductor die containing a three-dimensional memory array 550. The second semiconductor die may be a memory die 900, wherein the substrate 2 includes a semiconductor material layer 902 and a lower-level driver circuit structure. The semiconductor material layer 902 performs a reference... Figures 1A to 1EThe described substrate 2 functions as follows. The lower voltage driver circuit structure may include a semiconductor substrate 602 (such as a portion of a single-crystal silicon wafer), control circuitry 620 including semiconductor devices configured to control the operation of the three-dimensional memory array 550, and a lower metal interconnect structure 680 embedded within a lower dielectric material layer 660. The semiconductor material layer 902 may include a polycrystalline semiconductor material layer, which may be formed by depositing semiconductor material over the lower dielectric material layer 660; or may include a single-crystal semiconductor material layer (such as a single-crystal silicon layer), which may be formed by layer transfer from a source single-crystal semiconductor layer, for example, using a hydrogen-implanted stripping layer (commonly referred to as a Smart-cut). ™ (Method). The semiconductor material layer 902 can be patterned as needed. The electrical interconnect between the lower metal interconnect structure 680 and the upper metal interconnect structure 980 can be formed by metal vias passing through the semiconductor material layer 902 and the layers of the three-dimensional memory array 550. Alternatively, the semiconductor material layer 902 can be omitted. In this case, the etch stop structure 8 located at the bottommost layer of the three-dimensional memory array 550 can contact the topmost layer within the lower dielectric material layer 660.

[0218] refer to Figure 47 This can be achieved by removing substrate 2 and subsequently forming the backside structure of the memory die. Figure 45 The illustrated first semiconductor die leads to a third semiconductor die containing the three-dimensional memory array 550. The removal of the substrate 2 can be selectively performed relative to the etch stop structure 8, for example, by grinding, polishing, anisotropic etching processes, and / or isotropic etching processes. A back-side metal interconnect structure 880 can optionally be formed embedded within the back-side dielectric material layer 860. Back-side bonding pads 888 can be formed on the back-side metal interconnect structure 888 or on the electrical nodes of the three-dimensional memory array 550. The back-side bonding pads 888 can be metal-to-metal bonding pads or solder bonding pads.

[0219] refer to Figure 48 An example is illustrated of a fourth semiconductor die containing a three-dimensional memory array 550, which can be obtained from a reference in the following manner. Figure 45 The first semiconductor die described or from the reference Figure 48The described third semiconductor die derivation involves forming a combination of a through-substrate via dielectric pad 712 and a through-substrate via structure 714 in the upper portion of the logic-side substrate 702 prior to the formation of the control circuit 720. After the logic die 702 is bonded to the memory die 900, the logic die substrate 702 is thinned from the back side. A logic die back-side insulating layer 716 is formed on the back-side surface of the thinned logic-side substrate 700, and a logic die back-side bonding pad 728 is formed. The logic die back-side bonding pad 728 can be a metal-to-metal bonding pad or a solder bonding pad.

[0220] refer to Figure 49 Multiple memory dies 900 can be vertically stacked to obtain from the reference. Figure 48 The described fourth semiconductor die leads to a fifth semiconductor die containing a three-dimensional memory array 550. In the illustrated example, metal-to-metal bonding is used to vertically stack multiple memory dies 900.

[0221] refer to Figure 50 Multiple memory dies 900 can be vertically stacked to obtain from the reference. Figure 48 The described fourth semiconductor die leads to a sixth semiconductor die containing a three-dimensional memory array 550. In the illustrated example, microbump bonding is used to vertically stack multiple memory dies 900. An array of solder material portions 794 can be interposed between each vertically adjacent pair of bonding pads. An underfill material portion 797 can fill the gaps between each vertically adjacent pair of semiconductor dies (700, 900).

[0222] refer to Figure 51A , Figure 51B , Figure 51C , Figure 51D , Figure 51E , Figure 51F and Figure 51G This illustrates a third exemplary structure according to a third embodiment of the present disclosure, which can be obtained by patterning a vertically alternating sequence (20L, 10L) of sacrificial layer 20L and semiconductor layer 10L. Figures 1A to 1E The illustrated first exemplary structure is derived. In one embodiment, (N+2) sacrificial layers 20L may be vertically staggered with (N+1) semiconductor layers 10L. Each of the (N+1) semiconductor layers 10L may have the same thickness overall. Each of the N sacrificial layers 20L, excluding the topmost and bottommost sacrificial layers 20L, may have the same thickness. The thickness of the bottommost and topmost sacrificial layers 20L may be adjusted as needed to be thinner or thicker than the rest of the sacrificial layers 20L.

[0223] A photoresist layer (not shown) may be applied over a vertically alternating sequence (20L, 10L) of sacrificial layer 20L and semiconductor layer 10L, and may be photolithographically patterned to form modified line and space patterns, wherein each space pattern has a periodic widening along a first horizontal direction hd1. In this case, the periodically widened pattern may be a two-dimensional periodic pattern of a rectangular shape or a rounded rectangular shape juxtaposed with a one-dimensional periodic space pattern. As a consequence, each line pattern is modified to include periodic raised areas.

[0224] An anisotropic etching process can be performed to transfer a pattern in a photoresist layer through a vertically alternating sequence (20L, 10L) of sacrificial layer 20L and semiconductor layer 10L. The vertically alternating sequence (20L, 10L) of sacrificial layer 20L and semiconductor layer 10L is patterned into a vertically alternating stack of horizontally extending semiconductor tracks 10' and horizontally extending sacrificial tracks 20'. Each horizontally extending semiconductor track 10' is a patterned portion of semiconductor layer 10L and extends laterally along a first horizontal direction hd1 with a uniform height and periodically modulated width. Each horizontally extending sacrificial track 20' is a patterned portion of sacrificial layer 20L and extends laterally along the first horizontal direction hd1 with a uniform height and periodically modulated width. The two-dimensional M x (N+1) array of horizontally extended semiconductor rails 10' and the two-dimensional M x (N+2) array of horizontally extended sacrificial rails 20' can be formed such that M vertically alternating stacks (10', 20') of (N+1) horizontally extended semiconductor rails 10' and (N+2) horizontally extended sacrificial rails 20' are formed.

[0225] Each of the vertically alternating stacks (10', 20') extends laterally along a first horizontal direction hd1. The vertically alternating stacks (10', 20') are laterally spaced from each other along a second horizontal direction hd2 by lateral isolation trenches 59. Each lateral isolation trench 59 may include (L+1) uniformly wide portions having a uniform width (which may be referred to as a first trench width tw1) and L lateral protrusions having a width greater than the uniform width, such as... Figure 51C and Figure 51D As shown. The lateral protrusions have a width greater than the width tw1 of the uniform width portion (which may be referred to as the second groove width tw2). Therefore, each lateral isolation groove in the lateral isolation groove 59 may include periodic lateral protrusions 59B, which have a greater width (such as the second groove width tw2) than the width of the uniform width portion (such as the first groove width tw1).

[0226] Each unit cell UC in the unit cell UC includes a portion of the horizontally extending semiconductor rail 10' during the process, a portion of the lower half of the horizontally extending sacrificial rail 20' during the overlay process, and a portion of the upper half of the horizontally extending sacrificial rail 20' during the underlay process. Each of the horizontally extending semiconductor rail 10' and the horizontally extending sacrificial rail 20' during the process may include (L+1) uniform width portions having a first width w1 and L notch portions having a second width w2 less than the first width w1, such as... Figure 51C and Figure 51D As shown. The first width w1 can be in the range of 30nm to 900nm (such as 100nm to 500nm), but smaller and larger sizes can also be used. The second width w2 can be in the range of 10nm to 300nm, but smaller and larger sizes can also be used. The first trench width tw1 can be in the range of 10nm to 200nm (such as 20nm to 100nm), but smaller and larger widths can also be used. The second trench width tw2 can be the same as the first trench width tw1 and the sum of the difference between the first width w1 and the second width w2, that is, tw2 = tw1 + (w2 - w1).

[0227] The center-to-center distance between the lateral protrusions of adjacent pairs of lateral isolation trenches 59 along the first horizontal direction hd1 can be the same as the first periodicity of the three-dimensional array of the unit cell UC along the first horizontal direction hd1. The first periodicity can be in the range of 200 nm to 10,000 nm (such as 400 nm to 1,000 nm), but smaller and larger sizes can also be used for the first periodicity. The center-to-center distance between adjacent pairs of lateral isolation trenches 59 can be the same as the second periodicity of the three-dimensional array of the unit cell UC along the second horizontal direction hd2. The second periodicity can be in the range of 20 nm to 1,000 nm (such as 40 nm to 500 nm), but smaller and larger sizes can also be used for the second periodicity.

[0228] refer to Figure 52A , Figure 52B , Figure 52C , Figure 52D , Figure 52E , Figure 52F and Figure 52GA sacrificial filler layer 57L may be deposited in the lateral isolation trench 59 and on the vertically alternating stacks (10', 20'). The sacrificial filler layer 57L may include carbon-based materials (such as amorphous carbon or diamond-like carbon), organosilicon glass, silicon oxide, silicon nitride, or polymeric materials. For example, the sacrificial filler may include silicon oxide. The sacrificial filler may differ from the material of the horizontally extending sacrificial track 20' during the process. The duration of the deposition process for the sacrificial filler is selected such that the uniform width portion of the lateral isolation trench 59 with a first trench width tw1 is filled, while the lateral protrusion portion 59B of the lateral isolation trench 59 with a second trench width tw2 is not completely filled, and thus has a corresponding vertically extending void 79' therein. If a conformal deposition process is used to deposit the sacrificial filler, the thickness of the deposited sacrificial filler may be greater than half the first trench width tw1 and less than half the second trench width tw2.

[0229] refer to Figure 53A , Figure 53B , Figure 53C , Figure 53D , Figure 53E , Figure 53F and Figure 53GAn isotropic etching process can be performed to isotropically etch the sacrificial filler material of the sacrificial filler material layer 57L. The duration of the isotropic etching process can be selected such that the etching distance of the isotropic etching process on the sacrificial filler material is in the range of 100% to 120% of the thickness of the sacrificial filler material layer 57L. The isotropic etching process removes the portion of the sacrificial filler material layer 57L that covers the horizontal plane of the top surface comprising vertically alternating stacks (10', 20') and removes the portion of the sacrificial filler material layer 57L located within the volume of the lateral protrusions 59B of the lateral isolation trench 59. The remaining portion of the volume of the sacrificial filler material layer 57L filling the uniform width portion of the lateral isolation trench 59 constitutes the sacrificial isolation trench filling structure 57. A two-dimensional array of sacrificial isolation trench filling structures 57 can be formed, which may include (L+1) x (M+1) sacrificial isolation trench filling structures 57. In one embodiment, the two-dimensional array of sacrificial isolation trench filling structures 57 may comprise at least a two-dimensional (L-1) x (M-1) rectangular periodic array of sacrificial isolation trench filling structures 57. The lateral dimensions of the voids 79' are enlarged by etching to form a two-dimensional array of cavities 79 within the volume of the lateral protrusions 59B of the lateral isolation trenches 59. The two-dimensional array of cavities 79 may comprise an L x (M+1) rectangular periodic array of cavities 79. While an embodiment in which each cavity 79 has a rectangular horizontal cross-sectional shape is illustrated, alternative embodiments in which each cavity 79 may have a rounded rectangular, elliptical, oval, or circular horizontal cross-sectional shape are explicitly contemplated herein. Generally, the maximum width of each cavity 79 along the second horizontal direction hd2 is referred to as the second trench width tw2.

[0230] refer to Figure 54A , Figure 54B , Figure 54C , Figure 54D , Figure 54E , Figure 54F and Figure 54GAn isotropic etching process can be performed to selectively and isotropically etch the material of the horizontally extending sacrificial rail 20' relative to the material of the horizontally extending semiconductor rail 10' and the sacrificial isolation trench filling structure 57. For example, if the horizontally extending sacrificial rail 20' comprises a silicon-germanium alloy and if the horizontally extending semiconductor rail 10 comprises silicon, a wet etching chemical using a mixture of acetic acid and hydrogen peroxide can be used to etch the portion of the horizontally extending sacrificial rail 20' near the pillar cavity 79. The lateral etching distance of the isotropic etching process for the material of the horizontally extending sacrificial rail 20' is greater than half the second width w2. Generally, the duration of the isotropic etching process can be selected such that each column of pillar cavities 79 arranged along the second horizontal direction hd2 is merged to form a corresponding continuous extension cavity through which a two-dimensional (M x (N+1)) array of physically exposed portions (e.g., bridge portions) of the horizontally extending semiconductor rail 10' extends laterally. Each such continuous extension cavity is referred to herein as a bridge-around cavity 77. As used herein, a bridge-around cavity refers to a cavity through which an array of bridge structures extends. In this case, a (M x (N+1)) array of portions of the horizontally extending semiconductor rails 10' extends through each bridge-around cavity 77. Each bridge-around cavity 77 has a flat wall of a certain volume, which includes (M x (N+1)) perforations passing through it. The physically exposed surfaces of each horizontally extending semiconductor rail 10' include the surface of the neck portion 10N of the horizontally extending semiconductor rail 10' having a second width w2, and the surface of the horizontally extending semiconductor rail 10' having a first width w1 and a uniform width portion near the neck portion 10N, as shown below. Figure 54C As shown.

[0231] In each process, the horizontally extending sacrificial track 20' is divided into a plurality of horizontally extending sacrificial tracks 20, which are laterally spaced from each other by the bridge surrounding cavity 77. In one embodiment, a three-dimensional (L+1) x M x (N+2) array of sacrificial tracks 20 may be formed. The three-dimensional (L+1) x M x (N+2) array of sacrificial tracks 20 may include at least a two-dimensional (L-1) x M x N periodic array of sacrificial tracks 20.

[0232] refer to Figure 55A , Figure 55B , Figure 55C , Figure 55D , Figure 55E , Figure 55F and Figure 55GAn isotropic doping process can be performed to introduce dopant into a portion of the process-exposed surface of the horizontally extending semiconductor track 10'. The physically exposed surface of the process-exposed horizontally extending semiconductor track 10' is exposed to a corresponding bridge-around cavity in the bridge-around cavity 77. The isotropic doping process may include a vapor-phase doping process or a thermal dopant diffusion process using a conformal sacrificial doped silicate glass layer containing a dopant species such as phosphorus, arsenic, or boron. Alternatively, a plasma doping process may be used to electrically dope the physically exposed surface of the process-exposed horizontally extending semiconductor track 10'.

[0233] If a gas-phase doping process is used, a dopant-type hydride gas (such as diborane, phosphine, or arsine) can be used as the dopant source gas. The process temperature for physically exposed surfaces of the horizontally extending semiconductor rails 10' to be exposed to the dopant-type hydride gas can range from 850 degrees Celsius to 1,000 degrees Celsius.

[0234] If a thermal dopant diffusion process is used, an arsenic silicate glass layer, a phosphosilicate glass layer, or a borosilicate glass layer can be used as the conformal sacrificial doped silicate glass layer. In this case, the third exemplary structure can be annealed at an elevated temperature (e.g., in the range of 800°C to 950°C) to induce dopant atoms to diffuse outward from the conformal sacrificial doped silicate glass layer after deposition. Subsequently, the conformal sacrificial doped silicate glass layer can be removed by performing an isotropic selective etching process, such as a timed wet etching process using diluted hydrofluoric acid.

[0235] By diffusing an electric dopant in the proximal portion (e.g., the neck region 10N and adjacent portions of the neck region) of the horizontally extending semiconductor track 10 surrounding the bridge cavity 77 (which includes the volume of the lateral protrusion 59B of the lateral isolation trench 59), the proximal portion is transformed into a three-dimensional array of doped semiconductor material portions 11. The electric dopant may include p-type or n-type dopant. The doped semiconductor material portions 11 have a higher doping concentration than the first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel (14, 34). The average atomic concentration of the electric dopant in the doped semiconductor material portions 11 can be 1 x 10⁻⁶. 18 / cm 3 Up to 5 x 10 20 / cm 3 (such as 3 x 10) 19 / cm 3 Up to 2 x 10 20 / cm 3Within the range of ), but smaller and larger average atomic concentrations can also be used. Each unit cell UC includes a first portion of the adjacent doped semiconductor material portion 11 of the horizontally extending semiconductor rail 10' during the process, which is subsequently used as a first horizontally extending semiconductor channel 14. Each unit cell UC includes a second portion of the adjacent doped semiconductor material portion 11 of the horizontally extending semiconductor rail 10' during the process, which is subsequently used as a second horizontally extending semiconductor channel 34, such as Figure 55C As shown.

[0236] The second horizontally extending semiconductor channel 34 may have the same material composition as the first horizontally extending semiconductor channel 14. A doped semiconductor material portion 11 contacts both the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34. The doped semiconductor material portion 11 may have the same conductivity type (i.e., the same doping type) or opposite conductivity type (i.e., opposite doping types) relative to the first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel (14, 34). If the doped semiconductor material portion 11 has a conductivity type opposite to that of the channels (14, 34), a first pn junction may be formed at the interface between the first horizontally extending semiconductor channel 14 and the doped semiconductor material portion 11, and a second pn junction may be formed at the interface between the second horizontally extending semiconductor channel 34 and the doped semiconductor material portion 11. Within each unit cell UC in the unit cell UC, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 extend laterally along the first horizontal direction hd1. The width (e.g., second width w2) of the central segment of the doped semiconductor material portion 11 along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1 is smaller than the width (e.g., first width w1) of the first horizontally extending semiconductor channel 14 along the second horizontal direction hd2. Within each unit cell UC in the unit cell UC, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 have a first uniform vertical extension; and the doped semiconductor material portion 11 may have the same uniform vertical extension, i.e., the first uniform vertical extension (which may also be referred to as vertical thickness or vertical height).

[0237] During the formation of the doped semiconductor material portion 11, the portions of the process-exposed horizontally extending sacrificial rails 20' to the bridge surrounding cavity 77 and the surface portions of the topmost process-exposed horizontally extending sacrificial rails 20' may be incidentally doped to form the doped sacrificial material portion 21. For example, if the process-exposed horizontally extending sacrificial rails 20' comprise monocrystalline silicon germanium or polycrystalline silicon germanium, the doped sacrificial material portion 21 may comprise doped silicon germanium.

[0238] refer to Figure 56A , Figure 56B , Figure 56C , Figure 56D , Figure 56E , Figure 56F and Figure 56G Sacrificial cavity filler material may be conformally deposited in the bridge surrounding cavity 77. The sacrificial cavity filler material differs from the material of the horizontally extending semiconductor rails 10', sacrificial rails 20, and sacrificial isolation trench filler structure 57 during the process. In exemplary examples, the sacrificial cavity filler material may include silicon nitride, silicon carbide, silicon carbonitride, and / or dielectric metal oxide. Excess portions of the sacrificial cavity filler material may be removed from a horizontal plane overlying the topmost surface of the horizontally extending semiconductor rails 10' during the process by performing a planarization process. The planarization process may include a chemical mechanical polishing process or a recess etching process. In some embodiments, the topmost region of the doped sacrificial material portion 21 and / or the topmost portion of the sacrificial isolation trench filler structure 57 may be incidentally removed during the planarization process. The filling of each remaining portion of the corresponding bridge surrounding cavity 77 with sacrificial cavity filler material constitutes a sacrificial through-hole wall structure 71. A one-dimensional array of sacrificial through-hole wall structures 71 may be formed. In one embodiment, each sacrificial perforation wall structure in the sacrificial perforation wall structure 71 surrounds a corresponding two-dimensional array of the doped semiconductor material portion 11 within a three-dimensional array of the doped semiconductor material portion 11.

[0239] refer to Figure 57A , Figure 57B , Figure 57C , Figure 57D , Figure 57E , Figure 57F and Figure 57GA photoresist layer (not shown) may be applied over the assembly of the horizontally extending semiconductor rails 10', sacrificial rails 20, sacrificial isolation trench fill structures 57, and sacrificial through-hole wall structures 71, and may be photolithographically patterned to form elongated openings extending laterally along a second horizontal direction hd2. The elongated openings may have a uniform width along a first horizontal direction hd1 and are formed at the boundaries of adjacent pairs of unit cells UC. An anisotropic etching process may be performed to transfer the pattern of the openings in the first photoresist layer through the assembly of the horizontally extending semiconductor rails 10', sacrificial rails 20, sacrificial isolation trench fill structures 57, and sacrificial through-hole wall structures 71. Trenches (49, 99) extending laterally along the second horizontal direction hd2 may be formed. The total number of trenches (49, 99) may be L+1. The trenches (49, 99) may comprise a lateral alternation sequence of source trenches 49 (e.g., write-side trenches) and bit line trenches 99 (e.g., read-side trenches) alternating along a first horizontal direction hd1. Each of the source trenches 49 and bit line trenches 99 may have a corresponding uniform width along the first horizontal direction hd1, which may range from 50 nm to 600 nm (e.g., 100 nm to 400 nm), but smaller and larger widths may also be used. The center-to-center distance between adjacent pairs of trenches (49, 99) may be the same as the first periodicity of the three-dimensional array of the unit cell UC along the first horizontal direction hd1.

[0240] During the process, the assembly of the horizontally extending semiconductor rail 10', sacrificial rail 20, sacrificial isolation trench filling structure 57, and sacrificial through-hole wall structure 71 is divided into multiple sub-assemblies (20A, 20B, 14, 11, 34, 21, 71). Each sub-assembly may include an M x (N+1) two-dimensional array of a first horizontally extending semiconductor channel 14, an M x (N+1) two-dimensional array of a second horizontally extending semiconductor channel 34, an M x (N+1) two-dimensional array of a doped semiconductor material portion 11, an M x (N+2) two-dimensional array of a first type sacrificial rail 20A, an M x (N+2) two-dimensional array of a second type sacrificial rail 20B, a 2 x (M+1) array of a sacrificial isolation trench filling structure 57, a sacrificial through-hole wall structure 71, and a doped sacrificial material portion 21. The first type sacrificial rail 20A and the second type sacrificial rail 20B are collectively referred to as sacrificial rail 20. A first type of sacrificial rail 20A is accessible to a first horizontally extending semiconductor channel 14, and a second type of sacrificial rail 20B is accessible to a second horizontally extending semiconductor channel 34. Multiple segmented assemblies (20A, 20B, 14, 11, 34, 21, 71) are laterally spaced from each other by alternating sequences of source trenches 49 and bit line trenches 99. Each segmented assembly (20A, 20B, 14, 11, 34, 21, 71) may have a corresponding first flat sidewall perpendicular to the first horizontal direction hd1 and exposed to the corresponding bit line trench 99, and a corresponding second flat sidewall perpendicular to the first horizontal direction hd1 and exposed to the corresponding source trench 49. The photoresist layer can then be removed, for example, by ashing. Each adjacent combination of the first horizontally extending semiconductor channel 14, the doped semiconductor material portion 11, and the second horizontally extending semiconductor channel 34 constitutes a semiconductor rail (14, 11, 34).

[0241] Generally speaking, the formation of bit line trench 99 and source trench 49 is used to address issues related to reference... Figure 51A , Figure 51B , Figure 51C , Figure 51D , Figure 51E , Figure 51F and Figure 51G The described processing steps form a vertically alternating stack (10', 20') of horizontally extending semiconductor rails 10' and horizontally extending sacrificial rails 20'. The patterned portion of the vertically alternating stack (10', 20') includes a three-dimensional array of horizontally extending semiconductor rails 10, each of which contains a corresponding first horizontally extending semiconductor channel 14, a corresponding doped semiconductor material portion 11, and a second horizontally extending semiconductor channel 34, wherein the corresponding doped semiconductor material portion is a corresponding doped semiconductor material portion within the doped semiconductor material portion 11.

[0242] refer to Figure 58A , Figure 58B , Figure 58C , Figure 58D , Figure 58E , Figure 58F and Figure 58G Sacrificial filler material can be deposited in source trench 49 and bit line trench 99. The sacrificial filler material deposited at this processing step may include carbon-based materials (such as amorphous carbon or diamond-like carbon), organosilicon glass, silicon oxide, silicon nitride, or polymer materials. The sacrificial filler material deposited at this processing step may be different from or the same as the material of the sacrificial rail 20. Excess portions of the sacrificial filler material can be removed from a horizontal plane above the top surface of the sacrificial isolation trench fill structure 57 and / or the top surface of the sacrificial through-wall structure 71 by a planarization process. The planarization process may use chemical mechanical polishing and / or recess etching processes. Each portion of the sacrificial filler material filling the source trench 49 constitutes a sacrificial source trench fill structure 47. Each portion of the sacrificial filler material filling the bit line trench 99 constitutes a sacrificial bit line trench fill structure 97.

[0243] refer to Figure 59A , Figure 59B , Figure 59C , Figure 59D , Figure 59E , Figure 59F and Figure 59G An etch mask layer (not illustrated), such as a photoresist layer, may be formed over the third exemplary structure and may be patterned to form openings over regions of a first subset of the respective sacrificial bitline trench fill structures in the contact sacrificial bitline trench fill structure 97 and the sacrificial isolation trench fill structure 57. The etch mask layer may cover each of a second subset of the respective sacrificial source trench fill structures in the contact sacrificial source trench fill structure 47 of the sacrificial via wall structure 71, the sacrificial source trench fill structure 47, and the sacrificial isolation trench fill structure 57.

[0244] At least one first selective material removal process can be performed to selectively remove a first subset of the sacrificial bit line trench fill structure 97 and the sacrificial isolation trench fill structure 57 relative to the materials of the semiconductor rails (14, 11, 34), the etch stop structure 8, and the sacrificial through-hole wall structure 71. In an exemplary example, if the sacrificial bit line trench fill structure 97 comprises silicon nitride, a wet etching process using hot phosphoric acid can be performed to remove the sacrificial bit line trench fill structure 97 without removing the first subset of the sacrificial isolation trench fill structure 57. If the sacrificial bit line trench fill structure 97 comprises a carbon-based material (such as amorphous carbon or diamond-like carbon), an ashing process can be used to remove the sacrificial bit line trench fill structure 97. Voids are formed in the volume of the bit line trench 99. Subsequently, if the first subset of the sacrificial isolation trench fill structure 57 comprises a silicate glass-based material, a wet etching process using diluted hydrofluoric acid can be performed to selectively etch the first subset of the sacrificial isolation trench fill structure 57 relative to the materials of the semiconductor rails (14, 11, 34), the etch stop structure 8, and the sacrificial through-hole wall structure 71. Alternatively, if the sacrificial through-hole wall structure 71 comprises a material different from the materials of the sacrificial bit line trench fill structure 97 and the sacrificial isolation trench fill structure 57, a single isotropic etching process can be performed to simultaneously etch the materials of the sacrificial bit line trench fill structure 97 and the sacrificial isolation trench fill structure 57. A first lateral isolation trench 591 is formed in the volume from which the first subset of the sacrificial isolation trench fill structure 57 has been removed. By removing the first subset of the sacrificial isolation trench fill structure 57, the first lateral isolation trench 591 is formed between the first horizontally extending semiconductor channels 14 of laterally adjacent pairs.

[0245] refer to Figure 60A , Figure 60B , Figure 60C , Figure 60D , Figure 60E , Figure 60F and Figure 60G At least one second selective material removal process can be performed to remove each of the first type sacrificial rails 20A. A first inter-rail cavity 291 is formed in the volume from which the first type sacrificial rails 20A have been removed. By removing the first type sacrificial rails 20A, the first inter-rail cavity 291 is formed between vertically adjacent pairs of first horizontally extending semiconductor channels 14. The etch mask layer can then be removed.

[0246] In an alternative implementation scheme, refer to Figures 59A to 60G The described set of processing steps can be replaced by any alternative set of processing steps, provided that the material of the sacrificial bitline trench filling structure 97, the first subset of the sacrificial isolation trench filling structure 57, and the first type of sacrificial rail 20A is removed.

[0247] refer to Figure 61A , Figure 61B , Figure 61C , Figure 61D , Figure 61E , Figure 61F and Figure 61G A first gate dielectric material layer 60L is formed by conformal deposition of a gate dielectric material and / or by oxidation of the physically exposed surface portions of the semiconductor rails (14, 11, 34). The first gate dielectric material layer 60L comprises a first gate dielectric material, such as silicon oxide or a dielectric metal oxide. The thickness of the first gate dielectric material layer 60L may be in the range of 2 nm to 20 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses may also be used.

[0248] A continuous first gate electrode material layer 68L may be conformally deposited on a first gate dielectric material layer 60L. The continuous first gate electrode material layer 68L includes a first gate electrode material, which may include any suitable conductive material. For example, the continuous first gate electrode material layer 68L may include at least one metal barrier layer (such as TiN, TaN, WN, or MoN) and a metal filler layer (such as W, Ti, Ta, Ru, or Mo). The continuous first gate electrode material layer 68L may be formed around each first portion of the horizontally extending semiconductor rails (14, 11, 34), i.e., around each first horizontally extending semiconductor channel 14. The continuous first gate electrode material layer 68L is deposited as a continuous material layer such that the lateral gaps between the first portions of laterally adjacent pairs of the horizontally extending semiconductor rails (14, 11, 34) are filled with the first gate electrode material, while the vertical gaps between the first portions of vertically adjacent pairs of the horizontally extending semiconductor rails (14, 11, 34) are not completely filled with the first gate electrode material. Therefore, after the deposition of the first gate electrode material of the continuous first gate electrode material layer 68L, a first lateral extension void 99 extending laterally along the second horizontal direction hd2 exists in the unfilled volume of the vertical gap between the first portions of adjacent pairs of semiconductor rails (14, 11, 34). The lateral extension void 99' may exist within each bit line trench 99.

[0249] refer to Figure 62A , Figure 62B , Figure 62C , Figure 62D , Figure 62E , Figure 62F and Figure 62GA first dielectric filler material (such as silicon oxide) may be conformally deposited in the first laterally extending void 69, in the peripheral portion of the bit line trench 99, and on the horizontally extending portion of the continuous first gate electrode material layer 68L overlying the three-dimensional array of semiconductor rails (14, 11, 34). A recessed etching process may be performed to remove portions of the first dielectric filler material from outside the volume of the first laterally extending void 69. The remaining portion of the first dielectric filler material filling the first laterally extending void 69 constitutes a two-dimensional array of first dielectric plates 62. Each first dielectric plate 62 is formed between corresponding vertically adjacent pairs of laterally extending portions of the continuous first gate electrode material layer 68L extending laterally along the second horizontal direction hd2.

[0250] refer to Figure 63A , Figure 63B , Figure 63C , Figure 63D , Figure 63E , Figure 63F and Figure 63G A first selective isotropic etching process can be performed to etch portions of the continuous first gate electrode material layer 68L near or overlying the in-situ trench 99 of the first gate electrode material layer 68L. The first selective isotropic etching process can selectively etch the first gate electrode material relative to the first gate dielectric material. For example, a wet etching process that selectively isotropically etches the first gate electrode material relative to the first gate dielectric material can be used. The first selective isotropic etching process patterns the continuous first gate electrode material layer 68L into a one-dimensional array of first gate electrode material layers 68S laterally spaced along a first horizontal direction hd1. Each first gate electrode material layer 68S may surround a corresponding two-dimensional array of semiconductor tracks (14, 11, 34), i.e., a corresponding two-dimensional array of the first horizontally extending semiconductor channel 14. For example, each first gate electrode material layer 68S may have a rectangular array of vias through which the corresponding two-dimensional array of the first horizontally extending semiconductor channel 14 laterally extends along the first horizontal direction hd1, such as... Figure 63F As shown. Optionally, a second selective isotropic etching process may be performed to etch a portion of the in-situ trench 99 of the first gate dielectric material layer 60L near or overlying the topmost semiconductor rails (14, 11, 34).

[0251] refer to Figure 64A , Figure 64B , Figure 64C , Figure 64D , Figure 64E , Figure 64F and Figure 64GDielectric filler material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in the bit line trench 99. Planarization processes such as chemical mechanical polishing may be performed to remove portions of the dielectric filler material from above a horizontal plane including the top surface of the sacrificial through-wall structure 71. Each remaining portion of the filled bit line trench 99 with dielectric filler material constitutes a bit line trench isolation structure 94. In one embodiment, the top surface of the bit line trench isolation structure 94 may be formed within a horizontal plane including the top surface of the sacrificial through-wall structure 71 and / or the sacrificial source trench fill structure 47. Laterally alternating sequences of the bit line trench isolation structure 94 and the sacrificial source trench fill structure 47 may be arranged along a first horizontal direction hd1.

[0252] refer to Figure 65A , Figure 65B , Figure 65C , Figure 65D , Figure 65E , Figure 65F and Figure 65G An etch mask layer (not illustrated), such as a photoresist layer, may be formed over the third exemplary structure and may be patterned to form openings over regions of the second subset of the respective sacrificial source trench fill structures in the sacrificial source trench fill structure 47 and the sacrificial isolation trench fill structure 57 that contact the sacrificial source trench fill structure 47. The etch mask layer may cover each of the sacrificial through-hole wall structure 71 and the bit-line trench isolation structure 94.

[0253] At least one third selective material removal process can be performed to selectively remove a second subset of the sacrificial source trench fill structure 47 and the sacrificial isolation trench fill structure 57 relative to the materials of the semiconductor rails (14, 11, 34), the etch stop structure 8, and the sacrificial through-hole wall structure 71. In an exemplary example, if the sacrificial source trench fill structure 47 comprises silicon nitride, a wet etching process using hot phosphoric acid can be performed to remove the sacrificial source trench fill structure 47 without removing the second subset of the sacrificial isolation trench fill structure 57. If the sacrificial source trench fill structure 47 comprises a carbon-based material (such as amorphous carbon or diamond-like carbon), an ashing process can be used to remove the sacrificial source trench fill structure 47. Voids are formed in the volume of the source trench 49. Subsequently, if the second subset of the sacrificial isolation trench fill structure 57 comprises a silicate glass-based material, a wet etching process using diluted hydrofluoric acid can be performed to selectively etch the second subset of the sacrificial isolation trench fill structure 57 relative to the materials of the semiconductor rails (14, 11, 34), the etch stop structure 8, and the sacrificial through-hole wall structure 71. Alternatively, if the sacrificial through-hole wall structure 71 comprises a material different from the materials of the sacrificial source trench fill structure 47 and the sacrificial isolation trench fill structure 57, a single isotropic etching process can be performed to simultaneously etch the materials of the sacrificial source trench fill structure 47 and the sacrificial isolation trench fill structure 57. A second lateral isolation trench 592 is formed in the volume from which the second subset of the sacrificial isolation trench fill structure 57 has been removed. By removing the second subset of the sacrificial isolation trench fill structure 57, the second lateral isolation trench 592 is formed between the second horizontally extending semiconductor channels 34 of laterally adjacent pairs.

[0254] refer to Figure 66A , Figure 66B , Figure 66C , Figure 66D , Figure 66E , Figure 66F and Figure 66G At least one fourth selective material removal process can be performed to remove each of the second-type sacrificial rails 20B. A second inter-rail cavity 292 is formed in the volume from which the second-type sacrificial rails 20B have been removed. By removing the second-type sacrificial rails 20B, the second inter-rail cavity 292 is formed between vertically adjacent pairs of second horizontally extending semiconductor channels 34. The etch mask layer can then be removed.

[0255] In an alternative implementation scheme, refer to Figures 65A to 66G The described set of processing steps can be replaced by any alternative set of processing steps, provided that the material of the sacrificial source trench fill structure 47, the second subset of the sacrificial isolation trench fill structure 57, and the second type of sacrificial rail 20B is removed.

[0256] refer to Figure 67A , Figure 67B , Figure 67C , Figure 67D , Figure 67E , Figure 67F and Figure 67G A second gate dielectric material can be conformally deposited to form a second gate dielectric material layer 30L. For example, a chemical vapor deposition process or an atomic layer deposition process can be used to deposit the second gate dielectric material layer 30L. The thickness of the second gate dielectric material layer 30L can be in the range of 2 nm to 40 nm (such as 4 nm to 20 nm), but smaller and larger thicknesses can also be used.

[0257] According to one aspect of this disclosure, the second gate dielectric material comprises a ferroelectric or charge-trapping dielectric material having at least two programmable states. In one embodiment, the second gate dielectric material comprises or is substantially composed of the ferroelectric dielectric material described above. In one embodiment, the second gate dielectric material comprises a layer stack including a ferroelectric dielectric material layer and a non-ferroelectric dielectric material layer. In another embodiment, the second gate dielectric material comprises or is substantially composed of a charge-trapping dielectric material such as silicon nitride or silicon oxide, or a stack of silicon nitride and silicon oxide sublayers. Generally, the second gate dielectric material may comprise a memory dielectric material having at least two programmable states that provide different resistance or transconductance values ​​to the semiconductor material of the second horizontally extending semiconductor channel 34. In one embodiment, the second gate dielectric material comprises a memory dielectric material having at least two programmable states that modulate the electrical transconductance or resistance of the horizontally extending channel by at least an order of magnitude. For example, the ferroelectric polarization state of the ferroelectric dielectric material causes electrons to be depleted or accumulated in the second horizontally extended semiconductor channel 34, which affects the transconductance or resistance of the channel when current flows through it.

[0258] A continuous second gate electrode material layer 38L may be conformally deposited on a second gate dielectric material layer 30L. The continuous second gate electrode material layer 38L includes a second gate electrode material, which may comprise any suitable conductive material. For example, the continuous second gate electrode material layer 38L may comprise at least one metal barrier layer (such as TiN, TaN, WN, or MoN) and a metal filler layer (such as W, Ti, Ta, Ru, or Mo). The continuous second gate electrode material layer 38L may be formed around each second portion of the horizontally extending semiconductor rails (14, 11, 34), i.e., around each second horizontally extending semiconductor channel 34. The second gate electrode material of the continuous second gate electrode material layer 38L is deposited as a continuous material layer such that the lateral gaps between laterally adjacent pairs of second portions of the horizontally extending semiconductor rails (14, 11, 34) are filled with the second gate electrode material, while the vertical gaps between vertically adjacent pairs of second portions of the horizontally extending semiconductor rails (14, 11, 34) are not completely filled with the second gate electrode material. Therefore, after the deposition of the second gate electrode material in the continuous second gate electrode material layer 38L, a second lateral extension void 67 extending laterally along the second horizontal direction hd2 exists in the unfilled volume of the vertical gap between the second portions of adjacent pairs of semiconductor rails (14, 11, 34). Lateral extension voids 49' may exist within each source trench 49.

[0259] refer to Figure 68A , Figure 68B , Figure 68C , Figure 68D , Figure 68E , Figure 68F and Figure 68G A second dielectric filler material (such as silicon oxide) may be conformally deposited in the second lateral extension void 67, in the peripheral portion of the source trench 49, and on the horizontal extension portion of the continuous second gate electrode material layer 38L overlying the three-dimensional array of semiconductor rails (14, 11, 34). A recessed etching process may be performed to remove portions of the second dielectric filler material from outside the volume of the second lateral extension void 67. The remaining portion of the second dielectric filler material filling the second lateral extension void 67 constitutes a two-dimensional array of second dielectric plates 66. Each second dielectric plate 66 is formed between corresponding vertically adjacent pairs of lateral extension portions of the continuous second gate electrode material layer 38L extending laterally along the second horizontal direction hd2.

[0260] refer to Figure 69A , Figure 69B , Figure 69C , Figure 69D , Figure 69E , Figure 69F and Figure 69GA selective isotropic etching process can be performed to etch portions of the continuous second gate electrode material layer 38L near or overlying the topmost semiconductor rails (14, 11, 34) of the source trench 49. The selective isotropic etching process can selectively etch the second gate electrode material relative to the second gate dielectric material. For example, a wet etching process can be used to selectively etch the second gate electrode material relative to the second gate dielectric material. The selective isotropic etching process patterns the continuous second gate electrode material layers 38L into a one-dimensional array of second gate electrode material layers 38S laterally spaced along a first horizontal direction hd1. Each second gate electrode material layer 38S may surround a corresponding two-dimensional array of semiconductor rails (14, 11, 34), i.e., a corresponding two-dimensional array of the second horizontally extending semiconductor channels 34. For example, each second gate electrode material layer 38S may have a rectangular array of vias through which the corresponding two-dimensional array of the second horizontally extending semiconductor channels 34 laterally extends along the first horizontal direction hd1, such as... Figure 69G As shown. Optionally, an additional selective isotropic etching process may be performed to etch portions of the second gate dielectric material layer 30L near or overlying the topmost semiconductor rails (14, 11, 34) of the source trench 49.

[0261] refer to Figure 70A , Figure 70B , Figure 70C , Figure 70D , Figure 70E , Figure 70F and Figure 70G Dielectric-filling material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in the source trench 49. Planarization processes such as chemical mechanical polishing may be performed to remove portions of the dielectric-filling material from above a horizontal plane including the top surface of the sacrificial through-wall structure 71. Each remaining portion of the source trench 49 filled with dielectric-filling material constitutes a source trench isolation structure 44. In one embodiment, the top surface of the source trench isolation structure 44 may be formed within a horizontal plane including the top surface of the sacrificial through-wall structure 71 and / or the bit line trench isolation structure 94. Laterally alternating sequences of the bit line trench isolation structure 94 and the source trench isolation structure 44 may be arranged along a first horizontal direction hd1.

[0262] In an alternative implementation, the above-described method can be performed relative to... Figures 59A to 64G The steps described above were performed before the actual execution of the steps above. Figures 65A to 70G The steps described.

[0263] refer to Figure 71A , Figure 71B , Figure 71C , Figure 71D , Figure 71E , Figure 71F and Figure 71G A photoresist layer (not shown) may be applied over the third exemplary structure and may be photolithographically patterned to form a total of (L+1) x M openings over the bit line trench isolation structure 94 and the source trench isolation structure 44. Each opening in the photoresist layer may have area overlap in a planar view with a corresponding vertical stack of (N+1) semiconductor rails (14, 11, 34) and (N+1) interfaces between the bit line trench isolation structure 94 or the source trench isolation structure 44. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the bit line trench isolation structure 94 and the source trench isolation structure 44, as well as the end segments of the semiconductor rails (14, 11, 34). A bit line via cavity 95 may be formed through the bit line trench isolation structure 94, extending vertically downward to the etch stop structure 8 (or, if the etch stop structure is omitted, to the substrate 2). A source line via cavity 45 can be formed through the source trench isolation structure 44, extending vertically downward to the etch stop structure 8 (or, if the etch stop structure is omitted, to the substrate 2). The photoresist layer can then be removed, for example, by ashing.

[0264] For each bitline via cavity 95 located between two M x (N+1) arrays 2 x M x (N+1) of semiconductor rails (14, 11, 34), the end sidewall of a first horizontally extending semiconductor channel 14 may be physically exposed to the bitline via cavity 95. For each source via cavity 45 located between two M x (N+1) arrays 2 x M x (N+1) of semiconductor rails (14, 11, 34), the end sidewall of a second horizontally extending semiconductor channel 34 may be physically exposed to the source via cavity 45. Each bitline via cavity 95 may include at least two straight sidewalls extending vertically from the top surface of the bitline trench isolation structure 94 to the top surface of the etch stop structure 8. Each source via cavity 45 may include at least two straight sidewalls extending vertically from the top surface of the source trench isolation structure 44 to the top surface of the etch stop structure 8.

[0265] refer to Figure 72A , Figure 72B , Figure 72C , Figure 72D , Figure 72E , Figure 72F and Figure 72GOptional extension region doping processes can be performed to electrically dope the edge portions of the semiconductor rails (14, 11, 34) near the physically exposed sidewall surfaces of the semiconductor rails (14, 11, 34). For example, vapor phase doping processes or outward diffusion processes using conformally deposited sacrificial doped silicate glass layers (such as sacrificial phosphosilicate glass layers or sacrificial arsenicilicate glass layers) can be used to convert the surface portions of the semiconductor rails (14, 11, 34) near the source via cavity 45 into source extension regions 33, and the surface portions of the semiconductor rails (14, 11, 34) near the in-situ via cavity 95 into drain extension regions 15. In other words, the surface portions of the second horizontally extending semiconductor channel 34 near the source via cavity 45 are converted into source extension regions 33, and the surface portions of the first horizontally extending semiconductor channel 14 near the in-situ via cavity 95 are converted into drain extension regions 15.

[0266] The remaining portion of the first horizontally extended semiconductor channel 14 serves as the channel region for a first field-effect transistor to be subsequently formed. The remaining portion of the second horizontally extended semiconductor channel 34 serves as the channel region for a second field-effect transistor to be subsequently formed. In one embodiment, the first horizontally extended semiconductor channel 14 and the second horizontally extended semiconductor channel 34 may be doped with a first conductivity type, and the source extension region 33 and the drain extension region 15 may be doped with a second conductivity type opposite to the first conductivity type. The extension regions (13, 15) may include lightly doped regions of the second conductivity type. Alternatively, the formation of the source extension region 33 and the drain extension region 15 may be omitted.

[0267] A selective doping semiconductor deposition process can be performed to grow a doped semiconductor material with a second conductivity type from the first physically exposed semiconductor surface of the horizontally extending semiconductor tracks (15, 14, 11, 34, 33) exposed to the source via cavity 45 and the second physically exposed semiconductor surface of the horizontally extending semiconductor tracks (15, 14, 11, 34, 33) exposed to the bit line via cavity 95. In one embodiment, the doped semiconductor material with the second conductivity type can be grown from the physically exposed semiconductor surface of the source extension region 33 exposed to the source via cavity 45 and the physically exposed semiconductor surface of the drain extension region 15 exposed to the bit line via cavity 95.

[0268] The source region 32 is formed on a first sidewall of the semiconductor rails (15, 14, 11, 34, 33) located in the peripheral portion of the source via cavity 44, and the drain region 16 is formed on a second sidewall of the semiconductor rails (14, 11, 34) located in the peripheral portion of the bit line via cavity 95. In one embodiment, the source region 32 may be formed directly on the source extension region 33, and the drain region 16 may be formed directly on the drain extension region 15.

[0269] Source region 32 and drain region 16 may include heavily doped regions of a second conductivity type, having a higher dopant concentration compared to optional extended regions (33, 15). Source region 32 may have different horizontal cross-sectional shapes in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1, varying according to the lateral distance from the nearest semiconductor rail among the semiconductor rails (15, 14, 11, 34, 33). Drain region 16 may also have different horizontal cross-sectional shapes in a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1, varying according to the lateral distance from the nearest semiconductor rail among the semiconductor rails (14, 11, 34). If etch stop structure 8 is omitted, doped semiconductor regions of the second conductivity type are also formed on the exposed etched portion of substrate 2.

[0270] At least one conductive material layer may be deposited in the remaining volume of the bit line via cavity 95 and the source line via cavity 45. The at least one conductive material layer may comprise a combination of a metal barrier material and a metal filler material. Exemplary metal barrier materials include TiN, TaN, WN, and / or MoN. Exemplary metal filler materials include W, Co, Ru, Mo, Ti, Ta, Cu, etc. Excess portions of the at least one conductive material may be removed from above a horizontal plane comprising the top surfaces of the bit line trench isolation structure 94 and the source trench isolation structure 44. The filling of each remaining portion of the corresponding source line via cavity 45 with the at least one conductive material constitutes a vertical source line 46. Each vertical source line 46 located between a pair of M x (N+1) arrays of semiconductor rails (15, 14, 11, 34, 33) contacts two vertical stacks of N source regions 32 and may contact overlying dummy source regions located on dummy semiconductor rails. An L x M array of vertical source lines 46 may be formed. Each remaining portion of the corresponding bit line via cavity 95, filled with at least one conductive material, constitutes a bit line 98. Each bit line 98, located between a pair of M x (N+1) arrays of semiconductor rails (15, 14, 11, 34, 33), contacts two vertically stacked N drain regions 16 and may contact two overlying dummy drain regions. An L' x M array of bit lines 98 may be formed, where the integer L' is (L+1) / 2 or L / 2 or L / 2+1. An L” x M array of vertical source lines 46 may be formed, where the integer L” is (L+1) / 2 or L / 2 or L / 2+1.

[0271] In summary, the two-dimensional array of vertical bit lines 98 can be configured such that each vertical bit line in the vertical bit lines 98 contacts a set of drain regions 16 located within the corresponding vertical stack of the unit cell UC. The two-dimensional array of vertical source lines 46 can be configured such that each vertical source line in the vertical source lines 46 contacts a set of source regions 32 located within the corresponding vertical stack of the unit cell UC.

[0272] In an alternative embodiment, the vertical bit line 98 and the vertical source line 46 may be formed during separate patterning and etching steps. For example, the bit line via cavity 95 and the vertical bit line 98 may be formed in Figures 64A to 64G The steps illustrated and Figures 65A to 65G Between the steps shown. The source line via cavity 45 and the vertical source line 46 can be as described above. Figures 70A to 70G It is formed after the steps shown.

[0273] refer to Figure 73A , Figure 73B , Figure 73C , Figure 73D , Figure 73E , Figure 73F and Figure 73GA selective isotropic etching process can be performed to isotropically etch the material of the one-dimensional array of sacrificial through-wall structures 71. For example, if the sacrificial through-wall structures 71 comprise silicon nitride, a wet etching process using thermal phosphoric acid can be performed to selectively remove the sacrificial through-wall structures 71 relative to the materials of the bit line trench isolation structure 94, the source trench isolation structure 44, the vertical bit line 98, the vertical source line 46, the semiconductor rails (15, 14, 11, 34, 33), the first gate dielectric material layer 60L (or the first gate electrode material layer 68S), and the second gate dielectric material layer 30L (or the second gate electrode material layer 38S). A one-dimensional array of bridge surrounding cavities 77 is formed by removing the one-dimensional array of sacrificial through-wall structures 71. The volume of the one-dimensional array of bridge surrounding cavities 77 formed at this processing step can be compared with that in the reference... Figure 54A , Figure 54B , Figure 54C , Figure 54D , Figure 54E , Figure 54F and Figure 54G The one-dimensional array of bridge-surround cavities formed at the described processing steps has substantially the same volume. Each M x (N+1) two-dimensional array of doped semiconductor material portions 11 arranged along a direction perpendicular to the first horizontal direction hd1 is exposed to a corresponding bridge-surround cavity in the bridge-surround cavity 77.

[0274] refer to Figure 74A , Figure 74B , Figure 74C , Figure 74D , Figure 74E , Figure 74F and Figure 74G Optionally, a metal that can form a metal-semiconductor alloy upon reaction with the semiconductor material of the doped semiconductor material portion 11 may be conformally deposited on the physically exposed surface of the doped semiconductor material portion 11, deposited in the peripheral region of the bridge surrounding cavity 77, and deposited on the bit line trench isolation structure 94 and the source trench isolation cavity 44. The metal may include at least one metal, such as nickel, cobalt, titanium, tantalum, tungsten, molybdenum, platinum, palladium, etc. The metal may be deposited as a conformal metal layer using a conformal deposition process such as chemical vapor deposition. The thickness of the metal may be selected to ensure that the metal layer is formed only in the peripheral portion of the bridge surrounding cavity 77, and that continuously extending voids exist within each bridge surrounding cavity of the bridge surrounding cavity 77.

[0275] An annealing process can then be performed to initiate the formation of a metal-semiconductor alloy region 82 through a reaction between the surface portions of the metal and the doped semiconductor material portion 11 in contact with the metal. If the doped semiconductor material portion 11 comprises silicon, the metal-semiconductor alloy region 82 may comprise a metal silicide. Each unit cell UC in the unit cell UC includes an optional corresponding metal-semiconductor alloy region 82 in contact with the corresponding doped semiconductor material portion 11. In one embodiment, each metal-semiconductor alloy region 82 may be tubularly configured to laterally surround the corresponding doped semiconductor material portion 11.

[0276] Generally, during the formation of the metal-semiconductor alloy region 82, the surface portion of each doped semiconductor material portion 11 can be consumed. In this case, the width of each doped semiconductor material portion 11 along the second horizontal direction hd2 can be reduced. Figure 74C As shown, the reduced width of each doped semiconductor material portion 11 is referred to herein as a reduced second width w2' (e.g., a modified second width w2' or simply the second width w2'), which is smaller than a reference width w2'. Figures 51A to 51G The second width w2 is described. Each metal-semiconductor alloy region 82 may include two horizontal metal-semiconductor alloy plates and two vertical metal-semiconductor alloy plates adjacent to each other. The thickness of each metal-semiconductor alloy region 82 may range from 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0277] The metal-semiconductor alloy region 82 provides enhanced conductivity through the doped semiconductor material portions 11 between adjacent pairs of first horizontally extending semiconductor channels 14 and second horizontally extending semiconductor channels 34, and thus increases the on-state current of the first field-effect transistor and / or the second field-effect transistor to be formed. Within each unit cell UC in the unit cell UC, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 extend laterally along a first horizontal direction hd1. In one embodiment, the lateral extension of the doped semiconductor material portion 11 along the first horizontal direction hd1 is greater than the lateral extension of the metal-semiconductor alloy region 82 along the first horizontal direction hd1. In an alternative embodiment, the metal-semiconductor alloy region 82 may be omitted.

[0278] refer to Figure 75A , Figure 75B , Figure 75C , Figure 75D , Figure 75E , Figure 75F and Figure 75GA first isotropic etching process can be performed to isotropically etch physically exposed portions of the first and second gate dielectric materials surrounding the one-dimensional array of the bridge surrounding cavity 77. The first isotropic etching process can selectively and isotropically etch the materials of the first gate dielectric material layer 60L and the second gate dielectric material layer 30L relative to the materials of the semiconductor rails (15, 14, 11, 34, 33), the metal-semiconductor alloy region 82, the first gate electrode material layer 68S, and the second gate electrode material layer 38S. Each first gate dielectric material layer 60L can be divided into an M x (N+1) two-dimensional array of first gate dielectrics 60, each having a corresponding tubular configuration and laterally surrounding a corresponding first horizontally extending semiconductor channel 14. Each second gate dielectric material layer 30L can be divided into an M x (N+1) two-dimensional array of second gate dielectrics 30, each having a corresponding tubular configuration and laterally surrounding a corresponding second horizontally extending semiconductor channel 34. Therefore, the remaining portion of the first gate dielectric material constitutes a three-dimensional array of the first gate dielectric 60, and the remaining portion of the second gate dielectric material constitutes a three-dimensional array of the second gate dielectric 30.

[0279] A second isotropic etching process can be performed to isotropically etch physically exposed portions of the first and second gate electrode materials surrounding the one-dimensional array of the bridge surrounding cavity 77. The second isotropic etching process can selectively and isotropically etch the materials of the first gate electrode material layer 68S and the second gate electrode material layer 38S relative to the materials of the vertical bit line 98, the vertical source line 46, the semiconductor rails (15, 14, 11, 34, 33), the first gate dielectric 60, and the second gate dielectric 30. Each first gate electrode material layer 68S can be divided into N first word lines 68 and optionally one or more drain select lines. Each first word line 68 laterally surrounds a corresponding set of M first gate dielectrics 60 and thus includes the M first gate electrodes of the M first field-effect transistors. Each second gate electrode material layer 38S can be divided into N second word lines 38 and optionally one or more source select lines. Each second word line 38 laterally surrounds a corresponding set of M second gate dielectrics 30, and thus includes M second gate electrodes of M second field-effect transistors. Therefore, the remaining portion of the first gate electrode material constitutes a two-dimensional array of the first word lines 68, and the remaining portion of the second gate electrode material constitutes a two-dimensional array of the second word lines 38.

[0280] A third exemplary structure may include an L x M x N three-dimensional array of unit cells UC. Each unit cell UC in the unit cells UC includes: an access field-effect transistor (e.g., a read transistor) 100, which includes a first horizontally extending semiconductor channel 14, a first gate dielectric 60, and a first gate electrode (which is part of a first word line 68); and a memory field-effect transistor (e.g., a write transistor) 300, which includes a second horizontally extending semiconductor channel 34, a second gate dielectric 30, and a second gate electrode 38. The second gate dielectric 30 includes a memory dielectric material having at least two programmable states that modulate the resistance and / or transconductance of the second horizontally extending semiconductor channel 34. A doped semiconductor material portion 11 is interposed between the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34. The doped semiconductor material portion 11 has a higher doping concentration than the channels (14, 34).

[0281] In one embodiment, where the channels (14, 34) and the doped semiconductor material portion 11 have opposite conductivity types, a first pn junction exists between the first horizontally extending semiconductor channel 14 and the doped semiconductor material portion 11; and a second pn junction exists between the second horizontally extending semiconductor channel 34 and the doped semiconductor material portion 11. The first pn junction is in contact with a first gate dielectric 60, and the second pn junction is in contact with a second gate dielectric 30.

[0282] Within each unit cell UC of the unit cell UC, a first horizontally extending semiconductor channel 14 and a second horizontally extending semiconductor channel 34 extend laterally along a first horizontal direction hd1. The access field-effect transistor 100 includes a drain region 16 laterally spaced from the doped semiconductor material portion 11 and having a conductivity type opposite to that of the first horizontally extending semiconductor channel 14 (i.e., an opposite doping type). The drain region 16 may have the same or opposite doping type as the doped semiconductor material portion 11. The memory field-effect transistor 300 includes a source region 32 laterally spaced from the doped semiconductor material portion 11 and having a conductivity type opposite to that of the second horizontally extending semiconductor channel 34 (i.e., an opposite doping type). The source region 32 may have the same or opposite doping type as the doped semiconductor material portion 11.

[0283] In one embodiment, the three-dimensional array of unit cells UC includes rows of corresponding unit cells UC arranged along a second horizontal direction hd2, different from the first horizontal direction hd1; columns of corresponding unit cells UC arranged along the first horizontal direction hd1; and a vertical stack of corresponding unit cells UC arranged along a vertical direction. In one embodiment, the device structure includes a two-dimensional array of vertical bit lines 98. Each vertical bit line in the vertical bit lines 98 contacts a set of drain regions 16 located within a corresponding vertical stack of unit cells UC. The device structure also includes a two-dimensional array of vertical source lines 46. Each vertical source line in the vertical source lines 46 contacts a set of source regions 32 located within a corresponding vertical stack of unit cells UC.

[0284] refer to Figure 76A , Figure 76B , Figure 76C , Figure 76D , Figure 76E , Figure 76F and Figure 76G A dielectric filling material (such as silicon oxide) may be conformally deposited in the bridge surrounding cavity 77. Excess portions of the dielectric filling material may be removed above a horizontal plane comprising the top surfaces of the bit line trench isolation structure 94 and the source trench isolation structure 44 by performing a planarization process, which may include a chemical mechanical polishing process or a recess etching process. A one-dimensional array of through-hole dielectric walls 76 may be formed in the bridge surrounding cavity 77. The one-dimensional array of through-hole dielectric walls 76 may be arranged along a first horizontal direction hd1. Each through-hole dielectric wall 76 within the one-dimensional array of through-hole dielectric walls 76 surrounds a corresponding two-dimensional array of doped semiconductor material portions 11.

[0285] In one embodiment, each of the one-dimensional arrays of perforated dielectric walls 76 contacts a corresponding two-dimensional array of the first gate electrode (including the vertically stacked portion of the first word line 68) of the three-dimensional array of the unit cell UC, and contacts a corresponding two-dimensional array of the second gate electrode (including the vertically stacked portion of the second word line 38) of the three-dimensional array of the unit cell UC. In one embodiment, each of the one-dimensional arrays of perforated dielectric walls 76 contacts a corresponding two-dimensional array of the first gate dielectric 60, and contacts a corresponding two-dimensional array of the second gate dielectric 30.

[0286] In one embodiment, each of the perforated dielectric walls 76 in the one-dimensional array of perforated dielectric walls 76 directly contacts the corresponding two-dimensional array of tubular metal-semiconductor alloy regions 82; and each tubular metal-semiconductor alloy region in the tubular metal-semiconductor alloy region 82 surrounds and directly contacts the corresponding doped semiconductor material portion 11.

[0287] refer to Figure 77A , Figure 77B , Figure 77C , Figure 77D , Figure 77E , Figure 77F and Figure 77G This can be achieved by omitting the formation of the metal-semiconductor alloy region 82 (i.e., by omitting the reference). Figures 74A to 74G The described processing steps are used to derive a first alternative configuration of the third exemplary structure from the third exemplary structure described above. In this case, each of the perforated dielectric walls 76 within the one-dimensional array of perforated dielectric walls 76 directly contacts the corresponding two-dimensional array of the doped semiconductor material portion 11. Figures 77A to 77G The second width w2 of the doped semiconductor material portion 11 in the illustrated device structure can be compared with the reference... Figures 51A to 51G The second width w2 described is the same.

[0288] refer to Figure 78A , Figure 78B , Figure 78C , Figure 78D , Figure 78E , Figure 78F and Figure 78G References can be omitted Figures 72A to 72G The described selective semiconductor deposition process is used to derive a second alternative configuration of the third exemplary structure from the third exemplary structure. In this case, refer to Figures 72A to 72G The described source extension region 33 can serve as the source region 32 in a second alternative configuration of the third exemplary structure, and references Figures 72A to 72G The described drain extension region 15 can serve as the drain region 16 in a second alternative configuration of the third exemplary structure.

[0289] In the third embodiment, the doped semiconductor material portion 11 and the optional metal-semiconductor alloy region 82 reduce the resistance between the source region 32 and the drain region 16 of each pair of channels (14, 34) of the two transistors (100, 300). Furthermore, the formation of the bridge-around cavity 77 allows for easier access to pattern the first and second word lines.

[0290] Referring together to all embodiments, a device structure includes a three-dimensional array of unit cells UC. Each unit cell UC includes: a access field-effect transistor 100, which includes a first horizontally extending semiconductor channel 14, a drain region 16, a first gate dielectric 60, and a first gate electrode (which is part of a first word line 68); and a memory field-effect transistor 300, which includes a second horizontally extending semiconductor channel 34, a source region 32, a second gate dielectric 30, and a second gate electrode 38. The second gate dielectric 30 includes a memory dielectric material having at least two programmable states.

[0291] In one embodiment, the doped semiconductor material portion 11 is located between the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34.

[0292] In one embodiment, the doped semiconductor material portion 11 contacts a first sidewall of a first horizontally extending semiconductor channel 14 and a first sidewall of a second horizontally extending semiconductor channel 34. In one embodiment, within each unit cell UC: the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 extend laterally along a first horizontal direction hd1; and the width of the central segment of the doped semiconductor material portion 11 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 is smaller than the width of the first horizontally extending semiconductor channel 14 along the second horizontal direction hd2. In one embodiment, within each unit cell UC, the first horizontally extending semiconductor channel 14 has a first uniform vertical extension; and the doped semiconductor material portion 11 has a second uniform vertical extension not greater than the first uniform vertical extension.

[0293] In one embodiment, the device structure further includes a one-dimensional array of through-hole dielectric walls 76 arranged along a first horizontal direction hd1, wherein each through-hole dielectric wall 76 within the one-dimensional array surrounds a corresponding two-dimensional array of doped semiconductor material portions 11. In one embodiment, each through-hole dielectric wall 76 within the one-dimensional array contacts a corresponding two-dimensional array of first gate electrodes (including vertically stacked portions of first word lines 68) and a corresponding two-dimensional array of second gate electrodes (including vertically stacked portions of second word lines 38).

[0294] In one embodiment, each of the perforated dielectric walls 76 within the one-dimensional array of perforated dielectric walls 76 contacts a corresponding two-dimensional array of the first gate dielectric 60 and a corresponding two-dimensional array of the second gate dielectric 30. In another embodiment, each of the perforated dielectric walls 76 within the one-dimensional array of perforated dielectric walls 76 directly contacts a corresponding two-dimensional array of the doped semiconductor material portion 11.

[0295] In one embodiment, each of the perforated dielectric walls 76 in the one-dimensional array of perforated dielectric walls 76 directly contacts the corresponding two-dimensional array of the tubular metal-semiconductor alloy region 48; and the corresponding two-dimensional array of the tubular metal-semiconductor alloy region 48 surrounds the corresponding two-dimensional array of the doped semiconductor material portion 11 and directly contacts the corresponding two-dimensional array of the doped semiconductor material portion.

[0296] In one embodiment, each unit cell UC in the unit cell UC further includes a metal-semiconductor alloy region 82 in contact with the doped semiconductor material portion 11. In one embodiment, the metal-semiconductor alloy region 82 laterally surrounds the doped semiconductor material portion 11 and has a tubular configuration.

[0297] In one embodiment, the first horizontally extending semiconductor channel 14 and the second horizontally extending semiconductor channel 34 extend laterally along the first horizontal direction hd1; and the lateral extension of the doped semiconductor material portion 11 along the first horizontal direction hd1 is greater than the lateral extension of the metal-semiconductor alloy region 82 along the first horizontal direction hd1.

[0298] In one embodiment, the drain region 16 contacts the second sidewall of the first horizontally extending semiconductor channel 14 and has a conductivity type opposite to that of the first horizontally extending semiconductor channel 14; and the source region 32 contacts the second sidewall of the second horizontally extending semiconductor channel 34 and has a conductivity type opposite to that of the second horizontally extending semiconductor channel 34.

[0299] In one embodiment, the three-dimensional array of unit cells UC includes rows of corresponding unit cells UC arranged along a second horizontal direction hd2, different from the first horizontal direction hd1; columns of corresponding unit cells UC arranged along the first horizontal direction hd1; and a vertical stack of corresponding unit cells UC arranged along a vertical direction. In one embodiment, the device structure also includes a two-dimensional array of vertical bit lines 98, wherein each vertical bit line of the vertical bit lines 98 contacts a set of drain regions 16 located within the corresponding vertical stack of unit cells UC; and a two-dimensional array of vertical source lines 46, wherein each vertical source line of the vertical source lines 46 contacts a set of source regions 32 located within the corresponding vertical stack of unit cells UC.

[0300] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” envision that the words “substantially constitute…” or “consist of…” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In the cases where embodiments using specific structures and / or magnetic configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or magnetic configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A device structure comprising a three-dimensional array of unit cells, wherein each unit cell comprises: A field-effect transistor, the field-effect transistor comprising a first horizontally extending semiconductor channel, a drain region, a first gate dielectric, and a first gate electrode; A memory field-effect transistor, the memory field-effect transistor including a second horizontally extended semiconductor channel, a source region, a second gate dielectric and a second gate electrode, wherein the second gate dielectric includes a memory dielectric material having at least two programmable states.

2. The device structure according to claim 1, further comprising: The doped semiconductor material portion is located between the first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel.

3. The device structure of claim 2, wherein the doped semiconductor material portion contacts a first sidewall of the first horizontally extending semiconductor channel and a first sidewall of the second horizontally extending semiconductor channel.

4. The device structure according to claim 3, wherein: The first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel extend laterally along the first horizontal direction; and The width of the central segment of the doped semiconductor material portion along a second horizontal direction perpendicular to the first horizontal direction is smaller than the width of the semiconductor channel extending in the first horizontal direction along the second horizontal direction.

5. The device structure according to claim 4, wherein: The first horizontally extending semiconductor channel has a first uniform vertical extension; and The doped semiconductor material portion has a second uniform vertical extension that is no greater than the first uniform vertical extension.

6. The device structure according to claim 2, further comprising: A one-dimensional array of perforated dielectric walls arranged along a first horizontal direction, wherein each perforated dielectric wall within the one-dimensional array of perforated dielectric walls surrounds a corresponding two-dimensional array of the doped semiconductor material portion.

7. The device structure of claim 6, wherein each perforated dielectric wall in the one-dimensional array of perforated dielectric walls contacts a corresponding two-dimensional array of the first gate electrode and a corresponding two-dimensional array of the second gate electrode.

8. The device structure of claim 7, wherein each perforated dielectric wall in the one-dimensional array of perforated dielectric walls contacts a corresponding two-dimensional array of the first gate dielectric and a corresponding two-dimensional array of the second gate dielectric.

9. The device structure of claim 6, wherein each perforated dielectric wall in the one-dimensional array of perforated dielectric walls directly contacts the corresponding two-dimensional array of the doped semiconductor material portion.

10. The device structure according to claim 6, wherein: Each perforated dielectric wall in the one-dimensional array of perforated dielectric walls directly contacts the corresponding two-dimensional array of tubular metal-semiconductor alloy regions. and The corresponding two-dimensional array of the tubular metal-semiconductor alloy region surrounds and directly contacts the corresponding two-dimensional array of the doped semiconductor material portion.

11. The device structure of claim 2, wherein each unit cell further comprises a metal-semiconductor alloy region in contact with the doped semiconductor material portion.

12. The device structure according to claim 11, wherein: The metal-semiconductor alloy region laterally surrounds the doped semiconductor material portion and has a tubular configuration; The first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel extend laterally along the first horizontal direction; and The doped semiconductor material portion extends laterally along the first horizontal direction more than the metal-semiconductor alloy region extends laterally along the first horizontal direction.

13. The device structure according to claim 1, wherein the second gate dielectric comprises a ferroelectric dielectric material.

14. The device structure according to claim 1, wherein: The drain region contacts the second sidewall of the first horizontally extending semiconductor channel and has a conductivity type opposite to that of the first horizontally extending semiconductor channel. and The source region contacts the second sidewall of the second horizontally extending semiconductor channel and has a conductivity type opposite to that of the second horizontally extending semiconductor channel.

15. The device structure of claim 1, wherein the three-dimensional array of the unit cells comprises rows of corresponding unit cells arranged along a second horizontal direction different from the first horizontal direction, columns of corresponding unit cells arranged along the first horizontal direction, and vertical stacks of corresponding unit cells arranged along a vertical direction.

16. The device structure according to claim 15, further comprising: A two-dimensional array of vertical bit lines, wherein each vertical bit line contacts a set of drain regions located within a corresponding vertical stack of unit cells; as well as A two-dimensional array of vertical source lines, wherein each vertical source line contacts a set of source regions located within a corresponding vertical stack of unit cells.

17. A method for forming a device structure, the method comprising: The process involves vertically alternating stacks of horizontally extending semiconductor rails and horizontally extending sacrificial rails, wherein each vertically alternating stack extends laterally along a first horizontal direction, and the vertically alternating stacks are laterally spaced from each other along a second horizontal direction by lateral isolation trenches including uniform width portions and lateral protrusion portions. By diffusing an electric dopant in the proximal portion of the lateral protrusion surrounding the lateral isolation trench of the horizontally extending semiconductor track, the proximal portion is transformed into a three-dimensional array of doped semiconductor material portions. The vertically alternating stack is patterned, wherein the patterned portion of the vertically alternating stack includes a three-dimensional array of horizontally extending semiconductor rails, each of the horizontally extending semiconductor rails having a corresponding first horizontally extending semiconductor channel, a corresponding doped semiconductor material portion and a second horizontally extending semiconductor channel, wherein the corresponding doped semiconductor material portion is a corresponding doped semiconductor material portion within the doped semiconductor material portion. A first gate dielectric material and a first gate electrode material are deposited around the first horizontally extended semiconductor channel; A second gate dielectric material and a second gate electrode material are deposited around the second horizontally extended semiconductor channel; A one-dimensional array of bridge-around cavities is formed such that each two-dimensional array of doped semiconductor material portions arranged along a direction perpendicular to the first horizontal direction is exposed to a corresponding bridge-around cavity in the bridge-around cavity; as well as The first gate electrode material and the second gate electrode material around the one-dimensional array of the bridge surrounding cavity are etched isotropically, wherein the remaining portion of the first gate electrode material constitutes a two-dimensional array of the first word lines, and the remaining portion of the second gate electrode material constitutes a two-dimensional array of the second word lines.

18. The method according to claim 17, further comprising: The first gate dielectric material and the second gate dielectric material surrounding the one-dimensional array of the bridge surrounding cavity are etched isotropically, wherein the remaining portion of the first gate dielectric material constitutes a three-dimensional array of the first gate dielectric, and the remaining portion of the second gate dielectric material constitutes a three-dimensional array of the second gate dielectric.

19. The method of claim 17, further comprising: A one-dimensional array of sacrificial perforated wall structures is formed, wherein: Each sacrificial perforation wall structure in the sacrificial perforation wall structure surrounds a corresponding two-dimensional array of the doped semiconductor material portion within the three-dimensional array of the doped semiconductor material portion; and The one-dimensional array of the bridge surrounding cavity is formed by removing the one-dimensional array of the sacrificial perforated wall structure.

20. The method of claim 17, wherein the second gate dielectric material comprises a memory dielectric material having at least two programmable states.

21. A device structure comprising a three-dimensional array of unit cells, the three-dimensional array of unit cells comprising a vertical stack of the unit cells arranged along a vertical direction, wherein each unit cell comprises: An access field-effect transistor, the access field-effect transistor comprising a set of semiconductor material portions, the set of semiconductor material portions comprising a horizontally extending semiconductor channel; as well as A memory device having a first electrode electrically connected to a sidewall of the set of semiconductor material portions, a second electrode spaced apart from the access field-effect transistor, and a memory layer located between the first electrode and the second electrode.

22. The device structure of claim 21, wherein the first electrode physically contacts the sidewall of the set of semiconductor material portions.

23. The device structure according to claim 22, wherein the first electrode comprises: An end conductive plate, wherein the end conductive plate is perpendicular to the first horizontal direction; A top conductive plate, which is adjacent to the top of the end conductive plate and extends laterally along the first horizontal direction; A bottom conductive plate, the bottom conductive plate being adjacent to the bottom of the end conductive plate and extending laterally along the first horizontal direction; A first conductive sidewall plate, the first conductive sidewall plate being adjacent to the first vertically extending edge of the end conductive plate and extending laterally along the first horizontal direction; as well as The second conductive sidewall plate is adjacent to the second vertically extending edge of the end conductive plate and extends laterally along the first horizontal direction.

24. The device structure according to claim 23, wherein: The top surface of the set of semiconductor material portions and the top surface of the top conductive plate are located in a first horizontal plane; The bottom surface of the set of semiconductor material portions and the bottom surface of the bottom conductive plate are located in the second horizontal plane; The first sidewall of the semiconductor material portion and the outer sidewall of the first conductive sidewall plate are located in a first vertical plane parallel to the first horizontal direction; and The second sidewall of the semiconductor material portion and the outer sidewall of the second conductive sidewall plate are located in a second vertical plane parallel to the first horizontal direction.

25. The device structure of claim 21, wherein the set of semiconductor material portions further includes a source region in contact with the first electrode and a drain region located on the opposite side of the horizontally extending channel relative to the source region.

26. The device structure according to claim 25, wherein: The horizontally extending semiconductor channel and the source region have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the horizontally extending semiconductor channel or the source region and is perpendicular to the first horizontal direction, regardless of the position of the vertical cutting plane of the corresponding vertical cross-sectional view; and The drain region has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction, which varies according to the lateral distance from the horizontally extending semiconductor channel.

27. The device structure according to claim 25, wherein the access field-effect transistor further comprises: A tubular gate dielectric that laterally surrounds the horizontally extending semiconductor channel and extends laterally along the first horizontal direction; as well as A gate electrode that surrounds the tubular gate dielectric in a vertical cross-sectional view perpendicular to the first horizontal direction.

28. The device structure according to claim 27, wherein: The gate electrode includes a portion of the word line that extends laterally along a second horizontal direction as the gate electrode; and The tubular gate dielectric includes a top dielectric portion that contacts a horizontal top surface of the horizontally extending semiconductor channel, a bottom dielectric portion that contacts a horizontal bottom surface of the horizontally extending semiconductor channel, and a pair of sidewall dielectric portions that contact a pair of sidewalls of the horizontally extending semiconductor channel. and Each of the top dielectric portion, the bottom dielectric portion, and the pair of sidewall dielectric portions is contacted by the gate electrode.

29. The device structure according to claim 25, further comprising: A vertical bit line and a vertical write line, the vertical bit line contacting the drain region of the corresponding vertical stack in the vertical stack, and the vertical write line electrically connected to the second electrode of the corresponding vertical stack in the vertical stack.

30. The device structure according to claim 21, wherein the three-dimensional array of the unit cells further comprises: Rows of corresponding unit cells arranged along a second horizontal direction different from the first horizontal direction; as well as A column of corresponding unit cells arranged along the first horizontal direction.

31. The device structure according to claim 30, further comprising: A two-dimensional array of vertical bit lines and vertical write lines.

32. The device structure according to claim 31, wherein: Each of the vertical bit lines contacts a set of drain regions located within the corresponding vertical stack in the vertical stack of the unit cell; Each of the vertical write lines includes a vertical conductive wall structure extending laterally along the second horizontal direction; and Each of the second electrodes includes a conductive lateral protrusion that projects laterally from the conductive wall structure along the first horizontal direction.

33. The device structure according to claim 21, wherein the memory device is a ferroelectric capacitor and the memory layer comprises a ferroelectric dielectric material.

34. The device structure of claim 21, wherein the memory device is a charge storage capacitor and the memory layer comprises a charge storage dielectric material.

35. The device structure of claim 21, wherein the memory device is a variable resistor, and the memory layer comprises a material selected from: Filament-type resistive dielectric material; Oxygen vacancy-modulated resistive dielectric materials; Phase change materials; or Polymer materials exhibiting resistive switching characteristics.

36. A method for forming a device structure, the method comprising: A three-dimensional array of horizontally extending semiconductor tracks is formed on a substrate, which extends laterally along a first horizontal direction, wherein the three-dimensional array of horizontally extending semiconductor tracks is structurally supported by a three-dimensional array of horizontally extending sacrificial tracks. A first inter-rail cavity is formed between the first portions of the vertically adjacent pairs of the horizontally extending sacrificial rails by removing a first portion of each horizontally extending sacrificial rail. Deposit gate dielectric material and gate electrode material around each first portion of the horizontally extending semiconductor rail; A second inter-rail cavity is formed between the vertically adjacent pairs of the horizontally extending semiconductor rails by removing a second portion of each of the horizontally extending sacrificial rails. The gate dielectric material and the gate electrode material are patterned into a three-dimensional array of gate dielectric and a two-dimensional array of word lines; as well as The second portion of the horizontally extended semiconductor track is replaced with a three-dimensional array of instances of storage devices.

37. The method of claim 36, wherein the memory device comprises a two-terminal device, the two-terminal device comprising a first electrode, a second electrode, and a memory layer located between the first electrode and the second electrode.

38. The method of claim 37, wherein the storage device comprises a ferroelectric capacitor.

39. The method of claim 37, wherein the storage device comprises a charge storage capacitor.

40. The method of claim 37, wherein the storage device comprises a variable resistor.

41. A device structure comprising a three-dimensional array of unit cells, wherein each unit cell comprises: A field-effect transistor, the field-effect transistor including a first horizontally extended semiconductor channel, a first gate dielectric and a first gate electrode; as well as A memory field-effect transistor, the memory field-effect transistor including a second horizontally extended semiconductor channel, a second gate dielectric and a second gate electrode, wherein the second gate dielectric includes a memory dielectric material having at least two programmable states.

42. The device structure of claim 41, wherein the second horizontally extending semiconductor channel contacts the first horizontally extending semiconductor channel.

43. The device structure of claim 41, wherein the second horizontally extending semiconductor channel and the first horizontally extending semiconductor channel comprise the same semiconductor material, but comprise electrical dopants of the same conductivity type with different atomic concentrations.

44. The device structure of claim 41, wherein the second horizontally extending semiconductor channel and the first horizontally extending semiconductor channel have the same material composition.

45. The device structure according to claim 41, wherein: The first horizontally extending semiconductor channel and the second horizontally extending semiconductor channel have the same uniform vertical cross-sectional shape in any vertical cross-sectional view that cuts through the first horizontally extending semiconductor channel or the second horizontally extending semiconductor channel and is perpendicular to the first horizontal direction, regardless of the position of the vertical cutting plane of the respective vertical cross-sectional view. The access field-effect transistor includes a drain region; The memory field-effect transistor includes a source region having the same material composition as the drain region; and The drain region has a variable vertical cross-sectional shape in a vertical plane perpendicular to the first horizontal direction, which varies according to the lateral distance from the semiconductor channel extending from the first horizontal direction.

46. ​​The device structure of claim 41, wherein the sidewall of the second gate dielectric contacts the sidewall of the first gate electrode, and the interface between the sidewall of the second gate dielectric and the sidewall of the first gate electrode is perpendicular to the first horizontal direction.

47. The device structure of claim 41, wherein the first gate dielectric is in contact with the second gate dielectric, and wherein the interface between the first gate dielectric and the second gate dielectric includes a horizontal surface segment and a vertical surface segment parallel to the first horizontal direction.

48. The device structure according to claim 41, further comprising: A dielectric gate spacer that contacts the sidewall of the second gate electrode and is laterally spaced from the first gate electrode and the first gate dielectric by the second gate dielectric.

49. The device structure according to claim 41, wherein: The first gate dielectric has a first tubular configuration and laterally surrounds the first horizontally extending semiconductor channel and extends laterally along the first horizontal direction; The second gate dielectric includes a portion having a second tubular configuration and laterally surrounding the second horizontally extending semiconductor channel and extending laterally along the first horizontal direction; The first gate electrode includes a portion of the first word line extending laterally along a second horizontal direction; and The second gate electrode includes a portion of the second word line that extends laterally along the second horizontal direction.

50. The device structure according to claim 41, wherein: The first gate electrode surrounds the first gate dielectric in a first vertical cross-sectional view perpendicular to the first horizontal direction; and The second gate electrode surrounds the second gate dielectric in a second vertical cross-sectional view perpendicular to the first horizontal direction.

51. The device structure of claim 41, wherein the three-dimensional array of the unit cells is arranged to provide: Rows of corresponding unit cells arranged along a second horizontal direction different from the first horizontal direction; A column of corresponding unit cells arranged along the first horizontal direction; as well as Vertical stacking of corresponding unit cells arranged in a vertical direction.

52. The device structure of claim 51, wherein each second gate dielectric in the three-dimensional memory array is a portion of a corresponding continuous gate dielectric layer that extends laterally along the second horizontal direction and contacts the first gate electrode of each access field-effect transistor in the corresponding row unit cell.

53. The device structure according to claim 51, further comprising: A two-dimensional array of vertical bit lines, wherein each vertical bit line contacts a set of drain regions located within a corresponding vertical stack of unit cells; as well as A two-dimensional array of vertical source lines, wherein each vertical source line contacts a set of source regions located within a corresponding vertical stack of unit cells.

54. The device structure according to claim 41, further comprising: A two-dimensional array of dielectric plates arranged along the first horizontal direction and along the vertical direction, wherein each dielectric plate contacts the top surface of a corresponding lower overlay word line including the first row of the second gate electrodes and contacts the bottom surface of a corresponding upper overlay word line including the second row of the second gate electrodes.

55. The device structure according to claim 41, wherein the second gate dielectric comprises a ferroelectric dielectric material.

56. The device structure of claim 41, wherein the second gate dielectric comprises a charge trapping dielectric material.

57. A method for forming a device structure, the method comprising: A three-dimensional array of horizontally extending semiconductor tracks is formed on a substrate, which extends laterally along a first horizontal direction, wherein the three-dimensional array of horizontally extending semiconductor tracks is structurally supported by a three-dimensional array of horizontally extending sacrificial tracks. A first inter-rail cavity is formed between the first portions of the vertically adjacent pairs of the horizontally extending sacrificial rails by removing a first portion of each horizontally extending sacrificial rail. A first gate dielectric material and a first gate electrode material are deposited around each first portion of the horizontally extending semiconductor rail; A second inter-rail cavity is formed between the vertically adjacent pairs of the horizontally extending semiconductor rails by removing a second portion of each of the horizontally extending sacrificial rails. The first gate dielectric material and the first gate electrode material are patterned into a three-dimensional array of the first gate dielectric and a two-dimensional array of the first word lines, wherein each of the first word lines includes a corresponding row of first gate electrodes arranged along a second horizontal direction. as well as A second gate electrode is formed around the second portion of each of the horizontally extending semiconductor rails.

58. The method according to claim 57, further comprising: A second gate dielectric material, comprising a memory dielectric material having at least two programmable states, a dielectric gate spacer material, and a dielectric plate are deposited in the second inter-track cavity and around the second portion of each horizontally extending semiconductor track in the horizontally extending semiconductor track. as well as The first portion of the dielectric gate spacer material is replaced with the second gate electrode.

59. The method of claim 58, wherein the second gate dielectric material comprises a ferroelectric dielectric material.

60. The method of claim 58, wherein the second gate dielectric material comprises a charge trapping dielectric material.

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