Laminated ceramic electronic component

Abstract

The invention provides a laminated ceramic electronic component capable of suppressing delamination. The laminated ceramic electronic component has: a dielectric layer (11) having a main phase and a segregation substance (40) containing a first rare earth element, a second rare earth element, and magnesium; a plurality of internal electrode layers (12) provided with the dielectric layer therebetween; and external electrodes (20a, 20b) electrically connected to the internal electrode layer (12).

Description

Technical Field

[0001] This invention relates to laminated ceramic electronic components. Background Technology

[0002] In high-frequency communication systems, such as portable telephones, multi-layer ceramic electronic components, such as multi-layer ceramic capacitors (MLCCs), are used to remove noise (see, for example, Patent Documents 1-3).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-181537

[0006] Patent Document 2: Japanese Patent Application Publication No. 2015-182951

[0007] Patent Document 3: Japanese Patent Application Publication No. 2012-33556 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] The dielectric layer and internal electrode layer of a laminated ceramic electronic component can be formed by sintering powder materials. However, delamination can occur between the dielectric layer and the internal electrode layer after sintering.

[0010] The present invention was made in view of the above-mentioned technical problems, and its object is to provide a laminated ceramic electronic component capable of suppressing delamination.

[0011] Means for solving technical problems

[0012] The stacked ceramic electronic component of the present invention comprises: a dielectric layer having a main phase and a segregation comprising a first rare earth element, a second rare earth element and magnesium; a plurality of internal electrode layers disposed therebetween the dielectric layer; and external electrodes electrically connected to the internal electrode layers.

[0013] In the above-mentioned stacked ceramic electronic components, the segregated material may be in contact with the internal electrode layer.

[0014] In the above-mentioned stacked ceramic electronic components, the ionic radius of the second rare earth element may be greater than that of the first rare earth element.

[0015] In the aforementioned stacked ceramic electronic components, the first rare earth element may be holmium or yttrium, and the second rare earth element may be gadolinium or europium.

[0016] In the above-mentioned multilayer ceramic electronic components, the molar ratio of the first rare earth element to magnesium in the segregated material may be 1.5 to 50, and the molar ratio of the second rare earth element to magnesium may be 0.3 to 10.

[0017] In the above-mentioned stacked ceramic electronic components, the molar ratio of the first rare earth element to the second rare earth element in the segregated material may be more than 1 and less than 16.

[0018] In the above-mentioned stacked ceramic electronic components, the average particle size of the segregated material may be 0.1 μm or more and 2.0 μm or less.

[0019] In the aforementioned stacked ceramic electronic components, it can be that, in the cross-section of the dielectric layer, per μm 2 On average, it contains more than 0.01 and less than 1 of the aforementioned segregants.

[0020] In the above-mentioned stacked ceramic electronic components, the main phase may have a grain boundary phase, which includes silicon, aluminum, manganese and vanadium.

[0021] In the aforementioned stacked ceramic electronic components, the thickness of the grain boundary phase may be between 10 nm and 150 nm, and in the cross-section of the dielectric layer, per μm 2 On average, it contains more than 0.01 and less than 1 grain boundary phase.

[0022] Invention Effects

[0023] Using this invention, it is possible to provide a laminated ceramic electronic component that can suppress delamination. Attached Figure Description

[0024] Figure 1 This is a three-dimensional view of a partial cross-section of a multilayer ceramic capacitor.

[0025] Figure 2 yes Figure 1 AA-line cross-section diagram.

[0026] Figure 3 yes Figure 1 BB line cross-section diagram.

[0027] Figure 4 (a) and (b) are enlarged views of the XZ section.

[0028] Figure 5 This is a cross-sectional view of the dielectric layer.

[0029] Figure 6 It is a cross-sectional view of the dielectric layer and the internal electrode layer.

[0030] Figure 7It is a cross-sectional view of the dielectric layer and the internal electrode layer.

[0031] Figure 8 It is a cross-sectional view of the dielectric layer and the internal electrode layer.

[0032] Figure 9 This is a flowchart illustrating a method for manufacturing multilayer ceramic capacitors.

[0033] Figure 10 (a) and (b) are diagrams illustrating the internal electrode formation process.

[0034] Figure 11 This is a diagram illustrating the crimping process.

[0035] Explanation of reference numerals in the attached figures

[0036] 10 Main body, 11 Dielectric layer, 12 Internal electrode layer, 13 Cover layer, 14 Capacitor section, 15 End edge, 16 Side edge, 20a, 20b External electrodes, 30 Dielectric particles, 31 Core, 32 Shell, 40 Segregation, 41 Interface, 42 Grain boundary phase, 51 Dielectric green sheet, 52 Internal electrode pattern, 53 Dielectric pattern, 54 Cover sheet, 100 Multilayer ceramic capacitor. Detailed Implementation

[0037] The embodiments will now be described with reference to the accompanying drawings.

[0038] (Implementation Method)

[0039] Figure 1 This is a partial cross-sectional perspective view of the stacked ceramic capacitor 100 according to the embodiment. Figure 2 yes Figure 1 AA-line cross-section diagram. Figure 3 yes Figure 1 The BB line cross-sectional view. (See diagram below.) Figures 1-3 As illustrated, the multilayer ceramic capacitor 100 includes: a body 10 having a generally cuboid shape; and external electrodes 20a and 20b disposed on any two opposite end faces of the body 10. Furthermore, the two surfaces of the body 10 other than the two end faces, excluding the upper and lower surfaces in the stacking direction, are referred to as side faces. The external electrodes 20a and 20b extend along the upper surface, lower surface, and two side faces of the body 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0040] In addition, Figures 1-3In this diagram, the Z-axis direction (first direction) is the stacking direction and the direction in which the internal electrode layers are opposite to each other. The X-axis direction (second direction) is the length direction of the main body 10, the direction in which the two end faces of the main body 10 are opposite to each other, and the direction in which the external electrodes 20a and 20b are opposite to each other. The Y-axis direction (third direction) is the width direction of the internal electrode layers and the direction in which the two sides of the main body 10 other than the two end faces are opposite to each other. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other.

[0041] The main body 10 has a structure in which dielectric layers 11, comprising ceramic material that functions as a dielectric, and internal electrode layers 12 are alternately stacked. The end edges of each internal electrode layer 12 are alternately exposed on the end face of the main body 10 where external electrodes 20a and 20b are disposed. Thus, each internal electrode layer 12 is alternately connected to both external electrodes 20a and 20b. As a result, the multilayer ceramic capacitor 100 has a structure in which multiple dielectric layers 11 are stacked with internal electrode layers 12 in between. Furthermore, in the stack of dielectric layers 11 and internal electrode layers 12, the internal electrode layers 12 are disposed on the outermost layer in the stacking direction, and the upper and lower surfaces of this stack are covered by a capping layer 13. The capping layer 13 is primarily composed of ceramic material. For example, the composition of the capping layer 13 can be the same as or different from that of the dielectric layers 11. Moreover, it is not limited to the structure as long as the internal electrode layers 12 are exposed on two different surfaces and connected to different external electrodes. Figures 1 to 3 The structure.

[0042] The dimensions of the multilayer ceramic capacitor 100 are, for example, a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm; or a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm; or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm; or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm; or a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm; or a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm, but are not limited to these dimensions.

[0043] The internal electrode layer 12 is primarily composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn), or alloys containing them. Alternatively, noble metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing them, can also be used as the internal electrode layer 12. The average thickness of each internal electrode layer 12 in the Z-axis direction is, for example, 1.0 μm or less, 0.5 μm or less, or 0.2 μm or less. The thickness of the internal electrode layer 12 can be measured by observing the cross-section of the stacked ceramic capacitor 100 using a SEM (scanning electron microscope), measuring the thickness at 10 points for each of the 10 different internal electrode layers 12, and deriving the average value of all measured points.

[0044] The dielectric layer 11 is primarily composed of a ceramic material having a perovskite structure represented by the general formula ABO3. Furthermore, this perovskite structure contains ABO3, deviating from its stoichiometric composition. 3-α For example, as this ceramic material, materials selected from barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and Ba, which form a perovskite structure, can be used. 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≤x≤1, 0≤y≤1, 0≤z≤1), etc. Ba 1-x- y Ca x Sr y Ti 1-z Zr z O3 can be barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, or barium calcium zirconate titanate. For example, the dielectric layer 11 contains more than 90 at% of the main component ceramic. The thickness of the dielectric layer 11 is, for example, 1 μm to 11 μm, 1 μm to 10 μm, or 1 μm to 9 μm. The thickness of the dielectric layer 11 can be measured by observing the cross-section of the multilayer ceramic capacitor 100 using a SEM (scanning electron microscope), measuring the thickness at 10 points for each of the 10 different dielectric layers 11, and deriving the average value of all measured points.

[0045] Additives may be added to the dielectric layer 11. Examples of additives added to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] like Figure 2 As illustrated, the regions of the inner electrode layer 12 connected to the external electrode 20a and the inner electrode layer 12 connected to the external electrode 20b, which are opposite each other, are the regions in the multilayer ceramic capacitor 100 that generate capacitance. Therefore, this region that generates capacitance is called the capacitor section 14. That is, the capacitor section 14 is the region of adjacent inner electrode layers 12 connected to different external electrodes that are opposite each other.

[0047] The region of the internal electrode layers 12 connected to the external electrode 20a that is opposite to each other without being separated from the internal electrode layers 12 connected to the external electrode 20b is called the end edge 15. Similarly, the region of the internal electrode layers 12 connected to the external electrode 20b that is opposite to each other without being separated from the internal electrode layers 12 connected to the external electrode 20a is also the end edge 15. In other words, the end edge 15 is the region of the internal electrode layers 12 connected to the same external electrode that is opposite to the internal electrode layers 12 connected to different external electrodes. The end edge 15 is a region that does not generate capacitance.

[0048] like Figure 3 As illustrated, in the main body 10, the side edge 16 is a region that covers the ends (ends in the Y-axis direction) of the two side surfaces of the dielectric layer 11 and the internal electrode layer 12. That is, the side edge 16 is a region located outside the capacitor section 14 in the Y-axis direction. The side edge 16 is also a region that does not generate capacitance.

[0049] Figure 4 (a) is an enlarged cross-sectional view near the external electrode 20a. Figure 4 (b) is an enlarged cross-sectional view near the external electrode 20b. Figure 4 (a) and Figure 4 In (b), the shading is omitted. For example... Figure 4 (a) and Figure 4As illustrated in (b), the external electrodes 20a and 20b have a structure in which a plating layer 22 is provided on a base layer 21. The base layer 21 is mainly composed of nickel, copper, etc. The base layer 21 may contain ceramic particles as a common material, or it may contain glass. The plating layer 22 is mainly composed of metals such as nickel, copper, aluminum, zinc, tin, or alloys of two or more of these metals. The plating layer 22 may be a plating layer with a single metal composition, or it may be multiple plating layers with different metal compositions. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed sequentially from the base layer 21 side. The first plating layer 23 is, for example, a copper plating layer. The second plating layer 24 is, for example, a nickel plating layer. The third plating layer 25 is, for example, a tin plating layer.

[0050] Figure 5 This is a cross-sectional view of dielectric layer 11. (Example) Figure 5 As illustrated, the dielectric layer 11 has a structure formed by sintering dielectric particles 30. For example, the dielectric layer 11 may have one dielectric particle 30 in the thickness direction, or it may be as follows: Figure 5 This results in a structure with multiple dielectric particles 30 continuously connected via grain boundaries. The dielectric particles 30 can be the main component ceramic of the dielectric layer 11, or a substance in which other elements are dissolved in the main component ceramic.

[0051] In such a structure, during the firing process, when the powder materials of the dielectric layer 11 and the internal electrode layer 12 are sintered, good bonding cannot be obtained between the dielectric layer 11 and the internal electrode layer 12, and delamination may occur between the dielectric layer 11 and the internal electrode layer 12.

[0052] Therefore, the inventors conducted in-depth research and discovered that by segregating a precipitate containing magnesium and at least two rare earth elements (a first rare earth element and a second rare earth element) in the dielectric layer 11, delamination can be suppressed. This is because the precipitate containing magnesium and the first and second rare earth elements exhibits less shrinkage during the sintering of the powder material of the dielectric layer 11, thus improving the interfacial bonding between the dielectric layer 11 and the internal electrode layer 12. Furthermore, this is because the magnesium contained in the precipitate promotes sintering, thus enabling not only the area near the internal electrode layer 12 but also the entire dielectric layer 11 to be sintered at low temperatures.

[0053] Therefore, in this embodiment, as Figure 6 As illustrated, in the dielectric layer 11, segregates 40 are segregated at the grain boundaries of any dielectric particles 30.

[0054] The location of the segregation 40 in the dielectric layer 11 is not particularly limited, but it is preferably located at the interface between the dielectric layer 11 and the inner electrode layer 12, and in contact with the inner electrode layer 12. This is because by placing the segregation 40 in a region prone to delamination, delamination is more easily suppressed. Furthermore, pores are formed at the interface between the dielectric layer 11 and the inner electrode layer 12. Pores are areas that do not contribute to the capacitance of the dielectric layer 11. Therefore, by placing the segregation 40 at the interface between the dielectric layer 11 and the inner electrode layer 12, a region prone to pore formation is provided with the segregation 40, thus suppressing the decrease in capacitance of the dielectric layer 11. In addition, the segregation 40 is an insulator because its location at the interface between the dielectric layer 11 and the inner electrode layer 12 increases the resistance of the interface, thereby improving reliability.

[0055] Furthermore, magnesium has the effect of inhibiting grain growth, thus suppressing the grain growth of each dielectric particle 30 in the dielectric layer 11. This helps to suppress the decrease in grain boundary number and improve reliability. Furthermore, as... Figure 6 As illustrated, at the interface 41 between dielectric particles 30 and segregated material 40, a portion of the rare earth elements contained in segregated material 40 acts as a donor, thus reducing oxide ion defects at the interface. This further improves reliability. Moreover, because it contains two or more rare earth elements, at the interface 41 between dielectric particles 30 and segregated material 40, ΔS (entropy) increases, and ΔG (Gibbs free energy) at this interface increases negatively and becomes stable, allowing rare earth elements to exist at high concentrations, thus further improving reliability.

[0056] For example, in segregate 40, the second rare earth element has a larger ionic radius than the first rare earth element. In perovskite, the larger the ionic radius of a rare earth element, the more preferentially it dissolves at site A; the smaller the ionic radius, the more preferentially it dissolves at site B. To selectively dissolve the first rare earth element at site B and the second rare earth element at site A, it is preferable to set a lower limit for the difference in ionic radii between the first and second rare earth elements in segregate 40. In this embodiment, the difference in ionic radii between the first and second rare earth elements is preferably 0.025 Å or more, more preferably 0.030 Å or more, and even more preferably 0.035 Å or more.

[0057] On the other hand, in perovskites, the larger the ionic radius of rare earth elements, the more preferentially they dissolve at site A, and the smaller the ionic radius of rare earth elements, the more preferentially they dissolve at site B. To selectively dissolve the first rare earth element at site B and the second rare earth element at site A, it is preferable to set an upper limit on the difference in ionic radii between the first and second rare earth elements in the segregated product 40. In this embodiment, the difference in ionic radii between the first and second rare earth elements is preferably 0.055 Å or less, more preferably 0.050 Å or less, and even more preferably 0.045 Å or less.

[0058] Table 1 shows the ionic radii of the six coordination groups of each rare earth element. The source of Table 1 is "RD Shannon, Acta Crystallogr., A32, 751 (1976)".

[0059] [Table 1]

[0060]

[0061] For example, the first rare earth element is preferably holmium or yttrium. The second rare earth element is preferably gadolinium or europium.

[0062] When the amounts of the first and second rare earth elements in the segregate 40 are too small, it may be impossible to sufficiently reduce oxide ion defects at the interface between the dielectric particles 30 and the segregate 40. Therefore, it is preferable to set a lower limit on the amounts of the first and second rare earth elements in the segregate 40. On the other hand, when the amounts of the first and second rare earth elements in the segregate 40 are too large, sintering will be delayed and residual porosity may remain, potentially worsening the moisture resistance. Therefore, it is preferable to set an upper limit on the amounts of the first and second rare earth elements in the segregate 40. In this embodiment, the molar ratio of the first rare earth element to magnesium, Ra / Mg, in the segregate 40 is preferably 1.5 to 50 or less, more preferably 3.0 to 40.0 or less, and even more preferably 4.0 to 30.0 or less. In the segregated product 40, the molar ratio of the second rare earth element to magnesium, Rb / Mg, is preferably 0.3 or more and 10.0 or less, more preferably 0.3 or more and 9.0 or less, and even more preferably 0.3 or more and 8.0 or less.

[0063] When the amount of the second rare earth element is high, the surrounding dielectric particles 30 may undergo grain growth, potentially failing to meet temperature characteristics. Therefore, in the segregate 40, it is preferable that the amount of the first rare earth element is the same as or greater than that of the second rare earth element. For example, in the segregate 40, the molar ratio Ra / Rb of the first rare earth element relative to the second rare earth element is preferably 1.0 to 16.0 or less, more preferably 2.0 to 14.0 or less, and even more preferably 3.0 to 12.0 or less.

[0064] The molar ratios Ra / Mg, Rb / Mg, and Ra / Rb can be measured using the following method. First, in the cross-section of dielectric layer 11, a transmission electron microscope (TEM) image is taken at 15000x magnification, followed by elemental analysis using EDS to identify segregation of the first and second rare earth elements and magnesium. Point analysis is then performed on the identified segregations, and the molar ratios Ra / Mg, Rb / Mg, and Ra / Rb are measured.

[0065] In the dielectric layer 11, if the segregated material 40 is too small, delamination and grain growth may occur. Therefore, it is preferable to set a lower limit on the size of the segregated material 40. In this embodiment, the average particle size of the segregated material 40 in the cross-section of the dielectric layer 11 is preferably 0.1 μm or more, more preferably 0.2 μm or more, and even more preferably 0.3 μm or more.

[0066] In the dielectric layer 11, if the segregation 40 is too large, the dielectric constant may decrease. Therefore, it is preferable to set an upper limit on the size of the segregation 40. In this embodiment, the average particle size of the segregation 40 in the cross-section of the dielectric layer 11 is preferably 2.0 μm or less, more preferably 1.5 μm or less, and even more preferably 1.0 μm or less.

[0067] The average particle size of segregant 40 can be measured using the following method. First, a BSE image of the cross-section of dielectric layer 11 is captured at 5000x magnification using a SEM (scanning electron microscope). Next, elemental EDS mapping is performed at this magnification, and the area of ​​segregant 40 is measured using area measurement software. Assuming the area of ​​segregant 40 is circular, the diameter is calculated. The diameter calculated using (diameter = 2 × √(area of ​​segregant 40 / π)) is taken as the diameter of segregant 40. The average diameter of all segregants 40 is taken as the average particle size of segregant 40.

[0068] Furthermore, if the number of segregates 40 in the dielectric layer 11 is too small, reliability may not be sufficiently improved. Therefore, it is preferable to set a lower limit on the number of segregates 40 in the dielectric layer 11. In this embodiment, it is preferable that the number of segregates 40 per μm in the cross-section of the dielectric layer 11 is... 2 On average, it contains more than 0.01 segregants 40, more preferably per μm. 2 On average, it contains more than 0.02 segregants 40, and is further preferred to have more than 0.02 segregants per μm. 2 On average, it contains more than 0.03 segregants (40).

[0069] Furthermore, in the dielectric layer 11, if the number of segregates 40 is excessive, the dielectric constant may decrease. Therefore, it is preferable to set an upper limit on the number of segregates 40 in the dielectric layer 11. In this embodiment, it is preferable that the number of segregates 40 per μm in the cross-section of the dielectric layer 11 is... 2 On average, it contains less than one segregant 40, more preferably per μm. 2 On average, it contains less than 0.5 segregants 40, and is further preferred to have 40 segregants per μm. 2 On average, it contains less than 0.1 segregants per 40.

[0070] The number of segregates 40 can be measured using the following method. First, a BSE image of the cross-section of the dielectric layer 11 is taken at 5000x magnification using a SEM (scanning electron microscope). Next, elemental EDS analysis is performed at this magnification to locate the segregates 40. The number of segregates 40 measured is divided by the area of ​​the field of view, and the resulting value is taken as the number of segregates 40.

[0071] Furthermore, dielectric particles 30, preferably as shown in the image, are preferred. Figure 7 As illustrated, a grain boundary phase 42 is present at the portion in contact with the grain boundary. The grain boundary phase 42 comprises silicon, aluminum, manganese, and vanadium. By including silicon and aluminum in the grain boundary phase 42, a structure in which the grain boundary phase 42 is wetting and expanding can be obtained. For example, a structure in which the dielectric particles 30 are coated with the grain boundary phase 42 can be obtained. The grain boundary phase 42 contains manganese and vanadium as elements present at the grain boundary to improve lifetime, thus creating a structure in which manganese and vanadium are also wetting and expanding. Manganese forms positively charged double Schottky atoms at the grain boundary, causing positively charged oxide ion defects to undergo charge repulsion and become unable to cross the grain boundary, thus improving reliability. Vanadium is a donor that readily exists at grain boundaries, thus reducing oxide ion defects at the grain boundary. Therefore, the generation and migration of oxide ion defects at the grain boundary can be suppressed, improving reliability.

[0072] The thickness of the grain boundary phase 42 is between 10 nm and 150 nm, and in the cross-section of the dielectric layer 11, per μm 2 On average, it contains more than 0.01 and less than 1 grain boundary phase 42, which increases the resistance of the grain boundary phase 42 and improves the reliability.

[0073] The average number of grain boundary phases 42 with a thickness of 10 nm or more in the cross-section of the dielectric layer 11 can be measured by the following method. First, in the cross-section of the dielectric layer 11, a transmission electron microscope (TEM) image is taken using the NEOARM lens, and line analysis is performed using EDS. The TEM image is taken at 40,000x magnification, and candidate locations with thick grain boundary phases are identified within the field of view. Next, the locations with thick grain boundary phases are magnified and TEM images are taken at 100,000x magnification, followed by line analysis using EDS. For the EDS line analysis, three locations are analyzed for each grain boundary phase. It is confirmed that the amounts of silicon, aluminum, manganese, and vanadium are greater in the grain boundary phases than in the dielectric particles. The average value of three locations representing the length of silicon within the grain boundary phases containing silicon, aluminum, manganese, and vanadium is calculated. Count the number of grain boundary phases 42 with an average thickness of 10 nm or more, divide the count result by the field of view area of ​​the initially captured transmission electron image, and use the resulting value as the average number (number / μm) of grain boundary phases 42 with a thickness of 10 nm or more. 2 ).

[0074] In addition, preferred options include Figure 8 As illustrated, at least one dielectric particle 30 has a core-shell structure. For example, in the capacitor section 14, when at least a portion of the dielectric particles included in the dielectric layer 11 have a core-shell structure, the dielectric layer 11 in the capacitor section 14 has a high dielectric constant, excellent temperature characteristics, and stable coexistence of microstructures.

[0075] Here, a summary of a dielectric particle with a core-shell structure is described. The dielectric particle 30 with a core-shell structure includes: a generally spherical core 31; and a shell 32 that surrounds the core 31. The core 31 is a crystalline portion without a solid solution of an added compound or with a small amount of the added compound dissolved in it. The shell 32 is a crystalline portion with a solid solution of an added compound and having a higher concentration of the added compound than that in the core 31. The concentration of the added compound in the shell 32 is higher than that in the core 31. Alternatively, the added compound diffuses into the shell 32 but not into the core 31.

[0076] In the dielectric layer 11, the average particle size of the dielectric particles 30 is, for example, 0.1 μm to 0.5 μm. The average particle size of the dielectric particles 30 can be measured by the following method. First, a BSE image is taken at 15,000x magnification using a SEM (scanning electron microscope) in a cross-section of the dielectric layer 11. Next, a straight line of approximately 6 μm is drawn parallel to the inner electrode layer 12 on the dielectric layer 11, and its length is measured and denoted as a. The dielectric particles 30 along the straight line are counted, and their number is denoted as n. The value of a / n is taken as the average particle size of the dielectric particles 30.

[0077] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 9 This is a flowchart illustrating the manufacturing method of a multilayer ceramic capacitor 100.

[0078] (First mixing process)

[0079] In the first mixing step, the raw material powder of the ceramic, the main component of the dielectric layer 11, is first prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically included in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, barium titanate is a tetragonal compound with a perovskite structure, exhibiting a high relative permittivity. This barium titanate can usually be obtained by reacting titanium raw materials such as titanium dioxide with barium raw materials such as barium carbonate to synthesize barium titanate. Various methods are known in the past for synthesizing the ceramic, the main component of the dielectric layer 11, such as solid-state methods, sol-gel methods, and hydrothermal methods. In this embodiment, any of these methods can be used.

[0080] In the obtained raw material powder, a specified additive compound is added in accordance with the intended purpose. Examples of additive compounds include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), or oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0081] For example, the raw material powder is wet-mixed with an additive compound, then dried and pulverized to prepare the material. For example, the raw material powder obtained as described above can be pulverized as needed to adjust the particle size, or the particle size can be adjusted by combining it with a classification process. Through the above steps, a dielectric material is obtained.

[0082] Next, ethanol, toluene, and other organic solvents, dispersants, and binders such as polyvinyl butyral (PVB) resin are mixed into the obtained dielectric material in a wet mixing process. This yields a slurry.

[0083] (Coating process)

[0084] Using the obtained slurry, a dielectric green sheet 51 is coated onto a substrate by, for example, molding or blade coating and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film.

[0085] (Temporary firing process)

[0086] On the other hand, oxides of the first rare earth element, oxides of the second rare earth element, and magnesium oxide are mixed in a mortar or similar container and temporarily fired in the atmosphere at a temperature range of 900°C to 1000°C. This yields powder A. Powder A is the substance that becomes segregant 40 in the firing process described later.

[0087] (Second mixing process)

[0088] A metal paste containing powder A is prepared by mixing the powder A with the metal that is the main component of the internal electrode layer 12.

[0089] (Printing process)

[0090] Next, as Figure 10 As illustrated in (a), the aforementioned metal paste containing A powder, comprising an organic binder, is printed onto the surface of the dielectric sheet 51 using screen printing, gravure printing, or the like to configure an internal electrode pattern 52 that is alternately drawn to a pair of external electrodes with different polarities. Ceramic particles are added to the metal paste containing A powder as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferably the same as the main component ceramic of the dielectric layer 11. For example, barium calcium titanate with an average particle size of 50 nm or less can be uniformly dispersed.

[0091] Next, in the dielectric ceramic composition obtained in the raw material powder preparation process, binders such as ethyl cellulose and organic solvents such as terpineols are added, and the mixture is kneaded using a roller mill to obtain a dielectric patterning paste for the reverse patterning layer. For example... Figure 10 As illustrated in (a), dielectric pattern 53 is configured on the dielectric green sheet 51 by printing dielectric pattern paste in the peripheral area where the internal electrode pattern 52 is not printed, filling the steps of the internal electrode pattern 52. The dielectric pattern paste can be the same material as the dielectric green sheet 51, or it can be a material with different additive compounds added to the main component ceramic. The dielectric green sheet 51 with the internal electrode pattern 52 and dielectric pattern 53 printed on it is referred to as a stacked unit.

[0092] (Layering process)

[0093] After that, as Figure 10 As illustrated in (b), the stacked units are stacked in a manner that alternating between the inner electrode layer 12 and the dielectric layer 11, and in a manner in which the end edges of the inner electrode layer 12 are alternately exposed on both ends of the dielectric layer 11 along its length and are alternately led out to a pair of external electrodes 20a, 20b with different polarities. For example, the number of layers in the inner electrode pattern 52 is 100 to 1000.

[0094] (Crimping process)

[0095] like Figure 11 As illustrated, a predetermined number (e.g., 2 to 10 layers) of cover sheets 54 are stacked on top of each other in a laminate obtained by stacking laminated units, and then heat-pressed together. As an example, the dielectric ceramic composition described above can be used as the ceramic material for the cover sheet 54.

[0096] (Cutting process)

[0097] Then, it is cut into the specified chip size (e.g., 1.0mm × 0.5mm) to obtain a chip.

[0098] (External electrode formation process)

[0099] The sheet obtained above before firing is subjected to a debinding treatment in an N2 atmosphere, an atmospheric atmosphere, etc., and then coated with metal paste to become the base layer of the external electrodes 20a and 20b by an impregnation method.

[0100] (Firing process)

[0101] Then, at an oxygen partial pressure of 10 -10 ~10 -7 The ceramic capacitor 100 is obtained by firing it at 1100–1300°C for 10 minutes to 2 hours in a reducing atmosphere of atm.

[0102] Furthermore, a re-oxidation treatment can then be performed at 600°C to 1000°C in an N2 gas atmosphere. Subsequently, a plating process can be performed to coat the substrate layers of the external electrodes 20a and 20b with metals such as Cu, Ni, and Sn.

[0103] According to the manufacturing method of this embodiment, by pre-firing the A powder, the first rare earth element, the second rare earth element, and magnesium are prevented from dispersing and instead remain segregated. Therefore, during the firing process, the segregated material 40 can be segregated within the dielectric layer 11. Furthermore, by including the A powder in the internal electrode pattern 52 rather than in the dielectric green sheet 51, the solid dissolution of the first rare earth element, the second rare earth element, and magnesium in the main component ceramic of the dielectric layer 11 during the firing process can be suppressed, and the segregated material 40 tends to be located closer to the interface between the dielectric layer 11 and the internal electrode layer 12 than the interior of the dielectric layer 11.

[0104] In the above embodiments, a multilayer ceramic capacitor was described as an example of a multilayer ceramic electronic component, but it is not limited to this. For example, other multilayer ceramic electronic components such as varistors and thermistors can also be used.

[0105] [Example]

[0106] Next, we will fabricate a multilayer ceramic capacitor according to the embodiment and investigate its characteristics.

[0107] (Comparative Examples 1-3)

[0108] Barium titanate with an average particle size of approximately 250 nm as the main raw material was weighed. Various additives, alumina (Al₂O₃), rare earth elements, organic solvents, and binders were mixed and dispersed in a specified ratio to obtain a slurry. Regarding Al₂O₃, no Al₂O₃ was added in Comparative Example 1, 0.2 mol% was added relative to barium titanate in Comparative Example 2, and 0.5 mol% was added relative to barium titanate in Comparative Example 3. The slurry was applied using a doctor blade to form a 4.0 μm thick dielectric green sheet, which was then dried. Ni paste was screen-printed onto the dielectric green sheet as an internal electrode pattern. To fill the step between the dielectric green sheet and the internal electrode pattern, a dielectric pattern with a pattern complementary to the internal electrode pattern was screen-printed onto the dielectric green sheet. Ten layers were then stacked, pressed, and cut. This yielded an MLCC molded body with dimensions of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. Ni paste for external electrodes was applied to the exposed end faces of the internal electrode pattern.

[0109] (Example 1)

[0110] Barium titanate with an average particle size of approximately 250 nm was weighed as the main raw material. Various additives, Al₂O₃, rare earth elements, organic solvents, and binders were mixed and dispersed in a specified ratio to obtain a slurry. Regarding Al₂O₃, 0.5 mol% was added relative to barium titanate. The slurry was coated using a doctor blade to form a 4.0 μm thick dielectric green sheet, which was then dried. Separately, holmium oxide (Ho₂O₃), gadolinium oxide (Gd₂O₃), and magnesium oxide (MgO) were mixed in a mortar in a specified ratio and temporarily calcined at 900℃–1000℃ for 1 hour in atmospheric conditions. The temporarily calcined Al₂O₃ powder was then ground using a needle mill for 10 hours. Holmium was used as the first rare earth element, and gadolinium as the second. The ground Al₂O₃ powder was mixed with Ni paste. 5 mol% of Al₂O₃ powder was added relative to Ni. Ni paste was screen-printed onto the dielectric green sheet as the internal electrode pattern. To fill the step between the dielectric green sheet and the internal electrode pattern, a dielectric pattern with a pattern complementary to the internal electrode pattern is screen-printed onto the dielectric green sheet. Then, 10 layers are stacked, pressed together, and cut. This yields an MLCC molded body with dimensions of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. Ni paste for the external electrodes is applied to the exposed end faces of the internal electrode pattern.

[0111] The MLCC molded specimens of Comparative Examples 1-3 and Example 1 were debonded in a nitrogen atmosphere at 300°C. Then, they were fired at the highest temperature (1150°C-1250°C) for 1 hour. The temperature was increased slowly at a rate of 400°C / h. The atmosphere was an oxygen partial pressure of 10. -9A strong reducing atmosphere above atm. After cooling, the temperature is raised to 800℃~1050℃ in a N2 atmosphere and maintained at this temperature for re-oxidation treatment.

[0112] When confirming the cross-section of the dielectric layer, in Example 1, segregates containing holmium, gadolinium, and magnesium (hereinafter referred to as Ho-Gd-Mg segregates) were identified. This can be attributed to the fact that holmium oxide, gadolinium oxide, and magnesium oxide were temporarily calcined and mixed into the Ni paste. The identified Ho-Gd-Mg segregates were mostly located at the interface between the dielectric layer and the inner electrode layer. In Example 1, the average particle size of the Ho-Gd-Mg segregates in the cross-section of the dielectric layer was 0.2 μm. Furthermore, in Example 1, the number of Ho-Gd-Mg segregates in the cross-section of the dielectric layer was 0.04 per μm. 2 Furthermore, no Ho-Gd-Mg segregates were identified in Comparative Examples 1-3.

[0113] In the cross-section of the dielectric layer, the average particle size of the dielectric particles is 330 nm in Example 1, 400 nm in Comparative Example 1, 440 nm in Comparative Example 2, and 500 nm in Comparative Example 3.

[0114] The number of grain boundary phases with a thickness of 10 nm to 150 nm and containing silicon, aluminum, manganese, and vanadium was 0.01 per μm in Example 1. 2 The number was 0 in Comparative Example 1 and 0.001 per μm in Comparative Example 2. 2 In Comparative Example 3, it was 0.02 cells / μm. 2 .

[0115] (Presence or absence of delamination)

[0116] The presence or absence of delamination was investigated for each sample from Example 1 and Comparative Examples 1-3. Delamination was confirmed in all of Comparative Examples 1-3. However, no delamination was confirmed in Example 1. This can be attributed to the fact that, in Example 1, Ho-Gd-Mg segregates segregated in the dielectric layer, thereby improving the bonding between the dielectric layer and the internal electrode layer.

[0117] (Dielectric constant)

[0118] After thermal recovery (treatment at 150°C for 1 hour) of the samples from Examples 1 and Comparative Examples 1-3, the capacitance was measured using an LCR meter after 24 hours at 1 kHz and 0.5 Vrms, and the dielectric constant was calculated based on the capacitance. Dielectric constants between 2000 and 3500 were rated as "0", and others as "×". In Comparative Example 3, the dielectric constant was rated as "×". This can be attributed to the increased average particle size of the dielectric particles.

[0119] (Temperature characteristics)

[0120] After thermal recovery (treatment at 150°C for 1 hour) of the samples from Examples 1 and Comparative Examples 1-3, the temperature was varied between -55°C and 150°C for 24 hours, and the rate of change of capacitance at each temperature was measured with 25°C as the reference. Measurements were performed at 1 kHz - 0.5 Vrms. Temperature characteristics meeting X7S (capacitance change rate ±22% at -55°C to 125°C) were rated as "0", and temperature characteristics below X7T (capacitance change rate +22% / -33% at -55°C to 125°C) were rated as "×". Furthermore, X7R (capacitance change rate ±15% at -55°C to 125°C) was better than X7S.

[0121] The temperature characteristics of Comparative Examples 1 and 2 are X7T. This can be attributed to the fact that grain growth led to further solid solution development of the additives, making it impossible to ensure large-diameter barium titanate nuclei. The temperature characteristic of Comparative Example 3 does not even meet the X7T requirement. This can be attributed to the fact that the presence of a large amount of aluminum caused significant grain growth, resulting in a deterioration of the temperature characteristics. The temperature characteristic of Example 1 is X7S. This can be attributed to the fact that even with a large amount of aluminum, the presence of Ho-Gd-Mg segregates suppressed grain growth, thereby ensuring large-diameter barium titanate nuclei.

[0122] (reliability)

[0123] For the samples of Example 1 and Comparative Examples 1-3, HALT (High Accelerated Life Test) was performed at 150°C and 50V / μm. Ten measurements were taken, and a current value exceeding 1000μA was considered a fault. The average time taken at this point was taken as the HALT life. A HALT life exceeding 5000 min was rated as "0", and a HALT life less than 5000 min was rated as "×".

[0124] In Comparative Example 1, the HALT lifetime was 450 min. This can be attributed to the fact that the thin grain boundaries resulted in lower grain boundary resistivity, thus eliminating Ho-Gd-Mg segregation, leading to grain growth and a reduction in the number of grain boundaries. In Comparative Example 2, the HALT lifetime was 1100 min. This can be attributed to the fact that the addition of aluminum thickened the grain boundaries, resulting in an improved lifetime compared to Comparative Example 1. In Comparative Example 3, the HALT lifetime was 3500 min. This can be attributed to the fact that the addition of aluminum thickened the grain boundaries, resulting in an improved lifetime compared to Comparative Example 2. In Example 1, the HALT lifetime was 5800 min. This can be attributed to the fact that the sufficient addition of aluminum increased the number of areas with sufficiently thickened grain boundaries, thereby improving the lifetime.

[0125] The results are shown in Table 2.

[0126] [Table 2]

[0127]

[0128] (Example 2)

[0129] In Example 2, only the molar ratios of holmium to magnesium (Ra / Mg), gadolinium to magnesium (Rb / Mg), and holmium to gadolinium (Ra / Rb) were changed compared to Example 1. All other conditions remained the same as in Example 1. Furthermore, the molar ratio Ra / Mg was 11.3 in Example 1 and 11.3 in Example 2. The molar ratio Rb / Mg was 1.7 in Example 1 and 0.3 in Example 2. The molar ratio Ra / Rb was 6.6 in Example 1 and 37.7 in Example 2.

[0130] For Example 2, the presence or absence of delamination, dielectric constant, temperature characteristics, and reliability were investigated in the same manner as in Example 1. The results are shown in Table 3. Furthermore, in Example 2, grain growth was suppressed compared to Example 1. This can be attributed to the lower amount of gadolinium.

[0131] [Table 3]

[0132]

[0133] In Example 2, similar to Example 1, no delamination was observed. This can be attributed to the fact that, in Example 2, Ho-Gd-Mg segregates segregated within the dielectric layer, thereby improving the bonding between the dielectric layer and the internal electrode layer.

[0134] In Example 2, as in Example 1, the dielectric constant was determined to be "0". This can be attributed to the fact that the average particle size of the dielectric particles is similar to that in Example 1.

[0135] The temperature characteristics of Example 2 deviate slightly from X7R, instead being X7S. This can be attributed to the fact that the amount of gadolinium is less than in Example 1, thereby suppressing grain growth compared to Example 1 and ensuring large-diameter barium titanate nuclei.

[0136] The HALT lifetime of Example 2 was 4100 min. This can be attributed to the fact that there was less gadolinium than in Example 1, and therefore, the entropy effect was not achieved as in Example 1.

[0137] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to these specific embodiments, and various modifications and changes can be made within the scope of the spirit of the present invention as set forth in the claims.

Claims

1. A laminated ceramic electronic component, characterized in that, have: A dielectric layer having a main phase and segregates comprising a first rare earth element, a second rare earth element, and magnesium; Multiple internal electrode layers disposed between the dielectric layer; and An external electrode electrically connected to the internal electrode layer.

2. The laminated ceramic electronic component according to claim 1, characterized in that: The segregated material is in contact with the internal electrode layer.

3. The laminated ceramic electronic component according to claim 1 or 2, characterized in that: The ionic radius of the second rare earth element is greater than that of the first rare earth element.

4. The laminated ceramic electronic component according to any one of claims 1 to 3, characterized in that: The first rare earth element is holmium or yttrium. The second rare earth element is gadolinium or europium.

5. The laminated ceramic electronic component according to any one of claims 1 to 4, characterized in that: In the segregated product, the molar ratio of the first rare earth element to magnesium is 1.5 to 50, and the molar ratio of the second rare earth element to magnesium is 0.3 to 10.

6. The laminated ceramic electronic component according to any one of claims 1 to 5, characterized in that: In the segregated product, the molar ratio of the first rare earth element to the second rare earth element is more than 1 and less than 16.

7. The laminated ceramic electronic component according to any one of claims 1 to 6, characterized in that: The average particle size of the segregated material is between 0.1 μm and 2.0 μm.

8. The laminated ceramic electronic component according to any one of claims 1 to 7, characterized in that: In the cross-section of the dielectric layer, per μm 2 On average, it contains more than 0.01 and less than 1 of the aforementioned segregants.

9. The laminated ceramic electronic component according to any one of claims 1 to 8, characterized in that: The main phase has a grain boundary phase. The grain boundary phase comprises silicon, aluminum, manganese, and vanadium.

10. The laminated ceramic electronic component according to claim 9, characterized in that: The thickness of the grain boundary phase is between 10 nm and 150 nm. In the cross-section of the dielectric layer, per μm 2 On average, it contains more than 0.01 and less than 1 grain boundary phase.

Images