image sensor

Abstract

An image sensor includes a pixel array including a plurality of pixel groups arranged in a first direction and a second direction crossing the first direction, wherein each of the plurality of pixel groups includes a plurality of photodiodes and a pixel circuit configured to output a signal corresponding to a charge generated by at least one of the plurality of photodiodes. The plurality of photodiodes includes a primary photodiode and a secondary photodiode. The pixel circuit includes a first floating diffusion node, a second floating diffusion node, a first switch transistor connected between the first floating diffusion node and the second floating diffusion node, a reset transistor and a gain control transistor connected in series between a second power supply node and the first floating diffusion node, a capacitor and a second switch transistor connected in series with each other between a first power supply node and the second floating diffusion node, an amplification transistor, and a selection transistor.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0166075, filed on November 20, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] An example embodiment of this disclosure relates to an image sensor. Background Technology

[0003] An image sensor can receive light and generate electrical signals, and may include a pixel array having multiple pixels and peripheral circuitry for driving the pixel array and generating an image. Each of the multiple pixel groups may include multiple photodiodes and pixel circuitry configured to convert the charge generated by the multiple photodiodes into an electrical signal. The range of light intensity represented by the image sensor can be defined as the dynamic range. The dynamic range can be improved by including a capacitor in each of the multiple pixel groups, but the sensitivity of the image sensor may be reduced. Summary of the Invention

[0004] Example embodiments of this disclosure are used to selectively control the sensitivity of a readout operation that reads the voltage corresponding to the charge stored in a capacitor by using a switching transistor to control the number of photodiodes connected to each capacitor in a plurality of pixel groups during an exposure period.

[0005] According to an example embodiment of this disclosure, an image sensor includes a pixel array comprising a plurality of pixel groups, wherein each of the plurality of pixel groups includes a plurality of PD (photodiode) regions arranged in a first direction and a second direction intersecting the first direction, wherein each of the plurality of pixel groups includes a plurality of photodiodes and a pixel circuit, the plurality of photodiodes being disposed in the plurality of PD regions, and the pixel circuit being configured to output a signal corresponding to a charge generated by at least one of the plurality of photodiodes. The plurality of photodiodes includes at least a first-stage photodiode and at least a first-second-stage photodiode. The pixel circuit includes: a first floating diffusion node connected to the first-stage photodiode via a first-stage transfer transistor; a second floating diffusion node connected to the first-second-stage photodiode via a first-second-stage transfer transistor; a first switching transistor connected between the first floating diffusion node and the second floating diffusion node; a reset transistor and a gain control transistor connected in series between a second power node and the first floating diffusion node; a capacitor and a second switching transistor connected in series between the first power node and the second floating diffusion node; an amplifying transistor having a gate connected to the first floating diffusion node and connected to a third power node; and a selection transistor connected between the amplifying transistor and a column line.

[0006] According to an example embodiment of this disclosure, an image sensor includes: a pixel array comprising a plurality of pixel groups, each of the plurality of pixel groups including a plurality of PD (photodiode) regions arranged in a first direction and a second direction intersecting the first direction; and peripheral circuitry connected to the plurality of pixel groups via a plurality of row lines and a plurality of column lines, and configured to drive the plurality of pixel groups. Each of the plurality of pixel groups includes at least a first-stage photodiode, at least a first-second-stage photodiode, and pixel circuitry connecting the first-stage photodiode and the first-second-stage photodiode to the peripheral circuitry. The pixel circuitry includes a capacitor configured to store at least a portion of the charge generated by the first-second-stage photodiode during an exposure period. The peripheral circuitry is configured to: obtain a first pixel signal and a second pixel signal by performing a first readout operation on each of the plurality of pixel groups after the exposure period, obtain a third pixel signal corresponding to the charge stored in the capacitor by performing a second readout operation, and generate image data using the first pixel signal, the second pixel signal, and the third pixel signal. The first pixel signal is the signal output by each of the plurality of pixel groups under high conversion gain conditions, and the second pixel signal is the signal output by each of the plurality of pixel groups under low conversion gain conditions.

[0007] According to an example embodiment of this disclosure, an image sensor includes: a plurality of pixel groups, each of the plurality of pixel groups including a plurality of PD (photodiode) regions arranged in a first direction and a second direction intersecting the first direction; and peripheral circuitry connected to the plurality of pixel groups via a plurality of row lines and a plurality of column lines, and configured to drive the plurality of pixel groups. Each of the plurality of pixel groups includes at least a first-stage photodiode, at least a first-second-stage photodiode, and pixel circuitry connecting the first-stage photodiode and the first-second-stage photodiode to the peripheral circuitry. Pixel circuitry includes: a first floating diffusion node; a first transfer transistor connected between the first floating diffusion node and the first-stage photodiode; a first switching transistor connected between the first floating diffusion node and a second floating diffusion node; a second switching transistor and a capacitor connected to the second floating diffusion node and connected in series with each other; and a first-second-stage transfer transistor connected between the second floating diffusion node and the first-second-stage photodiode. The capacitor is configured to store at least a portion of the charge generated by the first-second-stage photodiode during an exposure time period, but not the charge generated by the first-stage photodiode. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure.

[0010] Figure 2 This is a diagram illustrating the pixel array structure of an image sensor according to an exemplary embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0012] Figure 4 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0013] Figure 5 It shows the basis Figure 4 The diagram illustrates the operation of pixel groups in an example embodiment.

[0014] Figure 6 It shows the basis Figure 4 The diagram shows a layout of pixel groups in an example embodiment.

[0015] Figure 7 It shows the basis Figure 4 The diagram shows a layout of pixel groups in an example embodiment.

[0016] Figure 8 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0017] Figure 9 It shows the basis Figure 8 The diagram illustrates the operation of pixel groups in an example embodiment.

[0018] Figure 10 It shows the basis Figure 8 The diagram shows a layout of pixel groups in an example embodiment.

[0019] Figure 11 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0020] Figure 12 It shows the basis Figure 11 The diagram illustrates the operation of pixel groups in an example embodiment.

[0021] Figure 13 It shows the basis Figure 11 The diagram shows a layout of pixel groups in an example embodiment.

[0022] Figure 14 This is a diagram illustrating the pixel array structure of an image sensor according to an exemplary embodiment of the present disclosure.

[0023] Figure 15 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0024] Figure 16 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0025] Figure 17 It shows the basis Figure 16 The diagram illustrates the operation of pixel groups in an example embodiment.

[0026] Figure 18 It shows the basis Figure 16 The diagram shows a layout of pixel groups in an example embodiment.

[0027] Figure 19 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0028] Figure 20 It shows the basis Figure 19 The diagram illustrates the operation of pixel groups in an example embodiment.

[0029] Figure 21 It shows the basis Figure 19 The diagram shows a layout of pixel groups in an example embodiment.

[0030] Figure 22 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0031] Figure 23 It shows the basis Figure 22 The diagram illustrates the operation of pixel groups in an example embodiment.

[0032] Figure 24 It shows the basis Figure 22 The diagram shows a layout of pixel groups in an example embodiment.

[0033] Figure 25 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0034] Figure 26 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0035] Figure 27 It shows the basis Figure 25 The diagram illustrates the operation of pixel groups in an example embodiment.

[0036] Figure 28 It shows the basis Figure 25 The diagram shows a layout of pixel groups in an example embodiment.

[0037] Figure 29 This is a diagram illustrating the pixel array structure of an image sensor according to an exemplary embodiment of the present disclosure.

[0038] Figure 30 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure.

[0039] Figure 31 This is a circuit diagram illustrating a pixel group according to an example embodiment of the present disclosure.

[0040] Figure 32 It shows the basis Figure 31 The diagram illustrates the operation of a pixel group in an example embodiment.

[0041] Figure 33 It shows the basis Figure 31 The diagram shows a layout of pixel groups in an example embodiment. Detailed Implementation

[0042] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] As can be seen, for example, in the accompanying drawings, items described herein in the singular may be provided in the plural. Therefore, unless the context otherwise indicates, a description of a single item provided in the plural should be understood to apply to the remaining multiple items.

[0044] For ease of description, spatial relative terms (such as "below," "under," "below," "above," "above," "top," "bottom," etc.) are used herein to describe the relationship of one element or feature as shown in the accompanying drawings to another element(s) or feature(s). It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings were flipped, an element described as "below" or "under" another element or feature would then be oriented "above" that other element or feature. Thus, the term "below" can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0045] Ordinal numbers (such as "first," "second," "third," "primary," "secondary," "tertiary," etc.) can simply be used as labels for specific elements, steps, etc., to distinguish them from one another. Terms that are not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be referenced elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0046] Figure 1 This is a block diagram illustrating an image sensor according to an example embodiment.

[0047] Reference Figure 1 The image sensor 10 may include a pixel array 20 and peripheral circuitry 30. The pixel array 20 may include multiple rows and multiple columns, and may include multiple pixel groups arranged in an array. Each of the multiple pixel groups may include multiple pixels and pixel circuitry. In the region of each of the multiple pixels, a photoelectric conversion element may be disposed, configured to generate charge in response to light. The photoelectric conversion element may be connected to the pixel circuitry, which is configured to generate and output a signal corresponding to the charge generated by the photoelectric conversion element.

[0048] A pixel group can be implemented using photoelectric conversion elements and pixel circuitry. The photoelectric conversion elements can be photodiodes formed of semiconductor materials and / or organic photodiodes formed of organic materials. In one example embodiment, multiple photodiodes included in a pixel group may be of the same size.

[0049] For example, a pixel circuit may include multiple transistors and a capacitor. The capacitor may store excess charge generated by the photodiode (e.g., at least a portion of the charge generated by the photodiode) and may be connected to the photodiode via at least one transistor. In one example embodiment, the capacitor may be a metal-insulator-metal (MIM) capacitor.

[0050] The peripheral circuitry 30 may include circuitry for controlling the pixel array 20. For example, the peripheral circuitry 30 may include a row driver 31, a readout circuitry 32, a data output circuitry 33, and control logic 34. The row driver 31 may drive the pixel array 20 on a row-by-row basis. For example, the row driver 31 may input control signals to the pixel array 20 on a row-by-row basis to control the on / off state of each transistor included in the pixel circuitry.

[0051] Within a pixel, in the row ROW direction ( Figure 1Pixels positioned at the same location in the horizontal direction (of the column) can share the same column line. Figure 1 Pixels positioned at the same location in the vertical direction (of the image) can be simultaneously selected by the row driver 31, and pixel signals can be output via column lines. In one example embodiment, the readout circuit 32 can simultaneously receive signals from the pixels selected by the row driver 31 via column lines. For example, the readout circuit 32 can sequentially receive a reset voltage and a signal voltage from each of the plurality of pixels, and the signal voltage can be obtained by reflecting the charge generated by the photodiode of each pixel region in the reset voltage.

[0052] The readout circuit 32 may include multiple correlated double samplers and multiple counters, and the correlated double samplers may be connected to pixels via column lines. For example, one correlated double sampler and one counter may be connected to a column line. The correlated double sampler may read voltage signals from pixels connected to row lines selected by the row line selection signal of the row driver 31 via the column lines. One input terminal of each of the correlated double samplers may be connected to a column line, and another input terminal may receive a ramp voltage.

[0053] The output terminal of each of the correlated double samplers can be connected to a counter, and the counter can generate a digital pixel signal by counting the time periods during which the output of each of the correlated double samplers is held at a specific voltage. For example, the counter can convert the output of the correlated double sampler into a digital pixel signal by counting the time periods during which the ramp voltage input to the correlated double sampler is greater than the voltage of the column line. The data output circuit 33 may include a memory (such as latches and buffer circuitry) for temporarily storing the digital pixel signal.

[0054] Control logic 34 may include a timing controller for controlling the operating timing of the row driver 31, the readout circuit 32, and the data output circuit 33. In an example embodiment, control logic 34 may determine the data format to be output by the data output circuit 33, or may perform preprocessing on the data to be output by the data output circuit 33.

[0055] In one example embodiment, the readout circuit 32 may perform a readout operation two or more times for each of a plurality of pixel groups. For example, when one of a plurality of row lines is selected, the readout circuit 32 may read a signal corresponding to the charge generated by exposing the pixel group arranged along the selected row line to light. In one example embodiment, the readout circuit 32 may read the signal corresponding to the charge generated by the pixel group multiple times during a single exposure time period.

[0056] The readout circuit 32 can obtain signals from the pixel group under different operating conditions. For example, the readout circuit 32 can perform at least one readout operation under conditions where the conversion gain of each in the pixel group is large and small. The conversion gain of each in the plurality of pixel groups can vary depending on the on / off state of the transistors connected to the floating diffusion node (or floating diffusion region) of each in the pixel group.

[0057] As described above, each of the multiple pixel groups may include a capacitor. During the exposure period, charge generated by the photodiode exceeding the full-well capacity (FWC) of the photodiode can be transferred to the capacitor and stored, and the readout circuit 32 can perform a readout operation to obtain a signal corresponding to the charge stored in the capacitor. By generating an image using signals obtained from the pixel groups under different operating conditions, the readout circuit 32 expands the intensity of the light range that the image sensor 10 can represent, and the dynamic range can be improved.

[0058] In one example embodiment, the number of photodiodes actively electrically connected to a capacitor in each of a plurality of pixel groups can be controlled. By controlling the number of photodiodes actively electrically connected to the capacitor during the exposure time period, the amount of charge generated beyond the photodiodes' field of view (FWC) and moving to and stored in the capacitor can be selectively controlled. When the number of photodiodes actively electrically connected to the capacitor during the exposure time period is reduced, the amount of charge moving to and stored in the capacitor can be reduced. Therefore, the sensitivity of the readout operation corresponding to the charge stored in the capacitor can be improved. As used herein, items described as "electrically connected" are configured such that an electrical signal can be transferred from one item to another. Therefore, passive conductive components (e.g., wires, pads, internal wires, etc.) physically connected to passive electrically insulating components (e.g., a prepreg layer (or prepreg layer) of a printed circuit board, an electrically insulating adhesive connecting two devices, an electrically insulating underfill, or a molding layer, etc.) are not electrically connected to that component. Furthermore, items that are “directly electrically connected” to each other are electrically connected via one or more passive elements (such as, for example, wires, pads, internal wires, through-holes, etc.). Directly electrically connected elements can be directly physically connected and directly electrically connected. Directly electrically connected components do not include components electrically connected via active elements (such as transistors or diodes). Based on active components positioned between components described as “actively electrically connected,” the components are connected such that a signal or voltage or charge can be transferred from one component to another, the active component being in an active state or affected by excess charge, such that charge can pass through the active component even if it is not controlled to be in an active state. For example, if a transistor is between two components connected to the source and drain of the transistor respectively, the two components are actively electrically connected when the transistor is in a conducting state. As another example, if a photodiode connected to the source of a transistor contains sufficient excess charge so that charge passes through the transistor to the node at the drain, the photodiode is actively electrically connected to the node.

[0059] Figure 2 This is a diagram illustrating the pixel array structure of an image sensor according to an example embodiment.

[0060] Reference Figure 2 The pixel array 100 of the image sensor according to the example embodiment may include a plurality of pixel groups PG1 arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). Each of the plurality of pixel groups PG1 may include a pixel region (or referred to as a photodiode (PD) region) PA.

[0061] The pixel array 100 according to an example embodiment may include a color filter scheme having an array configured to generate images with a tetra (or simply tetra pixel, or pixel-to-tetra) pattern. Figure 2 In the example embodiment shown, pixel array 100 may have a 4×4 quad-pixel color filter array FA1, in which each of red, green, and blue is arranged in a 2×2 configuration. Each of the plurality of pixel groups PG1 may include a 2×2 PD (photodiode) region PA. The 2×2 PD regions PA included in the plurality of pixel groups PG1 may include color filters of the same color. However, the array of color filters is not limited to this. For example, each of the PD regions PA may include at least one photodiode.

[0062] exist Figure 2 In the example embodiment shown, each of the plurality of pixel groups PG1 may include a capacitor and four photodiodes. According to the example embodiment, the sensitivity of the readout operation corresponding to the voltage stored in the capacitor can be controlled by controlling the number of photodiodes connected to the capacitor in each of the plurality of pixel groups PG1.

[0063] Figure 3 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an example embodiment.

[0064] Based on one example, Figure 3 The pixel group PG1 shown is the one that is shown Figure 2 A cross-sectional view of pixel group PG1 of pixel array 100 shown in the diagram. For example, Figure 3 It is shown Figure 2 A cross-sectional view of two PD regions PA arranged in the first direction in pixel group PG1.

[0065] An image sensor according to an example embodiment may include a first layer L1 and a second layer L2. The first layer L1 and the second layer L2 may be stacked in a third direction (Z-axis direction). The first layer L1 may include a first substrate 101. The first substrate 101 may have a first surface and a second surface parallel to the first surface. A first interlayer insulating layer 120 may be disposed on the first surface of the first substrate 101. A color filter 103 and a microlens 105 may be disposed on the second surface of the first substrate 101. A pixel group PG1 may be defined by a device isolation film DTI. For example, the device isolation film DTI may be an insulating film for isolating the pixel group PG1 from each other.

[0066] Reference Figure 2 and Figure 3Multiple photodiodes PD and multiple transistors 110 may be formed on or within the first substrate 101. The device isolation film DTI may be an insulating film used to isolate the photodiodes PD included in the pixel group PG1 from each other. The multiple transistors 110 may be interconnected via metal wiring 111 and may provide pixel circuitry connected to the photodiodes PD.

[0067] A photodiode PD can be disposed in the first substrate 101 and can be defined by a device isolation film DTI. Specifically, refer to Figure 3 The device isolation film (DTI) disposed between the photodiodes (PDs) can be an insulating film used to improve the performance of the image sensor by controlling the movement of electrons in a pixel region (PA). Incident light can be incident on a surface of the first layer L1. For example, the incident light can be incident upwards from the outside of the image sensor. A surface of the first substrate 101 can be used to house a plurality of transistors 110 for processing the electrical signals generated by the photodiodes (PDs).

[0068] The plurality of transistors 110 may include a transfer transistor. A portion of the gate TG of the transfer transistor may be stacked with a photodiode PD. Figure 3 In the example embodiment shown, the gate TG of the transmission transistor can be formed as a vertical transmission gate and can be a single transmission gate.

[0069] and Figure 3 Unlike the example embodiments shown, the gate TG of the transport transistor can be a planar transport gate, or it can be formed in a shape combining a planar transport gate and a vertical transport gate. Furthermore, the gate TG of the transport transistor can be a dual transport gate. However, the shape and / or number of gates of the gate TG of the transport transistor are not limited thereto.

[0070] Metallic wiring 111 may be disposed in a first interlayer insulating layer 120 formed on a first surface of a first substrate 101. The uppermost wiring 115 disposed on the uppermost end of the first interlayer insulating layer 120 may be connected to the uppermost wiring 155 of the second layer L2.

[0071] exist Figure 3 In the example embodiment shown, capacitor 130 may be connected to multiple transistors 110 and is included in the pixel circuitry. Capacitor 130 may be disposed in a first interlayer insulating layer 120. A pixel group PG1 may include one capacitor 130. For example, multiple PD regions PA included in pixel group PG1 may share one capacitor 130.

[0072] As an example, capacitor 130 can be configured as a MIM capacitor having a multi-metal layer structure comprising multiple metal layers and multiple dielectric layers. Figure 3In the example embodiment shown, multiple metal layers and multiple dielectric layers may be stacked alternately in a first direction (X-axis direction). Figure 3 Unlike the example embodiment shown, multiple metal layers and multiple dielectric layers may be stacked alternately in the third-party orientation. Capacitor 130 may be stacked in the third-party orientation with a photodiode PD included in the pixel region PA.

[0073] A portion of the metal layer of capacitor 130 can be connected to the peripheral circuitry of the second layer L2. Therefore, a constant voltage can be applied to a portion of the metal layer. Another portion of the metal layer of capacitor 130 can be connected to at least one of the photodiodes PD. Therefore, the charge generated exceeding the FWC of at least one photodiode connected to capacitor 130 can be stored in capacitor 130.

[0074] The second layer L2 may include a second substrate 102, and a plurality of transistors 140 may be formed on the second substrate 102. The plurality of transistors 140 may be interconnected by metal wiring 151 disposed in the second interlayer insulating layer 150, and may provide peripheral circuitry (such as row drivers and readout circuitry) for driving the pixel array. The uppermost wiring 155 disposed in the uppermost portion of the second interlayer insulating layer 150 may be connected to the uppermost wiring 115 of the first layer L1.

[0075] In one example embodiment, a plurality of first conductive pads may be formed on one surface of a first layer L1, and a plurality of second conductive pads may be formed on one surface of a second layer L2. The first and second conductive pads may be positioned facing each other. Thus, one surface of the first layer L1 and one surface of the second layer L2 may be joined to each other by hybrid bonding or direct bonding without connecting members (such as metal bumps). However, the example embodiment is not limited thereto.

[0076] Figure 4 This is a circuit diagram illustrating a pixel group according to an example embodiment.

[0077] exist Figure 4 In the example embodiment shown, the pixel group PG1 included in the image sensor may include a plurality of photodiodes PD1 and PD2 and pixel circuitry. The plurality of photodiodes PD1 and PD2 may include at least one first photodiode PD1 (e.g., at least one primary photodiode that may serve as a first type of photodiode) and at least one second photodiode PD2 (e.g., at least one secondary photodiode that may serve as a second type of photodiode). The first type of photodiode(s) may differ from the second type of photodiode(s) in one or more of their function, layout, and interconnection.

[0078] exist Figure 4In the example embodiment shown, pixel group PG1 may include a total of four photodiodes. Pixel group PG1 may include three first photodiodes PD1 and one second photodiode PD2. However, the number of first and second photodiodes is not limited to this. The first photodiodes PD1 and the second photodiodes PD2 may be the same size. Therefore, the light-receiving areas of the first photodiodes PD1 and the second photodiodes PD2 may be the same.

[0079] according to Figure 4 In the example embodiment shown, three first photodiodes PD1 can be connected in parallel between each other between the first floating diffusion node FD1 and the reference node. In this case, the reference node can be a ground node.

[0080] The pixel circuit may include a first floating diffusion node FD1, a second floating diffusion node FD2, a first transmission transistor TX1 (e.g., multiple first transmission transistors TX1, also described as first-stage transmission transistors), a second transmission transistor TX2 (also described as second-stage transmission transistors), a gain control transistor DRX, a reset transistor RX, an amplification transistor SF, a selection transistor SX, a first switching transistor SW1, and a second switching transistor SW2. Control signals TG1, TG2, DRG, RG, SEL, SG1, and SG2 for controlling the multiple transistors included in the pixel circuit may be output by a row driver. In an example embodiment, reference numerals indicating control signals for controlling transistors may also be used to indicate the gate of the transistor (e.g., reference numerals indicating a first transmission control signal TG1 for controlling a first transmission transistor may also be used to indicate the gate TG1 of the first transmission transistor).

[0081] In the pixel circuitry of pixel group PG1 according to the example embodiment, a capacitor CAP may be included. During the exposure period, at least one of the plurality of photodiodes PD1 and PD2 included in pixel group PG1 may be electrically connected to capacitor CAP.

[0082] The first floating diffusion node FD1 can be connected to the first photodiode PD1 via the first transmission transistor TX1. When the first transmission transistor TX1 is turned on by the first transmission control signal TG1, the charge of the first photodiode PD1 can be stored in the first floating diffusion node FD1, which can serve as a floating diffusion region.

[0083] The second floating diffusion node FD2, which can also serve as a floating diffusion region, can be connected to the second photodiode PD2 via the second transmission transistor TX2. When the second transmission transistor TX2 is turned on by the second transmission control signal TG2, the charge of the second photodiode PD2 can be stored in the second floating diffusion node FD2. In cases where more than one second photodiode is included, multiple second photodiodes PD2 can be connected in parallel between the second floating diffusion node FD2 and the reference node, and each second photodiode PD2 can be connected in series with the second transmission transistor TX2.

[0084] The first switching transistor SW1 can be connected between the first floating diffusion node FD1 and the second floating diffusion node FD2. In the operation of transferring the charge generated by the second photodiode PD2 to the first floating diffusion node FD1, the first switching transistor SW1 can be turned on by the first switching control signal SG1.

[0085] Capacitor CAP and second switching transistor SW2 can be connected in series between the first power node and the second floating diffusion node FD2. Figure 4 In the example embodiment shown, capacitor CAP may be connected between a first power node and a second node (or referred to as the second node region) N2, and a second switching transistor SW2 may be connected between the second node N2 and a second floating diffusion node FD2. The first power node may be the node supplying a first power supply voltage VDD1.

[0086] The reset transistor RX and the gain control transistor DRX can be connected in series between the second power supply node and the first floating diffusion node FD1. Figure 4 In the example embodiment shown, the reset transistor RX may be connected between the second power node and the first node (or referred to as the first node region) N1, and the gain control transistor DRX may be connected between the first node N1 and the first floating diffusion node FD1. The second power node may be the node supplying the second power supply voltage VDD2. In the example embodiment, the second power supply voltage VDD2 may be the same voltage as the first power supply voltage VDD1, or it may be a different voltage than the first power supply voltage VDD1.

[0087] When the gain control transistor DRX is turned on by the gain control signal DCG, the capacitance of the first floating diffusion node FD1 can be increased, thereby reducing the conversion gain of pixel group PG1. Conversely, when the gain control transistor DRX is turned off, the conversion gain of pixel group PG1 can be increased.

[0088] The gate of the amplifying transistor SF can be connected to the first floating diffusion node FD1, and the amplifying transistor SF can be connected between the third power node and the selection transistor SX. The third power node can be the node supplying the third power supply voltage VDD3. In an example embodiment, the third power supply voltage VDD3 can be the same as at least one of the first power supply voltage VDD1 and the second power supply voltage VDD2. In one example embodiment, the third power supply voltage VDD3 can be equal to the second power supply voltage VDD2 and can be greater than the first power supply voltage VDD1. Furthermore, in one example embodiment, the third power supply voltage VDD3 can be greater than the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0089] The amplifying transistor SF can operate as a source follower amplifier and can generate a signal by amplifying the voltage of the first floating diffusion node FD1. The signal generated by the amplifying transistor SF can be output to the column line COL by turning on the selection transistor SX. The column line COL can be connected to one of the input terminals of a correlated dual sampler, and the correlated dual sampler can transmit the signal output from the column line COL and the output signal determined by the ramp voltage to a counter.

[0090] The operation of pixel group PG1 may include shutter operation, exposure operation, and readout operation. During shutter operation, the charge on the first floating diffuser node FD1, the second floating diffuser node FD2, the first photodiode PD1, and the second photodiode PD2 can be removed. During exposure operation, the first photodiode PD1 and the second photodiode PD2 can be exposed to light for a predetermined exposure time period, and charge can be generated.

[0091] In one example embodiment, the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP, and the charge generated exceeding the FWC of each of the first photodiodes PD1 can be released through the second power node. Therefore, during the exposure period, only the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP.

[0092] During the readout operation, the voltage of the first floating diffusion node FD1 can be amplified and output to the column line COL, and for example, a reset voltage and a signal voltage can be output to the column line COL. When the first floating diffusion node FD1 is reset, the reset voltage can be output to the column line COL by the pixel circuit, and when at least a portion of the charge generated by the photodiode PD is stored in the first floating diffusion node FD1, the signal voltage can be output to the column line COL by the pixel circuit.

[0093] In one example embodiment, the pixel circuitry may perform the operation of outputting a voltage to column line COL two or more times after an exposure period. For example, a readout operation performed after an exposure period may include multiple readout operations performed sequentially. In at least a portion of the multiple readout operations, the conversion gain of pixel group PG1 may be configured differently.

[0094] In one example embodiment, the readout operation may include a high conversion gain (HCG) readout operation and a low conversion gain (LCG) readout operation, wherein the high conversion gain (HCG) readout operation is performed when pixel group PG1 has a relatively large conversion gain, and the low conversion gain (LCG) readout operation is performed when pixel group PG1 has a relatively small conversion gain. Furthermore, the readout operation may include a lateral overflow integrated capacitor (LOFIC) readout operation that reads the voltage corresponding to the FWC generated during the exposure time period exceeding that of the second photodiode PD2 and overflows the charge stored in capacitor CAP.

[0095] In one example embodiment, among the plurality of photodiodes PD1 and PD2 included in pixel group PG1, only the second photodiode PD2 is actively electrically connected to capacitor CAP during the exposure time period. Therefore, the amount of charge stored in capacitor CAP during the exposure time period can be reduced, thereby improving the sensitivity of LOFIC readout operation. Consequently, high dynamic range (HDR) can be altered, or the relative level (decibels, dB) of signal-to-noise ratio (SNR) can be improved.

[0096] Figure 5 It shows the basis Figure 4 The diagram illustrates the operation of a pixel group in an example embodiment.

[0097] Figure 5 This illustrates the shutter operation, exposure operation, and readout operation for a pixel group PG1. (Refer to...) Figures 2 to 4 In the operation of the pixel group PG1 described, the on / off state of transistors SX, RX, DRX, SW1, SW2, TX1 and TX2 included in the pixel group PG1 can be determined by the control signals SEL, RG, DRG, SG1, SG2, TG1 and TG2 output by the row driver.

[0098] During the shutter operation time TSH of pixel group PG1, the selection transistor SX is turned off, and the first transmission transistor TX1, the second transmission transistor TX2, the gain control transistor DRX, the reset transistor RX, the first switching transistor SW1, and the second switching transistor SW2 are turned on. Therefore, the charge on the first photodiode PD1, the second photodiode PD2, the first floating diffusion node FD1, the second floating diffusion node FD2, and the capacitor CAP can be removed by the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0099] During the exposure time interval (EIT), the reset transistor RX, the gain control transistor DRX, and the second switching transistor SW2 are turned on, while the other transistors SX, SW1, TX1, and TX2 are turned off. The first photodiode PD1 and the second photodiode PD2 generate charge in response to light, and this generated charge can be retained in both photodiodes PD1 and PD2. However, under relatively strong light input, a charge exceeding the free float (FWC) of the first photodiode PD1 and the second photodiode PD2 can be generated. In the following text, for ease of description, the generated charge exceeding the FWC of each of the first photodiode PD1 and the second photodiode PD2 can be defined as excess charge.

[0100] When excess charge is generated by the first photodiode PD1, the voltage at the node where the first transfer transistor TX1 and the first photodiode PD1 are connected (e.g., the source of the first transfer transistor TX1) can decrease due to the excess charge. Therefore, even if the first transfer control signal TG1 input to the gate of the first transfer transistor TX1 is held at a voltage corresponding to logic low, a path for moving charge can still be formed through the channel of the first transfer transistor TX1. The excess charge of the first photodiode PD1 can then be moved to the first floating diffusion node FD1.

[0101] In this case, since the gain control signal DRG input to the gate of the gain control transistor DRX and the reset control signal RG input to the gate of the reset transistor RX are maintained at a voltage corresponding to logic high, the excess charge of the first photodiode PD1 can be released to the second power supply node.

[0102] Furthermore, in one example embodiment, when excess charge is generated by the second photodiode PD2, the voltage at the node where the second transfer transistor TX2 and the second photodiode PD2 are connected (e.g., the source voltage of the second transfer transistor TX2) can decrease due to the excess charge. Therefore, even if the second transfer control signal TG2 input to the gate of the second transfer transistor TX2 is held at a voltage corresponding to logic low, a path for moving the charge can still be formed through the channel of the second transfer transistor TX2. The excess charge of the second photodiode PD2 can then be moved to the second floating diffusion node FD2.

[0103] In one example embodiment, the source voltage of the second switching transistor SW2 can be reduced due to the charge on the second floating diffusion node FD2. Furthermore, the second switching control signal SG2 input to the gate of the second switching transistor SW2 is maintained at a voltage corresponding to a logic high, thus a path for moving charge can be formed through the channel of the second switching transistor SW2, and excess charge moving to the second floating diffusion node FD2 can move to the capacitor CAP and be stored in the capacitor CAP. Therefore, during the exposure time period EIT, only excess charge of the second photodiode PD2 can be stored in the capacitor CAP. The first switching transistor SW1 can be turned off, so that excess charge does not move to the first floating diffusion node FD1.

[0104] Pixel group PG1 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG1 can output a voltage corresponding to the charge generated by the first photodiode PD1 and the second photodiode PD2 under high conversion gain conditions and low conversion gain conditions, respectively. In the second readout operation, pixel group PG1 can output a voltage corresponding to the excess charge generated by the second photodiode PD2 and stored in the capacitor CAP.

[0105] Reference Figure 5 The reset voltage can be output twice. The first reset voltage can be output with the gain control transistor DRX turned on, and the second reset voltage can be output with the gain control transistor DRX turned off. The first reset voltage can be output when pixel group PG1 has a low conversion gain, and the second reset voltage can be output when pixel group PG1 has a high conversion gain.

[0106] Reference Figure 5During the first readout time period TRD1, the selection transistor SX can be turned on by the selection control signal SEL, and the second switching transistor SW2 can be turned off by the second switching control signal SG2. Subsequently, the reset transistor RX can be turned off by the reset control signal RG, the first switching transistor SW1 can be turned on by the first switching control signal SG1, and the amplifying transistor SF can amplify the voltage of the first floating diffusion node FD1 and output the first reset voltage.

[0107] When the first reset voltage is output (e.g., after the first reset voltage has already been output), the gain control transistor DRX can be turned off by the gain control signal DRG, so that the first node N1 and the first floating diffusion node FD1 can be isolated from each other. The capacitance of the first floating diffusion node FD1 can be kept relatively small, and the second reset voltage can be output under the condition that the pixel group PG1 has a high conversion gain.

[0108] Subsequently, the first transmission transistor TX1 and the second transmission transistor TX2 can be turned on, and the charge of the first photodiode PD1 and the second photodiode PD2 can be transferred to the first floating diffusion node FD1. The amplification transistor SF can output the first signal voltage (which is the voltage of the first floating diffusion node FD1) to the column line COL. Since the gain control transistor DRX remains off, the first signal voltage can be output under the condition that the pixel group PG1 has a high conversion gain.

[0109] The readout circuit connected to column line COL can generate a first pixel signal based on the difference between a second reset voltage and a first signal voltage. The first pixel signal can be a signal used to cover a relatively low first range of illumination.

[0110] Reference Figure 5 After pixel group PG1 outputs the first signal voltage to column line COL, the gain control transistor DRX can be turned on by the gain control signal DRG. Therefore, the capacitance of the first floating diffusion node FD1 can be kept high, and the second signal voltage can be output under the condition that pixel group PG1 has low conversion gain.

[0111] The readout circuit connected to column line COL generates a second pixel signal based on the difference between a first reset voltage and a second signal voltage. The second pixel signal can be a signal used to cover an illuminance range higher than the first range. Here, "the second range is higher than the first range" can mean that the lower limit of the second range is higher than the upper limit of the first range.

[0112] Subsequently, during the second readout time period TRD2 of pixel group PG1, the second switching transistor SW2 can be turned on, allowing the charge stored in capacitor CAP to move to the first floating diffusion node FD1. A signal voltage corresponding to the charge stored in capacitor CAP can then be output via column line COL.

[0113] After the signal voltage is output, the row driver can turn on the reset transistor RX. Therefore, a reset operation to remove the charge from the first floating diffusion node FD1, the second floating diffusion node FD2, and the capacitor CAP can be performed, and the reset voltage can be output via the column line COL. The readout circuit can use the difference between the reset voltage output by pixel group PG1 and the signal voltage to generate a third pixel signal corresponding to the charge stored in capacitor CAP. The third pixel signal can be a signal used to cover an illumination range higher than the second range. Here, "the third range is higher than the second range" can mean that the lower limit of the third range is higher than the upper limit of the second range. In one example, the peripheral circuitry can use the first pixel signal, the second pixel signal, and the third pixel signal to generate image data.

[0114] As described above, excess charge exceeding the field-wound charge (FWC) of the second photodiode PD2 generated only during the exposure time interval (EIT) can be stored in the capacitor CAP. When strong light generating an FWC exceeding that of the second photodiode PD2 enters pixel group PG1, the charge can also be stored in the capacitor CAP. Therefore, a third pixel signal generated from the charge stored in the capacitor CAP can be used to cover relatively high illuminance.

[0115] The first and second pixel signals can be generated from the charges stored in the four photodiodes PD1 and PD2. Optionally, the third pixel signal can be generated from excess charge generated beyond the FWC of one second photodiode PD2. When compared with a typical third pixel signal generated from the excess charge of the four photodiodes PD1 and PD2, the sensitivity of the third pixel signal generated from the excess charge of one second photodiode PD2 in the example embodiment can be improved by approximately four times.

[0116] Figure 6 It shows the basis Figure 4 The diagram shows a layout of pixel groups in an example embodiment. Figure 7 It shows the basis Figure 4 The diagram shows a layout of pixel groups in an example embodiment.

[0117] Figure 6 and Figure 7 It can be shown as a reference. Figures 2 to 4 A diagram illustrating the layout of pixel group PG1. First, refer to... Figure 6 and Figure 7 The device isolation film (DTI) can be an insulating film used to isolate the pixel group PG1 from each other and to isolate the multiple photodiodes PD included in the pixel group PG1 from each other. The pixel group PG1 may include multiple pixel regions PA1 to PA4.

[0118] exist Figure 6 and Figure 7 In the example embodiment shown, pixel group PG1 may include four pixel regions PA1 to PA4 arranged in a 2×2 structure, and each of the four pixel regions PA1 to PA4 may include a photodiode. (See also...) Figures 2 to 4 A first photodiode PD1 (e.g., a primary photodiode) may be disposed in each of the first pixel regions PA1 to the third pixel regions PA3, and a second photodiode PD2 (e.g., a secondary photodiode) may be disposed in the fourth pixel region PA4. A ground region GND to which a ground voltage is applied may be disposed in each of the first pixel regions PA1 to the fourth pixel regions PA4.

[0119] First refer to Figure 6 The gate TG1 of the first transmission transistor and the gate of the amplification transistor SF can be disposed in the first pixel region PA1. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. Highly doped regions disposed on both sides of the gate of the amplification transistor SF can be included in the amplification transistor. A region disposed on one side of the gate of the amplification transistor SF can be included in the third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplification transistor SF.

[0120] In the second pixel region PA2, the gate TG1 of the first transmission transistor and the gate SEL of the selection transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate SEL of the selection transistor and the highly doped regions disposed on both sides of the gate SEL of the selection transistor can be included in the selection transistor. The region disposed on one side of the gate SEL of the selection transistor can be included in the third node region N3, and the region disposed on the other side of the gate SEL of the selection transistor can be connected to the column line.

[0121] In the third pixel region PA3, the gate TG1 of the first transmission transistor and the gate SG1 of the first switching transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. Highly doped regions disposed on both sides of the gate SG1 of the first switching transistor can be included in the first switching transistor. A region disposed on one side of the gate SG1 of the first switching transistor can be included in the first floating diffusion region FD1, and a region disposed on the other side of the gate SG1 of the first switching transistor can be included in the second floating diffusion region FD2.

[0122] In the fourth pixel region PA4, the gate TG2 of the second transmission transistor and the gate SG2 of the second switching transistor can be configured. A highly doped region between the gate TG2 of the second transmission transistor and the gate SG2 of the second switching transistor can be included in the second floating diffusion region FD2. A highly doped region disposed on one side of the gate SG2 of the second switching transistor can be included in the second node region N2.

[0123] Will Figure 6 and Figure 7 In comparison, aside from the difference in the formation of the first floating diffusion region FD1, the layout of pixel group PG1 is similar. (Refer to...) Figure 7 The first floating diffusion region FD1 can be shared among the first pixel region PA1 to the third pixel region PA3. For example, the first floating diffusion region FD1 can be located in a region from which a portion of the device isolation film between the first pixel region PA1 and the third pixel region PA3 can be removed.

[0124] In Figure 7 In different example embodiments shown, the first floating diffusion region FD1 may be disposed in a region from which a portion of the device isolation film between the first pixel region PA1 and the fourth pixel region PA4 can be removed, such that the first floating diffusion region FD1 may be shared in the first pixel region PA1 to the fourth pixel region PA4.

[0125] In addition, in relation to Figure 7 In different example embodiments shown, a portion of the device isolation film between the first pixel region PA1 and the second pixel region PA2 may be removed, and a portion of the device isolation film between the third pixel region PA3 and the fourth pixel region PA4 may be removed. A first floating diffusion region FD1 may be disposed in each of the partial regions. The first pixel region PA1 and the second pixel region PA2, as well as the third pixel region PA3 and the fourth pixel region PA4, may share the first floating diffusion region FD1. However, the formation location of the first floating diffusion region FD1 and / or the relationship of the shared pixel regions are not limited to this.

[0126] Figure 8 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 9 It shows the basis Figure 8 The diagram illustrates the operation of a pixel group in an example embodiment. Figure 10 It shows the basis Figure 8 The diagram shows a layout of pixel groups in an example embodiment.

[0127] Figure 8 It is shown Figure 2 and Figure 3 A circuit diagram of an example embodiment of pixel group PG1. Figure 8 In the example embodiment shown, the pixel group PG1 included in the image sensor may include a plurality of photodiodes PD1, PD2 and PD3 and pixel circuitry. The plurality of photodiodes PD1, PD2 and PD3 may include at least one first photodiode PD1 (e.g., at least one primary photodiode), at least one second photodiode PD2 (e.g., at least one secondary photodiode), and at least one third photodiode PD3 (e.g., at least one tertiary photodiode).

[0128] according to Figure 8 In the example embodiment shown, two first photodiodes PD1 can be connected in parallel between the first floating diffusion node FD1 and the reference node. In this case, the reference node can be a ground node.

[0129] Will Figure 4 Pixel group PG1 and Figure 8 Compare the pixel group PG1 in the data. Figure 8 The pixel group PG1 may also include a third photodiode PD3. The differences will be described in the following description.

[0130] First, refer to Figure 8 Pixel group PG1 may also include a third photodiode PD3. Figure 8 In the example embodiment shown, pixel group PG1 may include a total of four photodiodes. Pixel group PG1 may include two first photodiodes PD1, one second photodiode PD2, and one third photodiode PD3. However, the number of first to third photodiodes is not limited to this. The first to third photodiodes PD1 may be the same size. Therefore, the light-receiving areas of the first to third photodiodes PD1 and PD3 may be the same.

[0131] The pixel circuit may further include a third floating diffusion node FD3 and a third switching transistor SW3. The third floating diffusion node FD3 is connected to a third photodiode PD3 via a third transmission transistor TX3 (e.g., a three-stage transmission transistor TX3). The third switching transistor SW3 is connected between the second floating diffusion node FD2 and the third floating diffusion node FD3. In an example embodiment, a first switching transistor SW1 may be connected between the first floating diffusion node FD1 and the third floating diffusion node FD3. Control signals TG3 and SG3 controlling the third transmission transistor TX3 and the third switching transistor SW3 may be output by the line driver.

[0132] and Figure 8 Unlike the example embodiment shown, when multiple third photodiodes PD3 are configured, the third photodiodes PD3 can be connected in parallel between the third floating diffusion node FD3 and the reference node. In this case, the reference node can be a ground node.

[0133] At least one of the multiple photodiodes PD1, PD2, and PD3 included in pixel group PG1 is electrically connected to capacitor CAP. According to Figure 8 In the example embodiment shown, at least one of the first photodiode PD1 and the third photodiode PD3 may be actively electrically connected to the capacitor CAP during the exposure period.

[0134] Refer to together Figure 8 and Figure 9 The number of photodiodes PDs actively connected to capacitor CAP during the exposure time period EIT can be controlled by controlling the on / off state of the third switching transistor SW3.

[0135] In one example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic low during the exposure time interval EIT, the third photodiode PD3 can be non-actively electrically connected to the capacitor CAP. During the exposure time interval EIT, because the third switch transistor SW3 remains off, only excess charge of the second photodiode PD2 can be transferred to the second floating diffusion node FD2 and the capacitor CAP and can be stored therein. Therefore, Figure 8 and Figure 9 Pixel group PG1 in the reference can be compared with the reference Figures 4 to 7 The example embodiments described are operated in the same manner.

[0136] In another example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic high during the exposure time interval EIT, the third photodiode PD3 may be electrically connected to the capacitor CAP. During the exposure time interval EIT, when excess charge is generated by the second photodiode PD2 and the third photodiode PD3, the source voltages of the second transfer transistor TX2 and the third transfer transistor TX3 may decrease due to the excess charge. Paths for moving the charge can be formed through the channels of the second transfer transistor TX2 and the third transfer transistor TX3, such that the excess charge of the second photodiode PD2 and the third photodiode PD3 can be moved to the second floating diffusion node FD2.

[0137] The source voltage of the second switching transistor SW2 can be reduced due to the charge at the second floating diffusion node FD2. A path for moving the charge can be formed through the channel of the second switching transistor SW2, and excess charge moving to the second floating diffusion node FD2 can move to and be stored in the capacitor CAP. Therefore, during the exposure time period EIT, only the excess charge of the second photodiode PD2 and the third photodiode PD3 is stored in the capacitor CAP. The first switching transistor SW1 can be turned off, preventing excess charge from moving to the first floating diffusion node FD1. Therefore, according to... Figure 8 and Figure 9 In one embodiment, the number of photodiodes actively connected to capacitor CAP during the exposure time period EIT can be controlled and adjusted.

[0138] Pixel group PG1 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG1 may output a voltage corresponding to the charge generated by the first photodiode PD1 to the third photodiode PD3 under high conversion gain conditions and low conversion gain conditions, respectively. In the second readout operation, pixel group PG1 may output a voltage corresponding to the excess charge generated by the second photodiode PD2 and / or the third photodiode PD3 and stored in the capacitor CAP.

[0139] Figure 8 and Figure 9 In the example embodiment shown, pixel group PG1 can use the on / off control of the third switching transistor SW3 to control the amount of excess charge stored in capacitor CAP. Therefore, the excess charge of a second photodiode PD2 and / or a third photodiode PD3 can be used to generate a third pixel signal.

[0140] When compared with a typical third pixel signal generated by excess charge from four photodiodes PD1 to PD3, the sensitivity of the third pixel signal generated by excess charge from a second photodiode PD2 in the example embodiment can be improved by approximately four times, and the sensitivity of the third pixel signal generated by excess charge from a second photodiode PD2 and a third photodiode PD3 in the example embodiment can be improved by approximately two times.

[0141] When Figure 10 The layout of pixel group PG1 and Figure 6 When comparing pixel group PG1, the layout of the third pixel region PA3 and the fourth pixel region PA4 may differ. The differences between the third pixel region PA3 and the fourth pixel region PA4 will be described below.

[0142] A third photodiode PD3 may be disposed in a third pixel region PA3. The gate TG3 of a third transmission transistor and the gate SG1 of a first switching transistor may be disposed in the third pixel region PA3. A highly doped region surrounding the gate TG3 of the third transmission transistor may be included in a third floating diffusion region FD3. Highly doped regions disposed on both sides of the gate SG1 of the first switching transistor may be included in the first switching transistor. A region disposed on one side of the gate SG1 of the first switching transistor may be included in the first floating diffusion region FD1, and a region disposed on the other side of the gate SG1 of the first switching transistor may be included in the third floating diffusion region FD3.

[0143] In the fourth pixel region PA4, the gate TG2 of the second transmission transistor, the gate SG2 of the second switching transistor, and the gate SG3 of the third switching transistor can be configured. A highly doped region between the gates TG2, SG2, and SG3 can be included in the second floating diffusion region FD2. A highly doped region on one side of the gate SG2 of the second switching transistor can be included in the second node region N2. A highly doped region on one side of the gate SG3 of the third switching transistor can be included in the third floating diffusion region FD3.

[0144] Figure 11 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 12 It shows the basis Figure 11 The diagram illustrates the operation of pixel groups in an example embodiment. Figure 13 It shows the basis Figure 11 The diagram shows a layout of pixel groups in an example embodiment.

[0145] Figure 11It can be shown Figure 2 and Figure 3 A circuit diagram of an example embodiment of pixel group PG1. Figure 11 In the example embodiment shown, the pixel group PG1 included in the image sensor may include a plurality of photodiodes PD1, PD2, and PD3 and pixel circuitry. The plurality of photodiodes PD1, PD2, and PD3 may include at least one first photodiode PD1, at least one second photodiode PD2, and at least one third photodiode PD3. Figure 8 Pixel group PG1 and Figure 11 Compare the pixel group PG1 in the data. Figure 11 The pixel group PG1 may also include a fourth switching transistor SW4. The differences will be described in detail below.

[0146] First refer to Figure 11 The pixel group PG1 may further include a fourth switching transistor SW4, which is connected between the first switching transistor SW1 and the first floating diffusion node FD1. The fourth switching control signal SG4, which controls the fourth switching transistor SW4, may be output by the row driver.

[0147] Refer to together Figure 11 and Figure 12 The number of photodiodes PD electrically connected to capacitor CAP during the exposure time period EIT can be controlled by controlling the on / off state of the first switching transistor SW1 and the third switching transistor SW3.

[0148] In one example embodiment, when the first switch control signal SG1 and the third switch control signal SG3 are held at a voltage corresponding to logic low during the exposure time interval EIT, the first photodiode PD1 and the third photodiode PD3 may not be electrically connected to the capacitor CAP. During the exposure time interval EIT, only the excess charge of the second photodiode PD2 can be transferred to the second floating diffusion node FD2 and the capacitor CAP, and can be stored therein. Therefore, Figure 11 and Figure 12 The pixel group PG1 in the reference above can be used as a reference. Figures 4 to 7 The example embodiments described operate in the same manner.

[0149] In another example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic high and the first switch control signal SG1 is held at a voltage corresponding to logic low during the exposure time interval EIT, the third photodiode PD3 can be electrically connected to the capacitor CAP. Excess charge generated by the second photodiode PD2 and the third photodiode PD3 during the exposure time interval EIT can be transferred to the second floating diffusion node FD2 and the capacitor CAP, and can be stored in the capacitor CAP. Therefore, during the exposure time interval EIT, only the excess charge of the second photodiode PD2 and the third photodiode PD3 can be stored in the capacitor CAP.

[0150] In another example embodiment, when the first switch control signal SG1 and the third switch control signal SG3 are held at a voltage corresponding to a logic high during the exposure time interval EIT, the first photodiode PD1 and the third photodiode PD3 can be electrically connected to the capacitor CAP. Excess charge generated in the first photodiode PD1 to the third photodiode PD3 during the exposure time interval EIT can move to the second floating diffusion node FD2 and the capacitor CAP, and can be stored in the capacitor CAP. Therefore, during the exposure time interval EIT, excess charge in the first photodiode PD1 to the third photodiode PD3 can be stored in the capacitor CAP.

[0151] Pixel group PG1 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG1 may output a voltage corresponding to the charge generated by the first photodiode PD1 to the third photodiode PD3 under high conversion gain conditions and low conversion gain conditions, respectively. In the second readout operation, pixel group PG1 may output a voltage corresponding to the excess charge generated by at least one of the first photodiode PD1 to the third photodiode PD3 and stored in the capacitor CAP.

[0152] Figure 11 and Figure 12 In the example embodiment shown, pixel group PG1 can control the amount of excess charge stored in capacitor CAP by controlling the on / off state of first switching transistor SW1 and third switching transistor SW3. Therefore, a third pixel signal can be generated from the excess charge of a second photodiode PD2 and / or a third photodiode PD3 and / or two first photodiodes PD1.

[0153] Compared to a typical third pixel signal generated by the excess charge of four photodiodes PD1 to PD3, the third pixel signal generated by the excess charge of a second photodiode PD2 in the example embodiment provides approximately a four-fold increase in sensitivity, and the third pixel signal generated by the excess charge of a second photodiode PD2 and a third photodiode PD3 in the example embodiment provides approximately a two-fold increase in sensitivity. Furthermore, the third pixel signal generated by the excess charge of a second photodiode PD2, a third photodiode PD3, and two first photodiodes PD1 in the example embodiment provides the same sensitivity.

[0154] Will Figure 13 The layout of pixel group PG1 in the middle and Figure 10 The layout of pixel group PG1 is compared, and the layouts of the first pixel region PA1 to the third pixel region PA3 may differ. The differences between the first pixel region PA1 and the third pixel region PA3 will be discussed below.

[0155] In the first pixel region PA1, the gate TG1 of the first transmission transistor, the gate of the amplification transistor SF, and the gate SG4 of the fourth switching transistor can be configured. A highly doped region between the gate TG1 of the first transmission transistor and the gate SG4 of the fourth switching transistor can be included in a fourth floating diffusion region FD4. A highly doped region disposed on the other side of the gate SG4 of the fourth switching transistor can be included in the first floating diffusion region FD1.

[0156] High-concentration doped regions disposed on both sides of the gate of the amplifying transistor SF can be included in the amplifying transistor. A region disposed on one side of the gate of the amplifying transistor SF can be included in the third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplifying transistor SF. In the second pixel region PA2, the high-concentration doped region around the gate TG1 of the first transmission transistor can be included in the fourth floating diffusion region FD4. In the third pixel region PA3, a region disposed on one side of the gate SG1 of the first switching transistor can be included in the third floating diffusion region FD3, and a region disposed on the other side of the gate SG1 of the first switching transistor can be included in the fourth floating diffusion region FD4.

[0157] Figure 14 This is a diagram illustrating the pixel array structure of an image sensor according to an example embodiment.

[0158] Reference Figure 14The pixel array 200 of the image sensor according to the example embodiment may include a plurality of pixel groups PG2 arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). Each of the plurality of pixel groups PG2 may include a pixel region PA.

[0159] According to an example embodiment, the pixel array 200 may include a color filter having an array configured to generate an image with a nona (or nine-in-one pixel, or pixel-nine-in-one) pattern. Figure 14 In the example embodiment shown, pixel array 200 may have a 6×6 nine-pixel-in-one color filter array FA2, in which each of red, green, and blue is arranged in a 3×3 configuration. Each of the plurality of pixel groups PG2 may include a 3×3 pixel area PA. The 3×3 PD areas PA included in the plurality of pixel groups PG2 may include color filters of the same color. However, the array of color filters is not limited to this.

[0160] exist Figure 14 In the example embodiment shown, each of the plurality of pixel groups PG2 may include a capacitor and nine photodiodes. According to the example embodiment, the sensitivity of the readout operation corresponding to the charge stored in the capacitor can be controlled by controlling the number of photodiodes actively connected to the capacitor in each of the plurality of pixel groups PG2.

[0161] Figure 15 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an example embodiment.

[0162] Figure 15 The pixel group PG2 shown in the image can be the one shown. Figure 14 A cross-sectional view of pixel group PG2 of pixel array 200 is shown. For example, Figure 15 For example, in Figure 14 A cross-section of the three PD regions PA arranged in the first direction in pixel group PG2.

[0163] The image sensor according to the example embodiment may include a first layer L1 and a second layer L2. The first layer L1 and the second layer L2 may be stacked in a third direction (Z-axis direction). The first layer L1 may include a first substrate 201. The first substrate 201 may have a first surface and a second surface parallel to the first surface. A first interlayer insulating layer 220 may be disposed on the first surface of the first substrate 201. A color filter 203 and a microlens 205 may be disposed on the second surface of the first substrate 201. A pixel group PG2 may be defined by a device isolation film DTI. For example, the device isolation film DTI may be an insulating film for isolating the pixel group PG2 from each other.

[0164] Refer to together Figure 14 and Figure 15 Multiple photodiodes PD and multiple transistors 210 may be formed on the first substrate 201. The device isolation film DTI may be an insulating film used to isolate the photodiodes PD included in the pixel group PG2 from each other. The multiple transistors 210 may be interconnected with each other via metal wiring 211, and pixel circuitry connected to the photodiodes PD may be provided.

[0165] A photodiode PD can be disposed in the first substrate 201 and can be defined by a device isolation film DTI. Specifically, refer to Figure 15 The device isolation film (DTI) disposed between the photodiodes (PDs) can be an insulating film used to improve the performance of the image sensor by controlling the movement of electrons in a pixel region (PA). Incident light can be incident on a surface of the first layer L1. For example, the incident light can be incident from outside the image sensor in a third direction. A surface of the first substrate 201 can be used to house a plurality of transistors 210 for processing the electrical signals generated by the photodiodes (PDs).

[0166] Multiple transistors 210 may include a transfer transistor. A portion of the gate TG of the transfer transistor may be stacked with a photodiode PD. According to... Figure 15 In the example embodiment shown, the gate TG of the transmission transistor can be formed as a vertical transmission gate and can be a single transmission gate.

[0167] and Figure 15 Unlike the example embodiments shown, the gate TG of the transport transistor can be a planar transport gate, or it can be formed in a shape combining a planar transport gate and a vertical transport gate. Furthermore, the gate TG of the transport transistor can be a dual transport gate. However, the shape and / or number of gates of the gate TG of the transport transistor are not limited thereto.

[0168] Metallic wiring 211 may be disposed in a first interlayer insulating layer 220 formed on a first surface of the first substrate 201. The uppermost wiring 215 disposed on the uppermost end of the first interlayer insulating layer 220 may be connected to the uppermost wiring 255 of the second layer L2.

[0169] exist Figure 15 In the example embodiment shown, capacitor 230 may be connected to multiple transistors 210 and is included in the pixel circuitry. Capacitor 230 may be disposed in a first interlayer insulating layer 220. A pixel group PG2 may include one capacitor 230. Multiple PD regions PA included in pixel group PG2 may share one capacitor 230.

[0170] As an example, capacitor 230 can be a MIM capacitor having a multi-metal layer structure comprising multiple metal layers and multiple dielectric layers. Figure 15In the example embodiment shown, multiple metal layers and multiple dielectric layers may be stacked alternately in a first direction (X-axis direction). Figure 15 Unlike the example embodiment shown, multiple metal layers and multiple dielectric layers may be stacked alternately in the third-party orientation. Capacitor 230 may be stacked in the third-party orientation with a photodiode PD included in the pixel region PA.

[0171] A portion of the metal layer of capacitor 230 can be connected to the peripheral circuitry of the second layer L2. Therefore, a constant voltage can be applied to a portion of the metal layer. Another portion of the metal layer of capacitor 230 can be connected to at least one of the photodiodes PD. Therefore, the charge generated exceeding the FWC of at least one photodiode connected to capacitor 230 can be stored in capacitor 230.

[0172] The second layer L2 may include a second substrate 202, and a plurality of transistors 240 may be formed on the second substrate 202. The plurality of transistors 240 may be interconnected by metal wiring 251 disposed in the second interlayer insulating layer 250, and may provide peripheral circuitry (such as row drivers and readout circuitry) for driving the pixel array. The uppermost wiring 255 disposed in the uppermost portion of the second interlayer insulating layer 250 may be connected to the uppermost wiring 215 of the first layer L1.

[0173] In one example embodiment, a plurality of first conductive pads may be formed on one surface of a first layer L1, and a plurality of second conductive pads may be formed on one surface of a second layer L2. The first and second conductive pads may be positioned facing each other. Thus, one surface of the first layer L1 and one surface of the second layer L2 may be joined to each other by hybrid bonding or direct bonding without connecting members (such as metal bumps). However, the example embodiment is not limited thereto.

[0174] Figure 16 This is a circuit diagram illustrating a pixel group according to an example embodiment.

[0175] exist Figure 16 In the example embodiment shown, the pixel group PG2 included in the image sensor may include a plurality of photodiodes PD1 and PD2 and pixel circuitry. The plurality of photodiodes PD1 and PD2 may include at least one first photodiode PD1 and at least one second photodiode PD2.

[0176] exist Figure 16In the example embodiment shown, pixel group PG2 may include nine photodiodes. Pixel group PG2 may include eight first photodiodes PD1 and one second photodiode PD2. However, the number of first photodiodes and second photodiodes is not limited to this. The first photodiodes PD1 and the second photodiodes PD2 may be the same size. Therefore, the light-receiving areas of the first photodiodes PD1 and the second photodiodes PD2 may be the same.

[0177] according to Figure 16 In the example embodiment shown, eight first photodiodes PD1 can be connected in parallel between the first floating diffusion node FD1 and the reference node. In this case, the reference node can be a ground node. Furthermore, Figure 4 Pixel group PG1 and Figure 16 The number of second photodiodes PD2 and second transmission transistors TX2 may be different when comparing the pixel group PG2 in the middle (for example, multiple pairs of second photodiodes PD2 and second transmission transistors TX2 connected in series may be connected in parallel between the ground node and the second floating diffusion node FD2).

[0178] The pixel circuit may include a first floating diffusion node FD1, a second floating diffusion node FD2, one or more first transmission transistors TX1, one or more second transmission transistors TX2, a gain control transistor DRX, a reset transistor RX, an amplification transistor SF, a selection transistor SX, a first switching transistor SW1, and a second switching transistor SW2. Control signals TG1, TG2, DRG, RG, SEL, SG1, and SG2 for controlling the multiple transistors included in the pixel circuit may be output by a row driver.

[0179] In the pixel circuitry of pixel group PG2 according to the example embodiment, a capacitor CAP may be included. During the exposure period, at least one of the plurality of photodiodes PD1 and PD2 included in pixel group PG2 may be actively electrically connected to capacitor CAP.

[0180] The first floating diffusion node FD1 can be connected to the first photodiode PD1 via the first transmission transistor TX1. When the first transmission transistor TX1 is turned on by the first transmission control signal TG1, the charge of the first photodiode PD1 can be stored in the first floating diffusion node FD1.

[0181] The second floating diffusion node FD2 can be connected to the second photodiode PD2 via the second transmission transistor TX2. When the second transmission transistor TX2 is turned on by the second transmission control signal TG2, the charge of the second photodiode PD2 can be stored in the second floating diffusion node FD2.

[0182] The first switching transistor SW1 can be connected between the first floating diffusion node FD1 and the second floating diffusion node FD2. In the operation of transferring the charge generated by the second photodiode PD2 to the first floating diffusion node FD1, the first switching transistor SW1 can be turned on by the first switching control signal SG1.

[0183] Capacitor CAP and second switching transistor SW2 can be connected in series between the first power node and the second floating diffusion node FD2. Figure 16 In the example embodiment shown, capacitor CAP may be connected between the first power node and the second node N2, and the second switching transistor SW2 may be connected between the second node N2 and the second floating diffusion node FD2. The first power node may be the node supplying the first power supply voltage VDD1.

[0184] The reset transistor RX and the gain control transistor DRX can be connected in series between the second power supply node and the first floating diffusion node FD1. Figure 16 In the example embodiment shown, the reset transistor RX may be connected between the second power node and the first node N1, and the gain control transistor DRX may be connected between the first node N1 and the first floating diffusion node FD1. The second power node may be the node supplying the second power supply voltage VDD2. In the example embodiment, the second power supply voltage VDD2 may be the same voltage as the first power supply voltage VDD1, or it may be a different voltage than the first power supply voltage VDD1.

[0185] When the gain control transistor DRX is turned on by the gain control signal DCG, the capacitance of the first floating diffusion node FD1 can be increased, which reduces the conversion gain of pixel group PG2. Conversely, when the gain control transistor DRX is turned off, the conversion gain of pixel group PG2 can be increased.

[0186] The gate of the amplifying transistor SF can be connected to the first floating diffusion node FD1, and the amplifying transistor SF can be connected between the third power node and the selection transistor SX. The third power node can be a node supplying a third power supply voltage VDD3. In an example embodiment, the third power supply voltage VDD3 can be equal to at least one of the first power supply voltage VDD1 and the second power supply voltage VDD2. In one example embodiment, the third power supply voltage VDD3 can be equal to the second power supply voltage VDD2 and can be greater than the first power supply voltage VDD1. Furthermore, in one example embodiment, the third power supply voltage VDD3 can be greater than the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0187] The amplifying transistor SF can operate as a source follower amplifier and can generate a signal by amplifying the voltage of the first floating diffusion node FD1. The signal generated by the amplifying transistor SF can be output to the column line COL by turning on the selection transistor SX. The column line COL can be connected to one of the input terminals of a correlated dual sampler, and the correlated dual sampler can transmit the signal output from the column line COL and the output signal determined by the ramp voltage to a counter.

[0188] The operation of pixel group PG2 may include shutter operation, exposure operation, and readout operation. During shutter operation, the charge on the first floating diffuser node FD1, the second floating diffuser node FD2, the first photodiode PD1, and the second photodiode PD2 can be removed. During exposure operation, the first photodiode PD1 and the second photodiode PD2 can be exposed to light for a predetermined exposure time period, and charge can be generated.

[0189] In one example embodiment, the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP, and the charge generated exceeding the FWC of each of the first photodiodes PD1 can be released through the second power node. Therefore, during the exposure period, only the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP.

[0190] During the readout operation, the voltage of the first floating diffusion node FD1 can be amplified and output to the column line COL, and for example, a reset voltage and a signal voltage can be output to the column line COL. When the first floating diffusion node FD1 is reset, the reset voltage can be output to the column line COL by the pixel circuit, and when at least a portion of the charge generated by the photodiode PD is stored in the first floating diffusion node FD1, the signal voltage can be output to the column line COL by the pixel circuit.

[0191] In one example embodiment, the pixel circuitry may perform the operation of outputting a voltage to column line COL two or more times after an exposure period. For example, a readout operation performed after an exposure period may include multiple readout operations performed sequentially. In at least a portion of the multiple readout operations, the conversion gain of pixel group PG2 may be configured differently.

[0192] In one example embodiment, the readout operation may include an HCG readout operation and an LCG readout operation, wherein the HCG readout operation is performed under the condition that pixel group PG2 has a relatively large conversion gain, and the LCG readout operation is performed under the condition that pixel group PG2 has a relatively small conversion gain. Furthermore, the readout operation may include a LOFIC readout operation that reads the voltage corresponding to the charge generated by the overflow of the second photodiode PD2 and stored in the capacitor CAP during the exposure time period.

[0193] In one example embodiment, among the plurality of photodiodes PD1 and PD2 included in pixel group PG2, only the second photodiode PD2 can be connected to capacitor CAP. Therefore, the amount of charge stored in capacitor CAP during the exposure period can be reduced, thereby improving the sensitivity of the readout operation that reads the voltage corresponding to the charge stored in the capacitor.

[0194] Figure 17 It shows the basis Figure 16 The diagram illustrates the operation of pixel groups in an example embodiment.

[0195] Figure 17 This is a timing diagram showing the shutter operation, exposure operation, and readout operation of a pixel group PG2. (Refer to...) Figures 14 to 16 In the operation of the pixel group PG2 described, the on / off state of transistors SX, RX, DRX, SW1, SW2, TX1 and TX2 included in the pixel group PG2 can be determined by the control signals SEL, RG, DRG, SG1, SG2, TG1 and TG2 output by the row driver.

[0196] During the shutter operation time TSH of pixel group PG2, the selection transistor SX can be turned off, and the first transmission transistor TX1, the second transmission transistor TX2, the gain control transistor DRX, the reset transistor RX, the first switching transistor SW1, and the second switching transistor SW2 can be turned on. Therefore, the charge on the first photodiode PD1, the second photodiode PD2, the first floating diffusion node FD1, the second floating diffusion node FD2, and the capacitor CAP can be removed by the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0197] During the exposure time interval (EIT), the reset transistor RX, the gain control transistor DRX, and the second switching transistor SW2 are turned on, while the other transistors SX, SW1, TX1, and TX2 are turned off. The first photodiode PD1 and the second photodiode PD2 generate charge in response to light, and this generated charge can be retained in both photodiodes PD1 and PD2. However, under relatively strong light input, a charge exceeding the free float (FWC) of the first photodiode PD1 and the second photodiode PD2 can be generated. In the following text, for ease of description, the generated charge exceeding the FWC of each of the first photodiode PD1 and the second photodiode PD2 can be defined as excess charge.

[0198] When excess charge is generated by the first photodiode PD1, the voltage at the node where the first transfer transistor TX1 and the first photodiode PD1 are connected (e.g., the source of the first transfer transistor TX1) can decrease due to the excess charge. Therefore, even if the first transfer control signal TG1 input to the gate of the first transfer transistor TX1 can be maintained at a voltage corresponding to logic low, a path for moving charge can be formed through the channel of the first transfer transistor TX1. The excess charge of the first photodiode PD1 can be moved to the first floating diffusion node FD1.

[0199] In this case, since the gain control signal DRG input to the gate of the gain control transistor DRX and the reset control signal RG input to the gate of the reset transistor RX are maintained at a voltage corresponding to logic high, the excess charge of the first photodiode PD1 can be released to the second power supply node.

[0200] Furthermore, in one example embodiment, when excess charge is generated by the second photodiode PD2, the voltage at the node where the second transfer transistor TX2 and the second photodiode PD2 are connected (e.g., the source voltage of the second transfer transistor TX2) can be reduced due to the excess charge. Therefore, even if the second transfer control signal TG2 input to the gate of the second transfer transistor TX2 is held at a voltage corresponding to logic low, a path for moving the charge can be formed through the channel of the second transfer transistor TX2. The excess charge of the second photodiode PD2 can then be moved to the second floating diffusion node FD2.

[0201] In one example embodiment, the source voltage of the second switching transistor SW2 can be reduced due to the charge on the second floating diffusion node FD2. Furthermore, the second switching control signal SG2 input to the gate of the second switching transistor SW2 is maintained at a voltage corresponding to a logic high, thus a path for moving charge can be formed through the channel of the second switching transistor SW2, and excess charge moving to the second floating diffusion node FD2 can move to the capacitor CAP and be stored in the capacitor CAP. Therefore, during the exposure time period EIT, only excess charge of the second photodiode PD2 can be stored in the capacitor CAP. The first switching transistor SW1 can be turned off, so that excess charge does not move to the first floating diffusion node FD1.

[0202] Pixel group PG2 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG2 can output a voltage corresponding to the charge generated by the first photodiode PD1 and the second photodiode PD2 under high conversion gain conditions and low conversion gain conditions, respectively. In the second readout operation, pixel group PG2 can output a voltage corresponding to the excess charge generated by the second photodiode PD2 and stored in the capacitor CAP.

[0203] Reference Figure 17 The reset voltage can be output twice. The first reset voltage can be output with the gain control transistor DRX turned on, and the second reset voltage can be output with the gain control transistor DRX turned off. The first reset voltage can be output when pixel group PG2 has a low conversion gain, and the second reset voltage can be output when pixel group PG2 has a high conversion gain.

[0204] Reference Figure 17 During the first readout time period TRD1, the selection transistor SX can be turned on by the selection control signal SEL, and the second switching transistor SW2 can be turned off by the second switching control signal SG2. Subsequently, the reset transistor RX can be turned off by the reset control signal RG, the first switching transistor SW1 can be turned on by the first switching control signal SG1, and the amplifying transistor SF can amplify the voltage of the first floating diffusion node FD1 and output the first reset voltage.

[0205] When the first reset voltage is output (e.g., after the first reset voltage has already been output), the gain control transistor DRX can be turned off by the gain control signal DRG, and the first node N1 and the first floating diffusion node FD1 can be isolated. The capacitance of the first floating diffusion node FD1 can be kept relatively small, and the second reset voltage can be output under the condition that the pixel group PG2 has a high conversion gain.

[0206] Subsequently, the first transmission transistor TX1 and the second transmission transistor TX2 can be turned on, and the charges of the first photodiode PD1 and the second photodiode PD2 can be moved to the first floating diffusion node FD1. The amplification transistor SF can output the first signal voltage (which is the amplified voltage of the first floating diffusion node FD1) to the column line COL. Since the gain control transistor DRX remains in the off state, the pixel group PG2 can output the first signal voltage with high conversion gain.

[0207] The readout circuit connected to column line COL can derive the first pixel signal based on the difference between the second reset voltage and the first signal voltage. The first pixel signal can be a signal used to cover a relatively low first range of illumination.

[0208] Reference Figure 17 After pixel group PG2 outputs the first signal voltage to column line COL, the gain control transistor DRX can be turned on by the gain control signal DRG. Therefore, the capacitance of the first floating diffusion node FD1 can be kept large, and the second signal voltage can be output under the condition that pixel group PG2 has low conversion gain.

[0209] The readout circuit connected to column line COL can generate a second pixel signal based on the difference between a first reset voltage and a second signal voltage. The second pixel signal can be a signal used to cover a second range of illumination that is higher than the first range.

[0210] Subsequently, during the second readout time period TRD2 of pixel group PG2, the second switching transistor SW2 can be turned on, allowing the charge stored in capacitor CAP to move to the first floating diffusion node FD1. A signal voltage corresponding to the charge stored in capacitor CAP can then be output via column line COL.

[0211] After the signal voltage is output, the row driver can turn on the reset transistor RX. Therefore, a reset operation to remove the charge from the first floating diffusion node FD1, the second floating diffusion node FD2, and the capacitor CAP can be performed, and the reset voltage can be output through the column line COL. The readout circuit can use the difference between the reset voltage output from pixel group PG2 and the signal voltage to generate a third pixel signal. The third pixel signal can be a signal used to cover a third range of illumination that is higher than the second range.

[0212] As described above, only excess charge exceeding the field-wake capacity (FWC) of the second photodiode PD2 generated during the exposure time interval (EIT) can be stored in the capacitor CAP. When strong light generating a charge exceeding the FWC of the second photodiode PD2 enters pixel group PG2, the charge can also be stored in the capacitor CAP. Therefore, a third pixel signal generated from the charge stored in the capacitor CAP can be used to cover relatively high illuminance.

[0213] The first and second pixel signals can be generated from the charges stored in the nine photodiodes PD1 and PD2. Optionally, the third pixel signal can be generated from excess charge generated beyond the FWC of one second photodiode PD2. Compared to a typical third pixel signal generated from the excess charge of nine photodiodes PD1 and PD2, the third pixel signal generated from the excess charge of one second photodiode PD2 in the example embodiment provides approximately a nine-fold increase in sensitivity.

[0214] Figure 18 It shows the basis Figure 16 The diagram shows a layout of pixel groups in an example embodiment.

[0215] Figure 18 Show reference Figures 14 to 16 The example layout for pixel group PG2 is described. First, refer to... Figure 18 The device isolation film (DTI) can be an insulating film used to isolate pixel group PG2 from each other and to isolate multiple photodiodes PD included in pixel group PG2 from each other. Pixel group PG2 may include multiple pixel regions PA1 to PA9.

[0216] exist Figure 18 In the example embodiment shown, pixel group PG2 may include nine pixel regions PA1 to PA9 arranged in a 3×3 structure, and each of the nine pixel regions PA1 to PA9 may include a photodiode. (See also...) Figures 14 to 16 A first photodiode PD1 may be disposed in each of the first pixel regions PA1 to PA4 and the sixth pixel regions PA6 to PA9. A second photodiode PD2 may be disposed in the fifth pixel region PA5. A ground region GND to which a ground voltage is applied may be disposed in each of the first pixel regions PA1 to PA9.

[0217] In the first pixel region PA1 and the sixth pixel region PA6, the gate TG1 of the first transmission transistor and the gate of the amplification transistor SF can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. Highly doped regions disposed on both sides of the gate of the amplification transistor SF can be included within the amplification transistor. A region disposed on one side of the gate of the amplification transistor SF can be included in the third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplification transistor SF.

[0218] In each of the second pixel regions PA2 to the fourth pixel regions PA4, the gate TG1 of the first transmission transistor and the gate SEL of the selection transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in a first floating diffusion region FD1. The gate SEL of the selection transistor and highly doped regions disposed on both sides of the gate SEL of the selection transistor can be included in the selection transistor. A region disposed on one side of the gate SEL of the selection transistor can be included in a third node region N3, and a region disposed on the other side of the gate SEL of the selection transistor can be connected to a column line.

[0219] In the fifth pixel region PA5, the gate TG2 of the second transmission transistor, the gate SG1 of the first switching transistor, and the gate SG2 of the second switching transistor can be configured. A highly doped region between the gate TG2 of the second transmission transistor, the gate SG1 of the first switching transistor, and the gate SG2 of the second switching transistor can be included in the second floating diffusion region FD2. A highly doped region disposed on one side of the gate SG1 of the first switching transistor can be included in the first floating diffusion region FD1. A highly doped region disposed on one side of the gate SG2 of the second switching transistor can be included in the second node region N2.

[0220] In the seventh pixel region PA7, the gate TG1 of the first transfer transistor and the dummy gate DG can be configured. The highly doped region surrounding the gate TG1 of the first transfer transistor can be included in the first floating diffusion region FD1. The dummy gate DG can be used to implement the operating characteristics of pixel group PG2.

[0221] In the eighth pixel region PA8, the gate TG1 of the first transmission transistor and the gate RG of the reset transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate RG of the reset transistor and highly doped regions disposed on both sides of the gate RG of the reset transistor can be included in the reset transistor. A region disposed on one side of the gate RG of the reset transistor can be included in the first node region N1, and a second power supply voltage can be applied to the region disposed on the other side of the gate RG of the reset transistor.

[0222] In the ninth pixel region PA9, the gate TG1 of the first transmission transistor and the gate DRG of the gain control transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate DRG of the gain control transistor and the highly doped regions disposed on both sides of the gate DRG can be included in the gain control transistor. A region disposed on one side of the gate DRG of the gain control transistor can be included in the first node region N1, and a region disposed on the other side of the gate DRG of the gain control transistor can be included in the first floating diffusion region FD1.

[0223] Figure 19 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 20 It shows the basis Figure 19 The diagram illustrates the operation of pixel groups in an example embodiment. Figure 21 It shows the basis Figure 19 The diagram shows a layout of pixel groups in an example embodiment.

[0224] Figure 19 Show Figure 14 and Figure 15 An example embodiment of pixel group PG2. Figure 19 In the example embodiment shown, the pixel group PG2 included in the image sensor may include a plurality of photodiodes PD1, PD2, and PD3 and pixel circuitry. The plurality of photodiodes PD1, PD2, and PD3 may include at least one first photodiode PD1, at least one second photodiode PD2, and at least one third photodiode PD3.

[0225] according to Figure 19 In the example embodiment shown, four first photodiodes PD1 can be connected in parallel between the first floating diffusion node FD1 and the reference node. Four third photodiodes PD3 can be connected in parallel between the third floating diffusion node FD3 and the reference node. In this case, the reference node can be a ground node.

[0226] Will Figure 16 Pixel group PG2 and Figure 19 Compare the pixel group PG2 in the image. Figure 19 The pixel group PG2 may also include a third photodiode PD3. The differences will be described in the following description.

[0227] First, refer to Figure 19 The pixel group PG2 may also include a third photodiode PD3. Figure 19 In the example embodiment shown, pixel group PG2 may include nine photodiodes. Pixel group PG2 may include four first photodiodes PD1, one second photodiode PD2, and four third photodiodes PD3. However, the number of first to third photodiodes is not limited to this. The first to third photodiodes PD1 may be the same size. Therefore, the light-receiving areas of the first to third photodiodes PD1 and PD3 may be the same.

[0228] The pixel circuit may further include a third floating diffusion node FD3 and a third switching transistor SW3. The third floating diffusion node FD3 is connected to a third photodiode PD3 via a third transmission transistor TX3, and the third switching transistor SW3 is connected between the second floating diffusion node FD2 and the third floating diffusion node FD3. In an example embodiment, a first switching transistor SW1 may be connected between the first floating diffusion node FD1 and the third floating diffusion node FD3. Control signals TG3 and SG3 controlling the third transmission transistor TX3 and the third switching transistor SW3 may be output by the line driver.

[0229] according to Figure 19 In the example embodiment shown, four third photodiodes PD3 can be connected in parallel between the third floating diffusion node FD3 and the reference node. In this case, the reference node can be a ground node.

[0230] At least one of the multiple photodiodes PD1, PD2, and PD3 included in pixel group PG2 is electrically connected to capacitor CAP. According to Figure 19 In the example embodiment shown, the first photodiode PD1 and / or the third photodiode PD3 may be actively electrically connected to the capacitor CAP during the exposure period.

[0231] Reference Figure 19 and Figure 20 The number of photodiodes PDs actively connected to capacitor CAP during the exposure time period EIT can be controlled by controlling the on / off state of the third switching transistor SW3.

[0232] In one example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic low during the exposure time interval EIT, the third photodiode PD3 can be passively electrically connected to the capacitor CAP. During the exposure time interval EIT, only excess charge of the second photodiode PD2 can be transferred to the second floating diffusion node FD2 and the capacitor CAP, and can be stored therein. Therefore, Figure 19 and Figure 20 The pixel group PG2 in the reference above can be used as a reference. Figure 16 and Figure 17 The example embodiments described are operated in the same manner.

[0233] In another example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic high during the exposure time interval EIT, the third photodiode PD3 may be electrically connected to the capacitor CAP. During the exposure time interval EIT, when excess charge is generated by the second photodiode PD2 and the third photodiode PD3, the source voltages of the second transfer transistor TX2 and the third transfer transistor TX3 may decrease due to the excess charge. Paths for moving the charge can be formed through the channels of the second transfer transistor TX2 and the third transfer transistor TX3, such that the excess charge of the second photodiode PD2 and the third photodiode PD3 can be moved to the second floating diffusion node FD2.

[0234] The source voltage of the second switching transistor SW2 can be reduced due to the charge at the second floating diffusion node FD2. A path for moving the charge can be formed through the channel of the second switching transistor SW2, and excess charge moving to the second floating diffusion node FD2 can move to the capacitor CAP and be stored. Therefore, during the exposure time period EIT, only excess charge of the second photodiode PD2 and the third photodiode PD3 can be stored in the capacitor CAP. The first switching transistor SW1 can be turned off, preventing excess charge from moving to the first floating diffusion node FD1.

[0235] Pixel group PG2 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG2 may output a voltage corresponding to the charge generated by the first photodiode PD1 to the third photodiode PD3 under each of a high conversion gain condition and a low conversion gain condition. In the second readout operation, pixel group PG2 may output a voltage corresponding to the excess charge generated by the second photodiode PD2 and / or the third photodiode PD3 and stored in the capacitor CAP.

[0236] Figure 19 and Figure 20In the example embodiment shown, pixel group PG2 can use the on / off control of the third switching transistor SW3 to control the amount of excess charge stored in capacitor CAP. The excess charge of one second photodiode PD2 and / or four third photodiodes PD3 can generate the third pixel signal.

[0237] Compared to a typical third pixel signal generated by excess charge from nine photodiodes PD1 to PD3, the third pixel signal generated by excess charge from one second photodiode PD2 in the example embodiment provides approximately nine times the sensitivity, and the third pixel signal generated by excess charge from one second photodiode PD2 and four third photodiodes PD3 in the example embodiment provides approximately 1.8 times the sensitivity.

[0238] Reference Figure 21 A first photodiode PD1 can be disposed in a first pixel region PA1 and a third pixel region PA3. The gate TG1 of a first transmission transistor and the gate of an amplifying transistor SF can be disposed in the first pixel region PA1 and the third pixel region PA3. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in a first floating diffusion region FD1. The gate of the amplifying transistor SF and the highly doped regions disposed on both sides of the gate of the amplifying transistor SF can be included in the amplifying transistor. A region disposed on one side of the gate of the amplifying transistor SF can be included in a third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplifying transistor SF.

[0239] A third photodiode PD3 may be disposed in the second pixel region PA2. Within the second pixel region PA2, the gate TG3 of the third transmission transistor and the gate of the amplification transistor SF may be disposed. A highly doped region surrounding the gate TG3 of the third transmission transistor may be included in a third floating diffusion region FD3. Highly doped regions disposed on both sides of the gate of the amplification transistor SF may be included within the amplification transistor. A region disposed on one side of the gate of the amplification transistor SF may be included in a third node region N3, and a third power supply voltage may be applied to the region disposed on the other side of the gate of the amplification transistor SF.

[0240] A third photodiode PD3 can be disposed in a fourth pixel region PA4. In the fourth pixel region PA4, the gate TG3 of a third transmission transistor and the gate SEL of a select transistor can be disposed. A highly doped region surrounding the gate TG3 of the third transmission transistor can be included in a third floating diffusion region FD3. Highly doped regions disposed on both sides of the gate SEL of the select transistor can be included in the select transistor. A region disposed on one side of the gate SEL of the select transistor can be included in a third node region N3, and a region disposed on the other side of the gate SEL of the select transistor can be connected to a column line.

[0241] A second photodiode PD2 may be disposed in the fifth pixel region PA5. In the fifth pixel region PA5, the gate TG2 of the second transmission transistor, the gate SG2 of the second switching transistor, and the gate SG3 of the third switching transistor may be disposed. A highly doped region between the gates TG2, SG2, and SG3 may be included in the second floating diffusion region FD2. A highly doped region disposed on one side of the gate SG2 of the second switching transistor may be included in the second node region N2. A highly doped region disposed on one side of the gate SG3 of the third switching transistor may be included in the third floating diffusion region FD3.

[0242] A third photodiode PD3 may be disposed in the sixth pixel region PA6. In the sixth pixel region PA6, the gate TG3 of the third transmission transistor and the gate SG1 of the first switching transistor may be disposed. A highly doped region surrounding the gate TG3 of the third transmission transistor may be included in a third floating diffusion region FD3. Highly doped regions disposed on both sides of the gate SG1 of the first switching transistor may be included in the first switching transistor. A region disposed on one side of the gate SG1 of the first switching transistor may be included in the first floating diffusion region FD1, and a region disposed on the other side of the gate SG1 of the first switching transistor may be included in the third floating diffusion region FD3.

[0243] A first photodiode PD1 may be disposed in a seventh pixel region PA7. Within the seventh pixel region PA7, the gate TG1 of a first transmission transistor and the gate SG1 of a first switching transistor may be disposed. A highly doped region surrounding the gate TG1 of the first transmission transistor may be included in a first floating diffusion region FD1. A region disposed on one side of the gate SG1 of the first switching transistor may be included in the first floating diffusion region FD1, and a region disposed on the other side of the gate SG1 of the first switching transistor may be included in a third floating diffusion region FD3.

[0244] A third photodiode PD3 may be disposed in the eighth pixel region PA8. In the eighth pixel region PA8, the gate TG3 of the third transmission transistor and the gate RG of the reset transistor may be disposed. A highly doped region surrounding the gate TG3 of the third transmission transistor may be included in the third floating diffusion region FD3. The gate RG of the reset transistor and highly doped regions disposed on both sides of the gate RG of the reset transistor may be included in the reset transistor. The region disposed on one side of the gate RG of the reset transistor may be included in the first node region N1, and a second power supply voltage may be applied to the region disposed on the other side of the gate RG of the reset transistor.

[0245] A first photodiode PD1 may be disposed in the ninth pixel region PA9. The gate TG1 of the first transmission transistor and the gate DRG of the gain control transistor may be disposed in the ninth pixel region PA9. A highly doped region surrounding the gate TG1 of the first transmission transistor may be included in a first floating diffusion region FD1. The gate DRG of the gain control transistor and highly doped regions disposed on both sides of the gate DRG of the gain control transistor may be included in the gain control transistor. A region disposed on one side of the gate DRG of the gain control transistor may be included in a first node region N1, and a region disposed on the other side of the gate DRG of the gain control transistor may be included in the first floating diffusion region FD1.

[0246] Figure 22 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 23 It shows the basis Figure 22 The diagram illustrates the operation of a pixel group in an example embodiment. Figure 24 It shows the basis Figure 22 The diagram shows a layout of pixel groups in an example embodiment.

[0247] Figure 22 Show Figure 14 and Figure 15 An example embodiment of pixel group PG2. Figure 22 In the example embodiment shown, the pixel group PG2 included in the image sensor may include a plurality of photodiodes PD1, PD2, and PD3 and pixel circuitry. The plurality of photodiodes PD1, PD2, and PD3 may include at least one first photodiode PD1, at least one second photodiode PD2, and at least one third photodiode PD3. Figure 19 Pixel group PG2 and Figure 22 Compare the pixel group PG2 in the image. Figure 22 The pixel group PG2 may also include a fourth switching transistor SW4. The differences will be described in detail below.

[0248] First refer to Figure 22 Pixel group PG2 may further include a fourth switching transistor SW4, which is connected between the first switching transistor SW1 and the first floating diffusion node FD1. The fourth switching control signal SG4 controlling the fourth switching transistor SW4 may be output by the row driver.

[0249] Reference Figure 22 and Figure 23 By controlling the on / off state of the first switching transistor SW1 and the third switching transistor SW3, the number of photodiodes PD electrically connected to capacitor CAP during the exposure time period EIT can be controlled.

[0250] In one example embodiment, when the first switch control signal SG1 and the third switch control signal SG3 are held at a voltage corresponding to logic low during the exposure time interval EIT, the first photodiode PD1 and the third photodiode PD3 can be actively electrically connected to the capacitor CAP. During the exposure time interval EIT, only the excess charge of the second photodiode PD2 can be transferred to the second floating diffusion node FD2 and the capacitor CAP, and can be stored therein. Therefore, Figure 22 and Figure 23 The pixel group PG2 in the reference above can be used as a reference. Figure 16 and Figure 17 The example embodiments described operate in the same manner.

[0251] In another example embodiment, when the third switch control signal SG3 is held at a voltage corresponding to logic high and the first switch control signal SG1 is held at a voltage corresponding to logic low during the exposure time interval EIT, the third photodiode PD3 can be actively electrically connected to the capacitor CAP. Excess charge generated by the second photodiode PD2 and / or the third photodiode PD3 during the exposure time interval EIT can be transferred to the second floating diffusion node FD2 and the capacitor CAP, and can be stored in the capacitor CAP. Therefore, during the exposure time interval EIT, only the excess charge of the second photodiode PD2 and / or the third photodiode PD3 can be stored in the capacitor CAP.

[0252] In another example embodiment, when the first switch control signal SG1 and the third switch control signal SG3 are held at a voltage corresponding to a logic high during the exposure time interval EIT, the first photodiode PD1 and the third photodiode PD3 can be electrically connected to the capacitor CAP. Excess charge generated in the first photodiode PD1 to the third photodiode PD3 during the exposure time interval EIT can move to the second floating diffusion node FD2 and the capacitor CAP, and can be stored in the capacitor CAP. Therefore, during the exposure time interval EIT, excess charge in the first photodiode PD1 to the third photodiode PD3 can be stored in the capacitor CAP.

[0253] Pixel group PG2 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG2 may output a voltage corresponding to the charge generated by the first photodiode PD1 to the third photodiode PD3 under each of the high conversion gain condition and the low conversion gain condition. In the second readout operation, pixel group PG2 may output a voltage corresponding to the excess charge generated by at least one of the first photodiode PD1 to the third photodiode PD3 and stored in the capacitor CAP.

[0254] Figure 22 and Figure 23 In the example embodiment shown, pixel group PG2 can control the amount of excess charge stored in capacitor CAP by controlling the on / off state of first switching transistor SW1 and third switching transistor SW3. A third pixel signal can be generated from the excess charge of one second photodiode PD2 and / or four third photodiodes PD3 and / or four first photodiodes PD1.

[0255] Compared to a typical third pixel signal generated by excess charge from nine photodiodes PD1 to PD3, the third pixel signal generated by excess charge from one second photodiode PD2 in the example embodiment provides approximately a nine-fold increase in sensitivity, and the third pixel signal generated by excess charge from one second photodiode PD2 and four third photodiodes PD3 in the example embodiment provides approximately a 1.8-fold increase in sensitivity. Furthermore, the third pixel signal generated by excess charge from one second photodiode PD2, four third photodiodes PD3, and four first photodiodes PD1 in the example embodiment provides the same sensitivity.

[0256] Will Figure 21 The layout of pixel group PG2 and Figure 24The layout of pixel group PG2 is compared, and the layouts of the first pixel region PA1, the third pixel region PA3, the sixth pixel region PA6, the seventh pixel region PA7, and the ninth pixel region PA9 may differ. The differences between the first pixel region PA1, the third pixel region PA3, the sixth pixel region PA6, the seventh pixel region PA7, and the ninth pixel region PA9 will be described below.

[0257] In the first pixel region PA1 and the third pixel region PA3, the gate TG1 of the first transmission transistor and the gate of the amplification transistor SF can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in a fourth floating diffusion region FD4. Highly doped regions disposed on both sides of the gate of the amplification transistor SF can be included within the amplification transistor. A highly doped region disposed on one side of the gate of the amplification transistor SF can be included in a third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplification transistor SF.

[0258] In the sixth pixel region PA6, the gate TG3 of the third transmission transistor and the gate SG4 of the fourth switching transistor can be configured. A highly doped region surrounding the gate TG3 of the third transmission transistor can be included in the third floating diffusion region FD3. Highly doped regions disposed on both sides of the gate SG4 of the fourth switching transistor can be included in the fourth switching transistor. A region disposed on one side of the gate SG4 of the fourth switching transistor can be included in the first floating diffusion region FD1, and a region disposed on the other side of the gate SG4 of the fourth switching transistor can be included in the fourth floating diffusion region FD4.

[0259] In the seventh pixel region PA7, the gate TG1 of the first transmission transistor and the gate SG1 of the first switching transistor can be configured. A highly doped region between the gate TG1 of the first transmission transistor and the gate SG1 of the first switching transistor can be included in a fourth floating diffusion region FD4. A region disposed on one side of the gate SG1 of the first switching transistor can be included in a third floating diffusion region FD3.

[0260] In the ninth pixel region PA9, the gate TG1 of the first transmission transistor and the gate DRG of the gain control transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the fourth floating diffusion region FD4. The gate DRG of the gain control transistor and the highly doped regions disposed on both sides of the gate DRG can be included in the gain control transistor. The region disposed on one side of the gate DRG of the gain control transistor can be included in the first node region N1, and the region disposed on the other side of the gate DRG of the gain control transistor can be included in the first floating diffusion region FD1.

[0261] Figure 25 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 26 This is a circuit diagram illustrating a pixel group according to an example embodiment.

[0262] Reference Figure 25 and Figure 26 The pixel group PG2 included in the image sensor may include multiple photodiodes PD1 and PD2 and pixel circuitry. The multiple photodiodes PD1 and PD2 may include at least one first photodiode PD1 and at least one second photodiode PD2. The pixel group PG2 may include nine photodiodes. Alternatively, the pixel group PG2 may include eight first photodiodes PD1 and one second photodiode PD2. However, the number of first and second photodiodes is not limited to this.

[0263] The pixel circuit may include a first floating diffusion node FD1, a first transmission transistor TX1, a second transmission transistor TX2, a gain control transistor DRX, a reset transistor RX, an amplification transistor SF, a selection transistor SX, an overflow transistor OX, and a switching transistor SW. Control signals TG1, TG2, DRG, RG, SEL, OG, and SG used to control the multiple transistors included in the pixel circuit may be output by the row driver.

[0264] In the pixel circuitry of pixel group PG2 according to the example embodiment, a capacitor CAP may be included. During the exposure period, at least one of the plurality of photodiodes PD1 and PD2 included in pixel group PG2 may be electrically connected to capacitor CAP.

[0265] Will Figure 16 Pixel group PG2 and Figure 25 and Figure 26 Compare the pixel group PG2 in the image. Figure 25 and Figure 26 The pixel group PG2 may not include the first switching transistor SW1 and the second switching transistor SW2, and may include an overflow transistor OX. The differences will be described below.

[0266] First, refer to Figure 25 The overflow transistor OX provides a path for moving excess charge generated beyond the field-whole charge (FWC) in the photodiode PD to the capacitor CAP. The amount of excess charge moving to the capacitor CAP can be controlled by adjusting the voltage applied to the gate of the overflow transistor.

[0267] The first floating diffusion node FD1 can be connected to the first photodiode PD1 via the first transmission transistor TX1. When the first transmission transistor TX1 is turned on by the first transmission control signal TG1, the charge of the first photodiode PD1 can be stored in the first floating diffusion node FD1.

[0268] The second transfer transistor TX2 can be connected between the first floating diffusion node FD1 and the second photodiode PD2. In the operation of transferring the charge generated by the second photodiode PD2 to the first floating diffusion node FD1, the second transfer transistor TX2 can be turned on by the second transfer control signal TG2.

[0269] Capacitor CAP can be connected between the first power supply node and the overflow transistor OX. Figure 25 In the example embodiment shown, capacitor CAP may be connected between a first power node and a second node N2. The first power node may be the node supplying a first power supply voltage VDD1. An overflow transistor OX provides a path for moving the charge generated by the second photodiode PD2 to capacitor CAP.

[0270] The reset transistor RX and the gain control transistor DRX can be connected to each other between the second power node and the first floating diffusion node FD1. Figure 25 In the example embodiment shown, the reset transistor RX may be connected between the second power node and the first node N1, and the gain control transistor DRX may be connected between the first node N1 and the first floating diffusion node FD1. The second power node may be the node supplying the second power supply voltage VDD2. In the example embodiment, the second power supply voltage VDD2 may be the same voltage as the first power supply voltage VDD1, or it may be a different voltage than the first power supply voltage VDD1. The switching transistor SW may be connected between the first node N1 and the second node N2.

[0271] When the gain control transistor DRX is turned on by the gain control signal DCG, the capacitance of the first floating diffusion node FD1 can increase, thereby reducing the conversion gain of pixel group PG2. Conversely, when the gain control transistor DRX is turned off, the conversion gain of pixel group PG2 can increase.

[0272] The gate of the amplifying transistor SF can be connected to the first floating diffusion node FD1, and the amplifying transistor SF can be connected between the third power node and the selection transistor SX. The third power node can be a node supplying a third power supply voltage VDD3. In an example embodiment, the third power supply voltage VDD3 can be equal to at least one of the first power supply voltage VDD1 and the second power supply voltage VDD2. In one example embodiment, the third power supply voltage VDD3 can be equal to the second power supply voltage VDD2 and can be greater than the first power supply voltage VDD1. Furthermore, in one example embodiment, the third power supply voltage VDD3 can be greater than the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0273] The amplifying transistor SF can operate as a source follower amplifier and can generate a signal by amplifying the voltage of the first floating diffusion node FD1. The signal generated by the amplifying transistor SF can be output to the column line COL by turning on the selection transistor SX. The column line COL can be connected to one of the input terminals of a correlated dual sampler, and the correlated dual sampler can transmit the signal output from the column line COL and the output signal determined by the ramp voltage to a counter.

[0274] The operation of pixel group PG2 may include shutter operation, exposure operation, and readout operation. During shutter operation, the charge on the first floating diffusion node FD1, the first photodiode PD1, and the second photodiode PD2 can be removed. During exposure operation, the first photodiode PD1 and the second photodiode PD2 can be exposed to light for a predetermined exposure time period, and charge can be generated.

[0275] In one example embodiment, the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP, and the charge generated exceeding the FWC of each of the first photodiodes PD1 can be released through the second power node. Therefore, during the exposure period, only the charge generated exceeding the FWC of the second photodiode PD2 can be stored in the capacitor CAP.

[0276] During the readout operation, the voltage of the first floating diffusion node FD1 can be amplified and output to the column line COL, and for example, a reset voltage and a signal voltage can be output to the column line COL. When the first floating diffusion node FD1 is reset, the reset voltage can be output to the column line COL by the pixel circuit, and when at least a portion of the charge generated by the photodiode PD is stored in the first floating diffusion node FD1, the signal voltage can be output to the column line COL by the pixel circuit.

[0277] In one example embodiment, the pixel circuitry may perform the operation of outputting a voltage to column line COL two or more times after an exposure period. For example, a readout operation performed after an exposure period may include multiple readout operations performed sequentially. In at least a portion of the multiple readout operations, the conversion gain of pixel group PG2 may be configured differently.

[0278] In one example embodiment, the readout operation may include an HCG readout operation and an LCG readout operation, wherein the HCG readout operation is performed under the condition that pixel group PG2 has a relatively large conversion gain, and the LCG readout operation is performed under the condition that pixel group PG2 has a relatively small conversion gain. Furthermore, the readout operation may include a LOFIC readout operation that reads the voltage corresponding to the charge generated by the overflow of the second photodiode PD2 and stored in the capacitor CAP during the exposure time period. In this case, the switching transistor SW can be turned on by the switching control signal SG.

[0279] In one example embodiment, among the multiple photodiodes PD1 and PD2 included in pixel group PG2, only one second photodiode PD2 can be connected to capacitor CAP. Therefore, the amount of charge stored in capacitor CAP during the exposure period can be reduced, and the sensitivity of the readout operation corresponding to the charge stored in the capacitor can be improved.

[0280] Will Figure 26 Pixel group PG2 and Figure 25 The number of overflow transistors OX and the number of second transmission transistors TX2 can be different when comparing pixel group PG2. Figure 26 The pixel group PG2 may include three overflow transistors OX and three second transmission transistors TX2.

[0281] according to Figure 26 In the example embodiment shown, two first photodiodes PD1 can be connected in parallel between the first floating diffusion node FD1 and the reference node. In this case, the reference node can be a ground node.

[0282] Figure 27 It shows the basis Figure 25 The diagram illustrates the operation of pixel groups in an example embodiment.

[0283] Figure 27 This shows the shutter operation, exposure operation, and readout operation for a pixel group PG2. (Refer to...) Figure 25 and Figure 26In the pixel group PG2 described, the on / off state of each of the transistors TX1, TX2, DRX, RX, SX, OX and SW included in the pixel group PG2 can be determined by the control signals TG1, TG2, DRG, RG, SEL, OG and SG output by the row driver.

[0284] During the shutter operation time TSH of pixel group PG2, the selection transistor SX can be turned off, and the first transmission transistor TX1, the second transmission transistor TX2, the gain control transistor DRX, the reset transistor RX, the overflow transistor OX, and the switching transistor SW can be turned on. Therefore, the charge on the first photodiode PD1, the second photodiode PD2, the first floating diffusion node FD1, and the capacitor CAP can be removed by the first power supply voltage VDD1 and the second power supply voltage VDD2.

[0285] During the exposure time interval (EIT), the reset transistor RX, gain control transistor DRX, and overflow transistor OX are turned on, while other transistors SX, SW, TX1, and TX2 can be turned off. The first photodiode PD1 and the second photodiode PD2 can generate charge in response to light, and the generated charge can be retained in the first photodiode PD1 and the second photodiode PD2. However, under relatively strong light input, a charge exceeding the free float (FWC) of the first photodiode PD1 and the second photodiode PD2 can be generated. In the following text, for ease of description, the generated charge exceeding the FWC in each of the first photodiode PD1 and the second photodiode PD2 can be defined as excess charge.

[0286] When excess charge is generated by the first photodiode PD1, the voltage at the node where the first transfer transistor TX1 and the first photodiode PD1 are connected (e.g., the source voltage of each first transfer transistor TX1) can decrease due to the excess charge. Therefore, even if the first transfer control signal TG1 input to the gate of the first transfer transistor TX1 is held at a voltage corresponding to logic low, a path for moving charge can be formed through the channel of the first transfer transistor TX1. The excess charge of the first photodiode PD1 can be moved to the first floating diffusion node FD1.

[0287] In this case, since the gain control signal DRG input to the gate of the gain control transistor DRX and the reset control signal RG input to the gate of the reset transistor RX are maintained at a voltage corresponding to logic high, the excess charge of the first photodiode PD1 can be discharged to the second power supply node.

[0288] Furthermore, as an example embodiment, when excess charge is generated by the second photodiode PD2, since the overflow control signal OG input to the gate of the overflow transistor OX is maintained at a voltage corresponding to the logic middle, a path for moving the charge can be formed through the overflow transistor OX. The excess charge of the second photodiode PD2 can move to the second node N2. The excess charge moved to the second node N2 can move to the capacitor CAP and can be stored. Therefore, during the exposure time period EIT, only the excess charge of the second photodiode PD2 can be stored in the capacitor CAP.

[0289] The second transfer transistor TX2 can be turned off, preventing excess charge from moving to the first floating diffusion node FD1. Furthermore, the switching transistor SW can be turned off, preventing excess charge from moving to the first node N1.

[0290] Pixel group PG2 can perform a readout operation after the exposure time interval EIT has elapsed. The readout operation may include a first readout operation and a second readout operation. In the first readout operation, pixel group PG2 may output a voltage corresponding to the charge generated by the first photodiode PD1 and the second photodiode PD2 under each of the high conversion gain condition and the low conversion gain condition. In the second readout operation, pixel group PG2 may output a voltage corresponding to the excess charge generated by the second photodiode PD2 and stored in the capacitor CAP.

[0291] Reference Figure 27 The reset voltage can be output twice. The first reset voltage can be output with the gain control transistor DRX on, and the second reset voltage can be output with the gain control transistor DRX off. The first reset voltage can be output when pixel group PG2 has a low conversion gain, and the second reset voltage can be output when pixel group PG2 has a high conversion gain.

[0292] Reference Figure 27 During the first readout period TRD1, the selection transistor SX can be turned on by the selection control signal SEL, and the switching transistor SW can be turned off by the switching control signal SG. Subsequently, the reset transistor RX can be turned off by the reset control signal RG, and the amplifying transistor SF can amplify the voltage of the first floating diffusion node FD1 and output the first reset voltage.

[0293] When the first reset voltage is output, the gain control transistor DRX can be turned off by the gain control signal DRG, and the first node N1 and the first floating diffusion node FD1 can be isolated. The capacitance of the first floating diffusion node FD1 can be kept relatively small, and the second reset voltage can be output under the condition that the pixel group PG2 has a high conversion gain.

[0294] Subsequently, the first transmission transistor TX1 and the second transmission transistor TX2 can be turned on, and the charges of the first photodiode PD1 and the second photodiode PD2 can be moved to the first floating diffusion node FD1. The amplification transistor SF can output the first signal voltage (which is the amplified voltage of the first floating diffusion node FD1) to the column line COL. Since the gain control transistor DRX remains in the off state, the pixel group PG2 can output the first signal voltage with high conversion gain.

[0295] The readout circuit connected to column line COL can derive the first pixel signal based on the difference between the second reset voltage and the first signal voltage. The first pixel signal can be a signal used to cover a relatively low first range of illumination.

[0296] Reference Figure 27 After pixel group PG2 outputs the first signal voltage to column line COL, the gain control transistor DRX can be turned on by the gain control signal DRG. Therefore, the capacitance of the first floating diffusion node FD1 can be kept large, and the second signal voltage can be output under the condition that pixel group PG2 has low conversion gain.

[0297] The readout circuit connected to column line COL can generate a second pixel signal based on the difference between a first reset voltage and a second signal voltage. The second pixel signal can be a signal used to cover a second range of illumination that is higher than the first range.

[0298] Subsequently, during the second readout time period TRD2 of pixel group PG2, the switching transistor SW can be turned on, allowing the charge stored in capacitor CAP to move to the first floating diffusion node FD1. A signal voltage corresponding to the charge stored in capacitor CAP can then be output via column line COL.

[0299] After the signal voltage is output, the row driver can turn on the reset transistor RX. Therefore, a reset operation to remove the charge from the first floating diffusion node FD1 and capacitor CAP can be performed, and the reset voltage can be output through the column line COL. The readout circuit can use the difference between the reset voltage output from pixel group PG2 and the signal voltage to generate a third pixel signal. The third pixel signal can be a signal used to cover a third range of illumination that is higher than the second range.

[0300] As described above, only excess charge exceeding the field-wake capacity (FWC) of the second photodiode PD2 generated during the exposure time interval (EIT) can be stored in the capacitor CAP. When strong light generating a charge exceeding the FWC of the second photodiode PD2 enters pixel group PG2, the charge can also be stored in the capacitor CAP. Therefore, a third pixel signal generated from the charge stored in the capacitor CAP can be used to cover relatively high illuminance.

[0301] Show Figure 27 The timing diagrams of the example embodiments shown can be applied in the same way. Figure 26 The example embodiment shown is pixel group PG2.

[0302] The first and second pixel signals can be generated from the charges stored in the nine photodiodes PD1 and PD2. Optionally, the third pixel signal can be generated from the charges generated in the FWC of more than one second photodiode PD2.

[0303] according to Figure 25 The example embodiment shown can generate a third pixel signal from the excess charge generated by the FWC of more than one second photodiode PD2. According to... Figure 26 The example embodiment shown can generate a third pixel signal from the excess FWC charge of more than three second photodiodes PD2. Therefore, with... Figure 26 The sensitivity of the LOFIC readout operation in the example embodiments shown is compared. Figure 25 The sensitivity of the LOFIC readout operation in the example embodiment shown can be improved by three times.

[0304] Figure 28 It shows the basis Figure 25 The diagram shows a layout of pixel groups in an example embodiment.

[0305] Reference Figure 28 The device isolation film (DTI) can be an insulating film used to isolate pixel group PG2 from each other and to isolate multiple photodiodes PD included in pixel group PG2 from each other. Pixel group PG2 may include multiple pixel regions PA1 to PA9.

[0306] exist Figure 28 In the example embodiment shown, pixel group PG2 may include nine pixel regions PA1 to PA9 arranged in a 3×3 structure, and each of the nine pixel regions PA1 to PA9 may include a photodiode. (See also...) Figure 28A first photodiode PD1 may be disposed in each of the first pixel regions PA1 to PA4 and the sixth pixel regions PA6 to PA9. A second photodiode PD2 may be disposed in the fifth pixel region PA5. In each of the first pixel regions PA1 to PA9, a grounding region GND to which a ground voltage is applied may be provided.

[0307] In the first pixel region PA1 and the fourth pixel region PA4, the gate TG1 and the dummy gate DG of the first transmission transistor can be configured. The highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1.

[0308] In each of the second pixel region PA2, the third pixel region PA3, and the sixth pixel region PA6, the gate TG1 of the first transmission transistor and the gate of the amplification transistor SF can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in a first floating diffusion region FD1. The gate of the amplification transistor SF and highly doped regions disposed on both sides of the gate of the amplification transistor SF can be included in the amplification transistor. A region disposed on one side of the gate of the amplification transistor SF can be included in a third node region N3, and a third power supply voltage can be applied to the region disposed on the other side of the gate of the amplification transistor SF.

[0309] In the fifth pixel region PA5, the gate TG2 of the second transmission transistor, the gate OG of the overflow transistor, and the gate SEL of the selection transistor can be configured. A highly doped region surrounding the gate TG2 of the second transmission transistor can be included in the first floating diffusion region FD1. A highly doped region surrounding the gate OG of the overflow transistor can be included in the second node region N2. Highly doped regions located on both sides of the gate SEL of the selection transistor can be included in the selection transistor. A region located on one side of the gate SEL of the selection transistor can be included in the third node region N3, and a region located on the other side of the gate SEL of the selection transistor can be connected to a column line.

[0310] In the seventh pixel region PA7, the gate TG1 of the first transmission transistor and the gate RG of the reset transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate RG of the reset transistor and highly doped regions disposed on both sides of the gate RG of the reset transistor can be included in the reset transistor. A region disposed on one side of the gate RG of the reset transistor can be included in the first node region N1, and a second power supply voltage can be applied to the region disposed on the other side of the gate RG of the reset transistor.

[0311] In the eighth pixel region PA8, the gate TG1 of the first transmission transistor and the gate SG of the switching transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate SG of the switching transistor and highly doped regions disposed on both sides of the gate SG can be included in the switching transistor. A region disposed on one side of the gate SG of the switching transistor can be included in the first node region N1, and a region disposed on the other side of the gate SG of the switching transistor can be included in the second node region N2.

[0312] In the ninth pixel region PA9, the gate TG1 of the first transmission transistor and the gate DRG of the gain control transistor can be configured. A highly doped region surrounding the gate TG1 of the first transmission transistor can be included in the first floating diffusion region FD1. The gate DRG of the gain control transistor and the highly doped regions disposed on both sides of the gate DRG can be included in the gain control transistor. A region disposed on one side of the gate DRG of the gain control transistor can be included in the first node region N1, and a region disposed on the other side of the gate DRG of the gain control transistor can be included in the first floating diffusion region FD1.

[0313] Figure 29 This is a diagram illustrating the pixel array structure of an image sensor according to an example embodiment.

[0314] Reference Figure 29 The pixel array 300 of the image sensor according to the example embodiment may include a plurality of pixel groups PG3 arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). Each of the plurality of pixel groups PG3 may include a pixel region PA.

[0315] The pixel array 300 according to an example embodiment may include a color filter that generates an array having an image with a hexa (or hexa pixel, or pixel-hexa) pattern. Figure 29 In the example embodiment shown, pixel array 300 may have an 8×8 hexapole-based color filter array FA3, in which each of the red, green, and blue pixels is arranged in a 4×4 configuration. Each of the plurality of pixel groups PG3 may include a 4×4 pixel region PA. For example, the 4×4 PD regions PA included in the plurality of pixel groups PG4 may include the same color filter. However, the array of color filters is not limited to this.

[0316] exist Figure 29In the example embodiment shown, each of the plurality of pixel groups PG3 may include a capacitor and 16 photodiodes. According to the example embodiment, the sensitivity of the LOFIC readout operation can be controlled by controlling the number of photodiodes connected to the capacitor in each of the plurality of pixel groups PG3.

[0317] Figure 30 This is a diagram illustrating the structure of a group of pixels included in an image sensor according to an example embodiment.

[0318] Figure 30 The pixel group PG3 shown in the image shows Figure 29 The image shows a cross-section of pixel group PG3 of pixel array 300. For example, Figure 30 It is shown Figure 29 A cross-sectional view of the four PD regions PA arranged in the first direction in pixel group PG3.

[0319] Will Figure 30 Pixel group PG3 and Figure 15 Compare the pixel group PG2 in the data. Figure 30 Pixel group PG3 may also include a pixel region PA. Other specific example embodiments can be similar to those described in the reference. Figure 15 Example of the description.

[0320] Figure 31 This is a circuit diagram illustrating a pixel group according to an example embodiment. Figure 32 It shows the basis Figure 31 The diagram illustrates the operation of a pixel group in an example embodiment. Figure 33 It shows the basis Figure 31 The diagram shows a layout of pixel groups in an example embodiment.

[0321] Reference Figure 31 Pixel group PG3 may include 16 photodiodes. Pixel group PG3 may include 12 first photodiodes PD1 and 4 second photodiodes PD2. However, the number of first photodiodes and second photodiodes is not limited to this.

[0322] Pixel group PG3 may include a first sub-pixel group A and a second sub-pixel group B. Each of the first sub-pixel group A and the second sub-pixel group B may include multiple photodiodes PD and pixel circuitry. Each of the first sub-pixel group A and the second sub-pixel group B may include six first photodiodes PD1 and two second photodiodes PD2.

[0323] according to Figure 31In the example embodiment shown, six first photodiodes PD1 can be connected in parallel between the first floating diffusion node FD1 and the reference node. Two second photodiodes PD2 can be connected in parallel between the second floating diffusion node FD2 and the reference node. In this case, the reference node can be a ground node.

[0324] The pixel circuit of each of the first sub-pixel group A and the second sub-pixel group B may include a first floating diffusion node FD1, a second floating diffusion node FD2, a first transmission transistor TX1, a second transmission transistor TX2, a gain control transistor DRX, a reset transistor RX, an amplification transistor SF, a selection transistor SX, a first switching transistor SW1, a second switching transistor SW2, and a capacitor CAP.

[0325] Each of the first sub-pixel group A and the second sub-pixel group B can be similar to the above reference. Figure 16 An example of pixel group PG2 in the described circuit diagram. However, the number of the first photodiode / second photodiode and the first transmission transistor / second transmission transistor may differ. Furthermore, in Figure 31 The difference between each of the first sub-pixel group A and the second sub-pixel group B in the example embodiment shown may be that the sub-pixel group includes a dual-switch transistor (DSW). For example, in each of the first sub-pixel group A and the second sub-pixel group B, the dual-switch transistor DSW may be connected to a first node between the gain control transistor DRX and the reset transistor RX, and the dual-switch transistors DSW in the first sub-pixel group A and the second sub-pixel group B may be connected to each other.

[0326] Reference Figure 31 and Figure 32 The operation of each of the first sub-pixel group A and the second sub-pixel group B can be referenced above. Figure 16 The specific example implementation described is similar.

[0327] In one example embodiment, during the exposure time period EIT between the shutter operation time TSH and the readout time period TRD, the dual-switch control signal DSG input to the gate of the dual-switch transistor DSW can be maintained at a voltage corresponding to logic low. The first sub-pixel group A and the second sub-pixel group B can operate independently. The first sub-pixel group A and the second sub-pixel group B can operate simultaneously or with a predetermined time difference. The operation of each of the first sub-pixel group A and the second sub-pixel group B can be similar to that described above. Figure 16 The specific example embodiment described. The readout circuit connected to column line COL can average the signals of each of the first sub-pixel group A and the second sub-pixel group B, and can generate first pixel signals to third pixel signals.

[0328] In another example embodiment, during the shutter operation time TSH and readout time TRD, the dual-switch control signal DSG input to the gate of the dual-switch transistor DSW can be maintained at a voltage corresponding to a logic high. The first sub-pixel group A and the second sub-pixel group B can operate simultaneously. The operation of each of the first sub-pixel group A and the second sub-pixel group B can be similar to that described above. Figure 16 Specific example implementations described.

[0329] During the readout period TRD, when the dual-switch control signal DSG input to the gate of the dual-switch transistor DSW is held logic high, the first sub-pixel group A and the second sub-pixel group B can share the first floating diffusion region FD1. Therefore, the readout circuit connected to the column line COL can generate reset and voltage signals without computation. For example, a first reset signal and a second voltage signal for the first readout period TRD1, and a reset and voltage signal for the second readout period TRD2, can be generated without computation for the signals of the first sub-pixel group A and the second sub-pixel group B.

[0330] During the readout time period TRD, when the dual-switch control signal DSG input to the gate of the dual-switch transistor DSW is held low, the readout circuit connected to the column line COL can generate a reset signal and a voltage signal by averaging the signals of the first sub-pixel group A and the second sub-pixel group B. For example, a second reset signal and a first voltage signal during the first readout time period TRD1 can be generated by averaging the signals of the first sub-pixel group A and the second sub-pixel group B.

[0331] Reference Figure 33 The layout of the first sub-pixel group A and the layout of the second sub-pixel group B can be symmetrical. However, the example embodiments are not limited to this.

[0332] Referring to the layout of the first sub-pixel group A, each of the plurality of pixel regions may include a photodiode and at least one transistor. In the four pixel regions arranged in a 2×2 structure, the pixel region including the first photodiode PD1 may share the first floating diffusion region FD1. Specific example embodiments may be similar to those described above. Figure 7 The example described in [the document].

[0333] Show Figure 29 and Figure 30 Specific example embodiments of the pixel group PG3 and its operation circuit diagram shown herein can be applied to reference. Figures 2 to 13 Example embodiments of the described pixel group PG1 and / or references Figures 14 to 28 An example embodiment of pixel group PG2 is described. Furthermore, the structure of the pixel array and pixel group is not limited to... Figures 2 to 33 .

[0334] According to the aforementioned example embodiment, by setting a switching transistor in a circuit in which at least one of the multiple photodiodes is connected in parallel with each other and controlling the switching transistor to turn on / off, the number of photodiodes in each of the multiple pixel groups that are actively electrically connected to the capacitor can be controlled during the exposure time period, so that the sensitivity of the readout operation that reads the voltage corresponding to the charge stored in the capacitor can be selectively controlled.

[0335] Although exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure.

Claims

1. An image sensor, comprising: A pixel array, comprising multiple groups of pixels. Each of the plurality of pixel groups includes a plurality of photodiode regions, which are arranged in a first direction and a second direction intersecting the first direction. Each of the plurality of pixel groups includes a plurality of photodiodes and a pixel circuit, wherein the plurality of photodiodes are disposed in the plurality of photodiode regions, and the pixel circuit is configured to output a signal corresponding to a charge generated by at least one of the plurality of photodiodes. The plurality of photodiodes includes primary photodiodes and secondary photodiodes, and The pixel circuit includes: The first floating diffusion node is connected to the first-stage photodiode via a first-stage transmission transistor; The second floating diffusion node is connected to the second-level photodiode via a second-level transmission transistor; A first switching transistor is connected between a first floating diffusion node and a second floating diffusion node; A reset transistor and a gain control transistor are connected in series between the second power supply node and the first floating diffusion node; A capacitor and a second switching transistor are connected in series between the first power node and the second floating diffusion node; An amplifying transistor having a gate connected to a first floating diffusion node and a third power supply node; and Select a transistor and connect it between the amplifying transistor and the column line.

2. The image sensor according to claim 1, in, The plurality of photodiodes includes a plurality of primary photodiodes and a plurality of secondary photodiodes. The plurality of first-stage photodiodes are connected in parallel between the first floating diffusion node and the reference node, and The plurality of secondary photodiodes are connected in parallel between the second floating diffusion node and the reference node.

3. The image sensor according to claim 1, in, The plurality of photodiodes also includes tertiary photodiodes, and The pixel circuit includes a third floating diffusion node and a third switching transistor. The third floating diffusion node is connected to a third-level photodiode through a third-level transmission transistor, and the third switching transistor is connected between the second floating diffusion node and the third floating diffusion node.

4. The image sensor according to claim 3, wherein, The first switching transistor is connected between the first floating diffusion node and the third floating diffusion node.

5. The image sensor according to claim 4, wherein, The plurality of photodiodes includes a plurality of tertiary photodiodes, wherein the plurality of tertiary photodiodes are connected in parallel between the third floating diffusion node and the reference node.

6. The image sensor according to claim 3, wherein, The pixel circuit also includes a fourth switching transistor, which is connected between the first switching transistor and the first floating diffusion node.

7. The image sensor according to claim 1, wherein, The total number of photodiodes in each pixel group is four.

8. The image sensor according to claim 7, wherein, The plurality of photodiodes in each pixel group includes three primary photodiodes and one secondary photodiode.

9. The image sensor according to claim 7, wherein, The plurality of photodiodes in each pixel group include two first-level photodiodes, one second-level photodiode, and one third-level photodiode. The pixel circuit includes a third floating diffusion node and a third switching transistor. The third floating diffusion node is connected to the third-level photodiode through a third-level transmission transistor. The third switching transistor is connected between the second floating diffusion node and the third floating diffusion node.

10. The image sensor according to claim 1, wherein, The total number of photodiodes in each pixel group is nine.

11. The image sensor according to claim 10, wherein, The plurality of photodiodes includes eight primary photodiodes and one secondary photodiode.

12. The image sensor according to claim 10, wherein, The plurality of photodiodes includes four first-level photodiodes, one second-level photodiode, and four third-level photodiodes. The pixel circuit includes a third floating diffusion node and a third switching transistor. The third floating diffusion node is connected to the four third-level photodiodes through four third-level transmission transistors. The third switching transistor is connected between the second floating diffusion node and the third floating diffusion node.

13. The image sensor according to claim 1, in, Each of the plurality of pixel groups includes a first sub-pixel group and a second sub-pixel group, and Each of the first and second sub-pixel groups includes multiple photodiodes and pixel circuits.

14. The image sensor according to claim 13, wherein, The pixel circuit of each of the first and second sub-pixel groups also includes a dual-switching transistor connected to the node between the reset transistor and the gain control transistor, and the dual-switching transistors of each of the first and second sub-pixel groups are connected to each other.

15. The image sensor according to claim 13, wherein, Each of the first and second sub-pixel groups includes six primary photodiodes and two secondary photodiodes.

16. An image sensor, comprising: A pixel array includes multiple pixel groups, each of the multiple pixel groups including multiple photodiode regions, the multiple photodiode regions being arranged in a first direction and a second direction intersecting the first direction; as well as The peripheral circuitry is connected to the plurality of pixel groups via multiple row lines and multiple column lines, and is configured to drive the plurality of pixel groups. Each of the plurality of pixel groups includes a first-stage photodiode, a first-stage photodiode, and a pixel circuit. The pixel circuit connects the first-stage photodiode and the first-stage photodiode to an external circuit. The pixel circuit includes a capacitor configured to store at least a portion of the charge generated by the first and second-order photodiodes during the exposure time period. The peripheral circuitry is configured to: obtain a first pixel signal and a second pixel signal by performing a first readout operation on each of the plurality of pixel groups after the exposure time period; obtain a third pixel signal corresponding to the charge stored in the capacitor by performing a second readout operation; and generate image data using the first pixel signal, the second pixel signal, and the third pixel signal. Wherein, the first pixel signal is the signal output by each of the plurality of pixel groups under high conversion gain conditions, and the second pixel signal is the signal output by each of the plurality of pixel groups under low conversion gain conditions.

17. The image sensor according to claim 16, in, The pixel circuit includes: First floating diffusion node; The first-stage transmission transistor is connected between the first floating diffusion node and the first-stage photodiode; A first switching transistor is connected between a first floating diffusion node and a second floating diffusion node; The second switching transistor and the capacitor are connected to the second floating diffusion node and are connected in series with each other; The first and second stage transmission transistors are connected between the second floating diffusion node and the first and second stage photodiodes; and The gain control transistor is connected to the first floating diffusion node, and The peripheral circuit is configured to turn off the gain control transistor to select a high conversion gain condition, and turn on the gain control transistor to select a low conversion gain condition.

18. The image sensor according to claim 17, in, Each of the plurality of pixel groups further includes a first tertiary photodiode, and The pixel circuit also includes a third floating diffusion node and a third switching transistor. The third floating diffusion node is connected to the first third-level photodiode through the first third-level transmission transistor. The third switching transistor is connected between the second floating diffusion node and the third floating diffusion node, and the first switching transistor is connected between the first floating diffusion node and the third floating diffusion node.

19. The image sensor according to claim 18, in, In the first readout operation, each output of the plurality of pixel groups corresponds to a voltage corresponding to the charge generated by the first-stage photodiode, the first-stage photodiode, and the first-stage photodiode under each of the high-conversion-gain and low-conversion-gain conditions, and In the second readout operation, each output of the plurality of pixel groups corresponds to a voltage corresponding to a charge generated and stored in a capacitor by at least one of the first-level photodiode, the first-level photodiode, and the first-level photodiode.

20. An image sensor, comprising: Multiple pixel groups, each of the multiple pixel groups including multiple photodiode regions, the multiple photodiode regions being arranged in a first direction and a second direction intersecting the first direction; as well as The peripheral circuitry is connected to the plurality of pixel groups via multiple row lines and multiple column lines, and is configured to drive the plurality of pixel groups. Each of the plurality of pixel groups includes a first-stage photodiode, a first-stage photodiode, and a pixel circuit. The pixel circuit connects the first-stage photodiode and the first-stage photodiode to an external circuit. The pixel circuit includes: First floating diffusion node; The first-stage transmission transistor is connected between the first floating diffusion node and the first-stage photodiode; A first switching transistor is connected between a first floating diffusion node and a second floating diffusion node; A second switching transistor and a capacitor are connected in series with each other to a second floating diffusion node; and The first and second stage transmission transistors are connected between the second floating diffusion node and the first and second stage photodiodes, and The capacitor is configured to store at least a portion of the charge generated by the first secondary photodiode during the exposure time period, but not the charge generated by the first primary photodiode.

Images