Photoelectric memory structure and forming method thereof

Abstract

The invention provides a photoelectric memory structure and a forming method thereof, and the photoelectric memory structure comprises a substrate which comprises a top silicon layer, and the top silicon layer is divided into a first region and a second region by an isolation structure; the photoelectric detection unit takes the top silicon layer of the first region as an active region; the storage unit takes the top silicon layer of the second region as an active region; the interlayer dielectric layer is located on the top silicon layer and covers the photoelectric detection unit and the storage unit; and the metal interconnection structure is located in the interlayer dielectric layer and is electrically connected with a second contact region of the photoelectric detection unit and a source electrode of the storage unit. The invention provides a photoelectric memory structure and a forming method thereof. A high-performance photoelectric memory suitable for silicon-based high-density integration can be provided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a photoelectric memory structure and a method for forming the same. Background Technology

[0002] Optoelectronic memory (ODM) is a novel type of storage device that utilizes the interaction of photons and electrons to store and retrieve information, renowned for its high-speed data transmission and large-capacity storage. Compared to traditional electronic memory, ODM boasts faster transmission speeds, higher storage density, and lower power consumption. Furthermore, it features non-volatility, erasability, long lifespan, and interference resistance, making it suitable for large-scale data centers, high-speed communication networks, cloud computing, and other fields. Based on different principles, ODM can be classified into photochromic memories, photocapacitive memories, phase-change memories, and optical memories. Realizing large-scale, high-density, non-volatile memory is of paramount importance.

[0003] Most optoelectronic memories currently used in integrated circuits are made from organic or perovskite materials, which are not suitable for high-density silicon-based integration. Photochromic memories, photocapacitive memories, and optical memories cannot achieve large-scale, high-density optical storage. Phase-change memories, on the other hand, have advantages such as very fast read / write speeds, low power consumption, erasability, and non-volatility, but they are sensitive to temperature and cannot be used in extreme environments.

[0004] Therefore, it is necessary to provide a more efficient and reliable technical solution to provide high-performance optoelectronic memory suitable for silicon-based high-density integration. Summary of the Invention

[0005] This application provides a photoelectric memory structure and a method for forming the same, which can provide a high-performance photoelectric memory suitable for high-density integration on silicon.

[0006] One aspect of this application provides a method for forming a photoelectric memory structure, comprising: providing a substrate including a top silicon layer; forming an isolation structure in the top silicon layer to divide the top silicon layer into a first region and a second region; forming a photodetector unit with the top silicon layer of the first region as an active region and forming a memory unit with the top silicon layer of the second region as an active region; forming an interlayer dielectric layer on the top silicon layer covering the photodetector unit and the memory unit, and forming a metal interconnect structure in the interlayer dielectric layer electrically connecting a second contact region of the photodetector unit and the source of the memory unit.

[0007] In some embodiments of this application, the method of forming a photodetector unit with the top silicon layer of the first region as the active region and forming a memory unit with the top silicon layer of the second region as the active region includes: forming a first doped region and a second doped region in the top silicon layer of the first region and forming a third doped region in the top silicon layer of the second region; forming a memory stack layer on the surface of the top silicon layer of the second region; forming a source and a drain in the top silicon layers on both sides of the memory stack layer; forming a first contact region and a second contact region in the first doped region and the second doped region; forming a trench in the top silicon layer of the first region that spans the first doped region and the second doped region and the first contact region and the second contact region; and forming a germanium absorption layer in the trench with a top surface higher than the surface of the top silicon layer.

[0008] In some embodiments of this application, the first doped region is P-type doped, the second doped region is N-type doped, the third doped region is P-type doped, the first contact region is P-type doped, the second contact region is N-type doped, and the source and drain are N-type doped.

[0009] In some embodiments of this application, the first doped region and the second doped region have the same doping concentration; the first contact region, the second contact region, and the source and drain have the same doping concentration; the doping concentration of the first contact region, the second contact region, and the source and drain is greater than that of the first doped region, the doping concentration of the second doped region is greater than that of the third doped region.

[0010] In some embodiments of this application, a method for forming an interlayer dielectric layer covering the photodetector unit and the memory unit on the top silicon layer and forming a metal interconnect structure in the interlayer dielectric layer that electrically connects the second contact area of ​​the photodetector unit and the source of the memory unit includes: forming a first dielectric layer covering the photodetector unit and the memory unit on the top silicon layer; forming a first opening in the first dielectric layer that exposes the first contact area, the second contact area, the source and the drain, and the memory stack layer; forming a barrier layer on the sidewall of the first opening; forming a second dielectric layer on the surface of the first dielectric layer that fills the first opening, and forming a first contact structure and a second contact structure in the second dielectric layer that electrically connect the first contact area, the second contact area, the source and the drain, and the memory stack layer. The system comprises a third contact structure, a fourth contact structure, and a fifth contact structure; a third dielectric layer is formed on the surface of the second dielectric layer, covering the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure, and a first metal layer electrically connected to the first contact structure, a second metal layer electrically connected to the second contact structure and the third contact structure, a third metal layer electrically connected to the fourth contact structure, and a fourth metal layer electrically connected to the fifth contact structure are formed in the third dielectric layer; the first dielectric layer, the second dielectric layer, and the third dielectric layer constitute the interlayer dielectric layer, and the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure, as well as the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer constitute the metal interconnect structure.

[0011] Another aspect of this application provides a photoelectric memory structure, comprising: a substrate including a top silicon layer, the top silicon layer being divided into a first region and a second region by an isolation structure; a photodetector unit with the top silicon layer of the first region as the active region and a memory unit with the top silicon layer of the second region as the active region; an interlayer dielectric layer located on the top silicon layer covering the photodetector unit and the memory unit; and a metal interconnect structure located in the interlayer dielectric layer electrically connecting a second contact region of the photodetector unit and the source of the memory unit.

[0012] In some embodiments of this application, the photodetector unit includes: a first doped region and a second doped region located in the top silicon layer of the first region; a first contact region and a second contact region located in the first doped region and the second doped region, respectively; a trench located in the top silicon layer of the first region that spans the first doped region and the second doped region, as well as the first contact region and the second contact region; a germanium absorption layer located in the trench with its top surface higher than the surface of the top silicon layer; the memory unit includes: a third doped region located in the top silicon layer of the second region; a memory stack layer located on the surface of the top silicon layer of the second region; and a source and a drain in the top silicon layers located on both sides of the memory stack layer.

[0013] In some embodiments of this application, the first doped region is P-type doped, the second doped region is N-type doped, the third doped region is P-type doped, the first contact region is P-type doped, the second contact region is N-type doped, and the source and drain are N-type doped.

[0014] In some embodiments of this application, the first doped region and the second doped region have the same doping concentration; the first contact region, the second contact region, and the source and drain have the same doping concentration; the doping concentration of the first contact region, the second contact region, and the source and drain is greater than that of the first doped region, the doping concentration of the second doped region is greater than that of the third doped region.

[0015] In some embodiments of this application, the interlayer dielectric layer includes: a first dielectric layer covering the photodetector unit and the memory unit on the top silicon layer, wherein the first dielectric layer has a first opening exposing the first contact area, the second contact area, the source and drain, and the memory stack layer, and a barrier layer is formed on the sidewall of the first opening; a second dielectric layer filling the first opening on the surface of the first dielectric layer, and a first contact structure, a second contact structure, a third contact structure, a fourth contact structure, and a fifth contact structure electrically connected to the first contact area, the second contact area, the source and drain, and the memory stack layer, respectively, located in the second dielectric layer; a third dielectric layer covering the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure on the surface of the second dielectric layer, and a first metal layer electrically connected to the first contact structure, a second metal layer electrically connected to the second contact structure and the third contact structure, a third metal layer electrically connected to the fourth contact structure, and a fourth metal layer electrically connected to the fifth contact structure, respectively, located in the third dielectric layer; the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure, as well as the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer constitute the metal interconnect structure.

[0016] This application provides a photoelectric memory structure and its formation method. Based on flash memory, a novel dynamic photoelectric memory structure is proposed. It utilizes gate voltage to dissociate photogenerated carriers to realize the conversion of optical signals to electrical signals, and designs "NOT gate" logic circuits to realize signal storage. It can provide a high-performance photoelectric memory suitable for silicon-based high-density integration. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 11 This is a schematic diagram of each step in the method for forming the optoelectronic memory structure described in the embodiments of this application;

[0020] Figure 12 This is a schematic diagram of the circuit structure of an optoelectronic memory structure according to an embodiment of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] Figures 1 to 11 This is a schematic diagram of each step in the method for forming the optoelectronic memory structure described in the embodiments of this application.

[0024] refer to Figure 1 As shown, a substrate 100 is provided, the substrate 100 including a top silicon layer 103.

[0025] In some embodiments of this application, the substrate 100 described herein is an SOI substrate, and the substrate 100 includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103. The bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon.

[0026] refer to Figure 2 As shown, an isolation structure 190 is formed in the top silicon layer 103 to divide the top silicon layer 103 into a first region 104 and a second region 105. The first region 104 is used to fabricate a photodetector unit, and the second region 105 is used to fabricate a memory unit.

[0027] refer to Figures 3 to 8 As shown, a photodetector unit 110 is formed with the top silicon layer 103 of the first region 104 as the active region, and a memory unit 120 is formed with the top silicon layer 103 of the second region 105 as the active region. The photodetector unit 110 can be any type of photodetector structure; for example, this application uses a PIN-type germanium photodetector unit as an example.

[0028] refer to Figure 3 As shown, a first doped region 111 and a second doped region 112 located on both sides of the top silicon layer 103 in the first region 104 are respectively formed, and a third doped region 121 is formed in the top silicon layer 103 in the second region 105.

[0029] In some embodiments of this application, the first doped region 111 is P-type doped, the second doped region 112 is N-type doped, and the third doped region 121 is P-type doped. The first doped region 111, the top silicon layer 103, and the second doped region 112 in the first region 104 constitute a PIN structure. The third doped region 121 in the second region 105 serves as a well region.

[0030] In some embodiments of this application, the first doped region 111 and the second doped region 112 have the same doping concentration, for example, 1E13-1E14 / cm². 2 The doping concentration of the third doped region 121 is less than that of the first doped region 111 and the second doped region 113, for example, 1E12-1E13 / cm². 2 .

[0031] In some embodiments of this application, the method for forming the first doped region 111, the second doped region 112, and the third doped region 113 is, for example, an ion implantation process. The first doped region 111 and the third doped region 1121, which have the same doping type, can undergo ion implantation simultaneously.

[0032] refer to Figure 4As shown, a memory stack layer 122 is formed on the surface of the top silicon layer 103 in the second region 105. Taking a flash memory cell as an example, the memory stack layer 122 may include a floating gate dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate, and sidewalls located on the sidewalls of the floating gate dielectric layer, the floating gate layer, the inter-gate dielectric layer, and the control gate, stacked sequentially. The memory stack layer 122 is the gate stack layer of a flash memory structure. In other embodiments, the memory cell may be any other suitable type of memory.

[0033] refer to Figure 5 As shown, source 123 and drain 124 are formed in the top silicon layers 103 on both sides of the memory stack 122, respectively. The third doped region 121, memory stack 122, source 123 and drain 124 constitute the memory cell 120. The source 123 and drain 124 are further extended below the memory stack 122 after annealing.

[0034] In some embodiments of this application, the source 123 and drain 124 are N-type doped.

[0035] refer to Figure 6 As shown, a first contact region 114 and a second contact region 115 are formed in the first doped region 111 and the second doped region 112, respectively.

[0036] In some embodiments of this application, the first contact region 114 is P-type doped and the second contact region 115 is N-type doped.

[0037] In some embodiments of this application, the first contact region 114, the second contact region 115, and the source 123 and drain 124 have the same doping concentration, for example, 1E14-1E15 / cm. 2 .

[0038] In some embodiments of this application, the doping concentrations of the first contact region 114, the second contact region 115, the source 123, and the drain 124 are greater than the doping concentrations of the first doped region 111, the second doped region 112, and the third doped region 121.

[0039] refer to Figure 7 As shown, a trench 130 is formed in the top silicon layer 103 of the first region 104, spanning the first doped region 111 and the second doped region 112, as well as the first contact region 114 and the second contact region 115.

[0040] refer to Figure 8As shown, a germanium absorption layer 113 with its top surface higher than the surface of the top silicon layer 103 is formed in the trench 130. The first doped region 111, the second doped region 112, the germanium absorption layer 113, the first contact region 114, and the second contact region 115 constitute the photodetector unit 110.

[0041] In some embodiments of this application, the top surface of the germanium absorber layer 113 is flush with the top surface of the memory stack layer 122.

[0042] In some embodiments of this application, the method for forming the germanium absorber layer 113 includes an epitaxial growth process.

[0043] refer to Figures 9 to 11 As shown, an interlayer dielectric layer 140 is formed on the top silicon layer 103, covering the photodetector unit 110 and the storage unit 120, and a metal interconnect structure 150 is formed in the interlayer dielectric layer 140 to electrically connect the second contact area 115 of the photodetector unit 110 and the source electrode 123 of the storage unit 120.

[0044] refer to Figure 9 As shown, a first dielectric layer 141 covering the photodetector unit 110 and the memory unit 120 is formed on the top silicon layer 103. The material of the first dielectric layer 141 is, for example, silicon oxide.

[0045] Embodiments of this application further include: forming first openings in the first dielectric layer 141 to expose the first contact area 114, the second contact area 115, the source 123, the drain 124, and the memory stack layer 122, respectively; forming metal silicides on the surfaces of the first contact area 114, the second contact area 115, the source 123, the drain 124, and the memory stack layer 122 exposed by the first openings; and forming a barrier layer on the sidewall of the first opening. For simplicity, the first opening, the metal silicide, and the barrier layer are omitted in the accompanying drawings of the embodiments of this application. The barrier layer is used to form a self-aligned structure, so that the first contact area 114, the second contact area 115, the source 123, the drain 124, and the memory stack layer 122 exposed by the first opening can be accurately aligned when the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure are subsequently formed.

[0046] refer to Figure 10As shown, a second dielectric layer 142 is formed on the surface of the first dielectric layer 141 to fill the first opening, and a first contact structure 151, a second contact structure 152, a third contact structure 153, a fourth contact structure 154 and a fifth contact structure 158 are formed in the second dielectric layer 142 to electrically connect the first contact area 114, the second contact area 115, the source 123 and the drain 124 and the memory stack layer 122, respectively.

[0047] refer to Figure 11 As shown, a third dielectric layer 143 is formed on the surface of the second dielectric layer 142, covering the first contact structure 151, the second contact structure 152, the third contact structure 153, the fourth contact structure 154, and the fifth contact structure 158. In the third dielectric layer 143, a first metal layer 155 electrically connected to the first contact structure 151, a second metal layer 156 electrically connected to the second contact structure 152 and the third contact structure 153, a third metal layer 157 electrically connected to the fourth contact structure 154, and a fourth metal layer 159 electrically connected to the fifth contact structure 158 are formed respectively.

[0048] The first dielectric layer 141, the second dielectric layer 142, and the third dielectric layer 143 constitute the interlayer dielectric layer 140, and the first contact structure 151, the second contact structure 152, the third contact structure 153, the fourth contact structure 154, and the fifth contact structure 158, as well as the first metal layer 155, the second metal layer 156, the third metal layer 157, and the fourth metal layer 159 constitute the metal interconnect structure 150.

[0049] refer to Figure 11 As shown, the technical solution of this application connects the opto-memory 110 and the storage unit 120 in series. Using flash memory as the basic framework, a novel dynamic opto-memory structure is designed. The optical signal is converted into an electrical signal by dissociating photogenerated carriers using gate voltage, and a NOT gate logic circuit is designed to store the signal. This can provide a high-performance opto-memory suitable for high-density integration on silicon.

[0050] Figure 12 This is a schematic diagram of the circuit structure of an optoelectronic memory structure according to an embodiment of this application.

[0051] refer to Figure 12 As shown, the circuit structure of the optoelectronic memory structure described in this application includes: a photodetector module and an optical storage module. The photodetector module includes at least one set of photodetector units 110 and storage units 120 as described above. The optical storage module includes a plurality of transistors connected in series.

[0052] Combination Figure 11 and Figure 12As shown, the working principle of the optoelectronic memory structure described in this application is as follows: First, a programming source-drain voltage is applied between the first metal layer 155 electrically connecting the first contact area 114 and the second metal layer 156 and the third metal layer 157 electrically connecting the second contact area 115 and the source 123 and the drain 124. A programming gate voltage is applied between the fourth metal layer 159 electrically connecting the memory stack layer 122 and the bottom silicon layer 101. At this time, due to the presence of the forward conduction voltage of the PN diode in the first region, the electric field between the source and drain of the memory transistor in the second region is insufficient, and hot carriers cannot be generated. Therefore, the memory transistor is not programmed. When the optical signal enters the germanium absorption layer 113 in the first region through the optical fiber structure, the forward conduction voltage of the PN diode in the first region will decrease. This causes hot carriers to be generated between the source and drain of the memory transistor. The hot carriers generated near the drain will enter the floating gate of the memory through tunneling and other means. The memory transistor is programmed, and the recording of the optical signal is completed. By connecting multiple memory cells in series and applying voltage, other bit cells are programmed, thus transferring signals to other bit cells. Subsequently, by applying a reverse voltage to the gate, electrons entering the floating gate are allowed to enter the substrate of the third doped region, completing the erasure. The above-mentioned memory signal transfer, programming, and erasure principles are common knowledge and are already widely used in memory, so they will not be elaborated further.

[0053] The technical solution of this application provides a novel dynamic optoelectronic memory structure. It utilizes the absorption of light by the PN junction formed by the first doped region 111 and the second doped region 112 in the top silicon layer 103 of the photodetector unit 110 to generate photogenerated carriers. The photodetector unit 110 is connected in series with the memory unit 120. The device switching is controlled by light to control the hot carrier injection of the flash memory device, thereby recording the optical signal.

[0054] The technical solution of this application provides a photoelectric memory circuit structure including a photodetector module and a photoelectric storage module. Based on the silicon photonics fabrication process, the flash memory device storage cell 120 is inserted into the active region and interconnected with the photodetector module (photodetector unit 110). It can detect the intensity of the light signal at different positions and store the signal on different word lines, which can be used to reproduce the dynamic intensity of the incident light.

[0055] The technical solution of this application designs a logic circuit that connects a flash memory for recording optical signals in series with other memories. After the optical signal is recorded in the memory of the optical detection module, the bit to be stored is put into a programming state. An elevated threshold voltage is applied to the stored bit, and a standard voltage is applied to other devices. The "NOT gate" logic is realized by using principles such as hot carrier injection.

[0056] The technical solution of this application only uses a series circuit as an example to illustrate the dynamic function of the optoelectronic storage device. Alternatively, the one-to-one signal transfer between the flash memory that records the optical signal and the bit to be stored can be achieved by controlling the short-circuit state of the series bits in sequence.

[0057] This application provides a method for forming an optoelectronic memory structure. Using flash memory as the basic framework, a novel dynamic optoelectronic memory structure is proposed. The structure utilizes gate voltage to dissociate photogenerated carriers to realize the conversion of optical signals into electrical signals, and designs "NOT gate" logic circuits to realize signal storage. This can provide a high-performance optoelectronic memory suitable for silicon-based high-density integration.

[0058] This application also provides a photoelectric memory structure, see reference. Figure 11 As shown, the system includes: a substrate 100, the substrate 100 including a top silicon layer 103, the top silicon layer 103 being divided into a first region 104 and a second region 105 by an isolation structure 190; a photodetector unit 110 with the top silicon layer 103 of the first region 104 as the active region and a memory unit 120 with the top silicon layer 103 of the second region 105 as the active region; an interlayer dielectric layer 140 located on the top silicon layer 103 covering the photodetector unit 110 and the memory unit 120; and a metal interconnect structure 150 located in the interlayer dielectric layer 140 electrically connecting a second contact region 115 of the photodetector unit 110 and a source electrode 123 of the memory unit 120.

[0059] In some embodiments of this application, the substrate 100 described herein is an SOI substrate, and the substrate 100 includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103. The bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon.

[0060] Continue to refer to Figure 11 As shown, the photodetector unit 110 includes: a first doped region 111 and a second doped region 112 located in the top silicon layer 103 of the first region 104; a first contact region 114 and a second contact region 115 located in the first doped region 111 and the second doped region 112, respectively; a trench located in the top silicon layer 103 of the first region 104 spanning the first doped region 111 and the second doped region 112 and the first contact region 114 and the second contact region 115; and a germanium absorption layer 113 located in the trench with its top surface higher than the surface of the top silicon layer 103.

[0061] Continue to refer to Figure 11As shown, the memory cell 120 includes: a third doped region 121 located in the top silicon layer 103 of the second region 105; a memory stack layer 122 located on the surface of the top silicon layer 103 of the second region 105; and a source 123 and a drain 124 located in the top silicon layer 103 on both sides of the memory stack layer 122.

[0062] In some embodiments of this application, taking a flash memory cell as an example, the memory stack layer 122 may include a floating gate dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate, and sidewalls located on the sidewalls of the floating gate dielectric layer, the floating gate layer, the inter-gate dielectric layer, and the control gate, stacked sequentially.

[0063] In some embodiments of this application, the first doped region 111 is P-type doped, the second doped region 112 is N-type doped, and the third doped region 121 is P-type doped. The first doped region 111, the top silicon layer 103, and the second doped region 112 in the first region 104 constitute a PIN structure. The third doped region 121 in the second region 105 serves as a well region.

[0064] In some embodiments of this application, the first doped region 111 and the second doped region 112 have the same doping concentration, for example, 1E13-1E14 / cm². 2 The doping concentration of the third doped region 113 is less than that of the first doped region 111 and the second doped region 113, for example, 1E12-1E13 / cm². 2 .

[0065] In some embodiments of this application, the source 123 and drain 124 are N-type doped.

[0066] In some embodiments of this application, the top surface of the germanium absorber layer 113 is flush with the top surface of the memory stack layer 122.

[0067] In some embodiments of this application, the first contact region 114 is P-type doped and the second contact region 115 is N-type doped.

[0068] In some embodiments of this application, the first contact region 114, the second contact region 115, and the source 123 and drain 124 have the same doping concentration, for example, 1E14-1E15 / cm. 2 .

[0069] In some embodiments of this application, the doping concentrations of the first contact region 114, the second contact region 115, the source 123, and the drain 124 are greater than the doping concentrations of the first doped region 111, the second doped region 112, and the third doped region 121.

[0070] Continue to refer to Figure 11 As shown, in some embodiments of this application, the interlayer dielectric layer 140 includes: a first dielectric layer 141 located on the top silicon layer 103 covering the photodetector unit 110 and the memory unit 120, wherein the first dielectric layer 141 has first openings formed in the first dielectric layer 141 exposing the first contact area 114, the second contact area 115, the source 123 and the drain 124 and the memory stack layer 122, and the sidewalls of the first openings are formed with barrier layers; a second dielectric layer 142 located on the surface of the first dielectric layer 141 filling the first openings; and a first contact structure 151, a second contact structure 152, a third contact structure 153, a fourth contact structure 154 and a fifth contact structure 158 located in the second dielectric layer 142 electrically connecting the first contact area 114, the second contact area 115, the source 123 and the drain 124 and the memory stack layer 122, respectively; and the first contact structure 142 located on the surface of the first dielectric layer 141 filling the first openings; and a first contact structure 151, a second contact structure 152, a third contact structure 153, a fourth contact structure 154 and a fifth contact structure 158 located in the second dielectric layer 142 electrically connecting the first contact area 114, the second contact area 115, the source 123 and the drain 124 and the memory stack layer 122, respectively. The surface of the second dielectric layer 142 covers the first contact structure 151, the second contact structure 152, the third contact structure 153, the fourth contact structure 154, and the fifth contact structure 158. A first metal layer 155, a second metal layer 156, a third metal layer 157, and a fourth metal layer 159 are located in the third dielectric layer 143 and electrically connected to the first contact structure 151, the second contact structure 152, and the third contact structure 153, respectively; the first contact structure 151, the second contact structure 152, the third contact structure 153, the fourth contact structure 154, and the fifth contact structure 158, along with the first metal layer 155, the second metal layer 156, the third metal layer 157, and the fourth metal layer 159, constitute the metal interconnect structure 150.

[0071] For the sake of brevity, the first opening, metal silicide, and barrier layer are omitted in the accompanying drawings of this application embodiment. The barrier layer is used to form a self-aligned structure, so that the first contact area 114, the second contact area 115, the source 123 and the drain 124, and the memory stack layer 122 exposed by the first opening can be accurately aligned when the first contact structure, the second contact structure, the third contact structure and the fourth contact structure are subsequently formed.

[0072] Continue to refer to Figure 11 As shown, the technical solution of this application connects the opto-memory 110 and the storage unit 120 in series. Using flash memory as the basic framework, a novel dynamic opto-memory structure is designed. The optical signal is converted into an electrical signal by dissociating photogenerated carriers using gate voltage, and a NOT gate logic circuit is designed to store the signal. This can provide a high-performance opto-memory suitable for high-density integration on silicon.

[0073] refer to Figure 12 As shown, the circuit structure of the optoelectronic memory structure described in this application includes: a photodetector module and an optical storage module. The photodetector module includes at least one set of photodetector units 110 and storage units 120 as described above. The optical storage module includes a plurality of transistors connected in series.

[0074] The technical solution of this application provides a novel dynamic optoelectronic memory structure. It utilizes the absorption of light by the PN junction formed by the first doped region 111 and the second doped region 112 in the top silicon layer 103 of the photodetector unit 110 to generate photogenerated carriers. The photodetector unit 110 is connected in series with the memory unit 120. The device switching is controlled by light to control the hot carrier injection of the flash memory device, thereby recording the optical signal.

[0075] The technical solution of this application provides a photoelectric memory circuit structure including a photodetector module and a photoelectric storage module. Based on the silicon photonics fabrication process, the flash memory device storage cell 120 is inserted into the active region and interconnected with the photodetector module (photodetector unit 110). It can detect the intensity of the light signal at different positions and store the signal on different word lines, which can be used to reproduce the dynamic intensity of the incident light.

[0076] The technical solution of this application designs a logic circuit that connects a flash memory for recording optical signals in series with other memories. After the optical signal is recorded in the memory of the optical detection module, the bit to be stored is put into a programming state. An elevated threshold voltage is applied to the stored bit, and a standard voltage is applied to other devices. The "NOT gate" logic is realized by using principles such as hot carrier injection.

[0077] The technical solution of this application only uses a series circuit as an example to illustrate the dynamic function of the optoelectronic storage device. Alternatively, the one-to-one signal transfer between the flash memory that records the optical signal and the bit to be stored can be achieved by controlling the short-circuit state of the series bits in sequence.

[0078] This application provides a photoelectric memory structure and its formation method. Based on flash memory, a novel dynamic photoelectric memory structure is proposed. It utilizes gate voltage to dissociate photogenerated carriers to realize the conversion of optical signals to electrical signals, and designs "NOT gate" logic circuits to realize signal storage. It can provide a high-performance photoelectric memory suitable for silicon-based high-density integration.

[0079] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0080] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0081] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0082] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0083] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a photoelectric memory structure, characterized in that, include: A substrate is provided, the substrate including a top silicon layer; An isolation structure is formed in the top silicon layer to divide the top silicon layer into a first region and a second region; A photodetector unit is formed using the top silicon layer of the first region as the active region, and a memory unit is formed using the top silicon layer of the second region as the active region. An interlayer dielectric layer is formed on the top silicon layer, covering the photodetector unit and the memory unit, and a metal interconnect structure is formed in the interlayer dielectric layer to electrically connect the second contact area of ​​the photodetector unit and the source of the memory unit.

2. The method for forming the optoelectronic memory structure as described in claim 1, characterized in that, The method for forming a photodetector unit using the top silicon layer of the first region as the active region and a memory unit using the top silicon layer of the second region as the active region includes: A first doped region and a second doped region are formed in the top silicon layer of the first region, and a third doped region is formed in the top silicon layer of the second region; A memory stack layer is formed on the surface of the top silicon layer in the second region; The source and drain are formed in the top silicon layers on both sides of the memory stack layer, respectively; A first contact region and a second contact region are formed in the first doped region and the second doped region, respectively; A trench is formed in the top silicon layer of the first region, spanning the first doped region and the second doped region, as well as the first contact region and the second contact region. A germanium absorber layer is formed in the trench with its top surface higher than the surface of the top silicon layer.

3. The method for forming the optoelectronic memory structure as described in claim 2, characterized in that, The first doped region is P-type doped, the second doped region is N-type doped, the third doped region is P-type doped, the first contact region is P-type doped, the second contact region is N-type doped, and the source and drain are N-type doped.

4. The method for forming the optoelectronic memory structure as described in claim 3, characterized in that, The first doped region and the second doped region have the same doping concentration; the first contact region, the second contact region, and the source and drain have the same doping concentration; the first contact region, the second contact region, and the source and drain have a higher doping concentration than the first doped region, the second doped region has a higher doping concentration than the third doped region.

5. The method for forming the optoelectronic memory structure as described in claim 2, characterized in that, A method for forming an interlayer dielectric layer covering the photodetector unit and the memory unit on the top silicon layer, and forming a metal interconnect structure in the interlayer dielectric layer that electrically connects the second contact region of the photodetector unit and the source of the memory unit, includes: A first dielectric layer covering the photodetector unit and the memory unit is formed on the top silicon layer; First openings are formed in the first dielectric layer to expose the first contact area, the second contact area, the source and the drain, and the memory stack layer, respectively. A barrier layer is formed on the sidewall of the first opening; A second dielectric layer is formed on the surface of the first dielectric layer to fill the first opening, and a first contact structure, a second contact structure, a third contact structure, a fourth contact structure and a fifth contact structure are formed in the second dielectric layer to electrically connect the first contact area, the second contact area, the source and the drain, and the memory stack layer, respectively. A third dielectric layer is formed on the surface of the second dielectric layer, covering the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure. A first metal layer electrically connected to the first contact structure, a second metal layer electrically connected to the second contact structure and the third contact structure, a third metal layer electrically connected to the fourth contact structure, and a fourth metal layer electrically connected to the fifth contact structure are formed in the third dielectric layer. The first dielectric layer, the second dielectric layer, and the third dielectric layer constitute the interlayer dielectric layer, and the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure, as well as the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer constitute the metal interconnect structure.

6. A photoelectric memory structure, characterized in that, include: A substrate, the substrate including a top silicon layer, the top silicon layer being divided into a first region and a second region by an isolation structure; A photodetector unit with the top silicon layer of the first region as the active region and a memory unit with the top silicon layer of the second region as the active region; An interlayer dielectric layer covering the photodetector unit and the memory unit is located on the top silicon layer, and a metal interconnect structure in the interlayer dielectric layer electrically connects the second contact area of ​​the photodetector unit and the source of the memory unit.

7. The optoelectronic memory structure as described in claim 6, characterized in that, The photodetector unit includes: a first doped region and a second doped region located in the top silicon layer of the first region; a first contact region and a second contact region located in the first doped region and the second doped region, respectively; a trench located in the top silicon layer of the first region that spans the first doped region and the second doped region as well as the first contact region and the second contact region; and a germanium absorption layer located in the trench with its top surface higher than the surface of the top silicon layer. The memory cell includes: a third doped region in the top silicon layer of the second region; a memory stack layer on the surface of the top silicon layer of the second region; and source and drain electrodes in the top silicon layers on both sides of the memory stack layer.

8. The optoelectronic memory structure as described in claim 7, characterized in that, The first doped region is P-type doped, the second doped region is N-type doped, the third doped region is P-type doped, the first contact region is P-type doped, the second contact region is N-type doped, and the source and drain are N-type doped.

9. The optoelectronic memory structure as described in claim 8, characterized in that, The first doped region and the second doped region have the same doping concentration; the first contact region, the second contact region, and the source and drain have the same doping concentration; the first contact region, the second contact region, and the source and drain have a higher doping concentration than the first doped region, the second doped region has a higher doping concentration than the third doped region.

10. The optoelectronic memory structure as described in claim 7, characterized in that, The interlayer dielectric layer includes: a first dielectric layer covering the photodetector unit and the memory unit on the top silicon layer, wherein the first dielectric layer has a first opening exposing the first contact area, the second contact area, the source and drain, and the memory stack layer, and a barrier layer is formed on the sidewall of the first opening; a second dielectric layer filling the first opening on the surface of the first dielectric layer, and a first contact structure, a second contact structure, a third contact structure, a fourth contact structure, and a fifth contact structure electrically connected to the first contact area, the second contact area, the source and drain, and the memory stack layer in the second dielectric layer; a third dielectric layer covering the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure on the surface of the second dielectric layer, and a first metal layer electrically connected to the first contact structure, a second metal layer electrically connected to the second contact structure and the third contact structure, a third metal layer electrically connected to the fourth contact structure, and a fourth metal layer electrically connected to the fifth contact structure in the third dielectric layer; the first contact structure, the second contact structure, the third contact structure, the fourth contact structure, and the fifth contact structure, as well as the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer constitute the metal interconnect structure.

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