Wafer and wafer polishing surface scratch prediction method

Abstract

A wafer and a wafer grinding surface scratch prediction method are disclosed. The wafer has a ground top surface that can be used to obtain a plurality of detection points by topography measurement. The top surface has a plurality of annular sub-regions positioned within a range of 20% to 54% of its radius, and among the plurality of detection points corresponding to each of the annular sub-regions, the difference between the maximum value and the minimum value is defined as a sub-region total thickness deviation value. Among two of the annular sub-regions adjacent to the center of the top surface, the sub-region total thickness deviation value of one of the annular sub-regions close to the central region is greater than the other sub-region total thickness deviation value. Among any two of the annular sub-regions, the difference between the two sub-region total thickness deviation values is less than 0.5 microns. Thus, through the scratch prediction of the wafer, it can be assessed in real time whether continuous processing is likely to cause scratches.

Description

Technical Field

[0001] This invention relates to a wafer, and more particularly to a wafer and a method for predicting scratches on the polished surface of a wafer that facilitates scratch prediction. Background Technology

[0002] After a wafer undergoes a grinding and thinning process using a machine, the surface scratches are inconsistent, hindering subsequent adjustments to the machine. In other words, during the existing wafer grinding and thinning process, there is no mechanism to assess in real-time whether scratches might occur. Therefore, the inventors believed that this deficiency could be improved, and through dedicated research and the application of scientific principles, finally proposed an invention with a rational design that effectively addresses these shortcomings. Summary of the Invention

[0003] The present invention provides a wafer and a method for predicting scratches on the wafer grinding surface, which can effectively improve the defects that may occur in the existing wafer grinding and thinning process.

[0004] An embodiment of the present invention discloses a wafer comprising: an annular portion; and a processing portion connected within the annular portion, the processing portion having a ground top surface and a bottom surface opposite the top surface; wherein the top surface of the processing portion defines a center and a radius, and the top surface can be used to obtain multiple detection points by topography measurement; wherein the top surface has: a central region comprising a range within 20% of the radius of the top surface relative to the center; wherein, among the multiple detection points corresponding to the central region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the central region; a discrimination region, which is annular and surrounds the central region, and the discrimination region comprises a range within 20% to 54% of the radius of the top surface relative to the center; wherein the discrimination region comprises N annular sub-regions arranged in a direction away from the central region, where N is a positive integer greater than 1. The following parameters are considered: a total thickness deviation value for a sub-region; a chip removal region, which is annular and surrounds the discrimination region; wherein, among the multiple detection points corresponding to the chip removal region, the difference between the maximum and minimum values ​​is defined as the total thickness deviation value for the chip removal region; an edge region, which is annular and surrounds the chip removal region; wherein, among the multiple detection points corresponding to the edge region, the difference between the maximum and minimum values ​​is defined as the total thickness deviation value for the edge region; wherein, among two annular sub-regions adjacent to the central region, the total thickness deviation value of the sub-region closer to the central region is greater than or equal to the total thickness deviation value of the sub-region farther from the central region; wherein, in any two annular sub-regions, the difference between the total thickness deviation values ​​of the two sub-regions is less than 0.5 micrometers.

[0005] Optionally, the chip removal area includes the range of 54% to 72% of the radius of the top surface relative to the center; the edge area includes the range of 72% to 100% of the radius of the top surface relative to the center; the total thickness deviation of the edge area is greater than the total thickness deviation of the central area and is between 2.5 micrometers and 4.5 micrometers, the total thickness deviation of the central area is greater than the total thickness deviation of any sub-area and less than 2.2 micrometers, and the total thickness deviation of any sub-area is greater than the total thickness deviation of the chip removal area.

[0006] Optionally, the width of any one annular subregion is 60% to 155% of the width of another annular subregion.

[0007] Optionally, the total thickness deviation of the N sub-regions remains constant or gradually decreases in the direction away from the central region.

[0008] Optionally, multiple detection points are obtained by topographic measurement along one of the radii on the top surface, and the number of such points is not less than 150.

[0009] Optionally, the number of multiple detection points corresponding to the central area, the discrimination area, the chip removal area, and the edge area shall not be less than 25.

[0010] An embodiment of the present invention also discloses a method for predicting surface scratches on a wafer, comprising: a preliminary step: providing a wafer having an annular portion and a processing portion connected within the annular portion; wherein the processing portion has a polished top surface, which defines a center and a radius; wherein the top surface has: a central region, which includes a range within 20% of the radius of the top surface relative to the center; a discrimination region, which is annular and surrounds the central region, and the discrimination region includes a range from 20% to 54% of the radius of the top surface relative to the center; wherein the discrimination region includes N annular sub-regions arranged in a direction away from the central region, where N is a positive integer greater than 1; a chip removal region, which is annular and surrounds the discrimination region; and an edge region, which is annular and surrounds the chip removal region; a measurement step: obtaining multiple detection points on the top surface of the wafer using a morphology measurement instrument; wherein, among the multiple detection points corresponding to the central region, the maximum value is... The difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the central region; wherein, among the multiple detection points corresponding to each annular sub-region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the sub-region; wherein, among the multiple detection points corresponding to the chip removal region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the chip removal region; wherein, among the multiple detection points corresponding to the edge region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the edge region; a prediction step: when any one of the multiple prediction conditions cannot be met, it is determined that the top surface of the wafer has scratches; wherein, the multiple prediction conditions include: (1) among the two annular sub-regions adjacent to the central region, the total thickness deviation value of the sub-region of the annular sub-region closer to the central region is greater than or equal to the total thickness deviation value of the sub-region of the other annular sub-region farther from the central region; (2) in any two annular sub-regions, the difference between the total thickness deviation values ​​of the two sub-regions is less than 0.5 micrometers.

[0011] Optionally, in the prediction step, multiple prediction conditions further include: (3) the total thickness deviation value of the edge area is greater than the total thickness deviation value of the central area and is between 2.5 micrometers and 4.5 micrometers; (4) the total thickness deviation value of the central area is greater than the total thickness deviation value of any sub-region and less than 2.2 micrometers; (5) the total thickness deviation value of any sub-region is greater than the total thickness deviation value of the chip removal area.

[0012] Optionally, in the measurement step, multiple detection points are obtained by topographic measurement along one of the radii on the top surface, and the number of such points is not less than 150. The number of multiple detection points corresponding to the central region, the discrimination region, the chip removal region, and the edge region is not less than 25. Among them, any two adjacent detection points are separated by a distance of less than 300 micrometers.

[0013] Optionally, the width of any one annular subregion is 60% to 155% of the width of another annular subregion.

[0014] In summary, the wafer and wafer grinding surface scratch prediction method disclosed in the embodiments of the present invention can predict scratches under corresponding conditions by using specific parts of the wafer (such as the two annular sub-regions). This allows for real-time assessment of whether continuous processing is likely to cause scratches during the wafer grinding and thinning process, thereby facilitating the maintenance of the stability of the grinding and thinning process by adjusting the grinding machine (i.e., the scratch rate of the wafer can be effectively reduced).

[0015] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the steps in the wafer grinding surface scratch prediction method according to an embodiment of the present invention.

[0017] Figure 2 for Figure 1 A diagram illustrating the preliminary steps.

[0018] Figure 3 for Figure 1 A schematic diagram of the measurement steps.

[0019] Figure 4 for Figure 1 A schematic diagram of the prediction steps (I).

[0020] Figure 5 for Figure 1 Schematic diagram of the prediction steps (II). Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the "wafer and wafer grinding surface scratch prediction method" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0022] It should be understood that while terms such as “first,” “second,” and “third” may be used in this document to describe various elements or features, these elements or features should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one feature from another. Furthermore, the term “or” as used herein may, depending on the context, include any combination of one or more of the related listed items.

[0023] Please see Figures 1 to 5 As shown, this is an embodiment of the present invention. This embodiment discloses a wafer 100 and a method S100 for predicting surface scratches during wafer grinding. Preferably, the wafer 100 refers to a good product after implementing the method S100, but the present invention is not limited thereto. To facilitate understanding of this embodiment, the method S100 for predicting surface scratches during wafer grinding will be described first, followed by an explanation of the structure and conditions of the wafer 100.

[0024] The wafer grinding surface scratch prediction method S100 in this embodiment includes: a pre-step S110, a measurement step S130, and a prediction step S150. The following content will describe the specific implementation of each step of the wafer grinding surface scratch prediction method S100 in turn.

[0025] The preceding step S110: as follows Figure 1 and Figure 2 As shown, a wafer 100 is provided, having an annular portion 2 and a processing portion 1 connected within the annular portion 2. In this embodiment, the annular portion 2 is annular, and the processing portion 1 is circular, and the processing portion 1 has a ground top surface 11 and a bottom surface 12 opposite to the top surface 11, wherein the top surface 11 defines a center C and a radius R.

[0026] It should be noted that the wafer 100 has already undergone a grinding and thinning process using a grinding machine (not shown in the figure) in the preceding step S110, and the specific implementation of the grinding and thinning process can be adjusted and varied according to actual needs, and the present invention does not limit it. For example, the grinding and thinning process can be a Taiko thinning process, and the wafer 100 can have a W-shaped geometric shape on the top surface 11 after the grinding and thinning process, so as to reduce the proportion of grinding scratches that the top surface 11 may suffer.

[0027] Furthermore, in this embodiment, the top surface 11 of the processing portion 1 has a central region 111, a discriminant region 112 that is annular and surrounds the central region 111, a chip removal region 113 that is annular and surrounds the discriminant region 112, and an edge region 114 that is annular and surrounds the chip removal region 113. The central region 111 is circular, while the discriminant region 112, the chip removal region 113, and the edge region 114 are sequentially arranged outwards from the central region 111 and are all annular. The outer periphery of the edge region 114 is connected to the annular portion 2.

[0028] More specifically, the central region 111 encompasses the area within 20% of the radius R of the top surface 11 relative to the center C; the discrimination region 112 encompasses the area within 20% to 54% of the radius R of the top surface 11 relative to the center C; the chip removal region 113 encompasses the area within 54% to 72% of the radius R of the top surface 11 relative to the center C; and the edge region 114 encompasses the area within 72% to 100% of the radius R of the top surface 11 relative to the center C. However, the invention is not limited thereto. For example, in other embodiments of the invention not shown, the division of the chip removal region 113 and / or the edge region 114 may be adjusted and varied according to actual needs.

[0029] Furthermore, the discrimination region 112 includes N annular sub-regions 112a and 112b, which are arranged sequentially and connected in a direction away from the central region 111, where N is a positive integer greater than 1. The N annular sub-regions 112a and 112b may have the same or different widths W1 and W2, and the width W1 and W2 of any one annular sub-region 112a or 112b is preferably 60% to 155% of the width W1 and W2 of the other annular sub-region 112a or 112b. In this embodiment, N is represented by 2, but the invention is not limited thereto. For example, in other embodiments not shown in this invention, N can be adjusted to a positive integer greater than 2 according to actual needs.

[0030] Furthermore, when N is 2, the ratio of widths W1 and W2 can be 2 / 3 (66.7%) or 3 / 2 (150%). As long as the ratio falls within the preset range of 60% to 155%, it will help in predicting scratches. Conversely, when the ratio of widths W1 and W2 is 1 / 4 (25%), this ratio falls outside the preset range. Therefore, the difference between the two obtained ranges may be too large, resulting in insignificant changes or even distortion, thus causing the risk of incorrect prediction. In other words, when N is 3 or more, the ratio of widths W1 and W2 of the two widest and narrowest annular sub-regions 112a and 112b in the discrimination area 112 must fall within the preset range of 60% to 155% to effectively avoid the aforementioned problem of incorrect prediction.

[0031] The measurement step S130: as follows: Figure 1 and Figure 3 As shown, multiple detection points P are obtained on the top surface 11 of the wafer 100 using a topography measuring instrument (not shown). The topography measuring instrument may be, for example, an optical surface measuring instrument manufactured by FRT (Fries Research & Technology GmbH) in Germany, but the present invention is not limited thereto.

[0032] Furthermore, the number of the plurality of detection points P can be adjusted and varied according to actual needs (e.g., different sizes of the wafer 100 or different requirements for measurement accuracy). In this embodiment, the plurality of detection points P are preferably obtained by topographic measurement along one of the radius R on the top surface 11 (e.g., along one of the radius R perpendicular to the flat edge 13 of the wafer 100), and the number of such points is not less than 150. The number of the plurality of detection points P corresponding to the central region 111, the discrimination region 112, the chip removal region 113, and the edge region 114 is not less than 25, but the present invention is not limited thereto. It should be further noted that any two adjacent detection points P are preferably separated by a distance of less than 300 micrometers to provide the minimum scan line accuracy, thereby effectively avoiding the situation where the change amplitude is not obvious due to an excessively large acquisition range.

[0033] More specifically, among the plurality of detection points P corresponding to the central region 111, the difference between the maximum and minimum values ​​is defined as a central region total thickness deviation value S1. Among the plurality of detection points P corresponding to each of the annular sub-regions 112a, 112b, the difference between the maximum and minimum values ​​is defined as a sub-region total thickness deviation value S2a, S2b. Among the plurality of detection points P corresponding to the chip removal region 113, the difference between the maximum and minimum values ​​is defined as a chip removal region total thickness deviation value S3. Among the plurality of detection points P corresponding to the edge region 114, the difference between the maximum and minimum values ​​is defined as an edge region total thickness deviation value S4.

[0034] The prediction step S150: as follows: Figure 1 and Figures 3 to 5 As shown, if any one of the multiple pre-judgment conditions cannot be met, it is determined that the top surface 11 of the wafer 100 has scratches. In this embodiment, the execution of the multiple pre-judgment conditions can be implemented by a processing module (not shown, such as a computer), but the present invention is not limited thereto.

[0035] More specifically, the multiple prediction conditions in this embodiment include: (1) among the two annular sub-regions 112a and 112b adjacent to the central region 111, the total thickness deviation value S2a of the sub-region of the annular sub-region 112a closer to the central region 111 is greater than or equal to the total thickness deviation value S2b of the sub-region of the other annular sub-region 112b farther from the central region 111 (e.g., the total thickness deviation values ​​S2a and S2b of the N sub-regions are level or gradually decreasing in the direction away from the central region 111); (2) among any two annular sub-regions 112a and 112b, the difference between the total thickness deviation values ​​S2a and S2b of the two sub-regions is less than 0.5 micrometers.

[0036] Furthermore, the aforementioned prediction conditions may be further included according to actual needs: (3) the total thickness deviation value S4 of the edge area is greater than the total thickness deviation value S1 of the central area and is between 2.5 micrometers and 4.5 micrometers; (4) the total thickness deviation value S1 of the central area is greater than the total thickness deviation values ​​S2a and S2b of any of the sub-regions and is less than 2.2 micrometers; and (5) the total thickness deviation values ​​S2a and S2b of any of the sub-regions are greater than the total thickness deviation value S3 of the chip removal area.

[0037] For example, if the wafer 100 fails to meet at least one of the pre-judgment conditions (1) and (2), the top surface 11 of the wafer 100 will be judged to have a high probability of being scratched during continuous processing, and therefore the morphology of the wafer 100 or the grinding machine needs to be readjusted. Conversely, if the wafer 100 meets the pre-judgment conditions (1) and (2), the top surface 11 of the wafer 100 will have a high probability of not being scratched and will meet most of the requirements for the degree of scratching.

[0038] Therefore, in this embodiment, the wafer grinding surface scratch prediction method S100 can predict scratches under corresponding conditions at specific locations of the wafer 100. This allows for real-time assessment of whether continuous processing during the wafer 100's grinding and thinning process is prone to causing scratches, thereby facilitating the maintenance of the stability of the grinding and thinning process through adjustments to the grinding machine (i.e., effectively reducing the scratch rate of the wafer 100). For example, during the implementation of the wafer 100's grinding and thinning process, if the wafer 100 fails to meet at least one of the predicted conditions in any grinding stage (i.e., the wafer 100 has a non-compliant surface morphology), the grinding and thinning process can be paused and resumed after corresponding adjustments to the grinding machine, ensuring that the wafer 100 meets the relevant yield requirements after completing the grinding and thinning process.

[0039] The above is a description of the wafer grinding surface scratch prediction method S100 in this embodiment. The wafer 100 disclosed in this embodiment is then generally described below. It preferably meets multiple prediction conditions (1) to (5). Therefore, the technical content of the wafer 100 can be referred to the above description of the wafer grinding surface scratch prediction method S100, but the present invention is not limited thereto. For example, in other embodiments of the present invention not shown, the wafer 100 may only meet the prediction conditions (1) and (2).

[0040] like Figures 2 to 5 As shown, in this embodiment, the wafer 100 includes an annular portion 2 and a processing portion 1 connected within the annular portion 2. The processing portion 1 has a ground top surface 11 and a bottom surface 12 opposite to the top surface 11. Further, the top surface 11 of the processing portion 1 defines a center C and a radius R, and the top surface 11 can be used to obtain multiple detection points P through topography measurement.

[0041] More specifically, in this embodiment, the top surface 11 of the wafer 100 has a central region 111, a discriminant region 112 in an annular shape surrounding the central region 111, a chip removal region 113 in an annular shape surrounding the discriminant region 112, and an edge region 114 in an annular shape surrounding the chip removal region 113. Furthermore, the plurality of detection points P are obtained by topographic measurement along one of the radii R on the top surface 11, and the number of such points is not less than 150. The number of detection points P corresponding to each of the central region 111, the discriminant region 112, the chip removal region 113, and the edge region 114 is not less than 25.

[0042] The central region 111 encompasses the area within 20% of the radius R of the top surface 11 relative to the center C. The difference between the maximum and minimum values ​​of the plurality of detection points P corresponding to the central region 111 is defined as a total thickness deviation value S1 for the central region.

[0043] The discrimination region 112 is annular and surrounds the central region 111, and the discrimination region 112 includes a range of 20% to 54% of the radius R of the top surface 11 relative to the center C. The discrimination region 112 comprises N annular sub-regions 112a and 112b, arranged in a direction away from the central region 111, where N is a positive integer greater than 1 (e.g., 2). Among the plurality of detection points P corresponding to each annular sub-region 112a and 112b, the difference between the maximum and minimum values ​​is defined as the total thickness deviation values ​​S2a and S2b of a sub-region.

[0044] The chip removal area 113 is annular and surrounds the discrimination area 112, and the chip removal area 113 includes 54% to 72% of the radius R of the top surface 11 relative to the center C. Among the plurality of detection points P corresponding to the chip removal area 113, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value S3 for the chip removal area.

[0045] The edge region 114 is annular and surrounds the chip removal region 113, and the edge region 114 includes 72% to 100% of the radius R of the top surface 11 relative to the center C. The difference between the maximum and minimum values ​​of the plurality of detection points P corresponding to the edge region 114 is defined as a total edge region thickness deviation value S4.

[0046] Furthermore, among the two annular sub-regions 112a and 112b adjacent to the central region 111, the total thickness deviation value S2a of the annular sub-region 112a closer to the central region 111 is greater than the total thickness deviation value S2b of the other annular sub-region 112b farther from the central region 111 (e.g., the total thickness deviation values ​​S2a and S2b of the N sub-regions are equal or gradually decreasing in the direction away from the central region 111). Moreover, in any two annular sub-regions 112a and 112b, the difference between the two total thickness deviation values ​​S2a and S2b is less than 0.5 micrometers.

[0047] Furthermore, in this embodiment, the wafer 100 preferably meets at least a portion of the following conditions, but is not limited thereto: the total thickness deviation value S4 of the edge region is greater than the total thickness deviation value S1 of the central region and is between 2.5 micrometers (μm) and 4.5 micrometers; the total thickness deviation value S1 of the central region is greater than the total thickness deviation values ​​S2a and S2b of any of the sub-regions and is less than 2.2 micrometers; and the total thickness deviation values ​​S2a and S2b of any of the sub-regions are greater than the total thickness deviation value S3 of the chip removal region.

[0048] [Technical Effects of the Embodiments of the Invention]

[0049] In summary, the wafer and wafer grinding surface scratch prediction method disclosed in the embodiments of the present invention can predict scratches under corresponding conditions by using specific parts of the wafer (such as the two annular sub-regions). This allows for real-time assessment of whether continuous processing is likely to cause scratches during the wafer grinding and thinning process, thereby facilitating the maintenance of the stability of the grinding and thinning process by adjusting the grinding machine (that is, the scratch rate of the wafer can be effectively reduced).

[0050] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the patent scope of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the patent scope of the present invention.

Claims

1. A wafer, characterized in that, The wafer includes: A ring-shaped portion; and A processing section is connected within the annular portion, and the processing section has a ground top surface and a bottom surface opposite the top surface; wherein the top surface of the processing section defines a center and a radius, and the top surface can be used to obtain multiple detection points by morphological measurement; wherein the top surface has: A central region comprising the area within 20% of the radius of the top surface relative to the center of the circle; wherein, among the plurality of detection points corresponding to the central region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value for the central region. A discrimination region, which is annular and surrounds the central region, and the discrimination region includes a range of 20% to 54% of the radius of the top surface relative to the center of the circle; wherein the discrimination region includes N annular sub-regions arranged in a direction away from the central region, where N is a positive integer greater than 1; among the plurality of detection points corresponding to each annular sub-region, the difference between the maximum and minimum values ​​is defined as the total thickness deviation value of a sub-region; A chip removal region, which is annular and surrounds the discrimination region; wherein, among the plurality of detection points corresponding to the chip removal region, the difference between the maximum and minimum values ​​is defined as the total thickness deviation value of the chip removal region; and An edge region, which is annular and surrounds the chip removal area; wherein, among the plurality of detection points corresponding to the edge region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the edge region; Among the two annular sub-regions adjacent to the central region, the total thickness deviation of the sub-region of the annular sub-region closer to the central region is greater than or equal to the total thickness deviation of the sub-region of the other annular sub-region farther from the central region. Wherein, in any two of the annular sub-regions, the difference between the total thickness deviation values ​​of the two sub-regions is less than 0.5 micrometers.

2. The wafer according to claim 1, characterized in that, The chip removal area includes the range of 54% to 72% of the radius of the top surface relative to the center of the circle; the edge area includes the range of 72% to 100% of the radius of the top surface relative to the center of the circle; the total thickness deviation of the edge area is greater than the total thickness deviation of the central area and is between 2.5 micrometers and 4.5 micrometers, the total thickness deviation of the central area is greater than the total thickness deviation of any of the sub-regions and is less than 2.2 micrometers, and the total thickness deviation of any of the sub-regions is greater than the total thickness deviation of the chip removal area.

3. The wafer according to claim 1, characterized in that, The width of any one of the annular sub-regions is 60% to 155% of the width of the other annular sub-region.

4. The wafer according to claim 1, characterized in that, The total thickness deviation of the N sub-regions is either level or gradually decreases in the direction away from the central region.

5. The wafer according to claim 1, characterized in that, The plurality of the aforementioned detection points are obtained by topographic measurement along one of the aforementioned radii on the top surface, and the number thereof is not less than 150.

6. The wafer according to claim 1, characterized in that, The number of detection points corresponding to each of the central region, the discrimination region, the chip removal region, and the edge region is not less than 25.

7. A method for predicting surface scratches in wafer grinding, characterized in that, The method for predicting surface scratches on wafers includes: A preliminary step: A wafer is provided having an annular portion and a processing portion connected within the annular portion; wherein the processing portion has a polished top surface defining a center and a radius; wherein the top surface has: A central region comprising the area within 20% of the radius of the top surface relative to the center of the circle; A discrimination region is annular and surrounds the central region, and the discrimination region includes a range of 20% to 54% of the radius of the top surface relative to the center of the circle; wherein the discrimination region includes N annular sub-regions arranged in a direction away from the central region, where N is a positive integer greater than 1; A chip removal area, which is annular and surrounds the discrimination area; and An edge region, which is annular and surrounds the chip removal area; Measurement step 1: The top surface of the wafer is measured using a topography measuring instrument to obtain multiple detection points; Among the multiple detection points corresponding to the central region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the central region. Among the multiple detection points corresponding to each annular sub-region, the difference between the maximum and minimum values ​​is defined as the total thickness deviation value of a sub-region. Among the multiple detection points corresponding to the chip removal area, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value of the chip removal area. Among the multiple detection points corresponding to the edge region, the difference between the maximum and minimum values ​​is defined as a total thickness deviation value for the edge region; and A preliminary judgment step: If any one of a plurality of preliminary judgment conditions cannot be met, the top surface of the wafer is determined to have scratches; wherein the plurality of preliminary judgment conditions include: (1) Among the two annular sub-regions adjacent to the central region, the total thickness deviation of the sub-region of the annular sub-region closer to the central region is greater than or equal to the total thickness deviation of the sub-region of the other annular sub-region farther from the central region; and (2) In any two of the annular sub-regions, the difference between the total thickness deviation values ​​of the two sub-regions is less than 0.5 micrometers.

8. The method for predicting surface scratches in wafer grinding according to claim 7, characterized in that, In the prediction step, the multiple prediction conditions further include: (3) The total thickness deviation of the edge region is greater than the total thickness deviation of the central region and is between 2.5 micrometers and 4.5 micrometers; (4) The total thickness deviation of the central region is greater than the total thickness deviation of any of the sub-regions but less than 2.2 micrometers; and (5) The total thickness deviation of any of the sub-regions is greater than the total thickness deviation of the chip removal area.

9. The method for predicting surface scratches in wafer grinding according to claim 7, characterized in that, In the measurement step, the plurality of detection points are obtained by topographic measurement along one of the radii on the top surface, and the number of such points is not less than 150. The plurality of detection points corresponding to the central region, the discrimination region, the chip removal region, and the edge region are not less than 25. The detection points are spaced apart by a distance of less than 300 micrometers between any two adjacent detection points.

10. The method for predicting surface scratches in wafer grinding according to claim 7, characterized in that, The width of any one of the annular sub-regions is 60% to 155% of the width of the other annular sub-region.

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