Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal. The display panel comprises a driving circuit layer and a pixel electrode layer, the driving circuit layer comprises a data line group and a transistor group, the data line group comprises a first data line and a second data line, the transistor group comprises a first transistor and a second transistor, the pixel electrode layer comprises a pixel electrode group, and the pixel electrode group comprises a first pixel electrode and a second pixel electrode; the first data line is located between the first pixel electrode and the second pixel electrode, the second data line is overlapped with the second pixel electrode, one end of the first transistor is electrically connected with the first data line, and one end of the second transistor is electrically connected with the second data line. According to the array substrate, the distance between the first data line and the second data line which are adjacent can be reduced, meanwhile, the ends, close to each other, of the first transistor and the second transistor which are adjacent to each other are electrically connected with the data lines, the two adjacent transistors can be drawn close to each other, the area occupied by the transistor set is reduced, and therefore the aperture ratio is increased.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] Liquid crystal display (LCD) panels are the mainstream display products. LCD panels themselves cannot emit light and require a backlight module to provide a backlight source. When the light transmittance of an LCD panel is low, a higher brightness is required from the backlight module to achieve the same display brightness, which increases the power consumption of the backlight module.

[0003] To meet energy-saving requirements, the light transmittance of display panels needs to be improved. This can be achieved by increasing the aperture ratio of the display panel. However, as consumers' demands for LCD panel resolution continue to rise, it is difficult to further increase the aperture ratio simply by improving the precision of the manufacturing process. Summary of the Invention

[0004] This application provides a display panel and a display terminal, which improves the technical problem that it is difficult to further increase the aperture ratio by improving the precision of the manufacturing process.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including an array substrate, the array substrate comprising: substrate; A driving circuit layer is disposed on one side of the substrate. The driving circuit layer includes multiple data line groups and multiple transistor groups. The data line groups include adjacent first data lines and second data lines. The first data lines and the second data lines extend along a first direction and are arranged along a second direction perpendicular to the first direction. The transistor groups include adjacent first transistors and second transistors along the second direction. A pixel electrode layer is disposed on the side of the driving circuit layer away from the substrate and includes a plurality of pixel electrode groups. The pixel electrode group includes a first pixel electrode and a second pixel electrode adjacent to each other along the second direction. The first data line is electrically connected to the first pixel electrode through the first transistor, and the second data line is electrically connected to the second pixel electrode through the second transistor. The first data line is projected onto the substrate between the first pixel electrode and the second pixel electrode. The second data line and the second pixel electrode overlap in the thickness direction of the display panel. The end of the first transistor near the second transistor is electrically connected to the first data line, and the end of the second transistor near the first transistor is electrically connected to the second data line.

[0006] Optionally, the data line group further includes a third data line adjacent to the second data line, the third data line being located on the side of the second data line away from the first data line; the pixel electrode group further includes a third pixel electrode adjacent to the second pixel electrode along the second direction, the third pixel electrode being located on the side of the second pixel electrode away from the first pixel electrode; the transistor group further includes a third transistor adjacent to the second transistor along the second direction, the third transistor being located on the side of the second transistor away from the first transistor; The orthographic projection of the third data line on the substrate is located between the orthographic projections of the second pixel electrode and the third pixel electrode on the substrate. The end of the third transistor near the second transistor is electrically connected to the third data line, and the third data line is electrically connected to the third pixel electrode through the third transistor.

[0007] Optionally, the first transistor includes a first gate located in the driving circuit layer, the first gate being located on the side of the data line group closer to the substrate; the second transistor includes a second gate disposed in the same layer as the first gate; and the third transistor includes a third gate disposed in the same layer as the first gate. Wherein, the first gate and the second gate are integral structures, and / or, the second gate and the third gate are integral structures.

[0008] Optionally, the first transistor includes a first source and a first drain disposed on the same layer, and the third transistor includes a third source and a third drain disposed on the same layer; Wherein, the first data line is multiplexed as the first source, and the first drain is electrically connected to the first pixel electrode; the third data line is multiplexed as the third source, and the third drain is electrically connected to the third pixel electrode.

[0009] Optionally, in the second direction, the distance between two adjacent transistors in the same transistor group is less than the distance between two adjacent transistor groups.

[0010] Optionally, the display panel further includes: A counter substrate is disposed opposite to and spaced apart from the array substrate, and the counter substrate is located on the side of the pixel electrode layer away from the substrate; Multiple support portions are disposed between the array substrate and the opposing substrate, and the orthographic projection of the support portion on the substrate is located between the orthographic projections of two adjacent pixel electrodes on the substrate. A plurality of the transistors in the transistor group overlap with the same support portion in the thickness direction of the display panel.

[0011] Optionally, the dimension of the support portion in the second direction is greater than the dimension of the same support portion in the first direction.

[0012] Optionally, the driving circuit layer includes multiple touch lines disposed on the same layer as the data line, and the touch lines extend along the first direction; The area between any two adjacent touch lines and data lines is a first area, and the first area overlaps with at least a portion of the pixel electrodes in the thickness direction of the display panel.

[0013] Optionally, the orthographic projection of the touch line on the substrate is located between the orthographic projections of the adjacent pixel electrodes on the substrate.

[0014] Optionally, the touch line overlaps with the pixel electrode in the thickness direction of the display panel.

[0015] Optionally, the array substrate further includes: A first passivation layer is disposed on the side of the driving circuit layer away from the substrate; A common electrode layer is disposed on the side of the first passivation layer away from the substrate; A second passivation layer is disposed between the common electrode layer and the pixel electrode layer; The orthographic projection of the pixel electrode on the substrate is located within the orthographic projection of the common electrode layer on the substrate, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the common electrode layer on the substrate. The common electrode layer is provided with a plurality of clearance openings, which are located between two adjacent pixel electrodes in the second direction, and the clearance openings expose the touch line.

[0016] Optionally, the display panel further includes a light-shielding layer disposed on one side of the substrate, the light-shielding layer covering each of the transistor groups, the light-shielding layer having a notch corresponding to the area between two adjacent transistor groups in the second direction.

[0017] According to a second aspect of this application, a display terminal is provided, including the display panel described above.

[0018] In the display panel of this application embodiment, by overlapping the second data line and the second pixel electrode in the thickness direction of the display panel, the spacing between two adjacent data lines can be reduced. At the same time, by electrically connecting the ends of two adjacent transistors that are close to each other to the data line, the two adjacent transistors can be brought closer together, reducing the area occupied by the transistor group, thereby increasing the aperture ratio.

[0019] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0022] Figure 1 This is a top view of a display panel provided in an exemplary embodiment of this disclosure; Figure 2A yes Figure 1 A magnified view of a portion of the display area in the diagram; Figure 2B yes Figure 2A A magnified schematic diagram of the local structure; Figure 2C yes Figure 1 Another magnified view of the display area in the diagram; Figure 3A Is Figure 2A A schematic diagram of the structure with added support parts; Figure 3B yes Figure 2A A schematic diagram of the structure of some of the membrane layers; Figure 3C Is Figure 2A A schematic diagram of the structure with an added light-shielding layer; Figure 4 yes Figure 1 A cross-sectional structural diagram of the display area in the image; Figure 5 yes Figure 1 Another cross-sectional structural diagram of the display area in the diagram; Figure 6A This is a schematic diagram of a display panel using a horizontal inversion drive; Figure 6B This is a schematic diagram of a display panel using column inversion drive; Figure 7 This is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure.

[0023] Explanation of reference numerals in the attached figures: 1-Display panel; AA-Display area; NA-Non-display area; 11-Subpixel; 1a-First area; 101 - Array substrate; 102 - Opposite substrate; 10-Substrate; 20 - Driver circuit layer; 21-Data cable group; 211-First data cable; 212-Second data cable; 213-Third data cable; 22-Touch cable; 23 - Transistor group; 231 - First transistor; 2311 - First source; 2312 - First drain; 2313 - First gate; 2314 - First active part; 232 - Second transistor; 2321 - Second source; 2322 - Second drain; 2323 - Second gate; 2324 - Second active part; 233 - Third transistor; 2331 - Third source; 2332 - Third drain; 2333 - Third gate; 2334 - Third active part; 24 scan lines; 30 - Pixel electrode layer; 31 - Pixel electrode group; 311 - First pixel electrode; 312 - Second pixel electrode; 313 - Third pixel electrode; 41 - First passivation layer; 42-Common electrode layer; 42a-Avoidance opening; 43 - Second passivation layer; 51-Support section; 52 - Light-shielding layer; 52a - Notch; D1 - First direction; D2 - Second direction; 2-Display terminal; 3-Backlight module. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] According to the first aspect of this application, Figures 1 to 5As shown, a display panel 1 is provided, including an array substrate 101. The array substrate 101 includes a substrate 10, a driving circuit layer 20, and a pixel electrode layer 30. The driving circuit layer 20 is disposed on one side of the substrate 10 and includes multiple data line groups 21 and multiple transistor groups 23. The data line groups 21 include adjacent first data lines 211 and second data lines 212. The first data lines 211 and second data lines 212 extend along a first direction D1 and are arranged along a second direction D2 perpendicular to the first direction D1. The transistor groups 23 include adjacent first transistors 231 and second transistors 232 along the second direction D2. The pixel electrode layer 30 is disposed on the side of the driving circuit layer 20 away from the substrate 10 and includes multiple pixel electrode groups 31. Group 31 includes a first pixel electrode 311 and a second pixel electrode 312 adjacent to each other along the second direction D2. A first data line 211 is electrically connected to the first pixel electrode 311 through a first transistor 231, and a second data line 212 is electrically connected to the second pixel electrode 312 through a second transistor 232. The orthographic projection of the first data line 211 on the substrate 10 is located between the orthographic projections of the first pixel electrode 311 and the second pixel electrode 312 on the substrate 10. The second data line 212 overlaps with the second pixel electrode 312 in the thickness direction of the display panel 1. The end of the first transistor 231 near the second transistor 232 is electrically connected to the first data line 211, and the end of the second transistor 232 near the first transistor 231 is electrically connected to the second data line 212.

[0026] In some embodiments, the display panel 1 may be an LCD panel.

[0027] like Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA may have multiple sub-pixels 11, which may include a first sub-pixel 11, a second sub-pixel 11, and a third sub-pixel 11 of different emitting colors. The first sub-pixel 11, the second sub-pixel 11, and the third sub-pixel 11 may be one of a red sub-pixel 11, a green sub-pixel 11, and a blue sub-pixel 11, respectively, thereby achieving color display. The display area AA is provided with a pixel driving circuit, which drives the sub-pixels 11 for display. The non-display area NA may have a gate driving circuit, etc., which provides driving signals to the sub-pixels 11.

[0028] The substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz, or silicon wafer. The flexible material can be one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).

[0029] The driving circuit layer 20 is provided with driving circuits, such as gate driving circuits and pixel driving circuits, and the driving circuit layer 20 is used to provide driving signals for sub-pixels 11.

[0030] like Figure 2A As shown, the data line group 21 includes an adjacent first data line 211 and a second data line 212, wherein "adjacent" means that there are no other data lines between the first data line 211 and the second data line 212. The first data line 211 and the second data line 212 can be arranged on the same layer.

[0031] In some embodiments, the data cable in the data cable assembly 21 may be made of a conductive material, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0032] like Figure 2A As shown, transistor group 23 includes a first transistor 231 and a second transistor 232 that are adjacent along the second direction D2, that is, there are no other transistors between the first transistor 231 and the second transistor 232 in the second direction D2. The first transistor 231 and the second transistor 232 can be thin-film transistors.

[0033] In some embodiments, the pixel electrode layer 30 can be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), etc.

[0034] like Figure 2A As shown, the first data line 211 is electrically connected to the first pixel electrode 311 via the first transistor 231. The first data line 211 can input data signals to the first pixel electrode 311.

[0035] The second data line 212 is electrically connected to the second pixel electrode 312 via the second transistor 232. The second data line 212 can input data signals to the second pixel electrode 312.

[0036] like Figure 2A As shown, the orthographic projection of the first data line 211 on the substrate 10 is located between the orthographic projections of the first pixel electrode 311 and the second pixel electrode 312 on the substrate 10. That is, the orthographic projection pattern of the first data line 211 is located on the side of the orthographic projection pattern of the first pixel electrode 311 that is closer to the orthographic projection pattern of the second pixel electrode 312, and the orthographic projection pattern of the first data line 211 is located on the side of the orthographic projection pattern of the second pixel electrode 312 that is closer to the orthographic projection pattern of the first pixel electrode 311.

[0037] like Figure 2AAs shown, the second data line 212 and the second pixel electrode 312 overlap in the thickness direction of the display panel 1. That is to say, the orthographic projection of the second data line 212 on the substrate 10 overlaps with the orthographic projection of the second pixel electrode 312 on the substrate 10.

[0038] Since the first data line 211 is located between the first pixel electrode 311 and the second pixel electrode 312, and the second data line 212 overlaps with the second pixel electrode 312 in the thickness direction of the display panel 1, the spacing between adjacent first data lines 211 and second data lines 212 can be reduced.

[0039] like Figure 2A As shown, the end of the first transistor 231 closest to the second transistor 232 is electrically connected to the first data line 211, and the end of the second transistor 232 closest to the first transistor 231 is electrically connected to the second data line 212. This arrangement allows adjacent first transistors 231 and second transistors 232 to be brought closer together, reducing the area occupied by the transistor group 23 and thus increasing the aperture ratio.

[0040] It should be noted that the aperture ratio of the display panel 1 refers to the proportion of the area of ​​the light-transmitting region to the total area of ​​the sub-pixel 11. In the sub-pixel 11, the non-light-transmitting area is used to house structures such as transistors and data lines. The light-transmitting area refers to the area excluding the non-light-transmitting area.

[0041] Optionally, such as Figure 2A As shown, the data line group 21 further includes a third data line 213 adjacent to the second data line 212, and the third data line 213 is located on the side of the second data line 212 away from the first data line 211; the pixel electrode group 31 further includes a third pixel electrode 313 adjacent to the second pixel electrode 312 along the second direction D2, and the third pixel electrode 313 is located on the side of the second pixel electrode 312 away from the first pixel electrode 311; the transistor group 23 further includes a third transistor 233 adjacent to the second transistor 232 along the second direction D2, and the third transistor 233 is located on the side of the second transistor 232 away from the first transistor 231; wherein, the orthographic projection of the third data line 213 on the substrate 10 is located between the orthographic projections of the second pixel electrode 312 and the third pixel electrode 313 on the substrate 10, and the end of the third transistor 233 near the second transistor 232 is electrically connected to the third data line 213, and the third data line 213 is electrically connected to the third pixel electrode 313 through the third transistor 233.

[0042] like Figure 2AAs shown, the data line group 21 also includes a third data line 213, which can be arranged on the same layer as the first data line 211. The third data line 213 is adjacent to the second data line 212, meaning there are no other data lines between the third data line 213 and the second data line 212. In a data line group 21, the first data line 211, the second data line 212, and the third data line 213 are arranged sequentially along the second direction D2.

[0043] The second pixel electrode 312 and the third pixel electrode 313 are adjacent in the second direction D2, that is, there are no other pixel electrodes between the second pixel electrode 312 and the third pixel electrode 313 in the second direction D2.

[0044] In a pixel electrode group 31, the first pixel electrode 311, the second pixel electrode 312 and the third pixel electrode 313 are arranged sequentially along the second direction D2.

[0045] The transistor group 23 also includes a third transistor 233 adjacent to the second transistor 232 along the second direction D2, that is, there are no other transistors between the second transistor 232 and the third transistor 233 in the second direction D2.

[0046] In a transistor group 23, the first transistor 231, the second transistor 232 and the third transistor 233 are arranged sequentially along the second direction D2.

[0047] like Figure 2A As shown, the orthographic projection of the third data line 213 on the substrate 10 is located between the orthographic projections of the second pixel electrode 312 and the third pixel electrode 313 on the substrate 10. The end of the third transistor 233 closest to the second transistor 232 is electrically connected to the third data line 213, and the third data line 213 is electrically connected to the third pixel electrode 313 through the third transistor 233. This means that the orthographic projection pattern of the third data line 213 is located between the orthographic projection patterns of the second pixel electrode 312 and the third pixel electrode 313. The third data line 213 inputs a data signal to the third pixel electrode 313 through the third transistor 233.

[0048] Optionally, such as Figure 2B , Figure 4 and Figure 5As shown, the first transistor 231 includes a first gate 2313 located in the driving circuit layer 20. The first gate 2313 is located on the side of the data line group 21 close to the substrate 10. The second transistor 232 includes a second gate 2323 disposed in the same layer as the first gate 2313. The third transistor 233 includes a third gate 2333 disposed in the same layer as the first gate 2313. The first gate 2313 and the second gate 2323 are integral structures, and / or the second gate 2323 and the third gate 2333 are integral structures.

[0049] In some embodiments, the first gate 2313, the second gate 2323 and the third gate 2333 are all disposed on the same layer, thereby simplifying the manufacturing process of the display panel 1.

[0050] In some embodiments, the first gate 2313, the second gate 2323, and the third gate 2333 are all conductive materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0051] In some embodiments, such as Figure 2B As shown, the first gate 2313 and the second gate 2323 are an integral structure. That is to say, the first gate 2313 and the second gate 2323 are made of the same material, and the first gate 2313 and the second gate 2323 are continuously arranged in the second direction D2.

[0052] In some embodiments, such as Figure 2B As shown, the second gate 2323 and the third gate 2333 are an integral structure. That is to say, the second gate 2323 and the third gate 2333 are made of the same material, and the second gate 2323 and the third gate 2333 are continuously arranged in the second direction D2.

[0053] In some embodiments, such as Figure 2B As shown, the first gate 2313 and the second gate 2323 are integral structures, and the second gate 2323 and the third gate 2333 are integral structures. That is to say, the first gate 2313, the second gate 2323 and the third gate 2333 are all made of the same material, and the first gate 2313, the second gate 2323 and the third gate 2333 are continuously arranged in the second direction D2.

[0054] like Figure 2A As shown, the array substrate 101 also includes a scan line 24, which extends along the second direction D2. The scan line 24 is an integral structure with the first gate 2313, the second gate 2323 and the third gate 2333.

[0055] Optionally, such as Figure 2BAs shown, the first transistor 231 includes a first source 2311 and a first drain 2312 disposed on the same layer, and the third transistor 233 includes a third source 2331 and a third drain 2332 disposed on the same layer; wherein, the first data line 211 is multiplexed as the first source 2311, and the first drain 2312 is electrically connected to the first pixel electrode 311; the third data line 213 is multiplexed as the third source 2331, and the third drain 2332 is electrically connected to the third pixel electrode 313.

[0056] In some embodiments, such as Figure 2B As shown, the first data line 211 is multiplexed as the first source 2311. This means that the first data line 211 can extend along the first direction D1, and a segment of the first data line 211 serves as the source of the first transistor 231. With the above configuration, the first source 2311 can be omitted, further reducing the area occupied by the first transistor 231.

[0057] In some embodiments, such as Figure 2B As shown, the third data line 213 is multiplexed as the third source 2331. This means that the third data line 213 can extend along the first direction D1, and a segment of the third data line 213 serves as the source of the third transistor 233. With the above configuration, the third source 2331 can be omitted, further reducing the area occupied by the third transistor 233.

[0058] In some embodiments, such as Figure 2B As shown, the second data line 212 is multiplexed as the second source 2321. This means that the second data line 212 can extend along the first direction D1, and a segment of the second data line 212 serves as the source of the second transistor 232. With the above configuration, the second source 2321 can be omitted, further reducing the area occupied by the second transistor 232.

[0059] The first drain 2312 is electrically connected to the first pixel electrode 311, and the data signal in the first data line 211 can be input to the first pixel electrode 311 through the first drain 2312.

[0060] The second drain 2322 is electrically connected to the second pixel electrode 312, and the data signal in the second data line 212 can be input to the second pixel electrode 312 through the second drain 2322.

[0061] The third drain 2332 is electrically connected to the third pixel electrode 313, and the data signal in the third data line 213 can be input to the third pixel electrode 313 through the third drain 2332.

[0062] In some embodiments, the first transistor 231 includes a first active portion 2314, the second transistor 232 includes a second active portion 2324, and the third transistor 233 includes a third active portion 2334. The first active portion 2314, the second active portion 2324, and the third active portion 2334 are disposed in the same layer and are all located between the film layer of the first gate 2313 and the film layer of the first source 2311.

[0063] In some embodiments, the materials of the first active part 2314, the second active part 2324, and the third active part 2334 can be semiconductor materials, such as single-crystal silicon, polycrystalline silicon, metal oxides, etc.

[0064] Optionally, in the second direction D2, the distance between two adjacent transistors in the same transistor group 23 is less than the distance between two adjacent transistor groups 23.

[0065] In some embodiments, the distance between two adjacent transistors in the same transistor group 23 can be the distance between the first transistor 231 and the second transistor 232, or the distance between two adjacent transistors in the same transistor group 23 can be the distance between the second transistor 232 and the third transistor 233. The distance between the first transistor 231 and the second transistor 232 refers to the spacing between the closest ends of the first transistor 231 and the second transistor 232, and the distance between the second transistor 232 and the third transistor 233 refers to the spacing between the closest ends of the second transistor 232 and the third transistor 233.

[0066] The distance between two adjacent transistors refers to the spacing between the ends of two adjacent transistors that are closest to each other in the second direction D2.

[0067] By setting the distance between two adjacent transistors in the same transistor group 23 in the second direction D2 to be less than the distance between two adjacent transistor groups 23, multiple transistors in the same transistor group 23 can be brought closer together, thereby reducing the length of the transistor group 23 in the second direction D2 and reducing the area occupied by the transistor group 23. In other words, by making the distance between two adjacent transistor groups 23 in the second direction D2 greater than the distance between two adjacent transistors in the transistor group 23, the distance between two adjacent transistor groups 23 can be increased. The distance between two transistor groups 23 can contribute to the light-transmitting area, thereby improving the aperture ratio of the display panel 1.

[0068] Optionally, such as Figure 3A As shown, Figure 3A The embodiments and Figure 2AThe difference in the embodiment is the addition of a support portion 51. The display panel 1 also includes a counter substrate 102 and a plurality of support portions 51. The counter substrate 102 is opposite to and spaced apart from the array substrate 101. The counter substrate 102 is located on the side of the pixel electrode layer 30 away from the substrate 10. The support portions 51 are disposed between the array substrate 101 and the counter substrate 102. The orthographic projection of the support portion 51 on the substrate 10 is located between the orthographic projections of two adjacent pixel electrodes on the substrate 10. A plurality of transistors in a transistor group 23 overlap with the same support portion 51 in the thickness direction of the display panel 1.

[0069] Display panel 1 is a liquid crystal panel. Display panel 1 includes a counter substrate 102 disposed opposite to and spaced apart from array substrate 101, and a liquid crystal layer (not shown) disposed between substrate 10 and counter substrate 102. A first polarizer is disposed on the surface of substrate 10 away from counter substrate 102, and a second polarizer is disposed on the surface of counter substrate 102 away from substrate 10. The liquid crystal panel itself cannot emit light; a backlight module 3 is required on one side of the liquid crystal panel. Light emitted from the backlight module 3 enters display panel 1, and the liquid crystal molecules in the liquid crystal layer of display panel 1 are deflected under the action of an electric field. Liquid crystal molecules with different deflection angles correspond to different light transmittances, thereby controlling the light transmittance of display panel 1 and achieving brightness control of the displayed image.

[0070] The support portion 51 is located between the array substrate 101 and the opposing substrate 102, and the support portion 51 can be used to maintain the spacing between the array substrate 101 and the opposing substrate 102.

[0071] In some embodiments, the support portion 51 may be an insulating material, such as resin.

[0072] Since the area corresponding to the pixel electrode is the light-transmitting area of ​​the display panel 1, placing the orthographic projection pattern of the support portion 51 between the orthographic projection patterns of the pixel electrode can prevent the support portion 51 from occupying the area of ​​the light-transmitting area. The area where the transistor group 23 is located is a non-light-transmitting area; by overlapping the support portion 51 and the transistor group 23 in the thickness direction of the display panel 1, the support portion 51 will not occupy the area of ​​the light-transmitting area.

[0073] Optionally, the dimension of the support portion 51 in the second direction D2 is larger than the dimension of the same support portion 51 in the first direction D1. That is, the support portion 51 can be elongated, with its long side extending along the second direction D2. By aligning the support portion 51 with a transistor group 23, the length of the support portion 51 in the second direction D2 can be increased, thereby increasing the support area of ​​the support portion 51 without affecting the aperture ratio, thus improving the support effect. When the support effect of the support portion 51 is poor, the display panel 1 cannot maintain the distance between the array substrate 101 and the opposing substrate 102 after being pressed by external force. This will cause a reduction in the thickness of the liquid crystal layer at the pressed area, affecting the display effect.

[0074] Optionally, such as Figure 2A As shown, the driving circuit layer 20 includes multiple touch lines 22 disposed on the same layer as the data lines, and the touch lines 22 extend along the first direction D1; wherein, the area between any adjacent touch lines 22 and the data lines is a first region 1a, and the first region 1a overlaps with at least a portion of the pixel electrodes in the thickness direction of the display panel 1.

[0075] The touch line 22 is set on the same layer as the data line. The touch line 22 can be made of the same material as the data line and formed in the same patterning process, thereby simplifying the manufacturing process of the touch line 22.

[0076] The area between any two adjacent touch lines 22 and data lines is a first area 1a, and the first area 1a overlaps with at least a portion of the pixel electrodes in the thickness direction of the display panel 1. Any two adjacent touch lines 22 and data lines refer to a situation where there are no other touch lines 22 or data lines between a touch line 22 and a data line.

[0077] The first region 1a overlaps with at least a portion of the pixel electrodes in the thickness direction of the display panel 1. With this configuration, the first region 1a can serve as a light-transmitting region, and the first region 1a can contribute to the aperture ratio.

[0078] It should be understood that in related technologies, the area between any adjacent touch lines 22 and data lines does not overlap with the pixel electrodes, meaning that the area between any adjacent touch lines 22 and data lines cannot be used as a light-transmitting area, resulting in a loss of aperture ratio. However, in this application, by overlapping the first region 1a with at least a portion of the pixel electrodes in the thickness direction of the display panel 1, the first region 1a can be used as a light-transmitting area, thereby increasing the aperture ratio.

[0079] The number of pixel electrodes corresponding to the first region 1a can be set as needed. For example, the first region 1a can correspond to a portion of a pixel electrode, a single pixel electrode, or multiple pixel electrodes.

[0080] Optionally, such as Figure 2AAs shown, the orthographic projection of the touch line 22 on the substrate 10 lies between the orthographic projections of the adjacent pixel electrodes on the substrate 10. This means that the touch line 22 does not overlap with the pixel electrodes in the thickness direction of the display panel 1.

[0081] Optionally, such as Figure 2A As shown, the touch line 22 overlaps with the pixel electrode in the thickness direction of the display panel 1. This means that the touch line 22 does not occupy the area between the pixel electrodes, but rather overlaps with them in the thickness direction of the display panel 1. This arrangement saves the area originally occupied by the touch line 22, which can then be contributed to the pixel electrode, thereby further improving the aperture ratio of the display panel 1.

[0082] Optionally, such as Figure 2A , Figure 3B and Figure 5 As shown, the array substrate 101 further includes a first passivation layer 41, a common electrode layer 42, and a second passivation layer 43. The first passivation layer 41 is disposed on the side of the driving circuit layer 20 away from the substrate 10; the common electrode layer 42 is disposed on the side of the first passivation layer 41 away from the substrate 10; and the second passivation layer 43 is disposed between the common electrode layer 42 and the pixel electrode layer 30. The orthographic projection of the pixel electrode on the substrate 10 is located within the orthographic projection of the common electrode layer 42 on the substrate 10, and the orthographic projection of the data line on the substrate 10 is located within the orthographic projection of the common electrode layer 42 on the substrate 10. The common electrode layer 42 is provided with a plurality of clearance openings 42a, which are located between two adjacent pixel electrodes in the second direction D2, and the clearance openings 42a expose the touch line 22.

[0083] In some embodiments, the materials of the first passivation layer 41 and the second passivation layer 43 can be inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0084] In other embodiments, such as Figure 4 As shown, the common electrode layer 42 can be located on the side of the pixel electrode layer 30 away from the substrate 10. With the above arrangement, the first passivation layer 41 can be omitted, simplifying the manufacturing process of the display panel 1.

[0085] In some embodiments, the material of the common electrode layer 42 can be a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), etc.

[0086] The common electrode layer 42 can be used to provide a common voltage. Liquid crystal molecules in the liquid crystal layer are deflected in the electric field formed by the pixel electrode and the common electrode layer 42.

[0087] like Figure 3BAs shown, the orthographic projection of the pixel electrode on the substrate 10 lies within the orthographic projection of the common electrode layer 42 on the substrate 10, and the orthographic projection of the data line on the substrate 10 lies within the orthographic projection of the common electrode layer 42 on the substrate 10. Through this arrangement, the common electrode layer 42 can separate the lower data line from the upper pixel electrode layer 30, thereby improving signal crosstalk between the data line and the pixel electrode layer 30.

[0088] In some embodiments, such as Figure 3B As shown, the common electrode layer 42 has a clearance opening 42a, which exposes a portion of the touch line 22. This is because when the touch line 22 is working, the voltage on the touch line 22 is different from the voltage on the common electrode layer 42. If the clearance opening 42a were not provided, the touch line 22 and the common electrode layer 42 would form a capacitor, increasing the load on the touch line 22. However, by exposing the touch line 22 through the clearance opening 42a, the common electrode layer 42 at the clearance opening 42a is removed, preventing the formation of a capacitor with the touch line 22 and thus reducing the load on the touch line 22.

[0089] Optionally, such as Figure 3C As shown, the display panel 1 also includes a light-shielding layer 52 disposed on one side of the substrate 10. The light-shielding layer 52 covers each transistor group 23. The light-shielding layer 52 is provided with a notch 52a, which corresponds to the area between two adjacent transistor groups 23 in the second direction D2.

[0090] In some embodiments, the light-shielding layer 52 has a light-shielding effect, and the area covered by the light-shielding layer 52 is a non-transparent area. The light-shielding layer 52 covers each transistor group 23, thereby preventing light from shining on the active part of the transistor and causing electrical degradation of the transistor. The light-shielding layer 52 can also prevent light crosstalk between two adjacent sub-pixels 11, improving the display effect.

[0091] In some embodiments, the light-shielding layer 52 can be a black matrix, but is not limited thereto.

[0092] In some embodiments, the light-shielding layer 52 may be disposed between the substrate 10 and the liquid crystal layer, or the light-shielding layer 52 may be disposed between the opposing substrate 102 and the liquid crystal layer. In other words, the light-shielding layer 52 may be formed on the substrate 10 or on the opposing substrate 102. Figure 3C , Figure 4 and Figure 5 As shown, when the light-shielding layer 52 is formed on the opposing substrate 102, the light-shielding layer 52 will block the transistor group 23, some data lines and other film structures.

[0093] like Figure 3CAs shown, the light-shielding layer 52 has a notch 52a that allows light to pass through, meaning that the area at the notch 52a can contribute to the light-transmitting area. For example, the area at the notch 52a can be contributed to the pixel electrode, thereby increasing the area of ​​the pixel electrode. Through the above arrangement, the aperture ratio of the display panel 1 can be improved.

[0094] The notch 52a corresponds to the region between two adjacent transistor groups 23 in the second direction D2. This means that the length of the notch 52a in the second direction D2 can be approximately equal to the spacing between the two adjacent transistor groups 23 in the second direction D2. "Approximately equal" means equal within the allowable range of process tolerances.

[0095] In some embodiments, such as Figure 6A As shown, the display panel 1 can employ row inversion. Row inversion can improve flickering. During row inversion, multiple adjacent pixel electrodes on the second direction D2 can provide voltages of the same polarity, while two adjacent pixel electrodes on the first direction D1 can provide voltages of opposite polarity. For example, the first pixel electrode 311, the second pixel electrode 312, and the third pixel electrode 313 provide voltages of the same polarity.

[0096] In some embodiments, such as Figure 6B As shown, the display panel 1 can employ column inversion driving. Column inversion can improve flickering. In column inversion driving, multiple adjacent pixel electrodes in the second direction D2 can provide voltages of opposite polarities, while two adjacent pixel electrodes in the first direction D1 can provide voltages of the same polarity. For example, the first pixel electrode 311 and the third pixel electrode 313 provide a voltage of one polarity, while the second pixel electrode 312 provides a voltage of another polarity.

[0097] According to the second aspect of this application, such as Figure 7 As shown, a display terminal 2 is provided, including the display panel 1 described above.

[0098] In this embodiment, as Figure 7 As shown, the display terminal 2 includes a display panel 1 and a backlight module 3, which are integrated into one unit. The backlight module 3 provides a backlight source for the display panel 1. The backlight module 3 can be disposed on the side of the substrate 10 away from the driving circuit layer 20.

[0099] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0100] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0102] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0103] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, Includes an array substrate, the array substrate comprising: substrate; A driving circuit layer is disposed on one side of the substrate. The driving circuit layer includes multiple data line groups and multiple transistor groups. The data line groups include multiple data lines, and the transistor groups include multiple transistors. The data line groups include adjacent first data lines and second data lines. The first data lines and the second data lines extend along a first direction and are arranged along a second direction perpendicular to the first direction. The transistor groups include adjacent first transistors and second transistors along the second direction. A pixel electrode layer is disposed on the side of the driving circuit layer away from the substrate, and includes a plurality of pixel electrode groups. Each pixel electrode group includes a plurality of pixel electrodes and includes a first pixel electrode and a second pixel electrode adjacent to each other along the second direction. The first data line is electrically connected to the first pixel electrode through the first transistor, and the second data line is electrically connected to the second pixel electrode through the second transistor. The first data line is projected onto the substrate between the first pixel electrode and the second pixel electrode. The second data line and the second pixel electrode overlap in the thickness direction of the display panel. The end of the first transistor near the second transistor is electrically connected to the first data line, and the end of the second transistor near the first transistor is electrically connected to the second data line.

2. The display panel according to claim 1, characterized in that, The data line group further includes a third data line adjacent to the second data line, the third data line being located on the side of the second data line away from the first data line; the pixel electrode group further includes a third pixel electrode adjacent to the second pixel electrode along the second direction, the third pixel electrode being located on the side of the second pixel electrode away from the first pixel electrode; the transistor group further includes a third transistor adjacent to the second transistor along the second direction, the third transistor being located on the side of the second transistor away from the first transistor. The orthographic projection of the third data line on the substrate is located between the orthographic projections of the second pixel electrode and the third pixel electrode on the substrate. The end of the third transistor near the second transistor is electrically connected to the third data line, and the third data line is electrically connected to the third pixel electrode through the third transistor.

3. The display panel according to claim 2, characterized in that, The first transistor includes a first gate located in the driving circuit layer, the first gate being located on the side of the data line group closer to the substrate; the second transistor includes a second gate disposed in the same layer as the first gate; and the third transistor includes a third gate disposed in the same layer as the first gate. Wherein, the first gate and the second gate are integral structures, and / or, the second gate and the third gate are integral structures.

4. The display panel according to claim 3, characterized in that, The first transistor includes a first source and a first drain disposed on the same layer, and the third transistor includes a third source and a third drain disposed on the same layer; Wherein, the first data line is multiplexed as the first source, and the first drain is electrically connected to the first pixel electrode; the third data line is multiplexed as the third source, and the third drain is electrically connected to the third pixel electrode.

5. The display panel according to claim 1, characterized in that, In the second direction, the distance between two adjacent transistors in the same transistor group is less than the distance between two adjacent transistor groups.

6. The display panel according to any one of claims 1 to 5, characterized in that, The display panel also includes: A counter substrate is disposed opposite to and spaced apart from the array substrate, and the counter substrate is located on the side of the pixel electrode layer away from the substrate; Multiple support portions are disposed between the array substrate and the opposing substrate, and the orthographic projection of the support portion on the substrate is located between the orthographic projections of two adjacent pixel electrodes on the substrate. A plurality of the transistors in the transistor group overlap with the same support portion in the thickness direction of the display panel.

7. The display panel according to claim 6, characterized in that, The dimension of the support portion in the second direction is greater than the dimension of the same support portion in the first direction.

8. The display panel according to any one of claims 1 to 5, characterized in that, The driving circuit layer includes multiple touch lines disposed on the same layer as the data line, and the touch lines extend along the first direction; The area between any two adjacent touch lines and data lines is a first area, and the first area overlaps with at least a portion of the pixel electrodes in the thickness direction of the display panel.

9. The display panel according to claim 8, characterized in that, The orthographic projection of the touch line on the substrate is located between the orthographic projections of the adjacent pixel electrodes on the substrate.

10. The display panel according to claim 8, characterized in that, The touch line overlaps with the pixel electrode in the thickness direction of the display panel.

11. The display panel according to claim 8, characterized in that, The array substrate further includes: A first passivation layer is disposed on the side of the driving circuit layer away from the substrate; A common electrode layer is disposed on the side of the first passivation layer away from the substrate; A second passivation layer is disposed between the common electrode layer and the pixel electrode layer; The orthographic projection of the pixel electrode on the substrate is located within the orthographic projection of the common electrode layer on the substrate, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the common electrode layer on the substrate. The common electrode layer is provided with a plurality of clearance openings, which are located between two adjacent pixel electrodes in the second direction, and the clearance openings expose the touch line.

12. The display panel according to claim 8, characterized in that, The display panel further includes a light-shielding layer disposed on one side of the substrate, the light-shielding layer covering each of the transistor groups, the light-shielding layer having a notch corresponding to the area between two adjacent transistor groups in the second direction.

13. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 12.

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