Pointing stick analog signal sampling circuit and sampling method
By using a combination of signal source components and sampling capacitors in the analog signal sampling of the pointing stick, the problems of external interference and high cost were solved, resulting in improved signal-to-noise ratio and reduced production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHAOXING SPRINTEK ELECTRONIC TECH CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-26
Smart Images
Figure CN122086255A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electrical component technology, specifically to a pointing stick analog signal sampling circuit and sampling method. Background Technology
[0002] The TrackPoint, a pointing stick input device, is widely used as an embedded mouse in computer laptops, especially in Lenovo's THINKPAD series. The TrackPoint input device consists of a pressure-conducting rod, a strain gauge sensor, an analog signal sampling circuit, and a mouse function conversion chip.
[0003] The strain gauge sensor module consists of strain gauges distributed in four directions (up, down, left, and right), which are mounted on a substrate PCB. When the user points upwards in a certain direction and pushes the pressure transmission rod, this pressure is transmitted through the rod, causing downward compression in that direction, resulting in a decrease in resistance; conversely, the resistance in the opposite direction is stretched, resulting in an increase in resistance. These two resistors form a strain gauge pair. An analog circuit applies an excitation voltage to this pair, and their voltage division output is the signal output voltage. Because the strain gauges change resistance under pressure, the signal output voltage also changes accordingly. The analog signal sampling circuit converts this voltage signal into a digital signal, and through a filtering algorithm, maps this numerical change to the mouse output.
[0004] Strain gauge Wheatstone bridges are configured in three ways depending on the measurement purpose: quarter-bridge, half-bridge, or full-bridge. The pointing stick module invented by IBM uses a typical strain gauge Wheatstone bridge for analog signal sampling. A half-bridge configuration is used in the X and Y directions, and a quarter-bridge configuration in the Z direction. The output voltage of the strain gauge Wheatstone bridge is then fed to a comparator or amplifier for analog-to-digital conversion.
[0005] However, the above analog signal sampling method has the following drawbacks:
[0006] 1. When performing analog-to-digital conversion, the sensor is always connected and is easily affected by external factors such as mobile phone radiation and computer motherboards.
[0007] 2. The adjustment range of the Wheatstone bridge without strain resistance in the 1 / 4 and 1 / 2 bridges of the reference voltage strain gauge is relatively small, which requires high sensor matching accuracy, usually within ±1%. This requires the use of laser to adjust the sensor resistance during production, which significantly increases production costs.
[0008] 3. The output signals of strain gauges are relatively small, and can only be output as 1:1 signals, resulting in low signal-to-noise ratio. Summary of the Invention
[0009] The purpose of this invention is to solve the problems in the prior art and provide a pointer analog signal sampling circuit and sampling method.
[0010] To achieve the above objectives, the technical solution of the present invention is as follows:
[0011] A pointing stick analog signal sampling circuit includes a signal source element, an analog multiplexer connected to the signal source element and outputting a voltage signal according to the change of strain resistance in the signal source element, a sampling capacitor connected to the analog multiplexer, and a variable voltage unit, a sensing unit, and a signal processing element connected to the sampling capacitor.
[0012] Preferably, the circuit between the analog multiplexer and the sampling capacitor is provided with switches SW1 and SW6. The two ends of switch SW1 are connected to the analog multiplexer and the sampling capacitor, respectively, and the two ends of switch SW6 are connected to the sampling capacitor and ground, respectively.
[0013] Preferably, the variable voltage unit includes a digital-to-analog converter (DAC) and a switch SW2, with the two ends of the switch SW2 connected to the DAC and a sampling capacitor, respectively. Additionally, the sampling capacitor is connected to a switch SW5, the other end of which is grounded.
[0014] Preferably, the sensing unit includes a switch SW3, a resistor R8, a sensing boost capacitor C4, a voltage divider resistor R6, and a voltage divider resistor R7. The two ends of the resistor R8 are connected to the sensing boost capacitor C4 and the switch SW3, respectively. The switch SW3 is connected to the power supply VCC. The two ends of the sensing boost capacitor C4 are connected to the voltage divider resistor R7 and ground, respectively. The voltage divider resistors R7 and R6 are output to the sampling capacitor.
[0015] Preferably, the inductive boost capacitor C4 is also connected to a switch SW4, which is grounded.
[0016] Preferably, the signal processing element includes a comparator, a logic gate element, and a counter connected in sequence.
[0017] In another preferred embodiment, the sampling capacitor includes a sampling capacitor C1 and a superimposed sampling capacitor unit. The circuit of the analog multiplexer is provided with a switch SW1 and a switch SW6 in sequence. The switch SW6 is grounded. The circuit between the switch SW1 and the switch SW6 is divided into two paths and connected to the sampling capacitor C1 and the superimposed sampling capacitor unit respectively. The sampling capacitor C1 is connected to the variable voltage unit and the sensing unit in sequence. The superimposed sampling capacitor unit is connected to the signal processing element. The superimposed sampling capacitor unit includes a sampling capacitor C2, a switch SW8 and a switch SW13. The sampling capacitor C2 is connected in series with the sampling capacitor C1. The two ends of the switch SW8 are connected to the analog multiplexer (2) and the sampling capacitor C2 respectively. The two ends of the switch SW13 are connected to the sampling capacitor C2 and ground respectively.
[0018] Preferably, the sampling capacitor further includes multiple stacked sampling capacitor units connected in series with the sampling capacitor C1.
[0019] In another preferred embodiment, the sampling capacitor includes sampling capacitor C1 and sampling capacitor C3. A switch SW1 and a switch SW6 are provided on the circuit between the analog multiplexer and sampling capacitor C1. The two ends of switch SW1 are connected to the analog multiplexer and sampling capacitor C1, respectively, and the two ends of switch SW6 are connected to sampling capacitor C1 and ground, respectively. A switch SW9 is provided on the circuit between the analog multiplexer and the signal processing element. Switch SW9 is connected in parallel with switch SW1. A sampling capacitor C3 and a switch SW10 are also provided sequentially on the circuit between switch SW9 and the signal processing element. The two ends of sampling capacitor C3 are connected to switch SW9 and ground, respectively, and the two ends of switch SW10 are connected to the signal processing element and ground, respectively.
[0020] A method for sampling analog signals from a pointing stick includes the following steps:
[0021] Step 1: Reset the circuit to zero the accumulated charge in the sampling capacitor and the induction boost capacitor C4, and reset the counter to zero;
[0022] Step 2: Apply excitation voltage to the signal source component;
[0023] Step 3: Set the variable voltage unit to the predetermined voltage, and position it and the signal source element respectively across the sampling capacitor; wait for a sufficient time to convert the source signal of the signal source element and the bias voltage of the variable voltage unit to the sampling capacitor;
[0024] Step 4: Connect the sensing unit and the sampling capacitor in series to generate a superimposed voltage; increase the voltage of the sensing unit and compare the superimposed voltage of the two with the fixed voltage at the other input of the comparator;
[0025] Step 5: Within a predetermined fixed time, the counter starts counting. Observe the time when the comparator output is high. The change value of the counter is the voltage change value of the corresponding signal source element, completing the analog-to-digital conversion of the pressure change on the pointer to the digital value in the counter.
[0026] A method for sampling analog signals from a pointing stick using multiple series-superimposed sampling capacitors includes the following steps:
[0027] Step 1: Reset the circuit to zero the accumulated charge of sampling capacitor C1, superimposed sampling capacitor unit, and induced boost capacitor C4, and reset the counter to zero;
[0028] Step 2: Apply excitation voltage to the signal source component;
[0029] Step 3: Set the ground and signal source element to be located at the two ends of the superimposed sampling capacitor unit respectively; wait for a sufficient time, and convert the signal of the signal source element and its bias voltage to the superimposed sampling capacitor unit;
[0030] Step 4: Set the variable voltage unit to the predetermined voltage, and position it and the signal source element respectively across the sampling capacitor C1; wait for a sufficient time, and then convert the source signal of the signal source element and the bias voltage of the variable voltage unit to the sampling capacitor C1.
[0031] Step 5: Connect the sensing unit in series with the sampling capacitor C1, and superimpose the sampling capacitor unit to generate a superimposed voltage; increase the voltage of the sensing unit, and compare the superimposed voltage with the fixed voltage at the other input terminal of the comparator;
[0032] Step Six: Within a predetermined fixed time, the counter starts counting. Observe the time when the comparator output is high. The change value of the counter is the voltage change value of the corresponding signal source element, thus completing the analog-to-digital conversion of the pressure change on the pointer to the digital value in the counter.
[0033] A method for sampling analog signals from a pointing stick using superimposed dual-ended sampling capacitors includes the following steps:
[0034] Step 1: Reset the circuit to zero the accumulated charge of sampling capacitor C1, sampling capacitor C3, and induction boost capacitor C4, and reset the counter to zero;
[0035] Step 2: Apply reverse excitation voltage to the signal source element;
[0036] Step 3: Set the ground and signal source element to be located at the two ends of the sampling capacitor C3 at the positive terminal of comparator 51 respectively; wait for a sufficient time, and convert the signal of the signal source element and its bias voltage to the sampling capacitor C3;
[0037] Step 4: Apply excitation voltage to the signal source component;
[0038] Step 5: Set the variable voltage unit to the predetermined voltage, and position it and the signal source element respectively across the sampling capacitor C1; wait for a sufficient time, and then convert the source signal of the signal source element and the bias voltage of the variable voltage unit to the sampling capacitor C1.
[0039] Step 6: Connect the sensing unit and sampling capacitor C1 in series to generate a superimposed voltage; increase the voltage of the sensing unit and compare the superimposed voltage of the two with the voltage of sampling capacitor C3 at the other input of the comparator.
[0040] Step 7: Within a predetermined fixed time, the counter starts counting. Observe the time when the comparator output is high. The change value of the counter is the voltage change value of the corresponding signal source element, thus completing the analog-to-digital conversion of the pressure change on the pointer to the digital value in the counter.
[0041] The beneficial effects of this invention are:
[0042] This invention does not employ the traditional strain gauge Wheatstone bridge 1 / 4 bridge and 1 / 2 bridge, i.e., the signal resistor bridge and the reference voltage resistor bridge form a differential output; instead, it connects the strain gauge signal resistor bridge (signal source element) to one end of a sampling capacitor, connects the variable voltage unit to the other end of the capacitor, waits for a specified time to conduct the signal to the capacitor through charging, disconnects the strain gauge signal resistor bridge, and then further performs analog-to-digital conversion on the signal on the sampling capacitor.
[0043] This method simulates the crucial analog-to-digital conversion step in signal processing, where the sensor is completely disconnected from the circuit, thus reducing interference from external sources such as mobile phones during the conversion process. The circuit, which conducts the signal to a sampling capacitor via charging, is a low-frequency RC filter, which also filters out high-frequency signals from mobile phones and other radiated sources to some extent.
[0044] Furthermore, when transmitting the signal to the sampling capacitor, specifying the voltage of the variable voltage source can correct the resistance matching problem of the sensor in the strain gauge resistor bridge over a wide range. The variable voltage source is usually implemented by a digital-to-analog converter (DAC), and the adjustment range can almost reach the range of 0 to VCC. Therefore, the strain sensor can still work even if the resistance value is more than 20% different from the preset value.
[0045] Furthermore, if this signal conversion process is implemented using multiple sampling capacitors, and the signals on these capacitors are then connected in series and superimposed, followed by further analog-to-digital conversion of the signals on the sampling capacitors, the signal amplitude can be amplified by one or even several times, effectively improving the signal-to-noise ratio. Attached Figure Description
[0046] Figure 1 This is a schematic diagram of the structure of a pointing stick module in the prior art;
[0047] Figure 2 A schematic diagram of a 1 / 4 bridge configuration for a strain gauge Wheatstone bridge.
[0048] Figure 3 A schematic diagram of a 1 / 2 bridge configuration for a strain gauge Wheatstone bridge.
[0049] Figure 4 A schematic diagram of a full-bridge configuration for a strain gauge Wheatstone bridge.
[0050] Figure 5 This is a circuit diagram of the basic circuit scheme in Example 1;
[0051] Figure 6 This is a flowchart of the sampling method in Example 1;
[0052] Figure 7 Here is a circuit diagram of the double sampling capacitor circuit scheme in Example 2;
[0053] Figure 8 The circuit diagram of the multiple sampling capacitor circuit scheme in Example 2 is shown below.
[0054] Figure 9 This is a flowchart of the sampling method in Example 2;
[0055] Figure 10 This is a circuit diagram of the dual-ended sampling capacitor circuit scheme in Example 3;
[0056] Figure 11 This is a flowchart of the sampling method in Example 3;
[0057] Figure 12 The circuit diagram for the control chip implementation. Detailed Implementation
[0058] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0059] Example 1
[0060] Basic circuit scheme, circuit structure as follows Figure 5 As shown, the method flow is as follows: Figure 6 As shown.
[0061] Step 1: Reset Circuit. Set all circuits to the reset state as follows: switches SW1, SW6, SW5, and SW4 are in the connected state; switches SW2 and SW3 are in the disconnected state. This state resets the accumulated charge of sampling capacitor C1 and sensing boost capacitor C4 to zero; counter 53 (COUNTER) is reset to zero; and logic gate element 52 (COUTEN) is disabled.
[0062] Step 2: Apply excitation voltage to the pointing stick sensor resistor pair (signal source element 1). If X channel XSIG is selected, apply power supply voltage XYDRV to VCC and CDRV to GND; the strain gauge pairs R1 and R2 in the X direction generate a voltage divider output XSIG. The XSIG voltage signal reflects the change in strain resistance caused by the force applied to the pointing stick. The same logic applies to YSIG and ZSIG.
[0063] Step 3: Set the variable voltage unit 3 to a predetermined voltage, and position it and the signal source element 1 respectively across the sampling capacitor; wait for a sufficient time to convert the signal of the signal source element 1 and the bias voltage of the variable voltage unit 3 to the sampling capacitor.
[0064] Specifically, disconnect switches SW5 and SW6; connect switch SW1; set the digital-to-analog converter (DAC) in variable voltage unit 3 to a predetermined voltage; then connect switch SW2; wait sufficient time for the signal on SIGNAL to be fully transferred to the sampling capacitor C1. The voltage difference between the DAC and SIGNAL is also transferred to the sampling capacitor C1. This superimposed voltage on the sampling capacitor C1 is slightly lower than the fixed voltage VREF at the positive terminal of comparator 51. After completion, disconnect switches SW1 and SW2.
[0065] Step 4: Connect the sensing unit 4 in series with the sampling capacitor to generate a superimposed voltage; increase the voltage of the sensing unit 4, and compare the superimposed voltage of the two with the fixed voltage at the other input terminal of the comparator 51.
[0066] Specifically, switch SW4 is disconnected; switch SW3 is connected, and VCC charges the sensing boost capacitor C4 of sensing unit 4. The voltage is divided by resistors R7 and R6, and then superimposed with the voltage accumulated by sampling capacitor C1 in step three and input to the negative terminal of comparator 51 (CMP).
[0067] Step 5: Within a predetermined fixed time, counter 53 starts counting. Observe the time when the output of comparator 51 is high. The change value of counter 53 is the voltage change value of the corresponding signal source element 1, which is also the pressure change value acting on the pointer.
[0068] Specifically, because the voltage accumulated on the sampling capacitor C1 is slightly lower than the positive input voltage VREF of comparator 51, the COUT output is positive. This enables logic gate 52 (COUTEN), and the comparator 51 output enables counter 53 (COUNTER). Counter 53 (COUNTER) counts the time COUT is positive. When the boost capacitor C4 of sensing unit 4 charges beyond a certain value, the voltage superimposed between sensing unit 4 and sampling capacitor C1 exceeds the fixed positive voltage VREF of comparator 51 (CMP), causing the comparator 51 output COUT to change from positive to negative, and counter 53 (COUNTER) stops counting. At this time, the value of counter 53 (COUNTER) corresponds to the voltage value in SIGNAL. When the pressure applied to the pointing stick changes, the voltage value in SIGNAL also changes slightly, and this slight change also causes a change in the value of counter 53 (COUNTER). This completes the analog-to-digital conversion of the analog value of the pressure change on the pointing stick to the digital value in counter 53 (COUNTER).
[0069] Example 2
[0070] The double sampling capacitor circuit scheme has the following circuit structure: Figure 7 As shown, the method flow is as follows: Figure 9 As shown.
[0071] In the basic circuit, the signal is converted to the sampling capacitor C1 through a charging process. To improve the signal-to-noise ratio, this conversion process can be repeated multiple times to multiple sampling capacitors. These sampling capacitors are then connected in series to amplify the signal. The following steps demonstrate adding a superimposed sampling capacitor unit 7 (mainly the sampling capacitor C2 within it) to the basic circuit to convert the signal to the superimposed sampling capacitor unit 7. The design of multiple sampling capacitors can be deduced similarly.
[0072] Step 1: Reset Circuit. Set all circuits to the reset state as follows: switches SW1, SW8, SW13, SW5, and SW4 are in the connected state; switches SW2 and SW3 are in the disconnected state. This state resets the accumulated charge of sampling capacitors C1, C2, and C4 to zero; counter 53 (COUNTER) is reset to zero; and logic gate element 52 (COUTEN) is disabled.
[0073] Step 2: Apply excitation voltage to the pointing stick sensor resistor pair (signal source element). If X channel XSIG is selected, apply power supply voltage XYDRV to VCC and CDRV to GND; the strain gauge pairs R1 and R2 in the X direction will generate a voltage divider output XSIG. The XSIG voltage signal reflects the change in strain resistance caused by the force applied to the pointing stick. The same logic applies to YSIG and ZSIG.
[0074] Step 3: Set the ground and signal source element 1 to be located at the two ends of sampling capacitor C2 respectively; wait for a sufficient time to convert the signal of signal source element 1 and its bias voltage to sampling capacitor C2.
[0075] Specifically, disconnect switches SW1 and SW13, and connect switch SW8; wait sufficient time for the signal on SIGNAL to be fully transferred to the sampling capacitor C2. The bias voltage generated by the resistor on SIGNAL and the signal voltage generated by the pressure change are both transferred to the sampling capacitor C2. After completion, disconnect switch SW8.
[0076] Step 4: Set the variable voltage unit 3 to a predetermined voltage, and position it and the signal source element 1 respectively across the sampling capacitor C1; wait for a sufficient time, and then convert the signal of the signal source element 1 and the bias voltage of the variable voltage unit 3 to the sampling capacitor C1.
[0077] Specifically, disconnect switches SW5 and SW6; connect switch SW1; set the digital-to-analog converter (DAC) in variable voltage unit 3 to a predetermined voltage; then connect switch SW2; wait sufficient time for the signal on SIGNAL to be fully transferred to sampling capacitor C1. The voltage difference between the DAC and SIGNAL is also transferred to sampling capacitor C1. The sum of this superimposed voltage on sampling capacitor C1 and the voltage formed on sampling capacitor C2 in step three is slightly lower than the fixed voltage VREF at the positive terminal of comparator 51. After completion, disconnect switches SW1 and SW2.
[0078] Step 5: Connect the sensing unit 4 in series with the sampling capacitors C1 and C2 to generate a superimposed voltage; increase the voltage of the sensing unit 4, and compare the superimposed voltage of the three with the fixed voltage at the other input terminal of the comparator 51.
[0079] Specifically, switch SW4 is disconnected; switch SW3 is connected, and VCC charges the boost capacitor C4 of sensing unit 4. The voltage is divided by resistors R7 and R6, and then superimposed with the voltage accumulated by sampling capacitor C1 in step four and the voltage accumulated by sampling voltage C2 in step three, and input to the negative terminal of comparator 51 (CMP).
[0080] Step Six: Within a predetermined fixed time period, counter 53 starts counting, and the duration of the comparator 51 output being high is observed. The change value of counter 53 corresponds to the voltage change value of the signal source element 1, which is also the pressure change value acting on the pointer.
[0081] Specifically, because the sum of the voltages accumulated on sampling capacitors C1 and C2 is slightly lower than the positive input voltage VREF of comparator 51, the COUT output is positive. This enables logic gate 52 (COUTEN), and the comparator 51 output enables counter 53 (COUNTER). Counter 53 (COUNTER) counts the time COUT is positive. When the boost capacitor C4 of sensing unit 4 charges beyond a certain value, the voltage superimposed on sensing unit 4 and sampling capacitor C1 exceeds the fixed positive voltage VREF of comparator 51 (CMP), causing the comparator 51 output COUT to change from positive to negative, and counter 53 (COUNTER) stops counting. At this time, the value of counter 53 (COUNTER) corresponds to the voltage value in SIGNAL. When the pressure applied to the pointing stick changes, the voltage value in SIGNAL also changes slightly, and this slight change also causes a change in the value of counter 53 (COUNTER). This completes the analog-to-digital conversion of the analog value of the pressure change on the pointing stick to the digital value in counter 53 (COUNTER).
[0082] In addition, the multi-sampling capacitor circuit scheme has the following circuit structure: Figure 8 As shown.
[0083] The sampling capacitor C1 is connected in series with multiple superimposed sampling capacitor units 7. The sampling method is the same as the above method. The difference is that in step three, the multiple superimposed sampling capacitor units are operated sequentially from right to left as above, so that the signal on SIGNAL is completely transferred to the sampling capacitors C2_N, C2_N-1, and finally to C2.
[0084] Example 3
[0085] The dual-ended sampling capacitor circuit scheme has the following circuit structure: Figure 10 As shown, the method flow is as follows: Figure 11 As shown.
[0086] In the basic circuit, the signal is transferred to the sampling capacitor C1 through the charging process. To improve the signal-to-noise ratio, an additional sampling capacitor C3 can be added at the positive terminal of comparator 51, and then the sampling capacitor C1 at the negative terminal and the sampling capacitor C3 at the positive terminal are compared. However, the polarity of the signals at both ends needs to be reversed to produce a doubled effect, thus avoiding mutual cancellation.
[0087] Step 1: Reset Circuit. Set all circuits to the reset state as follows: Switches SW1, SW6, SW5, SW4, SW9, and SW10 are in the connected state; switches SW2 and SW3 are in the disconnected state. This state resets the accumulated charge of sampling capacitors C1, C3, and C4 to zero; counter 53 (COUNTER) is reset to zero; and logic gate element 52 (COUTEN) is disabled.
[0088] Step 2: Apply a reverse excitation voltage to the pointing stick sensor resistor pair (signal source element). If X channel XSIG is selected, apply the power supply voltage XYDRV to GND and CDRV to VCC; the strain gauge pair R1 and R2 in the X direction will generate a voltage divider output XSIG. The XSIG voltage signal reflects the reverse change in strain gauge caused by the force applied to the pointing stick. The same logic applies to YSIG and ZSIG.
[0089] Step 3: Set the ground and signal source element 1 to be located at the two ends of the sampling capacitor C3 at the positive terminal of comparator 51 respectively; wait for a sufficient time to convert the signal of signal source element 1 and its bias voltage to the sampling capacitor C3.
[0090] Specifically, disconnect switches SW1 and SW10, and connect switch SW9; wait sufficient time for the signal on SIGNAL to be fully transferred to the sampling capacitor C3 at the positive input of comparator 51. The bias voltage generated by the resistor on SIGNAL and the signal voltage generated by the pressure change are both transferred to the sampling capacitor C3. After completion, disconnect switch SW9.
[0091] Step 4: Apply a positive excitation voltage to the pointing stick sensor resistor pair (signal source element). If X channel XSIG is selected, apply the power supply voltage XYDRV to VCC and CDRV to GND; the strain gauge pair R1 and R2 in the X direction will generate a voltage divider output XSIG. The XSIG voltage signal reflects the change in strain resistance caused by the force applied to the pointing stick. The same logic applies to YSIG and ZSIG.
[0092] Step 5: Set the variable voltage unit 3 to a predetermined voltage, and position it and the signal source element 1 respectively across the sampling capacitor C1; wait for a sufficient time, and then convert the signal of the signal source element 1 and the bias voltage of the variable voltage unit 3 to the sampling capacitor C1.
[0093] Specifically, disconnect switches SW5 and SW6; connect switch SW1; set the digital-to-analog converter (DAC) in variable voltage unit 3 to a predetermined voltage; connect switch SW2; wait sufficient time for the signal on SIGNAL to be fully transferred to sampling capacitor C1. The voltage difference between the DAC and SIGNAL is also transferred to sampling capacitor C1. This superimposed voltage on sampling capacitor C1 is slightly lower than the voltage formed on sampling capacitor C3 in step three. After completion, disconnect switches SW1 and SW2.
[0094] Step 6: Connect the sensing unit 4 in series with the sampling capacitor C1 to generate a superimposed voltage; increase the voltage of the sensing unit 4, and compare the superimposed voltage of the two with the voltage of the sampling capacitor C3 at the other input terminal of the comparator 51.
[0095] Specifically, switch SW4 is disconnected; switch SW3 is connected, and VCC charges the boost capacitor C4 of sensing unit 4. The voltage is divided by resistors R7 and R6, and then superimposed with the voltage accumulated by sampling capacitor C1 in step five and input to the negative terminal of comparator 51CMP.
[0096] Step 7: Within a predetermined fixed time period, counter 53 starts counting and observes the duration when the comparator 51 outputs a high value. The change in the counter 53 value corresponds to the voltage change of the signal source element 1, which is also the pressure change applied to the pointer.
[0097] Specifically, because the voltage across the sampling capacitor C1 at the negative terminal of comparator 51 is slightly lower than the input voltage of the sampling capacitor C3 at the positive terminal of comparator 51, the COUT output is positive. This enables logic gate element 52 (COUTEN), and the output of comparator 51 enables counter 53 (COUNTER). Counter 53 (COUNTER) counts the time COUT is positive. When the boost capacitor C4 of sensing unit 4 charges beyond a certain value, the voltage superimposed between sensing unit 4 and sampling capacitor C1 exceeds the voltage of sampling capacitor C3 at the positive terminal of comparator 51 (CMP), causing the comparator 51 output COUT to change from positive to negative, and counter 53 (COUNTER) stops counting. At this time, the value of counter 53 (COUNTER) corresponds to the voltage value in SIGNAL. When the pressure applied to the pointing stick changes, the voltage value in SIGNAL also changes slightly, and this slight change also causes a change in the value of counter 53 (COUNTER). This completes the analog-to-digital conversion of the analog value of the pressure change on the pointing stick to the digital value in counter 53 (COUNTER). Because both the sampling capacitor C3 at the positive terminal of comparator 51 and the sampling capacitor C1 at the negative terminal of comparator 51 contain voltage change signals generated by pressure changes, and their polarities are opposite, the signal change is doubled.
[0098] In addition, such as Figure 12 As shown, only some resistors, capacitors and other components are needed to complete the various control circuits and algorithms in the above scheme, thereby achieving the goal of increasing the signal, reducing external components and lowering costs.
[0099] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A pointing stick analog signal sampling circuit, characterized in that: It includes a signal source element (1), an analog multiplexer (2) connected to the signal source element (1) and outputting a voltage signal according to the change of the strain resistance in the signal source element (1), a sampling capacitor connected to the analog multiplexer (2), a variable voltage unit (3) connected to the sampling capacitor, a sensing unit (4) and a signal processing element (5).
2. The analog signal sampling circuit for the pointing stick according to claim 1, characterized in that: The circuit between the analog multiplexer (2) and the sampling capacitor is equipped with switches SW1 and SW6. The two ends of switch SW1 are connected to the analog multiplexer (2) and the sampling capacitor, respectively, and the two ends of switch SW6 are connected to the sampling capacitor and ground, respectively.
3. The analog signal sampling circuit for the pointing stick according to claim 1 or 2, characterized in that: The variable voltage unit (3) includes a digital-to-analog converter (DAC) and a switch SW2, with the two ends of the switch SW2 connected to the DAC and the sampling capacitor, respectively.
4. The analog signal sampling circuit for the pointing stick according to claim 1 or 2, characterized in that: The sensing unit (4) includes a switch SW3, a resistor R8, a sensing boost capacitor C4, a voltage divider resistor R6 and a voltage divider resistor R7. The two ends of the resistor R8 are connected to the sensing boost capacitor C4 and the switch SW3 respectively. The switch SW3 is connected to the power supply VCC. The two ends of the sensing boost capacitor C4 are connected to the voltage divider resistor R7 and ground respectively. The voltage divider resistors R7 and R6 are output to the sampling capacitor.
5. The analog signal sampling circuit for the pointing stick according to claim 4, characterized in that: The inductive boost capacitor C4 is also connected to a switch SW4, which is grounded.
6. The analog signal sampling circuit for the pointing stick according to claim 1, characterized in that: The signal processing element (5) includes a comparator (51), a logic gate element (52), and a counter (53) connected in sequence.
7. The analog signal sampling circuit for the pointing stick according to claim 1, characterized in that: The sampling capacitor includes a sampling capacitor C1 and a superimposed sampling capacitor unit (7). The circuit of the analog multiplexer (2) is provided with a switch SW1 and a switch SW6 in sequence. The switch SW6 is grounded. The circuit between the switch SW1 and the switch SW6 is divided into two paths and connected to the sampling capacitor C1 and the superimposed sampling capacitor unit (7) respectively. The sampling capacitor C1 is connected to the variable voltage unit (3) and the sensing unit (4) in sequence. The superimposed sampling capacitor unit (7) is connected to the signal processing element (5). The superimposed sampling capacitor unit (7) includes a sampling capacitor C2, a switch SW8 and a switch SW13. The sampling capacitor C2 is connected in series with the sampling capacitor C1. The two ends of the switch SW8 are connected to the analog multiplexer (2) and the sampling capacitor C2 respectively. The two ends of the switch SW13 are connected to the sampling capacitor C2 and ground respectively.
8. The analog signal sampling circuit for the pointing stick according to claim 7, characterized in that: The sampling capacitor also includes multiple superimposed sampling capacitor units (7) connected in series with the sampling capacitor C1.
9. The analog signal sampling circuit for the pointing stick according to claim 1, characterized in that: The sampling capacitors include sampling capacitor C1 and sampling capacitor C3. Switches SW1 and SW6 are provided on the circuit between the analog multiplexer (2) and sampling capacitor C1. The two ends of switch SW1 are connected to the analog multiplexer (2) and sampling capacitor C1 respectively, and the two ends of switch SW6 are connected to sampling capacitor C1 and ground respectively. Switch SW9 is provided on the circuit between the analog multiplexer (2) and signal processing element (5). Switch SW9 is connected in parallel with switch SW1. Sampling capacitor C3 and switch SW10 are also provided on the circuit between switch SW9 and signal processing element (5). The two ends of sampling capacitor C3 are connected to switch SW9 and ground respectively, and the two ends of switch SW10 are connected to signal processing element (5) and ground respectively.
10. A method for sampling analog signals from a pointing stick, characterized in that: Includes the following steps, Step 1: Reset the circuit to zero the accumulated charge of the sampling capacitor and the induction boost capacitor C4, and reset the counter (53) to zero; Step 2: Apply excitation voltage to the signal source element (1); Step 3: Set the variable voltage unit (3) to a predetermined voltage, and position it at both ends of the sampling capacitor, respectively, along with the signal source element (1); Wait for a sufficient amount of time to convert the source signal of the signal source element (1) and the bias voltage of the variable voltage unit (3) to the sampling capacitor; Step 4: Connect the sensing unit (4) and the sampling capacitor in series to generate a superimposed voltage; increase the voltage of the sensing unit (4) and compare the superimposed voltage of the two with the fixed voltage at the other input terminal of the comparator (51); Step 5: Within a predetermined fixed time, the counter (53) starts counting. Observe the time when the comparator (51) output is high. The change value of the counter (53) is the voltage change value of the corresponding signal source element (1), completing the analog-to-digital conversion of the pressure change on the pointer to the digital value in the counter (53).
11. A method for sampling analog signals of a pointing stick using multiple series-superimposed sampling capacitors, characterized in that: Includes the following steps, Step 1: Reset the circuit to zero the accumulated charge of sampling capacitor C1, superimposed sampling capacitor unit (7), and induced boost capacitor C4, and reset the counter (53) to zero; Step 2: Apply excitation voltage to the signal source element (1); Step 3: Set the ground and signal source element (1) to be located at both ends of the superimposed sampling capacitor unit (7); Wait for a sufficient time to convert the signal source element (1) signal and its bias voltage to the superimposed sampling capacitor unit (7). Step 4: Set the variable voltage unit (3) to a predetermined voltage, and position it at both ends of the sampling capacitor C1, respectively, along with the signal source element (1); Wait for a sufficient amount of time to convert the source signal of the signal source element (1) and the bias voltage of the variable voltage unit (3) to the sampling capacitor C1; Step 5: Connect the induction unit (4) in series with the sampling capacitor C1 and the sampling capacitor unit (7) to generate a superimposed voltage; increase the voltage of the induction unit (4) and compare the superimposed voltage with the fixed voltage at the other input terminal of the comparator (51); Step 6: Within a predetermined fixed time, the counter (53) starts counting. Observe the time when the comparator (51) output is high. The change value of the counter (53) is the voltage change value of the corresponding signal source element (1), completing the analog-to-digital conversion of the pressure change on the pointer to the digital value in the counter (53).
12. A method for sampling analog signals of a pointing stick using superimposed dual-ended sampling capacitors, characterized in that: Includes the following steps, Step 1: Reset the circuit to zero the accumulated charge of sampling capacitor C1, sampling capacitor C3, and induction boost capacitor C4, and reset the counter (53) to zero; Step 2: Apply reverse excitation voltage to the signal source element (1); Step 3: Set the ground and signal source components (1) to be located at the two ends of the sampling capacitor C3 at the positive terminal of comparator 51 respectively; Wait for a sufficient amount of time to convert the signal source element (1) signal and its bias voltage to the sampling capacitor C3; Step 4: Apply excitation voltage to the signal source element (1); Step 5: Set the variable voltage unit (3) to the predetermined voltage, and position it at both ends of the sampling capacitor C1, respectively, along with the signal source element (1); Wait for a sufficient amount of time to convert the source signal of the signal source element (1) and the bias voltage of the variable voltage unit (3) to the sampling capacitor C1; Step 6: Connect the sensing unit (4) in series with the sampling capacitor C1 to generate a superimposed voltage; increase the voltage of the sensing unit (4) and compare the superimposed voltage of the two with the voltage of the sampling capacitor C3 at the other input terminal of the comparator (51); Step 7: Within a predetermined fixed time, the counter (53) starts counting. Observe the time when the comparator (51) output is high. The change value of the counter (53) is the voltage change value of the corresponding signal source element (1), completing the analog-to-digital conversion of the analog value of the pressure change on the pointer to the digital value in the counter (53).