Pipeline architecture for bitwise multiplier-accumulator (MAC)

Abstract

A unit for accumulating multiple M-bit values ​​multiplied by N includes: a receiving unit, a bitwise multiplier, and a bitwise accumulator. The receiving unit receives pipelined multiplicands A and B, such that a new set of multiplicands is received in each cycle. The bitwise multiplier multiplies the bits of the current multiplicand A with the bits of the current multiplicand B bitwise, and sums and carries between the bitwise multipliers. The bitwise accumulator accumulates the outputs of the bitwise multipliers, thereby accumulating the multiplicands during the pipelined process.

Description

[0001] This application is a divisional application of the same patent application filed on May 11, 2020, with application number 202010391403.9. Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application 62 / 850,033, filed May 20, 2019, which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to multiply-accumulate units. Background Technology

[0004] Multiplier-accumulator (MAC) is known in the art and is a common operation used to handle the summation of large numbers of multiplications. This operation is common in dot product multiplication and matrix multiplication, which are common in image processing, as well as in convolution used in neural networks.

[0005] In mathematics, the multiplication-addition operation is: , Formula 1 Where A i and k i It can be an 8-bit, 16-bit, or 32-bit word.

[0006] In the code, the MAC operation is: q i =q i +(A i *k i ), Formula 2 Where q i Variable cumulative value A i k i .

[0007] Because MAC operations are so common, they are typically implemented in hardware as separate units within a central processing unit (CPU) or digital signal processor (DSP). A typical MAC has a multiplier, adder, and accumulator register implemented using combinational logic. The output of the multiplier is fed into the adder, and the output of the adder is fed into the accumulator register. The output of the accumulator register is fed back to one input of the adder, thus generating an accumulation operation between the previous result and the new multiplication result. At the end of each clock cycle, the output of the multiplier is added to the register.

[0008] The multiplier section of a MAC is typically implemented using combinational logic, while the adder section is typically implemented as an accumulator register that stores the result. Summary of the Invention

[0009] Therefore, according to a preferred embodiment of the present invention, a method for accumulating multiple M-bit values ​​of N multiplications is provided. The method includes pipelined multiplicands A and B into a multiplier-accumulator such that a new set of multiplicands is received in each cycle; in each cycle, bitwise multiplication of the current multiplicand A with the current multiplicand B, and summation and carry between bit multipliers; and in each cycle, bitwise accumulation of the output of the bitwise multiplication, thereby accumulating the multiplicands during the pipelined process.

[0010] According to a preferred embodiment of the present invention, a method for accumulating multiple M-bit values ​​of N multiplications is also provided. The method includes performing the following steps for each pair of multiplicands A and B, each having M bits. In M rows, each having M multiplication units, each bit of multiplicand A is multiplied individually by each bit of multiplicand B, and the result from the row preceding the multiplication unit is summed individually. In the summation units of the M rows following the multiplication units, the result from the row preceding the summation unit or multiplication unit is summed individually. Rows are summed toward the output of an accumulator formed as columns. In the accumulator units, each bit of the result from the bit output of each row is accumulated individually, and the carry value is passed along the bits of the result from the LSB (least significant bit) to the MSB (most significant bit).

[0011] Furthermore, according to a preferred embodiment of the present invention, the multiplication unit, the summation unit, and the accumulator unit are bitline processors.

[0012] Furthermore, according to a preferred embodiment of the invention, the method further includes providing a new pair of multiplicands A and B to the top row of the multiplication unit in each operation cycle.

[0013] Furthermore, according to a preferred embodiment of the invention, summing individually includes at least: generating a sum and a carry value of at least one of the multiplication unit and the summing unit, and passing the carry value down one row and passing the sum value to the right and down one row in each cycle.

[0014] Additionally, according to a preferred embodiment of the invention, the method includes: passing a row down the bits of the multiplier A in each cycle, and passing a row right and down the bits of the multiplier B in each cycle.

[0015] Furthermore, according to a preferred embodiment of the invention, M is a power of 2.

[0016] Furthermore, according to a preferred embodiment of the invention, the method includes: after providing a stop, storing one bit of the result individually for each cycle, the storage starting at the LSB and moving toward the MSB.

[0017] Furthermore, according to a preferred embodiment of the present invention, when N is 1, the output of the accumulator is the multiplication of multiplicands A and B.

[0018] According to a preferred embodiment of the invention, a unit for accumulating multiple M-bit values ​​multiplied by N is also provided. The unit includes a receiving unit, a bitwise multiplier, and a bitwise accumulator. The receiving unit receives pipelined multiplicands A and B such that a new set of multiplicands is received in each cycle. The bitwise multiplier multiplies the bits of the current multiplicand A with the bits of the current multiplicand B bitwise, and sums and carries between the bitwise multipliers. The bitwise accumulator accumulates the outputs of the bitwise multipliers, thereby accumulating the multiplicands during the pipelined process.

[0019] Furthermore, according to a preferred embodiment of the invention, the bitwise multiplier includes M rows, each having M multiplication units, and M rows of summation units following the M rows of multiplication units, wherein each row includes M summation units. Each multiplication unit individually multiplies each bit of the multiplicand A with each bit of the multiplicand B, and individually sums the results from the row preceding the multiplication unit. Each summation unit individually sums the results from the row preceding either the summation unit or the multiplication unit, wherein the rows sum towards the output of the bitwise accumulator.

[0020] Furthermore, according to a preferred embodiment of the invention, the bitwise accumulator includes accumulator units formed as columns. Each accumulator unit individually accumulates the bits of the result from the bit output of its associated row, and passes the carry value along the bits of the result from the LSB (least significant bit) to the MSB (most significant bit).

[0021] Furthermore, according to a preferred embodiment of the present invention, the multiplication unit, the summation unit, and the accumulator unit are bitline processors.

[0022] Furthermore, according to a preferred embodiment of the invention, the top row of the multiplication unit receives a new pair of multiplicands A and B in each operation cycle.

[0023] Furthermore, according to a preferred embodiment of the invention, the summing unit communicates with the summing unit in the next row to pass the carry value down one row in each cycle, and to pass the sum value to the right and down one row.

[0024] Furthermore, according to a preferred embodiment of the invention, the multiplication unit communicates with the multiplication unit in the next row to pass the bits of the multiplier A down a row in each cycle.

[0025] Furthermore, according to a preferred embodiment of the invention, the unit further includes a bit-transfer unit for transferring each bit of the multiplier B to its associated row in the multiplication unit.

[0026] Furthermore, according to a preferred embodiment of the present invention, when N is 1, the output of the bitwise accumulator is the multiplication of multiplicands A and B. Attached Figure Description

[0027] The subject matter considered to be the present invention is specifically pointed out and explicitly claimed in the concluding section of the specification. However, the invention can be best understood, with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic diagram of a pipelined multiplier-accumulator constructed and operable according to a preferred embodiment of the present invention; Figure 2A , Figure 2B and Figure 2C They are in Figure 1 A schematic diagram of the multiplier processor, summer processor, and accumulator processor used in a multiplier-accumulator; Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H and Figure 3I These diagrams illustrate how data moves through the bitwise multiplier-accumulator 100 over nine cycles. These diagrams help to understand... Figure 1 Pipelined multiplier-accumulator; and Figure 4 This is a schematic diagram of three adjacent multiplication bitline processors 110M.

[0028] It should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be enlarged relative to others. Furthermore, reference numerals may be repeated in the figures where deemed appropriate to indicate corresponding or similar elements. Detailed Implementation

[0029] Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail to avoid obscuring the invention.

[0030] The applicant has recognized that results can be accumulated during multiplication. This is significantly faster and more efficient than accumulating only once a pair of values ​​has been multiplied. Furthermore, since the multiplier and accumulator are part of a single unit, rather than two separate units, it reduces chip footprint.

[0031] The applicant has further realized that when the multiplier and accumulator are part of a single unit, that unit should accumulate each bit separately when processing carry values. Furthermore, once each bit is processed individually, the operation can be pipelined. The applicant has also realized that when only one multiplication operation is provided to this pipelined multiplier-accumulator unit, the pipelined multiplier-accumulator unit can also perform only the multiplication. Then the accumulation is a single result.

[0032] Now for reference Figure 1 , Figure 1 A bitwise multiplier-accumulator 100 constructed and operable according to a preferred embodiment of the invention is shown. The bitwise multiplier-accumulator 100 can be implemented in an in-memory associative processor, for example, those discussed in U.S. Patents 8,238,173, 9,418,719, and 9,558,812, currently owned by the applicant of this application and incorporated herein by reference. The in-memory processor processes data in a memory array having multiple memory cells in the form of a matrix of rows and columns, with these columns organized into the processor. When multiple rows are activated together, Boolean operations occur in the processor, where the results are read in the processor's column decoder.

[0033] The bitwise multiplier-accumulator 100 includes separate input units 102A and 102B for each multiplicand A and B, a bitwise multiplier unit 104, and a bitwise accumulator unit 106, wherein each unit 102, 104, and 106 may be comprised of a plurality of processors 110, which can operate on a bit or a pair of bits (a bit from each of multiplicand A and multiplicand B) during each operation cycle. The processors 110 can be any suitable processor and can be implemented as bit-line processors 110 as described in the examples herein, which are described in more detail below.

[0034] In the bitwise multiplier-accumulator 100, the processor 110 can be configured as rows and columns, wherein the input unit 102A can be formed by a single row of the processor 110 above the multiplier 104, the accumulator 106 can be located to the right of the bitwise multiplier 104, and the input unit 102B can be located to the left of the upper portion of the bitwise multiplier 104.

[0035] The bitwise multiplier-accumulator 100 can perform operations on multiplicands A and B, which can have 4, 8, 16, 32, 64, or more bits as needed. Figure 1 In the example, the bitwise multiplier-accumulator operates only on the 4-bit multiplicands A and B.

[0036] The input unit 102A may include a row of M receiver processors 110A, where M is the number of bits in the multiplicand A, and where... Figure 1 M is 4. In each operation cycle, each processor 110A can receive one bit of the current multiplicand A, where the least significant bit A0 of the multiplicand A can be located at the rightmost end of the row, and the most significant bit A3 can be located at the leftmost end of the row. In the next operation cycle, processor 110A can pass the value stored therein from the previous cycle to the first row of processor 110M of multiplier 104, and can receive bits from the next multiplicand A. Therefore, for input unit 102A, all bits can be shifted down (i.e., vertically) one row in each cycle. As can be seen, for M cycles, the bits of multiplicand A are passed down to the next row. Therefore, Figure 1 The first four rows of the multiplier 104 in the diagram show bits A3–A0 from left to right.

[0037] Input unit 102A can provide the bits of multiplicand A to the next row in each cycle; however, according to a preferred embodiment of the invention, as described in more detail below, most of the processors 110 in the multiplier-accumulator 100 can pass their data down and to the right (towards accumulator 106) in each cycle.

[0038] Input unit 102B may include three types of processors 110: 1) a line receive processor 110A, which is typically aligned in the same line as processor 110A of input unit 102A; 2) a data transfer processor 110B, which can transfer the value stored therein from the previous cycle down and right in each cycle (as shown by slanted arrow 111); and 3) a signaling processor 110C, which can provide the value stored therein to the signaling line 112 that provides input to the line processor 110 in multiplier 104.

[0039] It should be understood that the signaling processor 110C can provide the associated bits of the multiplicand B to each of the first M rows of the bitwise multiplier 104. Furthermore, the data transfer processor 110B can be configured in a triangular shape to provide different bit values ​​to each of the first M rows of the multiplier 104. Therefore, the input unit 102B can provide the least significant bit B0 of the multiplicand B to the first row of the multiplier 104, the next significant bit of the multiplicand B to the second row of the multiplier 104, and so on. Figure 1 Four rows are shown, each receiving different bits of the multiplicand B along its signaling line 112. Figure 1 It also shows four columns, each receiving different bits of the multiplicand A, with the least significant bit on the right, the next significant bit on the left, and so on.

[0040] Bitwise multiplier unit 104 may include an MxM matrix of multiplier processors 110M and M rows of summer processors 110S. Each multiplier processor 110M in the first row of multiplier 104 can receive one multiplicand A and one multiplicand B as input, multiply them together, and produce a two-bit result (recall 1+1=10 in binary). These two bits are called the "sum" bit and the "carry" bit, where the sum is the rightmost bit of the result and the carry is the leftmost bit of the result (e.g., for 1+1=10, the sum bit is 0 and the carry bit is 1).

[0041] The remaining multiplication processors 110M can receive the sum bit (from the processor above and to its left), the carry bit, and the bit from the multiplicand A (from the processor above it), as well as the bit from the multiplicand B from its signaling line 112. These processors 110M can perform multiplication between their multiplicand bits (to which the sum and carry can be added), generating new sum bits and carry bits as output. Figure 1 In this process, the multiplier processor 110M is marked by the multiplicand digits they are multiplying.

[0042] For example, multiplier processor 110M-E can receive the value of bit A1 from the multiplier processor performing the multiplication A1*B1 directly above it, and can receive the value of bit B2 from its associated signaling line 112. Multiplier processor 110M-E can perform the multiplication A1*B2, and can add the sum S21 from the multiplication A2*B1 in the row above and to the left, and the carry C11 from the multiplication A1*B1 directly above it. Multiplier processor 110M-E can provide its sum S12 to the multiplier processor to perform the operation A0*B3 (e.g., the sum bit S12 is shifted down and to the right) and provide its carry C12 and the value of A1 to the multiplier processor to perform the operation A1*B3 (e.g., the carry bit C12 and bit A are shifted down).

[0043] like Figure 1 As can be seen, the multiplier processor 110M can provide their carry bits Cij (where i is the index of their A bits and j is the index of their B bits) and their multiplicand bits Ai vertically downwards to the multiplier processor 110M of the next row, and can provide their sum bits Sij downwards and to the right (i.e., to the multiplier processor 110M of the column to the right of the next row). Note that in this application, the i index refers to the column, and the j index refers to the row (each Ai bit in the column remains unchanged, while each Bj bit in the row remains unchanged).

[0044] It should be understood that for the MSB (most significant bit) bit ( Figure 1The multiplication processor 110M for operation A3 in the example only accepts the multiplicand ( Figure 1 In the example, A3 and Bj), and only the sum bit is generated as a result. The rest of unit 110M can receive the sum bit and the carry bit. It will be further understood that for the LSB (least significant bit) bit ( Figure 1 In the example, the multiplication processor 110M of the A0 operation can pass its sum bit to the bitwise accumulator unit 106.

[0045] Each summing processor 110S in the second part of multiplier 104 can be an adder processor 110SA that performs addition only on its inputs, or a data transfer processor 110SB that can pass the carry value stored therein from the previous cycle down and to the right in each cycle. No type of summing processor 110S receives any multiplicand bits as input.

[0046] Each summation processor 110SA can add the sum bit (from the processor above and to its left) and the carry bit (from the processor above it), and can provide the sum bit of the result to the processor below and to its right, and provide the carry bit to the processor below it. Because no new input is multiplied, there are fewer summation processors 110S per row. Figure 1 The diagram shows three summators in the first two rows, two summators in the third row, and one summator in the fourth and last rows. A similar arrangement can be made for multiplicands with more bits.

[0047] For example, the summation processor 110S-E can receive the sum bit S33 from the multiplication processor performing the multiplication of A3*B3 in the row above and to the left, and can receive the carry bit C23 from the multiplication processor performing the multiplication of A2*B3 directly above it. The summation processor 110S-E can add the sum bit S33 and the carry bit C23, and can provide its summation result S24 down and to its right to the summation processor, and provide its carry bit C24 to the summation processor directly below it.

[0048] It should be understood that each multiplier processor 110M performs bitwise multiplication. Instead of multiplying the two multi-bit input numbers A and B together and then adding them together, each multiplier processor 110M not only multiplies its associated multiplicand bits together, but also adds the sum and carry information received from its neighboring multiplier processor to its result. The multiplier processor then provides its sum and carry information to its neighboring multiplier processor. Therefore, multiplier 104 is a "bitwise" multiplier.

[0049] It will be further understood that each row of multiplier 104 can sum the output of that row toward bitwise accumulator 106.

[0050] The bitwise accumulator unit 106 may include a row accumulator processor 110U and a tail processor 110T to generate its corresponding result bit Pk. The applicant has recognized that each bit of the accumulated result is accumulated from LSB to MSB, and the LSB is always the accumulated value of LSB bit multiplication. Therefore, the LSB sum bit can be provided from the multiplication processor 110M that multiplies A0*B0 to the first accumulator processor 110U in the bitwise accumulator unit 106. Note that the first accumulator processor 110U begins in the second row of processor 110.

[0051] Furthermore, the applicant has realized that, due to the summation and carry operations performed in the bitwise multiplier 104, each accumulator 110U can receive a sum bit from its adjacent multiplier 110M or summator 110S to add the sum bit to its previously accumulated value.

[0052] Therefore, each processor 110U and 110T of accumulator unit 106 can generate a sum bit and a carry bit, can return its sum bit to itself (as indicated by return arrow 114, and as input for the next cycle), and can provide its carry bit to the next processor in the row (as indicated by arrow 115). As mentioned above, accumulator processor 110U can also receive sum bits from adjacent multiplier processor 110M and summer processor 110S. However, tail processor 110T can only operate on its returned sum bit and the carry bit from its predecessor processor 110S or 110T in the row.

[0053] Note that there may be M rows of multiplication processors 110M and M rows of summation processors 110S, such that there may be 2M accumulator processors 110U. There may be Q tail processors 110T, where Q is at least log2(N) and N is the number of values ​​to be multiplied and accumulated.

[0054] It should be understood that the operations in the multiplier-accumulator 100 can be performed in parallel, with each column being operated on simultaneously with the other columns. Therefore, increasing the precision from 4 bits to 8 bits will not significantly affect the timing of the multiplier-accumulator 100, although it does increase its size.

[0055] Furthermore, it should be understood that the multiplier-accumulator 100 may only be able to perform operations on integers, as it does not handle exponents.

[0056] Now for a brief reference Figure 2A , Figure 2B and Figure 2CThese figures illustrate processors 110M, 110S, and 110U, respectively. The multiplication processor 110M includes an XOR unit 120 and a full adder 122M.

[0057] The XOR operator 120 can receive the multiplicand bits Ai and Bj and can produce their multiplication Ai*Bj. The XOR operator 120 can be any suitable XOR operator. For example, the XOR operator 120 can be implemented on bit lines and its output can be provided to an input labeled In in the input of the full adder 122.

[0058] The 122M full adder can convert the input sum bit S received from the previous calculation into a single bit. in and input carry C in Add to the current input value (i.e., XOR the output). A full adder 122M can generate new sum bits S separately. out and carry position C out And it can pass the received Ai value.

[0059] The full adder 122M can be any suitable full adder. For example, the full adder 122M can be similar to the full adder described in U.S. Patent Application 15 / 708,181, published as US 2018 / 0157621, which is assigned to the applicant of this application and is incorporated herein by reference. US 2018 / 0157621 discusses how to implement multiple parallel full adders 122 within a memory array such that all addition operations occur in parallel. The XOR operation 120 adds a minimum number of operations and can also be performed in parallel. Thus, each row of the bitline processor 110 can be operated on in parallel with each other, multiplying Ai by Bj and then adding the result to the sum bits and carry bits provided to them.

[0060] like Figure 2B As shown, the summation processor 110SA can be similar to the multiplication bit-line processor 110M, but without the XOR unit 120. Instead, the summation processor 110SA only includes a full adder 122S, and can take the input sum bits S received from the previous calculation. in and input carry C in Addition. The full adder 122S can generate new sum bits S separately. out and carry position C out .

[0061] like Figure 2C As shown, the accumulator processor 110U can be similar to the summation bitline processor 110SA, but has S out The feedback loop. The full adder 122U can convert the input sum bit S received from the previous calculation. in and input carry Cin Add to the output sum S from the previous calculation. out The full adder 122U can generate new sum bits S separately. out and carry position C out .

[0062] The remaining discussion will present an exemplary implementation with processor 110 as a bit-line processor; however, it should be understood that the invention can also be implemented with a non-bit-line processor.

[0063] The applicant has realized that the structure of the bitwise multiplier-accumulator 100 enables pipelined operations, which are highly efficient. Once the first row of operations is completed (i.e., Ai is multiplied by B0 in the first cycle), Ai moves down one row, and Bj moves down and to the right, which brings B1–B3 to the second row.

[0064] In the next cycle, a new set of Ai and Bj is introduced and provided to the first row. Therefore, the second row can perform operations on the data from the first cycle, and the first row can perform operations on the data from the second cycle. In each cycle, the old data is shifted down one row, and the new data is shifted to the row preceding the currently vacated row.

[0065] In the second cycle, the LSB bit is provided to the first accumulator bit line processor 110U to begin accumulating the result bit P0. As mentioned above, each accumulator bit line processor 110U can output its carry bit, but its sum is returned to it to be added to the value generated in the next cycle. This is the accumulation operation—summing in place and carrying over to the next more significant bit.

[0066] Now for reference Figure 3A –3I, which illustrates how data moves through a bitwise multiplier-accumulator 100 in 9 cycles for a simple addition of 3 multiplications, where each multiplicand is 4 bits. Since all values ​​have multiple versions, Figure 3A -3F labels each value according to the period to which it belongs. Therefore, A01 comes from the first period, A02 comes from the second period, and so on.

[0067] exist Figure 3A In the preparation cycle shown, the first set of multiplicand bits Ai1 and Bi1 are received into the receive bit line processor 110A of input units 102A and 102B, respectively. In the first cycle following the preparation cycle, B01 can be passed to its signaling bit line processor 110C, which can then provide the value of B01 to its signaling line 112 for the first row of the multiplication bit line processor 110M.

[0068] The first row of the multiplication bitline processor 110M can multiply its Ai1 by B01 (e.g., Ai1*B01), and can pass its carry (labeled Ci0) and its Ai down to the next row, as well as its sum (labeled Si0) down and to the right in the next row. It should be understood that only the sum S001 from the rightmost multiplication bitline processor 110M can be passed to its associated accumulation bitline processor 110U (labeled P0 here) to begin calculation for P0 in the next cycle.

[0069] exist Figure 3B In the second cycle shown, B01 can be received in the signaling bitline processor 110C of the second row, and the signaling bitline processor 110C can then provide its value to the signaling line 112 of the second row. Simultaneously, the second set of multipliers Ai2 and Bj2 received by the receiving bitline processor 110A from the input units 102A and 102B respectively can be passed to the first row of the bitline processor of the multiplier-accumulator 100. Therefore, B02 can be passed to its signaling bitline processor 110C to provide its value to the first row of the multiplication bitline processor 110M. Thus, the first row of the multiplication bitline processor 110M can multiply Ai2 by B02, while the second row of the multiplication bitline processor 110M can multiply Ai1 by B01 (Ai1*B11), and the result can be added to the sum passed from the previous row along with the carry. For example, A11*B11 can be added to S201 and C101 to generate S111 and C111. At the end of the second cycle, as discussed above, the sum, carry, and Ai value from the two rows of the multiplication bit line processor 110M can be passed down one row.

[0070] In the second cycle, accumulation begins when the accumulation bitline processor P0 receives the value passed to it from cycle 1 (i.e., P01 = S001). Accumulation bitline processor P0 can feed the value of P01 back to itself and can pass its carry output CP01 to the next accumulation bitline processor 110U, denoted here as P1, which can calculate P1. Furthermore, at the end of this cycle, the rightmost multiplication bitline processors 110M of the first and second rows can pass the sum bits S002 and S011 to accumulation bitline processors P0 and P1, respectively.

[0071] Figure 3C The operation in the third cycle is shown. The multiplication operation is very similar to that in the second cycle. In this cycle, the third row of the bitwise multiplier 104 can operate on data from the first cycle, the second row can operate on data from the second cycle, and the first row can operate on data from the third cycle.

[0072] In this cycle, the accumulator bit line processor P0 adds the value of S002 passed to it from the second cycle to the previous value P01 to generate the accumulator bit P02. Accumulator bit line processor P0 can then return the value of P02 and pass its carry bit CP02 to accumulator bit line processor P1. Simultaneously, accumulator bit line processor P1 adds the sum bit S011 passed to it from the rightmost multiplication bit line processor 110M (which processes the data from the first cycle) of the second row to the carry bit CP01 received from accumulator bit line processor P0 in the previous cycle.

[0073] It should be understood that each accumulator bitline processor (e.g., P0 and P1) first receives data from cycle 1, then from cycle 2, and so on. Therefore, in cycle 3, P1 in the third row processes the cycle 1 data, while P0 in the second row accumulates the cycle 2 data based on the cycle 1 data it received in the previous cycle.

[0074] Figure 3D The fourth cycle is shown. Since this example only shows the accumulation of three multiplications, there are no further inputs in this fourth cycle. Typically, a bitwise multiplication-accumulator 100 can accumulate thousands of values, but at some point, the accumulation ends.

[0075] exist Figure 3D In this process, the accumulator bitline processor P0 accumulates the LSB data of the third cycle and completes the process. The value stored therein is the LSB of the product of three values ​​(i.e., P03), and therefore, the accumulator bitline processor P0 can move the value stored therein to an external register (not shown).

[0076] Although for ease of understanding Figure 3A –3I is not shown, but the bitwise multiplication-accumulator 100 can begin on the next MAC operation in the next cycle and can bring a new set of multiplicands A and B to be operated on by the now empty first row of the multiplication bit line processor 110M.

[0077] Accumulator bit line processors P1 and P2 can perform operations as discussed above, adding the received LSB sum bit to the value previously stored therein. Accumulator bit line processor P1 can perform operations on the data from cycle 2 (the sum from the rightmost multiplication bit line processor and the carry from accumulator bit line processor P0), and accumulator bit line processor P2 can perform operations on the data from cycle 1.

[0078] exist Figure 3E In the fifth cycle shown, the first row (not shown in the figure) and the second row (…) of multiplier 104 Figure 3EThe top of the array (shown) is empty, and the accumulator bitline processor P0 no longer accumulates. The data from the first cycle is now in the first row of the summator bitline processor 110S. As mentioned above, since the multiplier bitline processor 110M, which operates on the MSB (most significant bit), only generates a sum bit, there are only three summator bitline processors 110SA in the first row of the second part of the multiplier 104. The summator bitline processors 110SA in this row simply add the sum and carry received from the previous row and provide their result sum and carry to the next row. The LSB bit S041 of this row is provided to the accumulator bitline processor P4. The accumulator bitline processors P2 and P3 can operate as discussed above, and the accumulator bitline processor P1 accumulates the LSB data of the third cycle and completes the operation.

[0079] exist Figure 3F In the sixth cycle shown, the first three rows of multiplier 104 are empty (therefore, Figure 3F (The first two rows are not shown in the image), and the accumulating bitline processors P0 and P1 no longer accumulate. The data from the first cycle is now in the second row of the summing bitline processor 110S. In this second row, there are three bitline processors 110S, of which the leftmost processor is the data transfer processor 110SB, and the remaining processors are the summing bitline processors 110SA.

[0080] The data transfer processor 110SB can receive carry C24, which can be generated from the sum S33 of the multiplication from A3*B3 and the carry C23 from its neighbor. C24 will continue to be transferred until it is transferred to P7—the MSB of any of the individual multiplications.

[0081] The two summation bitline processors 110SA in this row add the sums and carry received from the three summation bitline processors 110SA in the previous row, and provide their result sum and carry to the next row. The LSB bit S051 of this row is provided to the accumulation bitline processor P5. Accumulation bitline processors P3 and P4 can operate as discussed above, and accumulation bitline processor P2 accumulates the data of the third cycle and completes the operation.

[0082] exist Figure 3G In the seventh cycle shown, the multiplier has completed its operation. The data from the first cycle is now in the third row of the summing bitline processor 110S, which has two bitline processors 110S, both of which are data transfer processors 110SB.

[0083] The data transfer processor 110SB can receive the carry C24 and the sum S15 (generated in the previous line) for data in cycle 1. The carry C24 can be passed to the next line, while the sum S15 can be passed to P6.

[0084] Accumulator bit line processors P4 and P5 can perform the operations as discussed above, and accumulator bit line processor P3 accumulates the data for the third cycle and completes the operation.

[0085] Multiplication processing in Figure 3H This is completed in the eighth cycle shown. The eighth row of multiplier 104 includes a single data transfer processor 110SB, which receives the data of carry C24 and passes it to the accumulator bit line processor P7. Accumulator bit line processors P5 and P6 can operate as discussed above, and accumulator bit line processor P4 accumulates the data of the third cycle and completes the process.

[0086] In the next three cycles (the first of which is in Figure 3I As shown in the figure, the accumulator bit line processors P5, P6 and P7 respectively accumulate the data of the third cycle, the second cycle and the third cycle, and the first cycle to the third cycle to complete their calculations.

[0087] If there are more than three multiplications to be accumulated, the output of the accumulation bit line processor 110U (i.e., processors P0–P7) can be passed to the tail processor 110T. Figure 1 (to continue accumulating bits.)

[0088] It should be understood that the bitwise multiplier-accumulator 100 has a very efficient structure for the MAC unit. It can be particularly efficient when implemented using a bitline processor, because the various bitline processors 110 have very similar structures, and all of these bitline processors 110 can be implemented in a memory array, as discussed in more detail below. Furthermore, the bitwise multiplier-accumulator 100 performs a portion of the accumulation operation during multiplication by operating on each bit, rather than on all the bit values ​​of the multiplicands A and B.

[0089] Furthermore, as mentioned above, when the multiplication operation is completed, a portion of the accumulation operation has already been completed, allowing the multiplier-accumulator 100 to begin the next multiplication-accumulation operation while completing the previous one.

[0090] In addition, as mentioned above, the bitwise multiplier-accumulator 100 can also be used as a multiplier when only a pair of multiplicands is provided to the bitwise multiplier-accumulator 100.

[0091] Now for reference Figure 4 , Figure 4Three adjacent multiplication bitline processors 110M are shown, where multiplication bitline processor 110M-ij is in the j-th row and i-th column of multiplier-accumulator 100, and performs operations on the i-th bit of multiplicand A and the j-th bit of multiplicand B. Multiplication bitline processor 110M-i-(j+1) is also in the i-th column, but in the (j+1)-th row, and multiplication bitline processor 110M-(i-1)-(j+1) is in the (i-1)-th column and (j+1)-th row.

[0092] Each bitline processor 110M can be formed by at least seven memory cells 202 in a single column, all memory cells 202 being attached to a single bitline 200. The bitline 200 and memory cells 202 can form part of a memory array in which a multiplier-accumulator 100 is implemented. Figure 4 As shown, each cell stores a different value, where, in Figure 4 In this embodiment, the first unit stores the multiplicand Ai, the second unit stores the multiplicand Bj, the third unit stores the carry Ci(j-1)i from the previous row, and the fourth unit stores the sum S(i+1)(j-1) from the previous row and the next column. These are the inputs of the bitline processor 110M, most of which are received from the previous cycle, but the multiplicand Bj can be received in the current cycle before the operation described below occurs.

[0093] Other units in the bitline processor 110M can store intermediate and final results of operations on four inputs.

[0094] The operation of the multiplication bit-line processor 110M can occur in four main steps. In the first step, the multiplication bit-line processor 110M-ij can perform an XOR operation on the cells storing Ai and Bj, and can store the result in the Ai XOR Bj cell. Figure 4 The fifth unit is shown in the diagram. The XOR operation is discussed in U.S. Patent 8,238,173 and may involve simultaneously activating two rows storing Ai and Bj to receive the Boolean function result in bit line 202.

[0095] In the second step, the multiplication bit line processor 110M-ij can implement the full adder 122M as discussed above to add the following bits together: Ci-(j-1), S(i+1)(j-1) and (Ai XOR Bj) to generate the carry bit Ci-j and the sum bit Si-j.

[0096] In the third step, the multiplication bit line processor 110M-ij can read and write bits Ai and Cij to the multiplication bit line processor 110M-i-(j+1); and in the fourth step, the multiplication bit line processor 110M-ij can read and write Si-j to the multiplication bit line processor 110M-(i-1)-(j+1). Alternatively, the full adder 122M can directly write the carry bit Ci-j and the sum bit Si-j.

[0097] It should be understood that the bitwise multiplier-accumulator 100 can activate each bitline processor 110 together, making each cycle a fully parallel operation. For example, in Figure 4 As can be seen in the bottom row, adjacent bitline processors 110M store bit values ​​of the same type in the same row. Therefore, in Figure 4 In this process, all rows storing Ai and Bj can be activated simultaneously, and the XOR result can be written to the (Ai XOR Bj) cells of all bitline processors 110 simultaneously. The same applies to full adder operations.

[0098] Parallel copying from one bitline processor to the next can be achieved via the multiplexer described in U.S. Patent 9,418,719 mentioned above.

[0099] Therefore, all operations in one cycle can be performed together, thereby further improving the pipeline efficiency of the bitwise multiplier-accumulator 100.

[0100] Although certain features of the invention have been described and illustrated herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations that fall within the true spirit and scope of the invention.

Claims

1. A unit for accumulating multiple multiplied bit values, said unit being implemented in an in-memory associative processor and comprising: An array of bitline processors arranged in rows and columns, each bitline processor including a plurality of memory cells coupled to a corresponding bitline, wherein the array is configured as follows: The bit is passed vertically down a column by writing the bit of the first multiplicand (A) into the memory cell of each successive bitline processor in a column of the array during successive operation cycles. The bits of the second multiplicand (B) are provided horizontally to the memory cells in each bitline processor of the corresponding row of the array; A carry bit is generated at each bitline processor, and the carry bit is vertically passed to the next bitline processor by writing it into the memory cell of the next bitline processor in the same column; and A sum bit is generated at each bitline processor, and the sum bit is diagonally passed to the next bitline processor by writing the sum bit to the memory cell of the next bitline processor in the next row and adjacent column.

2. The unit of claim 1, further comprising a first row input unit located above the array of the bit line processor, the first row input unit being configured to receive a pipeline of the bits of the first multiplicand (A).

3. The unit of claim 2 further includes a second set of input units located on the left side of the array of the bit line processor, the second set of input units being configured to receive pipelines of the bits of the second multiplicand (B).

4. The unit according to claim 3, wherein, The second set of input units includes a data transfer processor formed in a triangle, which is used to provide different bits of the second multiplicand (B) to each successive row of the array.

5. The unit according to claim 1 further includes a column of accumulator bit line processors located on the right side of the array of bit line processors.

6. The unit of claim 5, wherein each accumulator bit line processor is configured to receive a sum bit from the rightmost bit line processor of the corresponding row of the array.

7. The unit according to claim 5, wherein each accumulator bit line processor is configured to: generate an accumulated sum bit and an accumulated carry bit, feed back the accumulated sum bit to the accumulator bit line processor itself for use in the next operation cycle, and pass the accumulated carry bit to the next accumulator bit line processor in the column.

8. The unit according to claim 1, wherein, The array of bitline processors includes: a multiplication processor in the upper portion configured to receive the multiplicand bits; and a summation processor in the lower portion configured to receive the sum bits and carry bits only from the processors in the upper row.

9. The unit according to claim 1, wherein, The number of digits (M) in each multiplicand is a power of 2.

10. A unit for accumulating bit values ​​of multiplication, said unit being implemented in an in-memory associative processor and comprising: Multiple bitline processors, each bitline processor including multiple memory cells coupled to the bitline, wherein: The first subset of the bit line processors is a multiplication processor, each multiplication processor being used to perform an XOR operation by simultaneously activating a first memory unit storing bits of a first multiplicand and a second memory unit storing bits of a second multiplicand, and to perform a full adder operation using the result of the XOR operation and bits stored in other memory units of the same bit line processor. The second subset of the bitline processors is a summation processor, each summation processor being used to perform a full adder operation on bits stored in a corresponding memory cell of the summation processor; and The third subset of the bit line processors is the accumulator processors, each of which performs a full adder operation on bits stored in a corresponding memory cell of the accumulator processor and a feedback sum bit from another memory cell of the accumulator processor stored in the previous operation cycle.

11. The unit according to claim 10, wherein, The multiplication processor is arranged in the upper part of the computing array, and the summation processor is arranged in the lower part of the computing array.

12. The unit according to claim 11, wherein, The accumulator processor is arranged in a vertical column to the right of the computing array.

13. The unit according to claim 10, wherein, Each multiplication processor adds the result of the XOR operation to the sum bit received from the processor in the adjacent column and the carry bit received from the processor in the row above.

14. The unit according to claim 10, wherein, Each summation processor adds the sum bits received from the processors in the adjacent column to the carry bits received from the processors in the row above.

15. The unit according to claim 10, wherein, Each accumulator processor adds the sum bit received from the processor in the same row to the carry bit received from the accumulator processor in the row above.

16. The unit according to claim 10, wherein, For each multiplication processor, the plurality of memory units include: A first memory unit is used to store the bits (Ai) of the first multiplicand. The second memory unit is used to store the bits (Bj) of the second multiplicand. The third memory unit is used to store the input carry bit; and The fourth memory unit is used to store the input sum bits.

17. The unit of claim 16, wherein each multiplication processor is configured to store the output sum bit and the output carry bit obtained from the result in the corresponding memory unit of a subsequent bit line processor.

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