A method, apparatus, device, and medium for instruction control based on write-response words.

Abstract

This invention relates to the field of computer technology, specifically to an instruction control method, apparatus, device, and medium based on write-response words. Firstly, this application breaks away from the traditional reliance on hardware primitives by using a mechanism where asynchronous functional components write a write-response word to the corresponding register address area after completing a task. Traditional solutions suffer from limited hardware primitive adaptability, making it difficult to efficiently utilize resources across different cores. This solution, however, uses a unified write-response word to feedback completion status, enabling flexible resource allocation on demand and significantly improving resource utilization. Secondly, this solution does not involve complex API calls. The write-response word mechanism is simple and direct, easily adapting to changes in the number of processor cores, enhancing system scalability. Thirdly, traditional solutions struggle with complex dynamic cross-core task dependencies, while this solution can accurately grasp task completion status through write-response words, flexibly scheduling tasks and effectively adapting to complex dynamic scenarios.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and specifically to an instruction control method, apparatus, device, and medium based on write-response words. Background Technology

[0002] In the widespread application of multi-core and many-core processor architectures, the collaborative work between cores relies on efficient synchronization mechanisms to ensure the correctness and orderliness of task execution. Currently, synchronization mechanisms between cores mainly rely on hardware-level primitives (such as memory barriers and atomic operations) and software-level low-level APIs (such as locks). However, these traditional synchronization methods have significant inherent limitations: First, traditional methods often lead to thread blocking or busy-waiting states, which renders computing resources that could have been used to process effective tasks idle, reducing the utilization rate of system resources. Secondly, as the size of the core group continues to expand, the competition for locks on shared resources among multiple core groups becomes increasingly fierce, and the performance overhead of synchronization operations shows a sharp upward trend, which seriously restricts the scalability of the system. Third, such synchronization mechanisms are mostly coarse-grained designs, making it difficult to accurately express the complex and dynamically changing cross-core task dependencies. This not only increases the complexity of the programming model but also easily leads to runtime errors such as deadlocks and data inconsistencies, increasing development and maintenance costs. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an instruction control method, apparatus, device and medium based on write-response words to solve the problems of low resource utilization, poor scalability, difficulty in adapting to complex dynamic cross-core task dependencies and high development and maintenance costs in multi-core and many-core processor architecture scenarios, which rely on traditional solutions that depend on hardware primitives and low-level software APIs.

[0004] In a first aspect, embodiments of the present invention provide an instruction control method based on writing answer words, the method comprising: Obtain task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component; The task instruction is sent to the corresponding asynchronous functional unit, wherein the asynchronous functional unit executes the corresponding task according to the task instruction, and writes a write answer word to the corresponding register address area to indicate that the instruction is completed after each task is executed. Different asynchronous functional units correspond to different register address areas. Execute the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

[0005] Furthermore, the step of performing the corresponding instruction termination operation based on the instruction type corresponding to the task instruction includes: If the instruction type is the first type, then listen to the count value corresponding to the write reply word in the register address area corresponding to the asynchronous functional unit. The count value is used to indicate the number of times the asynchronous functional unit is currently executing the task instruction. Obtain the expected value corresponding to the task instruction, and compare the count value with the expected value; If the count value matches the expected value, it is determined that the asynchronous functional component has completed all execution operations of the corresponding task instruction, and the instruction termination operation is triggered to release the hardware resources occupied by the task instruction.

[0006] Furthermore, the method also includes: If the count value is less than the expected value, the instruction termination operation remains in a suspended state, and the count value corresponding to the write response word in the register address area corresponding to the asynchronous functional unit continues to be monitored. The corresponding termination operation is executed when the count value reaches the expected value.

[0007] Furthermore, the method also includes: Monitor the execution time of the asynchronous functional component when it executes the corresponding task according to the task instruction; If the execution time exceeds the preset time, then the corresponding exception handling operation will be performed according to the current running data of the asynchronous functional component and the dependency relationship of subsequent tasks.

[0008] Furthermore, the step of performing corresponding exception handling operations based on the current running data of the asynchronous functional component and the dependencies of subsequent tasks includes: The current running status of the asynchronous functional component is retrieved, and the dependency relationship between subsequent tasks to be executed and the current task is analyzed. If there is no dependency between the execution result of the current task and subsequent tasks, the instruction type of the task instruction is switched to the second type, and an instruction termination operation is triggered to release hardware resources; or, If subsequent tasks depend on the execution result of the current task, and the running data does not exhibit fault characteristics, the task instruction will be redistributed to the asynchronous functional component or other idle asynchronous functional components of the same type; or, if subsequent tasks depend on the execution result of the current task, and the running data exhibits fault characteristics, the asynchronous functional component will be marked as abnormal, and the task instruction will be scheduled to other available asynchronous functional components for execution.

[0009] Furthermore, the step of performing the corresponding instruction termination operation based on the instruction type corresponding to the task instruction includes: If the instruction type is the second type, then after the task instruction is successfully sent to the asynchronous functional unit, an instruction termination operation is triggered to release the hardware resources occupied by the task instruction.

[0010] Furthermore, after performing the corresponding instruction termination operation according to the instruction type corresponding to the task instruction, the method further includes: Write the release status of hardware resources into the shared register linkage area, and trigger batch scheduling logic when the number of releases of the same type of hardware resources reaches a preset threshold. Based on the batch scheduling logic, batch dispatch of the same type of task instructions in the waiting queue to idle hardware resources, and assign execution order to the batch tasks according to the historical execution data of the hardware resources.

[0011] Secondly, embodiments of the present invention provide an instruction control device based on writing response characters, the device comprising: An acquisition module is used to acquire task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component; The sending module is used to send the task instruction to the corresponding asynchronous functional unit, wherein the asynchronous functional unit executes the corresponding task according to the task instruction, and writes a write answer word to the corresponding register address area to indicate that the instruction is completed after each task is executed. Different asynchronous functional units correspond to different register address areas. The execution module is used to perform the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

[0012] Thirdly, embodiments of the present invention provide a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0013] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method described in the first aspect or any of its corresponding embodiments.

[0014] This application's embodiments first break away from the traditional approach's reliance on hardware primitives by using a mechanism where asynchronous functional components write a write response word to the corresponding register address area after completing a task. Traditional solutions, due to limited hardware primitive adaptability, struggle to efficiently utilize the resources of different cores in multi-core and many-core architectures. This solution, however, uses a unified write response word to feedback completion status, enabling flexible resource allocation on demand and significantly improving resource utilization. Secondly, compared to traditional solutions that rely on low-level software APIs, this solution avoids complex API calls, preventing scalability issues caused by API complexity. The write response word mechanism is simple and direct, easily adapting to any increase in the number of processor cores, enhancing system scalability. Thirdly, traditional solutions struggle with complex dynamic cross-core task dependencies, while this solution accurately grasps task completion status through write response words, flexibly scheduling tasks and effectively adapting to complex dynamic scenarios. Finally, the solution's logic is concise, reducing development difficulty and maintenance workload, thereby lowering development and maintenance costs. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating an instruction control method based on a write-response word according to some embodiments of the present invention; Figure 2 This is a schematic diagram of the register address region according to some embodiments of the present invention; Figure 3 This is a schematic diagram of the transmission flow of different task instructions according to some embodiments of the present invention; Figure 4 This is a structural block diagram of an instruction control device based on a write-response word according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] According to embodiments of the present invention, a method, apparatus, device, and medium for instruction control based on write-response words are provided. It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0019] This embodiment provides a command control method based on writing answer words. Figure 1 This is a flowchart of an instruction control method based on writing answer words according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component.

[0020] In this embodiment, after the system starts, the processor comprehensively collects task requirements submitted from different application scenarios or users. These task requirements come from a wide range of sources, covering various complex computing tasks, and explicitly include task instructions to be executed by at least one asynchronous functional component. For example, in a hybrid scenario involving multimedia processing and scientific computing, tasks such as high-speed data transfer using DMA (Direct Memory Access) components, image rendering algorithms using specific accelerators, and complex mathematical operations using computational matrices may be required simultaneously.

[0021] Secondly, the processor will parse these task requirements and extract the specific task instructions corresponding to each asynchronous functional unit, including key information such as operation type, data source, and target address.

[0022] Next, the processor begins planning its hardware resource allocation strategy. A software-defined register address region is reserved within the core group. This region is designed to provide centralized management and flexible mapping of the instruction completion status of different asynchronous functional units. Through software definition, the layout of the register address region can be dynamically adjusted according to actual task requirements, adapting it to diverse application scenarios. For example, for data transfer-intensive tasks, the register address range related to DMA units can be appropriately expanded to allow for more detailed monitoring of their transfer status; while for computation-intensive tasks, the focus is on allocating more register resources to components such as computation matrices.

[0023] Step S102: Send task instructions to the corresponding asynchronous functional units. The asynchronous functional units execute the corresponding tasks according to the task instructions. After each task is completed, write a write response word to the corresponding register address area to indicate that the instruction is completed. Different asynchronous functional units correspond to different register address areas.

[0024] In this embodiment, the corresponding task instructions are precisely sent to each corresponding asynchronous functional component. This process requires ensuring the accuracy and timeliness of instruction transmission to avoid problems in task execution due to instruction transmission errors or delays. For example, when sending data transmission instructions to the DMA component, key parameters such as the data source address, target address, and amount of data to be transmitted must be clearly specified to ensure that the DMA can accurately execute the data transfer task.

[0025] Secondly, after receiving the task instruction, the asynchronous functional components begin to execute the corresponding task based on their own hardware characteristics and algorithm logic. During task execution, each component operates independently, fully leveraging its advantage of efficiently processing specific tasks. For example, the accelerator component processes the input data quickly according to a preset algorithm flow, while the computation matrix utilizes powerful parallel computing capabilities to complete complex mathematical operations.

[0026] Then, after each task is completed, the asynchronous functional unit needs to write a write reply word to the corresponding register address area to indicate instruction completion. The write reply word plays a crucial role here; it is the key information carrier for the asynchronous functional unit to report the task execution status to the processor. Different asynchronous functional units correspond to different register address areas; this design aims to achieve state isolation and independent tracking. By allocating an independent register address space to each unit, the processor can clearly distinguish the task completion status of different units, avoiding state confusion. For example, after the DMA unit completes a data transfer, it performs an atomic increment operation at its dedicated register address, recording the number of transfer completions; the accelerator unit also records the number of algorithm processing completions in a similar way in its corresponding register area.

[0027] As an example, such as Figure 2 As shown, after the CPU issues asynchronous instructions to multiple asynchronous components (asynchronous component 1, asynchronous component 2, and asynchronous component n), each asynchronous component executes the corresponding asynchronous operation. When each asynchronous operation is completed, a counting accumulation operation is performed in the "instruction completion specified space" (corresponding to the register address area reserved in the core group in the patent scheme), and the completion status is recorded in the space in the form of a count value. Finally, the count value in this space is synchronized to the register or other storage space (as shown by "[N+1]" on the right), realizing centralized recording and monitoring of the instruction completion status of each asynchronous component. Its core is to achieve efficient tracking of the asynchronous instruction execution status through independent register address areas and write response words (count values).

[0028] Step S103: Execute the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

[0029] In this embodiment, the corresponding instruction termination operation is performed according to the instruction type corresponding to the task instruction, including: if the instruction type is the first type, then listening to the count value corresponding to the write reply word in the register address area corresponding to the asynchronous functional unit, the count value is used to represent the number of times the asynchronous functional unit currently executes the task instruction; obtaining the expected value corresponding to the task instruction, and comparing the count value with the expected value; if the count value is consistent with the expected value, then determining that the asynchronous functional unit has completed all execution operations of the corresponding task instruction, and triggering the instruction termination operation to release the hardware resources occupied by the task instruction.

[0030] It should be noted that if the instruction type is Type 1 (blocking retirement), the corresponding register address region is a configurable register space exclusively allocated within the core for this asynchronous functional unit. The address information in this region is bound to the instruction during task instruction dispatch and is the unique write and listen location for this unit's write reply word. The counter value corresponding to the write reply word is updated by the asynchronous functional unit through an atomic increment operation after each task instruction is completed. The cumulative result of this value directly corresponds to the total number of times the current task instruction has been executed by this unit.

[0031] The processor or scheduling unit continuously polls or monitors the write answer count value of the register address region. Simultaneously, the processor retrieves a pre-set expected value from the instruction descriptor; this expected value represents the total number of tasks the current task instruction requires the asynchronous functional unit to complete. When the monitored count value matches the expected value, it can be confirmed that the asynchronous functional unit has completed all execution operations of the corresponding task instruction. At this point, the processor triggers an instruction termination operation, releasing the hardware resources occupied by the task instruction. This process, through the binding of the write answer word to the register address, ensures strong consistency of the critical task execution results.

[0032] In this embodiment of the application, the corresponding instruction termination operation is performed according to the instruction type corresponding to the task instruction, including: if the instruction type is the second type, the instruction termination operation is triggered after the task instruction is successfully sent to the asynchronous functional component to release the hardware resources occupied by the task instruction.

[0033] It should be noted that if the instruction type is type 2 (non-blocking retirement), the corresponding register address region is also a dedicated configurable register space allocated within the core group for that asynchronous functional unit. The write answer word will still be atomically incremented by 1 after the asynchronous functional unit completes its task, but the state of this register address region will not affect the instruction retirement process. When the task instruction is successfully sent to the asynchronous functional unit, the processor will directly trigger the instruction termination operation, releasing the hardware resources occupied by the task instruction, without waiting for the asynchronous functional unit to complete its task and write the write answer word.

[0034] Based on this, the instruction sending status and execution status are decoupled through the write response word in the register address area. The write response word in the register address area will still record the task completion status for subsequent task progress statistics or performance analysis, but will not restrict the resource release of the current instruction or the execution of subsequent instructions, thereby improving the processor's resource utilization and execution efficiency.

[0035] As an example, such as Figure 3 As shown, the execution and status verification process of blocking asynchronous instructions based on the write-answer word mechanism is as follows: First, the CPU sends a blocking asynchronous instruction (i.e., a first-type task instruction) to the judgment unit. Then, the judgment unit reads the write-answer word count value N corresponding to the instruction from the register or other memory space. This count value is a status identifier written by the asynchronous functional unit after completing the task, designed to accurately record the number of task completions. Next, the judgment unit compares this count value with the preset expected value of the instruction. If the count value does not meet the expectation, it returns to step ② to continue reading the write-answer word count value. If the count value matches the expectation, the judgment unit sends a signal to the CPU indicating instruction completion, triggering the instruction termination operation. The entire process, through the write-answer word count value in the register address area, achieves accurate verification and strong consistency control of the blocking instruction execution status, solving the problem of ambiguous status monitoring in traditional synchronization mechanisms.

[0036] In this embodiment of the application, the method further includes: if the count value is less than the expected value, the instruction termination operation is kept in a suspended state, and the count value corresponding to the write answer word of the register address area corresponding to the asynchronous functional unit is monitored; until the count value reaches the expected value, the termination operation of the corresponding instruction is executed.

[0037] When the processor detects a write response count value lower than expected while monitoring the write response count of the register address area corresponding to an asynchronous functional unit, it indicates that the asynchronous functional unit has not yet completed the operation required by the current task instruction, and its execution result has not been fully written to the corresponding register address area. At this time, the processor will take measures to keep the instruction termination operation in a suspended state. Specifically, the processor will set a suspension flag in the instruction execution flow through hardware or software mechanisms. This flag will prevent the instruction termination operation from proceeding further, ensuring that the current instruction maintains its original state in terms of hardware resource usage and state management, and will not be prematurely released or enter the subsequent termination process.

[0038] Meanwhile, the processor does not cease monitoring the asynchronous functional units but continues to closely observe the register address region. The processor periodically reads the count value corresponding to the write response word in this register address region according to a preset monitoring cycle. After each count value read, the processor compares it in detail with the expected value. If the count value is still less than the expected value, the processor reconfirms the validity of the suspend state to ensure that the instruction termination operation is not unexpectedly triggered. Furthermore, the processor may analyze possible reasons why the count value has not reached the expected value, based on the type of asynchronous functional unit and task characteristics, such as whether it is due to internal processing delays, data transmission congestion, or task scheduling conflicts. Through this continuous monitoring and analysis, the processor can comprehensively grasp the execution progress of the asynchronous functional units, providing accurate basis for subsequent operational decisions. Only when the count value finally reaches the expected value will the processor release the suspend state of the instruction termination operation, execute the corresponding instruction termination operation, release relevant hardware resources, and complete the entire instruction execution process.

[0039] In this embodiment of the application, the method further includes: Step A1: Monitor the execution time of asynchronous functional components when they execute corresponding tasks according to task instructions.

[0040] After receiving a task instruction, the asynchronous functional component synchronously starts the timing module bound to that task to prevent the overall process from being blocked due to timeouts in the asynchronous component. The start of the timing module is strongly correlated with the start signal of the task instruction execution, ensuring the accuracy of the timing start point. At the same time, this module is mapped to a reserved field in the dedicated register address area of ​​the corresponding asynchronous component. Its technical characteristics are consistent with the "flexibly configurable write answer register space" architecture, with the aim of centrally managing the duration data and the write answer count in the same address area, improving the convenience of status query.

[0041] Secondly, the timing module uses the processor clock as a reference to continuously monitor the duration of the current task executed by the asynchronous functional unit. This duration data is then periodically updated and written to a temporary field in the corresponding register address. This achieves "dual-dimensional monitoring" of the execution status (a count records the number of completions, and the duration records execution efficiency), overcoming the limitation of traditional methods that rely solely on the number of completions to detect execution latency. Simultaneously, the update frequency of the duration data is dynamically adjusted according to task priority: higher-priority tasks receive more frequent updates, while lower-priority tasks receive fewer. This technical feature stems from the need to "balance monitoring accuracy and hardware resource consumption," avoiding excessive register bandwidth usage from frequent updates. Finally, the processor continuously compares the real-time execution duration with a preset timeout threshold and marks a "duration warning status" in the register address area. This provides a pre-emptive signal for subsequent exception handling, ensuring that processing logic is prepared in advance when the execution duration approaches the threshold, rather than triggering operations only after a timeout, thus improving the processor's responsiveness.

[0042] Step A2: If the execution time exceeds the preset time, then perform the corresponding exception handling operation based on the current running data of the asynchronous functional component and the dependency relationship of subsequent tasks.

[0043] First, the processor retrieves runtime data from the dedicated register address area of ​​the corresponding asynchronous functional unit. This data includes write response word counts, unit resource utilization, error codes, etc. The retrieval method relies on the isolation design of "different asynchronous units corresponding to different register address areas," ensuring the independence and accuracy of the runtime data. This technical feature stems from the need to "precisely locate the state of abnormal units," avoiding misjudgments caused by cross-unit data interference. Simultaneously, the processor synchronously parses the recorded dependencies of subsequent tasks to determine whether the execution result of the current task will affect subsequent processes. This design improves upon the inability of traditional synchronous mechanisms to handle complex task dependencies, ensuring that the exception handling strategy matches the task logic. Secondly, based on the analysis results of the runtime data and dependencies, the processor triggers corresponding exception handling operations: if subsequent tasks have no dependency on the current task, the instruction type of the current task is switched to the second type (non-blocking), and an instruction termination operation is triggered to release resources.

[0044] This strategy stems from the design objective of "improving resource utilization" to prevent timeouts of independent tasks from blocking subsequent processes. If a subsequent task depends on the current task and its running data shows no fault characteristics, the task instruction will be redeployed to the original component or another idle component of the same type. This design is based on an architecture where the write answer word register space supports multi-component mapping, ensuring that the redeployed task can still record its state in a unified address area. If the running data shows fault characteristics, the component is marked as abnormal, and the task is scheduled to another available component. This technical feature stems from the need to "ensure processor robustness," preventing faulty components from continuously occupying resources. Finally, the processor writes information such as the type, duration, and scheduling result of this exception handling into the traceability field of the corresponding register address area. This is to provide data support for subsequent performance optimization and to establish a correlation with the write answer word count. In this embodiment of the application, corresponding exception handling operations are performed based on the current running data of the asynchronous functional component and the dependencies of subsequent tasks, including: Step B1: Retrieve the current running status of the asynchronous functional component and analyze the dependency relationship between the subsequent tasks to be executed and the current task.

[0045] When the processor detects an anomaly where the counter value for an asynchronous functional unit executing task instructions fails to reach the expected value but the statistical duration exceeds the timeout threshold, it first retrieves the current running status data of that asynchronous functional unit. This running status data contains details of the task the unit is executing, resource usage, internal processing flow, and other information, providing a clear picture of the unit's current working status. For example, by reviewing the running status data, the processor can understand whether the unit is processing other high-priority tasks, causing the current task to be suspended; or whether there are hardware resource conflicts, such as memory access conflicts or bus occupancy conflicts, affecting the normal execution of the task.

[0046] Simultaneously, the processor analyzes the dependencies between subsequent tasks and the current task. These dependencies may involve data dependencies, meaning subsequent tasks require the data results generated by the current task as input; or they may involve control dependencies, meaning the execution order or conditions of subsequent tasks depend on the completion status of the current task. By comprehensively analyzing these dependencies, the processor can accurately determine whether subsequent tasks will be affected by an anomaly in the current task, providing crucial information for taking targeted action.

[0047] In step B2, if there is no dependency between the execution result of the current task and the subsequent tasks, the instruction type of the task instruction is switched to the second type, and the instruction termination operation is triggered to release hardware resources.

[0048] After retrieving the running status of asynchronous functional units and analyzing the dependencies between subsequent tasks and the current task, if the processor determines that there is no dependency between the execution results of subsequent tasks and the current task, it means that an exception in the current task will not have a substantial impact on the normal progress of subsequent tasks. In this case, the processor will switch the instruction type of the task instruction to the second type, which is a non-blocking instruction.

[0049] The characteristic of non-blocking instructions is that once an instruction is successfully sent to the target asynchronous component, its local retirement process can be completed without waiting for the instruction to actually finish executing remotely. Through this switching, the processor core can immediately release the hardware resources occupied by the instruction, such as register space and arithmetic units, allowing them to be used for subsequent tasks. This not only greatly improves the execution efficiency of the processor's front end, avoiding resource idleness caused by waiting for a task that does not affect subsequent processes to complete, but also effectively improves the overall resource utilization of the processor, ensuring that the processor can operate more flexibly and efficiently in the face of complex and ever-changing task environments, maximizing task-level parallelism and optimizing processor throughput.

[0050] Alternatively, in step B3, if there is a dependency between subsequent tasks and the execution result of the current task, and the running data does not have fault characteristics, the task instruction will be redistributed to the asynchronous functional component or other idle asynchronous functional components of the same type; or, if there is a dependency between subsequent tasks and the execution result of the current task, and the running data has fault characteristics, the asynchronous functional component will be marked as abnormal, and the task instruction will be scheduled to other available asynchronous functional components for execution.

[0051] When the processor determines that subsequent tasks depend on the execution result of the current task, it indicates that the successful completion of the current task is crucial for the smooth execution of subsequent tasks. At this point, the processor further checks the runtime data of the asynchronous functional unit for fault characteristics. If the runtime data does not exhibit fault characteristics, it means that the asynchronous functional unit itself is in normal hardware condition, and the current task timeout may be due to non-fault factors such as temporary resource constraints or unreasonable task scheduling. In this case, the processor will reassign the task instruction to the asynchronous functional unit, giving it another chance to execute the task successfully; or, to ensure the task completes as quickly as possible and avoid delaying subsequent tasks due to the failure of a single component, the processor may also consider reassigning the task instruction to other idle asynchronous functional units of the same type, utilizing idle resources to improve task execution efficiency. Conversely, if the runtime data exhibits fault characteristics, such as frequent error interrupts or abnormal hardware signals, it indicates that the asynchronous functional unit may have hardware failures or software configuration errors. Continuing to use this unit to execute tasks may lead to further task failures or even more serious problems. Therefore, the processor will mark the asynchronous functional unit as abnormal for subsequent troubleshooting and repair. Meanwhile, in order not to affect the normal execution of the task, the processor will schedule the task instruction to other available asynchronous functional units for execution, ensuring that the task can be completed smoothly on the normally operating units, thus guaranteeing the stability and reliability of the entire processor.

[0052] In this embodiment of the application, after executing the corresponding instruction termination operation according to the instruction type corresponding to the task instruction, the method further includes: writing the release status of hardware resources into a shared register linkage area, and triggering batch scheduling logic when the number of releases of the same type of hardware resources reaches a preset threshold; dispatching the same type of task instructions in the waiting queue to idle hardware resources in batches based on the batch scheduling logic, and allocating an execution order for the batch tasks according to the historical execution data of the hardware resources.

[0053] When a hardware resource completes the execution of its current task instruction, a resource release operation is required. To achieve efficient resource management and task scheduling, the processor writes the release status of the hardware resource in detail to a shared register-linked area. This write operation is performed collaboratively by hardware and software. The hardware part may contain specific status registers to record the usage status of the hardware resource, such as "busy" and "idle" flags; the software part is responsible for accurately writing this status information to the shared register-linked area according to a predetermined format and protocol. This shared area is a storage space that can be accessed by multiple modules or threads. In this way, other relevant modules can obtain the release status information of the hardware resource in real time.

[0054] Simultaneously, the processor continuously scans and reads the shared register linkage area. It periodically checks the number of released hardware resources of the same type according to a preset monitoring cycle. During each monitoring cycle, the monitoring module counts the number of released hardware resources of the same type and compares it with a preset threshold. This preset threshold is determined based on factors such as the processor's overall performance requirements, task type, and the quantity of hardware resources.

[0055] For example, in a high-performance computing processor, if there are many similar hardware resources and a large workload, the preset threshold may be set relatively high so that batch scheduling is triggered only when there are enough idle resources, thus improving scheduling efficiency. In a processor with relatively scarce resources, the preset threshold may be set lower to utilize the released resources to execute tasks as quickly as possible. When the number of similar hardware resources released reaches the preset threshold, the monitoring module will immediately trigger the batch scheduling logic.

[0056] Once the batch scheduling logic is triggered, the processor enters the batch task dispatch phase. The processor selects task instructions of the same type that match the currently available idle hardware resources from a pre-set waiting queue. The waiting queue sorts and stores task instructions according to certain rules and priorities, such as task urgency, estimated execution time, and dependencies. The processor then retrieves these task instructions from the waiting queue in the order they appear.

[0057] During the task dispatching process, the processor considers historical execution data of hardware resources. This historical execution data includes information such as execution time, resource usage, and task completion rate when hardware resources have performed different types of tasks in the past. By analyzing this data, the processor can evaluate the execution efficiency and stability of each hardware resource for different tasks. Based on these evaluation results, the processor assigns a reasonable execution order to the batch-dispatched task instructions.

[0058] For example, for tasks with short execution times and low resource requirements, the processor may prioritize allocating them to hardware resources that have performed efficiently in similar tasks in the past. Conversely, for tasks with longer execution times and higher complexity, the processor will consider the overall hardware load and select relatively idle and stable hardware resources for allocation. This execution order allocation method based on historical execution data allows the processor to maximize hardware resource utilization, reduce task execution waiting time, and optimize overall processor performance. Simultaneously, the processor updates relevant scheduling information when dispatching task instructions to ensure that the task execution process can be accurately tracked and managed.

[0059] This embodiment also provides a command control device based on written response characters, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0060] This embodiment provides a command control device based on writing answer words, such as... Figure 4 As shown, it includes: The acquisition module 401 is used to acquire task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component; The sending module 402 is used to send task instructions to the corresponding asynchronous functional units. The asynchronous functional units execute the corresponding tasks according to the task instructions. After each task is executed, a write reply word indicating that the instruction is completed is written to the corresponding register address area. Different asynchronous functional units correspond to different register address areas. The execution module 403 is used to perform the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

[0061] In this embodiment of the application, the execution module 403 is used to listen to the count value corresponding to the write answer word in the register address area corresponding to the asynchronous functional component if the instruction type is the first type. The count value is used to represent the number of times the asynchronous functional component is currently executing the task instruction. The module also obtains the expected value corresponding to the task instruction and compares the count value with the expected value. If the count value is consistent with the expected value, the module determines that the asynchronous functional component has completed all execution operations of the corresponding task instruction and triggers the instruction termination operation to release the hardware resources occupied by the task instruction.

[0062] In this embodiment of the application, the device further includes: a monitoring module, configured to keep the instruction termination operation in a suspended state if the count value is less than the expected value, and continue to monitor the count value corresponding to the write answer word in the register address area corresponding to the asynchronous functional component; until the count value reaches the expected value, execute the termination operation of the corresponding instruction.

[0063] In this embodiment of the application, the device further includes: a monitoring module, used to monitor the execution time of the asynchronous functional component when it executes the corresponding task according to the task instruction; if the execution time exceeds a preset time, the module performs corresponding exception handling operations based on the current running data of the asynchronous functional component and the dependency relationship of subsequent tasks.

[0064] In this embodiment, the monitoring module is used to retrieve the current running status of the asynchronous functional component and analyze the dependency relationship between subsequent tasks to be executed and the current task. If there is no dependency relationship between the execution result of the current task and the subsequent task, the instruction type of the task instruction is switched to the second type, and an instruction termination operation is triggered to release hardware resources. Alternatively, if there is a dependency relationship between the execution result of the current task and the subsequent task, and the running data does not have fault characteristics, the task instruction is redistributed to the asynchronous functional component or other idle asynchronous functional components of the same type. Alternatively, if there is a dependency relationship between the execution result of the current task and the running data has fault characteristics, the asynchronous functional component is marked as abnormal and the task instruction is scheduled to be executed by other available asynchronous functional components.

[0065] In this embodiment of the application, the execution module 403 is used to trigger an instruction termination operation after the task instruction is successfully sent to the asynchronous functional component if the instruction type is the second type, thereby releasing the hardware resources occupied by the task instruction.

[0066] In this embodiment of the application, the device further includes: an allocation module, configured to write the release status of hardware resources into a shared register linkage area, and trigger batch scheduling logic when the number of releases of the same type of hardware resources reaches a preset threshold; based on the batch scheduling logic, batch dispatch the same type of task instructions in the waiting queue to idle hardware resources, and allocate an execution order for the batch tasks according to the historical execution data of the hardware resources.

[0067] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 5 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0068] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0069] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0070] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0071] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0072] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0073] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0074] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A command control method based on writing answer words, characterized in that, The method includes: Obtain task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component; The task instruction is sent to the corresponding asynchronous functional unit, wherein the asynchronous functional unit executes the corresponding task according to the task instruction, and writes a write answer word to the corresponding register address area to indicate that the instruction is completed after each task is executed. Different asynchronous functional units correspond to different register address areas. Execute the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

2. The method according to claim 1, characterized in that, The step of performing the corresponding instruction termination operation according to the instruction type corresponding to the task instruction includes: If the instruction type is the first type, then listen to the count value corresponding to the write reply word in the register address area corresponding to the asynchronous functional unit. The count value is used to indicate the number of times the asynchronous functional unit is currently executing the task instruction. Obtain the expected value corresponding to the task instruction, and compare the count value with the expected value; If the count value matches the expected value, it is determined that the asynchronous functional component has completed all execution operations of the corresponding task instruction, and the instruction termination operation is triggered to release the hardware resources occupied by the task instruction.

3. The method according to claim 2, characterized in that, The method further includes: If the count value is less than the expected value, the instruction termination operation remains in a suspended state, and the count value corresponding to the write response word in the register address area corresponding to the asynchronous functional unit continues to be monitored. The corresponding termination operation is executed when the count value reaches the expected value.

4. The method according to claim 2, characterized in that, The method further includes: Monitor the execution time of the asynchronous functional component when it executes the corresponding task according to the task instruction; If the execution time exceeds the preset time, then the corresponding exception handling operation will be performed according to the current running data of the asynchronous functional component and the dependency relationship of subsequent tasks.

5. The method according to claim 4, characterized in that, The step of performing corresponding exception handling operations based on the current running data of the asynchronous functional component and the dependencies of subsequent tasks includes: The current running status of the asynchronous functional component is retrieved, and the dependency relationship between subsequent tasks to be executed and the current task is analyzed. If there is no dependency between the execution result of the current task and subsequent tasks, the instruction type of the task instruction is switched to the second type, and an instruction termination operation is triggered to release hardware resources; or, If subsequent tasks depend on the execution result of the current task, and the running data does not exhibit fault characteristics, the task instruction will be redistributed to the asynchronous functional component or other idle asynchronous functional components of the same type; or, if subsequent tasks depend on the execution result of the current task, and the running data exhibits fault characteristics, the asynchronous functional component will be marked as abnormal, and the task instruction will be scheduled to other available asynchronous functional components for execution.

6. The method according to claim 1, characterized in that, The step of performing the corresponding instruction termination operation according to the instruction type corresponding to the task instruction includes: If the instruction type is the second type, then after the task instruction is successfully sent to the asynchronous functional unit, an instruction termination operation is triggered to release the hardware resources occupied by the task instruction.

7. The method according to claim 1, characterized in that, After performing the corresponding instruction termination operation according to the instruction type corresponding to the task instruction, the method further includes: Write the release status of hardware resources into the shared register linkage area, and trigger batch scheduling logic when the number of releases of the same type of hardware resources reaches a preset threshold. Based on the batch scheduling logic, batch dispatch of the same type of task instructions in the waiting queue to idle hardware resources, and assign execution order to the batch tasks according to the historical execution data of the hardware resources.

8. A command control device based on written response characters, characterized in that, The device includes: An acquisition module is used to acquire task requirements, wherein the task requirements include task instructions to be executed by at least one asynchronous functional component; The sending module is used to send the task instruction to the corresponding asynchronous functional unit, wherein the asynchronous functional unit executes the corresponding task according to the task instruction, and writes a write answer word to the corresponding register address area to indicate that the instruction is completed after each task is executed. Different asynchronous functional units correspond to different register address areas. The execution module is used to perform the corresponding instruction termination operation according to the instruction type corresponding to the task instruction.

9. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

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