Data prefetching methods, products, devices, and media based on multiple memory access modes

Abstract

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and in particular to data prefetching methods, products, devices and media based on multiple memory access modes. Background Technology

[0002] In computer systems, cache is a key link between the processor and memory. Its core function is to store data that the processor has recently accessed frequently, reducing the processor's direct access to memory, thereby reducing memory access latency and improving system operating efficiency.

[0003] Currently, cache prefetching technology has become one of the core means to optimize memory access performance. As the requirements of computer systems for operating efficiency continue to increase, existing prefetching technology can no longer meet the memory access needs of complex programs. Especially in scenarios with multiple program switching and multiple memory access scenarios, relying solely on a single mode of prefetching cannot cover irregular memory access, continuous repeated memory access, and other scenarios, which can easily lead to problems such as prefetching failure, cache resource waste, and increased memory access latency.

[0004] It is evident that how to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a data prefetching method, apparatus, device, and medium based on multiple memory access modes, adaptable to various scenarios, and accurately identifying memory access patterns for more precise data prefetching. The specific solution is as follows: In a first aspect, the present invention discloses a data prefetching method based on multiple memory access modes, comprising: Monitor the current memory access miss event of the processor's L2 cache; If the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region; If the base address of the spatial region is hit when the pattern training table of the current program counter is queried, stride pattern training and spatiotemporal pattern training are performed on the offset address in the region to obtain memory access patterns corresponding to fixed stride access, spatially related access and time-related access respectively. The memory access patterns are classified and filtered according to their confidence levels to select effective memory access patterns. The effective memory access patterns are stored in the corresponding memory access pattern table in the cache LLC. The index information of the effective memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, and time pattern table. Based on the next memory access miss event and the index information of the prefetch pattern record table, the target memory access pattern is read from the corresponding memory access pattern table and the prefetch address is calculated to generate a prefetch request, and the data prefetch behavior corresponding to the prefetch request is executed.

[0006] Optionally, the current memory access miss event of the L2 cache of the monitoring processor includes: The system continuously monitors the memory access behavior of the processor's L2 cache. When a data access request initiated by the processor cannot be found in the L2 cache, the system identifies and captures the current memory access miss event.

[0007] Optionally, the current memory access miss event includes: the memory access miss address that triggered the miss, the program counter corresponding to the current access instruction, and the time and cache state at which the miss occurred.

[0008] Optionally, the data prefetching method based on multiple memory access modes further includes: If the current memory access miss event is not found when querying the miss status register, a new miss entry for recording the current memory access miss event is created in the miss status register, and the process jumps to the step of splitting the memory access miss address of the current memory access miss event.

[0009] Optional, also includes: If the base address of the spatial region is not hit when querying the pattern training table of the current program counter, the current program counter, the base address of the spatial region, and the offset address within the region are written into the lookup buffer to temporarily store the memory access behavior across spatial regions.

[0010] Optionally, writing the current program counter, the base address of the spatial region, and the offset address within the region into the lookup buffer includes: In the lookup buffer, a new current address association is created to store the current program counter, the base address of the spatial region, and the offset address within the region. The current address association is then recorded and updated with confidence according to a time pattern.

[0011] Optionally, stride pattern training is performed on the offset addresses within the region to obtain the memory access pattern corresponding to fixed stride access, including: The difference between the offset address within the region of the current memory miss event and the offset address within the region of the previous memory miss event is determined to obtain the current step value; Update the stride confidence score corresponding to the current stride value and the stride confidence scores corresponding to other current stride values ​​based on whether the query result of the current stride value is found in the stride pattern training table; When the confidence level of any step is greater than the preset emission threshold, a memory access mode with a corresponding fixed step is generated.

[0012] Optionally, spatiotemporal pattern training is performed on the offset addresses within the region to obtain the memory access patterns corresponding to spatially related accesses, including: The bit vector stream is updated based on the offset address within the region to mark the offsets within the region to which the offset address belongs. The time stream is also updated according to the order in which each offset is accessed to record the access order. The pattern confidence is updated based on the number of recurrences of each offset in the access order, and the reuse confidence is updated based on the number of occurrences of consecutive identical sequences in the access order. When the memory access mode of the offset address in the access sequence is determined to be in an idle state based on the access timestamp of each offset in the access sequence and the preset idle threshold, the memory access mode of the corresponding space-related access is obtained.

[0013] Optionally, obtain the memory access patterns related to the corresponding time, including: After obtaining the memory access patterns of the corresponding space-related accesses, the address access sequence relationships that meet the preset stability conditions in the memory access patterns of the corresponding space-related accesses are extracted to form the memory access patterns of the corresponding time-related accesses.

[0014] Optionally, the stride confidence represents the prediction accuracy of the current stride value, the pattern confidence represents the stability of the offset access pattern in the region to which the offset address belongs, and the reuse confidence represents the probability of the same set of access sequences repeating.

[0015] Optionally, the step of classifying and filtering each memory access pattern according to confidence level to select effective memory access patterns, and storing the effective memory access patterns in the corresponding memory access pattern table in the cache LLC, includes: The memory access mode whose bit vector stream length is greater than a first preset threshold and whose mode confidence is greater than a second preset threshold is determined as the first valid memory access mode, and the first valid memory access mode is stored in the space-time mode table in the cache LLC. The memory access mode that is determined to be a non-first valid memory access mode and whose reuse confidence is greater than a third preset threshold is determined to be a second valid memory access mode, and the second valid memory access mode is stored in the time pattern table in the cache LLC.

[0016] Optionally, the step of classifying and filtering each memory access pattern according to confidence level to select effective memory access patterns, and storing the effective memory access patterns in the corresponding memory access pattern table in the cache LLC, includes: The memory access mode with a stride confidence greater than a fourth preset threshold is determined as the third valid memory access mode, and the third valid memory access mode is stored in the stride mode table in the cache LLC.

[0017] Optionally, the index information includes an index, the schema table type to which each valid memory access mode belongs, and the corresponding entry identifier, wherein the index is a combination of the program counter and memory access miss events.

[0018] Optionally, the step of reading the target memory access pattern from the corresponding memory access pattern table and calculating the prefetch address based on the next memory access miss event and the index information of the prefetch pattern record table includes: When the next memory access miss event is detected, the prefetch mode record table is searched using the program counter and the base address of the memory region corresponding to the next memory access miss event as indexes to obtain the index information of the target valid memory access mode. Based on the index information of the target valid memory access mode, locate the corresponding target memory access mode table in the cache LLC, and read the target memory access mode already stored in the target memory access mode table; If the target memory access mode is a memory access mode corresponding to a fixed step size, then the memory miss address of the next memory miss event is added to the step size value to obtain the prefetch address. If the target memory access mode is a memory access mode corresponding to time-related access, then the next address of the memory miss address of the current memory miss event is determined from the memory access mode corresponding to time-related access, and the next address is determined as the prefetch address. If the target memory access mode is a memory access mode related to the corresponding space, then a prefetch address is generated based on the access priority of the memory access mode related to the corresponding space and the bit vector stream.

[0019] Optionally, a prefetch request is generated, and data prefetching behavior corresponding to the prefetch request is performed, including: Obtain the first prefetch coefficient corresponding to the real-time miss rate of the L2 cache and the second prefetch coefficient corresponding to the historical prefetch accuracy, and determine the product of the first prefetch coefficient and the second prefetch coefficient as the comprehensive prefetch coefficient. Adjust the number of prefetch addresses allowed to be issued according to the comprehensive prefetch coefficient. Each of the prefetch addresses is filtered, and the filtered prefetch addresses are aggregated based on the number of prefetch addresses to generate a prefetch request; Perform a data prefetch operation on the memory corresponding to the prefetch request.

[0020] Optionally, the data prefetching method based on multiple memory access modes further includes: When the processor's L2 cache is full and data replacement needs to be performed, the target replacement total score for each cache line is calculated based on the unused cycle counter of each cache line in the L2 cache, the number of hits queried in the missing status register, and the number of prefetch hits. Based on the target replacement total score, target cache lines are selected from each cache line, and a replacement operation is performed on the target cache lines.

[0021] Secondly, the present invention discloses a data prefetching device based on multiple memory access modes, comprising: The monitoring module is used to monitor the current memory access miss event of the processor's L2 cache; The address splitting module is used to split the memory access miss address of the current memory access miss event when the current memory access miss event is hit during the query in the miss status register, so as to obtain the spatial region base address and the offset address within the region. The training module is used to perform stride pattern training and spatiotemporal pattern training on the offset address in the spatial region if the base address of the spatial region is hit when the pattern training table of the current program counter is queried, so as to obtain each memory access pattern corresponding to fixed stride access, spatially related access and time-related access respectively. The information recording module is used to classify and filter the memory access patterns according to their confidence levels to select effective memory access patterns and store the effective memory access patterns in the corresponding memory access pattern table in the cache LLC. The index information of the effective memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, and time pattern table. The data prefetch module is used to read the target memory access pattern from the corresponding memory access pattern table and calculate the prefetch address based on the next memory access miss event and the index information of the prefetch pattern record table, so as to generate a prefetch request and execute the data prefetch behavior corresponding to the prefetch request.

[0022] Thirdly, the present invention discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the aforementioned disclosed data prefetching method based on multiple memory access modes.

[0023] Fourthly, the present invention discloses an electronic device, comprising: Memory, used to store computer programs; A processor for executing computer programs to implement the steps of the aforementioned disclosed data prefetching method based on multiple memory access modes.

[0024] Fifthly, the present invention discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed data prefetching method based on multiple memory access modes.

[0025] Therefore, this invention monitors the current memory access miss event of the processor's L2 cache; if the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region; if the spatial region base address is hit when querying the pattern training table of the current program counter, stride pattern training and spatiotemporal pattern training are performed on the offset address within the region to obtain each memory access pattern corresponding to fixed stride access, spatially dependent access, and temporally dependent access, respectively; and each memory access... The patterns are categorized and filtered according to confidence level to identify valid memory access patterns. These valid memory access patterns are then stored in the corresponding memory access pattern table in the cache LLC. The index information of the valid memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, or time pattern table. Based on the next memory access miss event and the index information of the prefetch pattern record table, the target memory access pattern is read from the corresponding memory access pattern table, and the prefetch address is calculated to generate a prefetch request. The data prefetch behavior corresponding to the prefetch request is then executed.

[0026] The beneficial effects are as follows: This invention can capture all memory access misses in real time by monitoring the current memory access miss events in the processor's L2 cache, providing accurate triggers and raw inputs for subsequent prefetching processes, ensuring that the prefetching process responds to memory access needs in a timely manner; by querying the miss status register and splitting the memory access miss address of the hit current memory access miss event, the base address of the spatial region and the offset address within the region can be accurately obtained, providing standardized address features for subsequent pattern training, ensuring the accuracy and relevance of pattern training; when the pattern training table of the current program counter hits the base address of the spatial region, stride pattern training and spatiotemporal pattern training are simultaneously performed on the offset address within the region, which can simultaneously obtain three memory access modes: fixed stride access, spatially related access, and temporally related access, comprehensively covering different types of memory access scenarios, improving the comprehensiveness and applicability of memory access pattern recognition; and classifying each memory access mode according to confidence level. The filtering process identifies stable and reliable effective memory access patterns, preventing invalid patterns from consuming storage resources. Effective memory access patterns are stored in the corresponding pattern table in the cache LLC and indexed in the prefetch pattern record table, separating the training unit from the storage unit and saving L2 cache resources. The index information also enables rapid subsequent location, reducing pattern lookup latency. Based on the next memory access miss event and the index information in the prefetch pattern record table, the target memory access pattern is read, the prefetch address is calculated, a prefetch request is generated, and data prefetching is executed. This allows data that the processor may access in the future to be backfilled into the L2 cache in advance, effectively reducing the L2 cache miss rate, decreasing processor memory access latency, and improving overall processor efficiency. Furthermore, multi-pattern fusion prefetching adapts to the memory access patterns of different programs and different stages of the same program, further improving prefetch accuracy and effectiveness and optimizing system memory access performance. Attached Figure Description

[0027] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of data access locality and storage hierarchy provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating potential risks of data prefetching, provided as an embodiment of the present invention. Figure 3 A hardware data prefetching phylogenetic diagram provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating an example of data prefetching provided in an embodiment of the present invention; Figure 5A flowchart of a data prefetching method based on multiple memory access modes provided in an embodiment of the present invention; Figure 6 A data prefetching architecture diagram provided in an embodiment of the present invention; Figure 7 A prefetching unit training module framework diagram provided in an embodiment of the present invention; Figure 8 A prefetching unit training flowchart is provided as an embodiment of the present invention; Figure 9 A prefetching unit initiates a prefetching module framework diagram provided in an embodiment of the present invention; Figure 10 A flowchart of a prefetching unit initiating a prefetching process is provided in an embodiment of the present invention; Figure 11 This is a structural diagram of a high-speed cache dynamic replacement unit module provided in an embodiment of the present invention; Figure 12 A flowchart illustrating a specific data prefetching method based on multiple memory access modes provided in this embodiment of the invention; Figure 13 A structural diagram of a pattern training unit provided in an embodiment of the present invention; Figure 14 A specific structural diagram of a pattern recording unit provided in an embodiment of the present invention; Figure 15 This is a structural diagram of a prefetching filter unit provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of a data prefetching device based on multiple memory access modes provided in an embodiment of the present invention; Figure 17 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0030] As the gap between memory access latency and processor cycle time widens, processors are experiencing increasingly severe memory access pauses, significantly impacting overall processor performance and a phenomenon known as the "memory wall" problem. Due to the principle of locality of reference—data accessed in the past may be accessed again soon—past accessed data can be stored in smaller SRAMs (Static Random Access Memory) closer to the CPU (Central Processing Unit), thus reducing the impact of memory access latency. Modern high-performance processors typically employ multi-level caches to further reduce the latency of frequently accessed data, such as... Figure 1 As shown, however, cache size has an upper limit, and cache cannot function effectively for first-time access or streaming access. Therefore, to better mask cache misses and improve processor performance, researchers chose to use data prefetching technology.

[0031] Hardware data prefetching technology primarily relies on adding extra hardware devices within the processor as prefetchers. By acquiring historical memory access information, it identifies potential memory access patterns, predicts future cache misses, and prefetches them into the cache in advance, thereby reducing memory access latency. This technology is now widely used in mainstream high-performance processors. The advantage of prefetching is its ability to eliminate first-time misses and patterned misses that cannot be resolved by replacement strategies or increasing cache size. Furthermore, unlike multithreading, which increases throughput to reduce computation unit wait time, data prefetching improves performance by shortening response time and is considered an effective means of addressing capacity misses and forced misses. Figure 2As shown, however, compared to software prefetching, hardware prefetching cannot obtain sufficient compilation information, which may introduce some potential risks, such as cache pollution, bandwidth, and energy consumption. Cache pollution stems from low accuracy and premature prefetching. If the data prefetching unit does not guarantee high accuracy, it may prefetch useless cache blocks and evict useful ones. Furthermore, even if the prefetched block will be used in the future, if the prefetching is too early, it may evict valid blocks within that early period, or the prefetched block may be evicted before it is used because it is unused, thus failing to provide effective cover for cache misses. In addition, the prefetching behavior issued by the data prefetching unit shares memory access bandwidth with normal memory access filling behavior. Therefore, prefetching behavior may preempt the MSHR (Miss-status Handling Registers) and bandwidth required for actual cache misses, thus causing normal memory miss latency. Especially in multi-core systems, simultaneous prefetching by multiple cores is more likely to exhaust bus bandwidth. In terms of energy consumption, prefetching useless cache blocks will result in a large number of cache and memory accesses, which may cause a significant loss of energy, especially when off-chip access or DRAM (Dynamic Random Access Memory) is required.

[0032] like Figure 3 As shown, hardware data prefetching is mainly divided into two types: historical information-based prefetching and execution-based prefetching. This solution focuses on historical information-based prefetching. Historical information-based prefetching involves studying historical memory access information to obtain memory access patterns and predict future missing memory addresses. It can be simply divided into four categories: sequential prefetching, stride prefetching, offset prefetching, and correlation prefetching. Correlation prefetching is further divided into time prefetching, spatial prefetching, and spatiotemporal prefetching.

[0033] like Figure 4The diagram illustrates the memory access patterns that different types of data prefetching units can acquire. The alphanumeric characters in the diagram represent memory access addresses over time. The top example is regular prefetching, where the interval between memory access addresses is 2. In this case, stride prefetching can be used for tracking. The address interval is determined to be 2 based on the preceding memory access sequence, meaning the stride is 2. Then, assuming a memory miss occurs at A+18, (A+18)+2=A+20 can be issued as the prefetch address. The middle example is irregular spatially dependent prefetching. Spatially dependent prefetching initially divides all data into equal-space regions. Therefore, the high-order bits of the memory access address serve as the base address of the spatial region, and the low-order bits serve as the offset address within the spatial region (assuming the memory access address is 1100011100111000, and a spatial region size is 32, then the lower 5 bits are the offset address within the spatial region, i.e., 11000, and the remaining high-order bits are the base address of the spatial region, i.e., 11000111001). A memory access sequence that occurs in one memory region may recur in another. Similarly, a memory access sequence that has appeared before may reappear in another memory region. For example, if memory access sequence {A, A+7, A+3, A+2} occurs in one memory region, and {B, B+7, B+3, B+2} occurs in another, then a memory access sequence that occurs in one region may recur in a later region. Therefore, this sequence can be prefetched. Timing prefetching refers to the sequential recurrence of memory accesses. As shown in the diagram, after address A is missing, address X can be prefetched.

[0034] Typically, each data prefetching algorithm excels at acquiring specific types of data. However, due to the differences in memory access sequence characteristics across various application scenarios, the prefetcher that delivers the best performance improvement often differs. For example, in applications containing a large number of loop instructions (memory access with regular strides under the same IP address), stride prefetching alone can achieve excellent performance improvements. However, in complex memory access environments, stride prefetching often fails to identify regular strides, requiring correlated prefetching to explore the implicit patterns between addresses as much as possible. Currently, prefetching technology suffers from the following problems: (1) The simulator test results show that MSHR Hit accounts for more than 50% of cache misses. Due to the slow bus data transmission and the large amount of missing data, the missing data does not return for a long time before it is filled back, so it keeps missing data. The missing of a single data may cause memory access delays for multiple instructions.

[0035] (2) Data prefetching is used to prefetch the memory access data that may be used in the future into the upper-level cache in advance, thereby reducing the cache miss situation. However, in some load scenarios, the cache miss rate is very low, and the data prefetched back may have a negative impact on the test results.

[0036] (3) A single data prefetching unit cannot effectively cover cache gaps in different scenarios. Because of different memory access characteristics, each prefetcher has different best applicable scenarios. Applicability can be increased by merging complementary prefetchers, but the cost of multi-mode record storage is relatively high.

[0037] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0038] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Next, we will describe in detail a data prefetching scheme based on multiple memory access modes provided by the embodiments of the present invention. Figure 5 A data prefetching method based on multiple memory access modes provided in this embodiment of the invention includes: Step S11: Listen for current memory access miss events in the processor's L2 cache.

[0040] like Figure 6 As shown, the overall architecture is mainly divided into three parts. The first part is the dynamic replacement algorithm in the L2 cache. The second part is the multi-mode fusion prefetch unit, which is independent of the cache. The third part is the pattern recording unit and prefetch filtering unit integrated into the L3 cache. The multi-mode fusion prefetch unit consists of pattern training, regional stride training, spatiotemporal pattern training, pattern table storage selection, and prefetch pattern recording. The pattern recording unit consists of a spatiotemporal pattern table, a time pattern table, and a stride pattern table.

[0041] In this embodiment, the monitoring of the current memory access miss event of the processor's L2 cache includes: continuously monitoring the memory access behavior of the processor's L2 cache, and identifying and capturing the current memory access miss event when the data access request initiated by the processor cannot be hit in the L2 cache.

[0042] In this embodiment, the current memory access miss event includes: the memory access miss address that triggered the miss, the program counter corresponding to the current access instruction, and the time and cache state at which the miss occurred.

[0043] Monitoring the current memory access miss event of the processor's L2 cache specifically refers to continuously monitoring and listening to all memory access behaviors of the processor's L2 cache in real time. When the processor core initiates a data access request to the L2 cache, and the data to be accessed cannot be hit in the L2 cache, resulting in a cache miss, the system will accurately identify and completely capture the current memory access miss event. In the specific implementation of this embodiment, the captured current memory access miss event is not a single signal, but contains a complete set of key information, including the core memory access miss address that triggered the cache miss, the program counter (PC) value corresponding to the data access instruction, the precise time when the miss occurred, and the running state of the L2 cache itself and the state of the cache entries at the moment the miss occurred. This complete information will be uniformly collected and transmitted to the subsequent MSHR query module, multi-mode fusion prefetch unit, and dynamic replacement unit as the key basis for memory access mode training, prefetch priority adjustment, and cache replacement decision-making.

[0044] Step S12: If the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region.

[0045] When an L2 cache miss occurs and the current miss event is captured, the missing address corresponding to the event is first sent to the Miss Status Register (MSHR) for query matching. If the query result is a match, it means that the missing request corresponding to the missing address has been recorded in the MSHR, the data is being backfilled and has not been returned. At this time, the system will perform an address splitting operation on the missing address of the current missing event. According to the preset spatial region division rules, the complete missing address is split into two parts: the high-order spatial region base address and the low-order intra-region offset address. The spatial region base address is used to identify the large spatial region to which the current memory access belongs, and the intra-region offset address is used to identify the specific location of the address in the corresponding spatial region. The two sets of address information obtained by splitting are synchronously sent to the pattern training module of the multi-mode fusion prefetch unit for subsequent stride pattern training and spatiotemporal pattern training, providing basic data support for memory access pattern recognition and prefetch address generation.

[0046] Step S13: If the base address of the spatial region is hit when querying the pattern training table of the current program counter, stride pattern training and spatiotemporal pattern training are performed on the offset address in the region to obtain each memory access pattern corresponding to fixed stride access, spatially related access and time-related access respectively.

[0047] like Figure 7As shown, the modular framework of the multi-mode fusion prefetching unit mainly includes a mode training table, a spatiotemporal mode training table, a stride mode training table, a prefetching mode record table, and spatiotemporal mode tables, temporal mode tables, and stride mode tables integrated in the L3 Cache. Furthermore, a separate buffer is designed at the same level as the mode training table to buffer the replacement of training unit entries and avoid frequent replacements.

[0048] like Figure 8 As shown, after the memory access miss address of the current memory access miss event is split to obtain the base address of the spatial region and the offset address within the region, the system will use the program counter corresponding to the current memory access miss event as a query index to access the pattern training table corresponding to the current program counter and perform a matching query on the base address of the spatial region.

[0049] If the query finds a match, it means that a corresponding historical memory access training record already exists in that spatial region, meeting the basic conditions for pattern training. At this point, the system will simultaneously perform stride pattern training and spatiotemporal pattern training on the offset addresses within the split region, thereby extracting three types of memory access patterns: fixed stride access, spatially related access, and temporally related access. The modules involved in initiating prefetching and their basic operational relationships are as follows: Figure 9 As shown, the system mainly includes a pattern training table and a stride pattern training table. These are used to issue prefetches when a suitable stride pattern is encountered during training. The corresponding pattern table index is searched in the prefetch pattern record, and the prefetch address is calculated based on the memory access pattern recorded in the corresponding pattern table (spatiotemporal, time, stride). All prefetch addresses are sent to the prefetch filtering unit. The number of prefetch addresses calculated (prefetch degree) is controlled by the prefetch filtering unit.

[0050] In a specific embodiment of stride pattern training, stride pattern training is performed on the offset addresses within the region to obtain a memory access pattern corresponding to a fixed stride access. This includes: determining the difference between the offset address within the region of the current memory miss event and the offset address within the region of the previous memory miss event to obtain the current stride value; updating the stride confidence corresponding to the current stride value and the stride confidence corresponding to other current stride values ​​based on the query result of whether the current stride value is found in the stride pattern training table; and generating a memory access pattern corresponding to a fixed stride access when any stride confidence is greater than a preset emission threshold.

[0051] In this embodiment, the stride pattern training for offset addresses within a region has a clear execution flow. First, the difference between the offset address within the region of the current memory access miss event and the offset address within the region of the previous memory access miss event in the same spatial region is calculated to obtain the current stride value. Then, the system accesses the stride pattern training table and updates the stride confidence corresponding to the current stride value based on the query result of whether the current stride value has a historical record in the table. At the same time, the stride confidence corresponding to other stride values ​​is adjusted synchronously to dynamically update the confidence level of each stride. When the stride confidence corresponding to any stride value is detected to be greater than the preset emission threshold, a memory access pattern corresponding to the fixed stride access is generated. Meanwhile, the spatiotemporal pattern training carried out simultaneously will complete the feature extraction of spatial locality and temporal locality respectively, and generate memory access patterns corresponding to spatially related access and temporally related access, providing complete pattern input for subsequent pattern filtering and prefetching operations.

[0052] In a specific embodiment of spatiotemporal pattern training, spatiotemporal pattern training is performed on the offset addresses within the region to obtain the memory access pattern corresponding to spatially related accesses. This includes: updating the bit vector stream based on the offset addresses within the region to mark the offsets within the region to which the offset addresses belong, and updating the time stream according to the order in which each offset is accessed to record the access order; updating the pattern confidence based on the number of times each offset appears in the access order, and updating the reuse confidence based on the number of times the same sequence appears consecutively in the access order; when the region to which the offset addresses belong is in an idle state is determined based on the access timestamps of each offset in the access order and a preset idle threshold, the memory access pattern corresponding to spatially related accesses is obtained.

[0053] Once the spatial region's base address is hit in the pattern training table of the current program counter, spatiotemporal pattern training is performed on the offset addresses within the already split region to generate memory access patterns for the corresponding space-related accesses. The specific process is as follows: First, the bit vector stream is updated in the spatiotemporal pattern training table based on the offset addresses in the current region, marking the corresponding position of the offset address in the spatial region as accessed, which is used to record all the offset positions that have been accessed in the spatial region. At the same time, the time stream is updated according to the order in which each offset address is actually accessed, completely preserving the order of memory accesses. Then, the pattern confidence is updated based on the number of times each offset appears repeatedly in the bit vector stream. The more times the offset appears, the higher the pattern confidence. Simultaneously, the reuse confidence is updated based on the number of times the same consecutive access sequence appears in the time stream. The more frequently the consecutive repeating sequence appears, the higher the reuse confidence. During this process, the timestamp of the spatial region corresponding to the offset address in the current region is continuously monitored. When the timestamp interval exceeds a preset idle threshold, it is determined that the spatial region has entered an idle state and the memory access pattern training is completed. Finally, the memory access pattern for the corresponding space-related accesses is generated, providing a basis for subsequent memory access pattern selection, storage, and prefetch address calculation.

[0054] In a specific embodiment of time pattern training, obtaining the memory access pattern corresponding to time-related access includes: after obtaining the memory access pattern corresponding to space-related access, extracting the address access sequence relationship that satisfies the preset stable conditions in the memory access pattern corresponding to space-related access, so as to form the memory access pattern corresponding to time-related access.

[0055] Obtaining the memory access pattern corresponding to time-related access requires relying on the completed training results of the spatially related access pattern. The specific process is as follows: After completing the training of the spatiotemporal pattern and obtaining the memory access pattern corresponding to the spatially related access, the system will extract the address access sequence relationship that meets the preset stability conditions from the bit vector stream, time stream, pattern confidence and reuse confidence information recorded in the spatially related access pattern. The stability conditions here refer to the bit vector stream length, pattern confidence and reuse confidence reaching the corresponding preset thresholds, and the address access order in the time stream showing a stable and repetitive pattern. The continuous address access order that meets the stability conditions and the corresponding association relationship are extracted to form a memory access pattern specifically corresponding to time-related access. This pattern will be selected and stored as an effective memory access pattern along with the stride pattern and the spatiotemporal pattern for subsequent prefetch address calculation and prefetch request generation.

[0056] In this embodiment, the stride confidence represents the prediction accuracy of the current stride value, the pattern confidence represents the stability of the offset access pattern in the region to which the offset address belongs, and the reuse confidence represents the probability of the same set of access sequences appearing repeatedly.

[0057] Stride confidence is used to characterize the accuracy of the currently calculated stride value in subsequent memory access predictions. It is a core indicator for judging the reliability of stride prefetching. The higher the confidence, the higher the prediction accuracy of the stride value. Pattern confidence is used to characterize whether the offset access pattern within the spatial region to which the offset address belongs in the current region is stable. The more times the offset address appears repeatedly, the higher the pattern confidence, indicating that the memory access offset pattern in this region is more stable and reliable. Reuse confidence is used to characterize the probability of the same set of memory access sequences appearing repeatedly. The more times the same sequence appears consecutively in the time stream, the higher the reuse confidence, indicating that the sequence is more likely to be reused. These three types of confidence indicators together serve as the key basis for memory access pattern screening, prefetch priority adjustment, cache dynamic replacement, and pattern table storage decisions.

[0058] Step S14: Classify and filter each memory access mode according to confidence level to select effective memory access modes, and store the effective memory access modes in the corresponding memory access mode table in the cache LLC. Record the index information of the effective memory access modes in the prefetch mode record table; wherein, the memory access mode table is any one of the stride mode table, spatiotemporal mode table and time mode table.

[0059] In this embodiment, the step of classifying and filtering each memory access mode according to its confidence level to select effective memory access modes and storing the effective memory access modes in the corresponding memory access mode table in the cache LLC includes: determining the memory access modes whose bit vector stream length is greater than a first preset threshold and whose mode confidence level is greater than a second preset threshold as first effective memory access modes, and storing the first effective memory access modes in the spatiotemporal mode table in the cache LLC; determining the memory access modes that are not first effective memory access modes and whose reuse confidence level is greater than a third preset threshold as second effective memory access modes, and storing the second effective memory access modes in the temporal mode table in the cache LLC.

[0060] Memory access patterns are categorized and filtered based on confidence level and bit vector stream length to determine effective memory access patterns, which are then stored in the corresponding memory access pattern table in the LLC. First, spatiotemporally related memory access patterns are judged. Memory access patterns with a bit vector stream length greater than a first preset threshold and a pattern confidence level greater than a second preset threshold are identified as the first effective memory access pattern. This pattern corresponds to a memory access rule combining spatial and temporal correlation. The first effective memory access pattern is then stored in the spatiotemporal pattern table in the LLC for subsequent data prefetching based on spatiotemporal correlation features. For memory access patterns that do not meet the first effective memory access pattern criteria, a second effective memory access pattern is further filtered. Memory access patterns in this category with a reuse confidence level greater than a third preset threshold are identified as the second effective memory access pattern. This pattern corresponds to a stable temporally related access sequence. The second effective memory access pattern is then stored in the temporal pattern table in the LLC, specifically for prefetching logic based on temporal order.

[0061] In this embodiment, the step of classifying and filtering each memory access mode according to confidence level to filter out effective memory access modes and storing the effective memory access modes in the corresponding memory access mode table in the cache LLC includes: determining the memory access mode with a step confidence level greater than a fourth preset threshold as a third effective memory access mode, and storing the third effective memory access mode in the step mode table in the cache LLC.

[0062] For memory access patterns of stride type, this embodiment sets an independent filtering rule to determine memory access patterns with stride confidence greater than the fourth preset threshold as the third effective memory access pattern. This pattern corresponds to a stable fixed stride access pattern. Finally, the third effective memory access pattern is stored in the stride pattern table in LLC to provide a reliable pattern basis for stride prefetching in the region.

[0063] In this embodiment, the index information includes an index, the schema table type to which each valid memory access mode belongs, and the corresponding entry identifier. The index is a combination of the program counter and memory access miss events.

[0064] After storing the valid memory access patterns into the corresponding schema table of the LLC, the index information of the valid memory access patterns needs to be accurately recorded in the prefetch schema record table. This index information is the key basis for quickly locating and finding the corresponding memory access patterns. Specifically, it includes the index used for matching and retrieval, the schema table type that identifies the storage location of the valid memory access patterns, and the unique entry identifier within the schema table. The index adopts a composite index form composed of the program counter (PC) and memory access miss event related information, which can uniquely correspond to a set of memory access contexts. The schema table type to which each valid memory access pattern belongs is used to distinguish whether it is stored in the spatiotemporal schema table, temporal schema table, or stride schema table in the LLC. The corresponding entry identifier is used to accurately locate the specific entry where the valid memory access pattern is located within the schema table. The high-order bits are used to identify the schema table to which it belongs, and the low-order bits are used to identify the specific position of the entry within the table. With this complete set of index information, when a new memory access miss event occurs in the future, the matching valid memory access pattern can be found directly and quickly, avoiding traversing all schema tables, improving search efficiency and reducing table lookup energy consumption.

[0065] Step S15: Based on the next memory access miss event and the index information of the prefetch pattern record table, read the target memory access pattern from the corresponding memory access pattern table and calculate the prefetch address to generate a prefetch request, and execute the data prefetch behavior corresponding to the prefetch request.

[0066] In this embodiment, the step of reading the target memory access pattern from the corresponding memory access pattern table and calculating the prefetch address based on the index information of the next memory access miss event and the prefetch pattern record table includes: when the next memory access miss event is detected, searching the prefetch pattern record table using the program counter and space region base address corresponding to the next memory access miss event as indexes to obtain the index information of the target valid memory access pattern; locating the corresponding target memory access pattern table in the cache LLC based on the index information of the target valid memory access pattern, and reading the target memory access pattern already stored in the target memory access pattern table; if the target memory access miss event is detected, the prefetch pattern table is searched to obtain the index information of the target valid memory access pattern; if the target memory access miss event is detected, the target memory access pattern table is searched to obtain the index information of the target valid memory access pattern; if the target memory access miss event is searched to obtain the index information of the target valid memory access pattern table, the target memory access pattern table is searched to obtain the index information of the target valid memory access pattern table ... If the target memory access mode is a memory access mode corresponding to fixed-step access, then the memory miss address of the next memory miss event is added to the step value to obtain the prefetch address; if the target memory access mode is a memory access mode corresponding to time-dependent access, then the next address of the memory miss address of the current memory miss event is determined from the memory access mode corresponding to time-dependent access, and the next address is determined as the prefetch address; if the target memory access mode is a memory access mode corresponding to space-dependent access, then the prefetch address is generated according to the access priority and bit vector stream of the memory access mode corresponding to space-dependent access.

[0067] The complete process of reading the target memory access pattern from the corresponding memory access pattern table and calculating the prefetch address based on the index information of the next memory access miss event and the prefetch pattern record table is as follows: When the system detects a new next memory access miss event, it uses the program counter (PC) and the spatial region base address corresponding to the event as a composite index to search the prefetch pattern record table, thereby matching and obtaining the index information of the target valid memory access pattern. Then, based on the pattern table type and entry identifier contained in the index information, it accurately locates the corresponding spatiotemporal pattern table, time pattern table, or stride pattern table in the LLC (Last Level Cache), and then retrieves the prefetch address from it. The system reads the stored target memory access patterns that have been trained. Then, it performs prefetch address calculations according to the different types of target memory access patterns. If the target memory access pattern corresponds to a fixed-step access pattern, the prefetch address is obtained by adding the memory miss address of the next memory miss event to the recorded step value. If it corresponds to a time-related access pattern, the system determines the next address of the current memory miss address from the pattern and uses it as the prefetch address. If it corresponds to a space-related access pattern, the system generates the corresponding prefetch addresses in sequence according to the access priority and bit vector stream information of the pattern. Finally, the prefetch address calculations for each type of pattern are completed.

[0068] like Figure 10 As shown, when an L2 cache miss occurs and the MSHR is missed, or a prefetch request hits, the address is simultaneously sent to both the region stride training table (where the entry location is found through the pattern training table) and the prefetch pattern record table for lookup. The region stride training table stores the addresses and strides of the region stride pattern being detected, but also maintains confidence information. To ensure effective prefetching, stride prefetching can be initiated if the confidence relationship is satisfied. If relevant entry information exists, and the stride between the new addresses is the same as the recorded stride and satisfies the confidence, the missing address is added to the stride to obtain the prefetch address, which is then sent to the prefetch filtering unit. The prefetch pattern record table records the locations of memory access patterns that have been trained and stored in the pattern table, i.e., which table and entry they are stored in. If corresponding information is found, the recorded memory access pattern is retrieved based on the specified location, the prefetch address is calculated based on the memory access pattern information, and then sent to the prefetch filtering unit.

[0069] In this embodiment, generating a prefetch request and performing data prefetching behavior corresponding to the prefetch request includes: obtaining a first prefetch degree coefficient corresponding to the real-time miss rate of the L2 cache and a second prefetch degree coefficient corresponding to the historical prefetch accuracy, and determining the product of the first prefetch degree coefficient and the second prefetch degree coefficient as a comprehensive prefetch degree coefficient; adjusting the number of allowed prefetch addresses to be issued according to the comprehensive prefetch degree coefficient; filtering each prefetch address, and summarizing the filtered prefetch addresses based on the number of prefetch addresses to generate a prefetch request; and performing data prefetching behavior on the memory corresponding to the prefetch request.

[0070] like Figure 10 As shown, the prefetch filtering unit has two functions: one is to feed back prefetch requests for prefetch degree adjustment based on the received cache miss information and prefetch accuracy information; the other is to filter out duplicate prefetch addresses. First, the prefetch filtering unit obtains the first prefetch degree coefficient corresponding to the real-time L2 cache miss rate and the second prefetch degree coefficient corresponding to the historical prefetch accuracy rate. The first and second prefetch degree coefficients are multiplied to obtain the comprehensive prefetch degree coefficient. Based on this comprehensive prefetch degree coefficient, the number of prefetch addresses currently allowed to be issued is dynamically adjusted to achieve adaptive control of the prefetch degree. Then, the Bloom filter inside the prefetch filtering unit filters all calculated prefetch addresses for duplicate addresses, removing recently issued prefetch addresses. The filtered valid prefetch addresses are then aggregated according to the adjusted number of prefetch addresses to generate a standardized prefetch request. Finally, an access is initiated to the memory level corresponding to the prefetch request to perform data prefetching behavior, thereby reducing the cache miss rate and memory access latency.

[0071] In this embodiment, the method further includes: when the processor's L2 cache is full and data replacement needs to be performed, calculating the target replacement total score for each cache line based on the unused cycle counter, the number of hits queried in the missing status register, and the number of prefetch hits for each cache line in the L2 cache; selecting target cache lines from each cache line based on the target replacement total score, and performing a replacement operation on the target cache lines.

[0072] In the L2 cache dynamic replacement logic, when the processor's L2 cache is full and a data replacement operation is required, the traditional LRU replacement strategy is not adopted. Instead, a multi-dimensional information is used to comprehensively calculate the target replacement total score for each cache line. Specifically, the target replacement total score for each cache line is calculated based on three key indicators: the unused cycle counter maintained by each cache line in the L2 cache, the number of cache line hits obtained from the Missing Status Register (MSHR), and the number of prefetch address hits for that cache line. Each indicator is assigned a corresponding weight coefficient and then weighted to obtain the target replacement total score for each cache line. The lower the score, the lower the probability of the cache line being accessed and the more suitable it is to be replaced. The higher the score, the higher its access value and the more it should be retained. Then, based on the calculated target replacement total score, all cache lines are sorted and filtered, and the target cache line with the lowest target replacement total score is selected. Finally, the data replacement operation is performed on the selected target cache line, thereby reducing the replacement of cache lines that are likely to be accessed in the future and have a large scope of miss impact, thus improving cache utilization and overall memory access performance.

[0073] like Figure 11 As shown, the dynamic replacement unit module structure for the cache receives signals from the L2MSHR and the prefetch unit. The dynamic replacement unit maintains a counter for each entry to record unused entries. Simultaneously, it combines MSHR hits and prefetch request cache hits to reduce the likelihood of replacing regions with high MSHR hit rates and cache lines with high prefetch request hit rates. The replacement entry's location is determined by comprehensively considering these three aspects and assigning weighted coefficients.

[0074] Therefore, this invention monitors the current memory access miss event of the processor's L2 cache; if the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region; if the spatial region base address is hit when querying the pattern training table of the current program counter, stride pattern training and spatiotemporal pattern training are performed on the offset address within the region to obtain each memory access pattern corresponding to fixed stride access, spatially dependent access, and temporally dependent access, respectively; and each memory access... The patterns are categorized and filtered according to confidence level to identify valid memory access patterns. These valid memory access patterns are then stored in the corresponding memory access pattern table in the cache LLC. The index information of the valid memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, or time pattern table. Based on the next memory access miss event and the index information of the prefetch pattern record table, the target memory access pattern is read from the corresponding memory access pattern table, and the prefetch address is calculated to generate a prefetch request. The data prefetch behavior corresponding to the prefetch request is then executed.

[0075] The beneficial effects are as follows: This invention can capture all memory access misses in real time by monitoring the current memory access miss events in the processor's L2 cache, providing accurate triggers and raw inputs for subsequent prefetching processes, ensuring that the prefetching process responds to memory access needs in a timely manner; by querying the miss status register and splitting the memory access miss address of the hit current memory access miss event, the base address of the spatial region and the offset address within the region can be accurately obtained, providing standardized address features for subsequent pattern training, ensuring the accuracy and relevance of pattern training; when the pattern training table of the current program counter hits the base address of the spatial region, stride pattern training and spatiotemporal pattern training are simultaneously performed on the offset address within the region, which can simultaneously obtain three memory access modes: fixed stride access, spatially related access, and temporally related access, comprehensively covering different types of memory access scenarios, improving the comprehensiveness and applicability of memory access pattern recognition; and classifying each memory access mode according to confidence level. The filtering process identifies stable and reliable effective memory access patterns, preventing invalid patterns from consuming storage resources. Effective memory access patterns are stored in the corresponding pattern table in the cache LLC and indexed in the prefetch pattern record table, separating the training unit from the storage unit and saving L2 cache resources. The index information also enables rapid subsequent location, reducing pattern lookup latency. Based on the next memory access miss event and the index information in the prefetch pattern record table, the target memory access pattern is read, the prefetch address is calculated, a prefetch request is generated, and data prefetching is executed. This allows data that the processor may access in the future to be backfilled into the L2 cache in advance, effectively reducing the L2 cache miss rate, decreasing processor memory access latency, and improving overall processor efficiency. Furthermore, multi-pattern fusion prefetching adapts to the memory access patterns of different programs and different stages of the same program, further improving prefetch accuracy and effectiveness and optimizing system memory access performance.

[0076] See Figure 12 This invention discloses a specific data prefetching method based on multiple memory access modes. Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. It includes: Step S21: Listen for current memory access miss events in the processor's L2 cache.

[0077] Step S22: If the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region.

[0078] When an L2 cache miss event occurs, the system first sends the miss address of the event to the Miss Status Register (MSHR) for matching. If the query result is a match, it means that the miss request corresponding to the memory address already exists in the MSHR, the data is being backfilled and has not yet been returned. At this time, the system will split the memory miss address of the current memory miss event according to the preset spatial region division rules, splitting the complete address into the high-order spatial region base address and the low-order intra-region offset address, providing basic address information for subsequent stride mode training and spatiotemporal mode training.

[0079] Step S23: If the current memory access miss event is not found when querying the miss status register, a new miss entry for recording the current memory access miss event is created in the miss status register, and the process jumps to the step of splitting the memory access miss address of the current memory access miss event.

[0080] If a miss is found when querying the memory access miss address for the current memory access miss event in the Miss Status Register (MSHR), it indicates that the miss request is the first occurrence and has not yet been recorded. The system will immediately create a new miss entry in the MSHR specifically for recording the current memory access miss event. After completing the entry creation and information registration, the system will directly jump to the memory access miss address splitting step, splitting the memory access miss address into the spatial region base address and the offset address within the spatial region according to the spatial region partitioning rules, and continue the subsequent memory access mode training process.

[0081] Step S24: If the spatial region base address is not hit when querying the pattern training table of the current program counter, write the current program counter, the spatial region base address and the offset address within the region into the lookup buffer to temporarily store the memory access behavior across spatial regions.

[0082] In this embodiment, writing the current program counter, the base address of the spatial region, and the offset address within the region into the lookup buffer includes: creating a new current address association relationship in the lookup buffer to store the current program counter, the base address of the spatial region, and the offset address within the region, and recording and updating the confidence level of the current address association relationship according to the time pattern.

[0083] When querying the pattern training table using the current program counter (PC) as an index, if the spatial region base address obtained from the splitting of the current memory access miss event is not found, it indicates that the current memory access scenario is a cross-spatial region, and the original training record is not applicable. At this time, the system will write the current program counter, the corresponding spatial region base address, and the offset address within the region into a specially set lookup buffer to temporarily store the cross-spatial region memory access behavior and avoid a small number of cross-region memory accesses interfering with the normal pattern training of the original region. In the specific implementation of this embodiment, when writing the above information into the lookup buffer, a new entry for storing the current address association relationship of the current program counter, spatial region base address, and offset address within the region will be created in the lookup buffer first. Then, the address association relationship will be recorded in time mode. At the same time, the pattern confidence and reuse confidence of the entry will be dynamically updated according to the confidence update rules of spatiotemporal pattern training. When the confidence of the entry meets the preset threshold condition, it will be used to update the pattern training table, and then continue to carry out normal stride pattern and spatiotemporal pattern training.

[0084] Step S25: If the base address of the spatial region is hit when querying the pattern training table of the current program counter, stride pattern training and spatiotemporal pattern training are performed on the offset address in the region to obtain memory access patterns corresponding to fixed stride access, spatially related access and time-related access respectively.

[0085] The specific structure of the pattern training unit is as follows: Figure 13 As shown, the system mainly consists of four parts: a pattern training table, a spatiotemporal pattern training table, a stride pattern training table, and a lookup buffer. The entries in the pattern training table are indexed by their program counters (PCs), and record the base address of the previous spatial region, the base address of the current spatial region, a timestamp, pattern confidence, reuse confidence, and entry position identifier. The spatiotemporal pattern training table is indexed by the entry identifier, which is provided by the pattern training table. Entry information includes the previous offset, bit vector stream, priority, time stream, and timestamp. The stride pattern training table includes the previous offset, stride, and confidence, allowing for independent training of multiple strides to improve prefetch probability. The lookup buffer is used to buffer changes in spatial regions. Entries in the lookup buffer are indexed by their PCs and record the base address of the previous spatial region, the base address of the current spatial region, a timestamp, pattern confidence, reuse confidence, bit vector stream, and time stream.

[0086] The spatiotemporal pattern training table is also used for: receiving MSHR hit feedback at fixed time intervals and increasing the prefetch priority of the corresponding memory access pattern based on the number of hits; terminating pattern training for a spatial region when its timestamp exceeds a preset idle threshold and sending an entry termination signal to the pattern training table. The pattern training table is configured with an independent lookup buffer, which temporarily stores cross-spatial region memory access information and updates the spatial region information of the pattern training table and synchronously refreshes the spatiotemporal pattern training table and stride pattern training table when the confidence level meets the threshold. The prefetch pattern record table is connected to a size adjustment module, which dynamically adjusts the capacity ratio of LLC and pattern record units and the storage space size of each pattern table based on the cache miss rate, prefetch optimized miss rate, and the number of effective memory access pattern entries. The spatiotemporal pattern training table receives MSHR data at fixed time intervals. The system provides hit feedback and adjusts the prefetch priority of corresponding memory access patterns based on the number of hits. This prioritizes the prefetching of high-hit, high-value memory access patterns, reduces cache misses for high-frequency memory access requests, further reduces memory access latency, and improves prefetching efficiency. When the timestamp of a spatial region exceeds a preset idle threshold, the training of patterns in that region is terminated and an entry termination signal is sent. This avoids invalid training on long-unaccessed spatial regions, saving hardware resources and computing power consumption for pattern training. At the same time, it releases storage resources occupied by idle regions, optimizing system resource allocation. The independent lookup buffer configured in the pattern training table can effectively store cross-spatial region memory access information, preventing a small number of cross-region memory accesses from interfering with the normal patterns of the original spatial regions. Training ensures the stability and accuracy of pattern training. When the confidence level meets the threshold, the pattern training table, spatiotemporal pattern training table, and stride pattern training table are updated synchronously to ensure the continuity and consistency of memory access pattern training and improve its effectiveness. The size adjustment module connected to the prefetch pattern record table dynamically adjusts the capacity ratio of the LLC and pattern record units, as well as the storage space size of each pattern table, based on the cache miss rate, prefetch optimized miss rate, and the number of valid memory access pattern entries. This enables adaptive adaptation to different load scenarios, avoiding storage space waste and shortage. While ensuring normal storage and fast lookup of valid memory access patterns, it reduces on-chip space resource consumption and optimizes overall memory access performance and system operating efficiency.

[0087] When a missing address in the L2 cache is not found in the MSHR (Memory Access Registry), it is sent to the pattern training table. The PC (Program Counter) is used as an index to search for a relevant entry. If found, the missing address is split: the high-order bits represent the spatial region base address, and the low-order bits represent the offset address within the region. The spatial region base address is compared with the current spatial region base address. If they are the same, it indicates that the previous memory access pattern training is continuing. Based on the entry's position identifier, the corresponding spatiotemporal pattern training table and stride pattern training table entries are found, and the offset address within the region is sent. The spatiotemporal pattern training table updates the bit vector stream according to the offset address position and records the time sequence, updating the previous offset to the current offset. Priority is initially recorded in chronological order. The MSHR reports the MSHR hit status at fixed intervals, adjusting the priority of entries with more hits upwards. If the interval timestamp is too long, it is recorded that the spatial region has not been used for a long time, at which point the spatial region training ends, and the termination entry is reported to the pattern training table. If the offset address has appeared before and its time sequence is the same as the previous offset, the reuse confidence value is increased. If the corresponding position in the bit vector stream is already 1, meaning the offset address appears repeatedly, the pattern confidence value is increased. The stride pattern training table calculates the current stride value by subtracting the previous offset value from the current one, increases the confidence of the corresponding stride, decreases the confidence of other strides, and then fills the previous offset position in the entry into the current offset value. If a corresponding stride is found and the confidence is higher than the transmission threshold, the stride is added to the offset value and combined with the spatial region base address to obtain the prefetch address, which is then sent to the filtering unit.

[0088] If a corresponding entry for the PC is found in the pattern training table, but the spatial region base address is different from the current recorded spatial region base address, it indicates that the previous spatial region training may have ended. The PC, spatial region base address, and offset value are then sent to the lookup buffer for storage. After finding the entry in the lookup buffer, the spatial region base address is compared, and the bit vector stream and confidence level are updated. The confidence level update method is the same as that described for the spatiotemporal pattern training table. If the spatial region base address is different, the confidence level is checked. If the bit vector stream length is large, the pattern confidence level is high, or the reuse confidence level is high, the entry in the pattern training table is updated and inserted into the spatiotemporal pattern training table, indicating that the spatial region training recorded in the pattern training table has ended. After the pattern training table is modified, the information in the lookup buffer is filled into the corresponding positions, and an update end signal is sent to the spatiotemporal pattern training table and the stride pattern training table. The two training tables will choose whether to store the previously recorded pattern confidence level and reuse confidence level information in the pattern table in the LLC and send it to the prefetch pattern record table. Specifically, if the bit vector stream is long and the pattern confidence is high, it is recorded as a spatiotemporal stream pattern table; if the spatiotemporal pattern recording conditions are not met, the reuse confidence is checked and the valid time pattern relationship is recorded as a time stream pattern relationship; for stride patterns, the stride confidence is checked to see if it exceeds the threshold, and if it does, it is recorded as a stride pattern relationship.

[0089] If no corresponding entry is found in the PC index of the pattern training table, a new entry is inserted, the base address of the current spatial region is filled in, and training begins. The remaining positions are set to the initial values.

[0090] Step S26: Classify and filter each memory access mode according to confidence level to select effective memory access modes, and store the effective memory access modes in the corresponding memory access mode table in the cache LLC. Record the index information of the effective memory access modes in the prefetch mode record table; wherein, the memory access mode table is any one of the stride mode table, spatiotemporal mode table and time mode table.

[0091] The specific structure of the pattern recording unit is as follows: Figure 14 As shown, the prefetch pattern record table uses the PC + previous spatial region as the entry index, recording the next spatial region, the initial offset, the table it belongs to, and the corresponding entry identifier. The high-order bits of the entry identifier indicate which pattern table it belongs to, and the low-order bits indicate the specific entry position in the table. After receiving memory access pattern information from the training unit, the prefetch pattern record identifies the memory access pattern type based on the source and identifier signal, and sends it to the corresponding pattern table for storage.

[0092] The pattern recording unit comprises three parts: a spatiotemporal pattern table, a temporal pattern table, and a stride pattern table. The spatiotemporal pattern table entries include entry identifier, bit vector stream, priority, and confidence level. When a corresponding entry is found, the bit vector stream is extracted sequentially according to the priority information and merged with the spatial region to obtain a prefetch address. The number of prefetch addresses issued at once is determined by the confidence level and the prefetch coefficients fed back from the prefetch filter table. The temporal pattern table entries include entry identifier, next address, confidence level, and consecutive entry identifier. When a corresponding entry is found based on the entry identifier, the next address is extracted as the prefetch address. The prefetch level is determined by multiplying the confidence level and the prefetch coefficients fed back from the prefetch filter table. If the prefetch level is not 1, the position of the next corresponding entry is found based on the consecutive entry identifier and issued. The stride pattern table entries include entry identifier, stride, and confidence level. After finding a corresponding entry, the missing address is added to the stride to obtain the prefetch address, which is then issued. Furthermore, the spatiotemporal pattern is further updated after being stored in the spatiotemporal pattern table. When a new spatiotemporal stream memory access mode arrives, it will also check if there are any identical bit vector streams. If the number of identical bit vectors is higher than the threshold, the value of the high bits in the confidence score will be increased. If it occurs several times, the same bit vector stream can be used in different spatial regions at the base address during prefetching. The next spatial region recorded by the corresponding prefetch mode will be identified by the high bits so that spatial prefetching can be performed in different spatial regions. However, the first offset must be the same as the previous spatial region to ensure the accuracy of prefetching.

[0093] As described above, the pattern recording unit is stored in the LLC, and the size ratio between the pattern recording unit and the LLC is controlled by the prefetch pattern table size adjustment module. The size adjustment module includes a Bloom filter that monitors the number of memory access patterns that have been trained and stored under various modes, i.e., the number of entries stored in the three pattern tables. It determines whether to expand or shrink the capacity based on the number of entries (larger capacity for more entries, smaller capacity for fewer entries). At the same time, by tracking the cache's own miss rate and comparing it with the miss rate information reduced by prefetching, it determines the size relationship between the entire pattern recording unit and the LLC capacity. That is, it determines whether the current capacity of the pattern table can bring good performance and whether there are enough entries or too much free space, and dynamically adjusts the overall size to adapt to different load application scenarios.

[0094] The specific structure of the prefetch filter unit is as follows: Figure 15The unit receives and monitors information from the L2 Cache, stride pattern training table, and pattern recording unit. Internally, it mainly consists of a Bloom filter and a prefetch adjustment table. The Bloom filter monitors whether prefetch addresses issued from the stride pattern training and pattern recording units have been issued recently. If they have, they are filtered out; otherwise, they are sent to the prefetch queue as real prefetch addresses. Issued prefetch addresses are recorded in the prefetch adjustment table along with their source. When a prefetch address hit occurs in the L2 Cache, the address is fed back to the prefetch filter unit. If it matches the recorded prefetch address, it is considered accurate; if it does not match before being evicted, it is considered inaccurate. This monitors the prefetch accuracy information for each memory access mode, with higher accuracy corresponding to a higher prefetch degree coefficient. Simultaneously, at fixed time intervals, the corresponding performance counter unit in the L2 Cache feeds back the miss rate to the prefetch adjustment table. A high miss rate increases the prefetch degree coefficient, while a low miss rate decreases it. The true prefetch coefficients can be obtained by multiplying the prefetch coefficients obtained from the two monitoring methods, and the prefetch status in stride pattern training and pattern recording units can be adjusted accordingly.

[0095] Step S27: Based on the next memory access miss event and the index information of the prefetch pattern record table, read the target memory access pattern from the corresponding memory access pattern table and calculate the prefetch address to generate a prefetch request, and execute the data prefetch behavior corresponding to the prefetch request.

[0096] By analyzing MSHR hit rates, entries with high hit frequencies are prefetched to reduce their probability of being replaced by the cache, thereby minimizing the impact of memory access latency on instruction execution. The pattern training unit is separated from the memory access pattern storage unit. The training unit performs pattern training independently, storing only valid memory access patterns filtered by confidence. The memory access pattern storage unit is placed in the LLC to reduce on-chip space resource consumption. After spatiotemporal pattern training is completed, it is stored according to confidence information and bit vector stream length, categorized into temporal and spatiotemporal patterns respectively, thus integrating temporal prefetching and spatial prefetching. The advantages include comprehensive coverage of various memory access loss scenarios; stride patterns can be prefetched both during training and after being stored in the pattern table, increasing the probability of stride prefetching triggering; stride patterns are confined to a single spatial region, enhancing stride regularity and saving storage capacity; and by setting multiple stride groups and independently maintaining their confidence, the probability of obtaining effective stride patterns and the accuracy and coverage of prefetching are improved; a pattern training table is set up to uniformly record common entry information of the spatiotemporal pattern training table and the stride pattern training table, avoiding duplicate information storage to reduce capacity overhead, and an independent lookup buffer is configured in the pattern training table. To prevent minor cross-region memory accesses from interfering with normal training in the original region, entry replacement is only performed and the pattern training in the corresponding region ends when the confidence level meets the standard. The effective memory access patterns obtained during training are stored in the pattern recording unit, and their entry positions are recorded in the prefetch pattern recording table, allowing for direct location lookup. This avoids repeatedly traversing all records for missing addresses without effective patterns, reducing lookup energy consumption and improving lookup efficiency. A size adjustment module is mounted on the prefetch pattern recording table to dynamically adjust the total space occupied by the LLC and the pattern recording unit based on the cache's own missing rate and the prefetch-optimized missing rate, and adjusts the space according to newly added effective memory accesses. The storage mode quantity adjustment adjusts the capacity of the three mode tables (space-time, time-based, and step-time) to adapt to different load scenarios. The prefetch filtering unit has a built-in Bloom filter to filter duplicate prefetch addresses, avoiding resource waste. At the same time, it monitors cache misses and prefetch accuracy through the prefetch adjustment table, configures corresponding prefetch coefficients for various memory access modes, and dynamically adjusts the number of prefetch requests from the outside to adapt to different load characteristics. The cache replacement strategy, based on the traditional LRU, additionally combines MSHR hit count and prefetch hit status for a comprehensive score, reducing the possibility of high-value, high-impact cache lines being replaced and improving overall cache efficiency.

[0097] Figure 16 A schematic diagram of a data prefetching device based on multiple memory access modes provided in an embodiment of the present invention includes: The monitoring module 11 is used to monitor the current memory access miss event of the processor's L2 cache; Address splitting module 12 is used to split the memory access miss address of the current memory access miss event when the current memory access miss event is hit during the query in the miss status register, so as to obtain the spatial region base address and the offset address within the region. Training module 13 is used to perform stride pattern training and spatiotemporal pattern training on the offset address in the spatial region if the base address of the spatial region is hit when the pattern training table of the current program counter is queried, so as to obtain each memory access pattern corresponding to fixed stride access, spatially related access and time-related access respectively. The information recording module 14 is used to classify and filter the memory access modes according to their confidence levels to select effective memory access modes and store the effective memory access modes in the corresponding memory access mode table in the cache LLC. The index information of the effective memory access modes is recorded in the prefetch mode record table. The memory access mode table can be any one of the stride mode table, spatiotemporal mode table, and time mode table. The data prefetch module 15 is used to read the target memory access pattern from the corresponding memory access pattern table and calculate the prefetch address based on the next memory access miss event and the index information of the prefetch pattern record table, so as to generate a prefetch request and execute the data prefetch behavior corresponding to the prefetch request.

[0098] Furthermore, embodiments of this application also disclose an electronic device, Figure 17 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data prefetching method based on multiple memory access modes disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0099] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0100] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0101] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the data prefetching method based on multiple memory access modes executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0102] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned data prefetching method based on multiple memory access modes. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0103] Furthermore, embodiments of this application also disclose a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the data prefetching method based on multiple memory access modes disclosed in any of the foregoing embodiments.

[0104] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0105] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0106] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0107] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for data prefetching based on multiple memory access patterns, the method comprising: include: Monitor the current memory access miss event of the processor's L2 cache; If the current memory access miss event is hit when querying the miss status register, the memory access miss address of the current memory access miss event is split to obtain the spatial region base address and the offset address within the region; If the base address of the spatial region is hit when the pattern training table of the current program counter is queried, stride pattern training and spatiotemporal pattern training are performed on the offset address in the region to obtain memory access patterns corresponding to fixed stride access, spatially related access and time-related access respectively. The memory access patterns are classified and filtered according to their confidence levels to select effective memory access patterns. The effective memory access patterns are stored in the corresponding memory access pattern table in the cache LLC. The index information of the effective memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, and time pattern table. Based on the next memory access miss event and the index information of the prefetch pattern record table, the target memory access pattern is read from the corresponding memory access pattern table and the prefetch address is calculated to generate a prefetch request, and the data prefetch behavior corresponding to the prefetch request is executed.

2. The method of claim 1, wherein, The current memory access miss events of the L2 cache of the monitoring processor include: The system continuously monitors the memory access behavior of the processor's L2 cache. When a data access request initiated by the processor cannot be found in the L2 cache, the system identifies and captures the current memory access miss event.

3. The method of claim 1, wherein, The current memory access miss event includes: the memory access miss address that triggered the miss, the program counter corresponding to the current access instruction, the time when the miss occurred, and the cache state.

4. The method of claim 1, wherein, Also includes: If the current memory access miss event is not found when querying the miss status register, a new miss entry for recording the current memory access miss event is created in the miss status register, and the process jumps to the step of splitting the memory access miss address of the current memory access miss event.

5. The method of claim 1, wherein, Also includes: If the base address of the spatial region is not hit when querying the pattern training table of the current program counter, the current program counter, the base address of the spatial region, and the offset address within the region are written into the lookup buffer to temporarily store the memory access behavior across spatial regions.

6. The method of claim 5, wherein, The step of writing the current program counter, the base address of the spatial region, and the offset address within the region into the lookup buffer includes: In the lookup buffer, a new current address association is created to store the current program counter, the base address of the spatial region, and the offset address within the region. The current address association is then recorded and updated with confidence according to a time pattern.

7. The data prefetching method based on multiple memory access modes according to claim 1, characterized in that, Step pattern training is performed on the offset addresses within the region to obtain the memory access pattern corresponding to fixed step size access, including: The difference between the offset address within the region of the current memory miss event and the offset address within the region of the previous memory miss event is determined to obtain the current step value; Update the stride confidence score corresponding to the current stride value and the stride confidence scores corresponding to other current stride values ​​based on whether the query result of the current stride value is found in the stride pattern training table; When the confidence level of any step is greater than the preset emission threshold, a memory access mode with a corresponding fixed step is generated.

8. The data prefetching method based on multiple memory access modes according to claim 7, characterized in that, Spatiotemporal pattern training is performed on the offset addresses within the region to obtain the memory access patterns corresponding to spatially related accesses, including: The bit vector stream is updated based on the offset address within the region to mark the offsets within the region to which the offset address belongs. The time stream is also updated according to the order in which each offset is accessed to record the access order. The pattern confidence is updated based on the number of recurrences of each offset in the access order, and the reuse confidence is updated based on the number of occurrences of consecutive identical sequences in the access order. When the memory access mode of the offset address in the access sequence is determined to be in an idle state based on the access timestamp of each offset in the access sequence and the preset idle threshold, the memory access mode of the corresponding space-related access is obtained.

9. The data prefetching method based on multiple memory access modes according to claim 8, characterized in that, Retrieve memory access patterns related to the corresponding time, including: After obtaining the memory access patterns of the corresponding space-related accesses, the address access sequence relationships that meet the preset stability conditions in the memory access patterns of the corresponding space-related accesses are extracted to form the memory access patterns of the corresponding time-related accesses.

10. The data prefetching method based on multiple memory access modes according to claim 9, characterized in that, The stride confidence represents the prediction accuracy of the current stride value, the pattern confidence represents the stability of the offset access pattern in the region to which the offset address belongs, and the reuse confidence represents the probability of the same set of access sequences repeating.

11. The data prefetching method based on multiple memory access modes according to claim 10, characterized in that, The step of classifying and filtering the memory access patterns according to their confidence levels to identify effective memory access patterns, and storing the effective memory access patterns in the corresponding memory access pattern table in the cache LLC, includes: The memory access mode whose bit vector stream length is greater than a first preset threshold and whose mode confidence is greater than a second preset threshold is determined as the first valid memory access mode, and the first valid memory access mode is stored in the space-time mode table in the cache LLC. The memory access mode that is determined to be a non-first valid memory access mode and whose reuse confidence is greater than a third preset threshold is determined to be a second valid memory access mode, and the second valid memory access mode is stored in the time pattern table in the cache LLC.

12. The data prefetching method based on multiple memory access modes according to claim 10, characterized in that, The step of classifying and filtering the memory access patterns according to their confidence levels to identify effective memory access patterns, and storing the effective memory access patterns in the corresponding memory access pattern table in the cache LLC, includes: The memory access mode with a stride confidence greater than a fourth preset threshold is determined as the third valid memory access mode, and the third valid memory access mode is stored in the stride mode table in the cache LLC.

13. The data prefetching method based on multiple memory access modes according to claim 1, characterized in that, The index information includes the index, the schema table type to which each valid memory access mode belongs, and the corresponding entry identifier. The index is a combination of the program counter and memory access miss events.

14. The data prefetching method based on multiple memory access modes according to claim 13, characterized in that, The step of reading the target memory access pattern from the corresponding memory access pattern table and calculating the prefetch address based on the next memory access miss event and the index information of the prefetch pattern record table includes: When the next memory access miss event is detected, the prefetch mode record table is searched using the program counter and the base address of the memory region corresponding to the next memory access miss event as indexes to obtain the index information of the target valid memory access mode. Based on the index information of the target valid memory access mode, locate the corresponding target memory access mode table in the cache LLC, and read the target memory access mode already stored in the target memory access mode table; If the target memory access mode is a memory access mode corresponding to a fixed step size, then the memory miss address of the next memory miss event is added to the step size value to obtain the prefetch address. If the target memory access mode is a memory access mode corresponding to time-related access, then the next address of the memory miss address of the current memory miss event is determined from the memory access mode corresponding to time-related access, and the next address is determined as the prefetch address. If the target memory access mode is a memory access mode related to the corresponding space, then a prefetch address is generated based on the access priority of the memory access mode related to the corresponding space and the bit vector stream.

15. The data prefetching method based on multiple memory access modes according to claim 13, characterized in that, Generate a prefetch request and perform data prefetching actions corresponding to the prefetch request, including: Obtain the first prefetch coefficient corresponding to the real-time miss rate of the L2 cache and the second prefetch coefficient corresponding to the historical prefetch accuracy, and determine the product of the first prefetch coefficient and the second prefetch coefficient as the comprehensive prefetch coefficient. Adjust the number of prefetch addresses allowed to be issued according to the comprehensive prefetch coefficient. Each of the prefetch addresses is filtered, and the filtered prefetch addresses are aggregated based on the number of prefetch addresses to generate a prefetch request; Perform a data prefetch operation on the memory corresponding to the prefetch request.

16. The data prefetching method based on multiple memory access modes according to any one of claims 1 to 15, characterized in that, Also includes: When the processor's L2 cache is full and data replacement needs to be performed, the target replacement total score for each cache line is calculated based on the unused cycle counter of each cache line in the L2 cache, the number of hits queried in the missing status register, and the number of prefetch hits. Based on the target replacement total score, target cache lines are selected from each cache line, and a replacement operation is performed on the target cache lines.

17. A data prefetching device based on multiple memory access modes, characterized in that, include: The monitoring module is used to monitor the current memory access miss event of the processor's L2 cache; The address splitting module is used to split the memory access miss address of the current memory access miss event when the current memory access miss event is hit during the query in the miss status register, so as to obtain the spatial region base address and the offset address within the region. The training module is used to perform stride pattern training and spatiotemporal pattern training on the offset address in the spatial region if the base address of the spatial region is hit when the pattern training table of the current program counter is queried, so as to obtain each memory access pattern corresponding to fixed stride access, spatially related access and time-related access respectively. The information recording module is used to classify and filter the memory access patterns according to their confidence levels to select effective memory access patterns and store the effective memory access patterns in the corresponding memory access pattern table in the cache LLC. The index information of the effective memory access patterns is recorded in the prefetch pattern record table. The memory access pattern table can be any one of the stride pattern table, spatiotemporal pattern table, and time pattern table. The data prefetch module is used to read the target memory access pattern from the corresponding memory access pattern table and calculate the prefetch address based on the next memory access miss event and the index information of the prefetch pattern record table, so as to generate a prefetch request and execute the data prefetch behavior corresponding to the prefetch request.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data prefetching method based on multiple memory access modes as described in any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein, when the computer programs are executed by a processor, they implement the steps of the data prefetching method based on any one of claims 1 to 16.

20. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the steps of the data prefetching method based on multiple memory access modes as described in any one of claims 1 to 16.

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