Peep-proof control pixel circuit, peep-proof control module, peep-proof control method and peep-proof control device

Abstract

The invention provides a peep-proof control pixel circuit, a peep-proof control module, a peep-proof control method and a peep-proof device.The peep-proof control pixel circuit comprises a light-emitting control line, a data line, a plurality of scanning lines, a driving module, a control module, a peep-proof module and a peep-proof signal line, and the driving module converts a data signal transmitted by the data line into a pixel driving signal; the pixel driving signal is output to the control module; the peep-proof signal line is used for transmitting a received peep-proof signal to the control module, and the control module controls the peep-proof module to perform peep-proof display based on the peep-proof signal and the pixel driving signal; by changing the size of the signal received by the peep-proof signal line, the peep-proof module is further changed to select peep-proof display or conventional display, so that peep-proof display is flexibly selected, peep-proof control of any area is realized, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of display control technology, specifically to a privacy control pixel circuit, a privacy control module, a method, and an apparatus. Background Technology

[0002] Organic Matrix Organic Light Emitting Diode (AMOLED) flat panel displays use organic materials to create light-emitting devices and TFTs (thin-film transistors) to construct pixel circuits. Pixels are arranged in an array, and the display uses a line-by-line scanning refresh method.

[0003] Currently, the use of privacy films or full-screen privacy materials to achieve privacy effects is insufficient. This approach does not allow for flexible selection of the privacy area size or complex modifications to the pixel circuitry, increasing wiring difficulties, raising costs, and reducing the user experience. Summary of the Invention

[0004] To address the aforementioned technical problem of not being able to select a specific area for privacy protection, this invention provides a privacy control pixel circuit, a privacy control module, a method, and an apparatus.

[0005] In a first aspect, embodiments of this application provide a privacy control pixel circuit. The privacy control pixel circuit includes an emission control line, a data line, and multiple scan lines. The privacy control pixel circuit further includes a driving module, a control module, a privacy module, and a privacy signal line. The first input terminal of the driving module is connected to the data line, and the output terminal of the driving module is connected to the first input terminal of the control module. The driving module is used to convert the data signal transmitted by the data line into a pixel driving signal and output the pixel driving signal to the control module. The second input terminal of the control module is connected to the privacy signal line, and the privacy signal line is used to transmit the received privacy signal to the control module. The control module controls the privacy module to perform privacy display based on the privacy signal and the pixel driving signal.

[0006] In conjunction with the first aspect, in one possible implementation, the control module includes: a first transistor and a second transistor, the control terminals of the first transistor and the second transistor being connected to a first node and receiving a privacy signal transmitted via a privacy signal line, the privacy signal including a tri-state signal used to control both the first transistor and the second transistor to be in an off state; preferably, the control module further includes a third transistor, the first terminal of the third transistor being connected to the first node, and the second terminal of the third transistor being connected to the privacy signal line as a second input terminal of the control module; preferably, the control module further includes a first capacitor, the first terminal of the first capacitor being connected to the first node, and the second terminal of the first capacitor being connected to a first power supply voltage line.

[0007] In conjunction with the first aspect, in one possible implementation, the first transistor and the second transistor are of different types; preferably, the first transistor is an N-type thin-film transistor and the second transistor is a P-type thin-film transistor.

[0008] In conjunction with the first aspect, in one possible implementation, the control module further includes a third input terminal, which is connected to the light emission control line; or, the third input terminal of the control module is connected to the third scan line; preferably, the control module includes a third transistor, the control terminal of which serves as the third input terminal of the control module and is connected to the light emission control line, or, the control terminal of which serves as the third input terminal of the control module and is connected to the third scan line; preferably, the driving module further includes a second input terminal, a third input terminal, and a fourth input terminal, the second input terminal of which is connected to the light emission control line, the third input terminal of which is connected to the first scan line, and the fourth input terminal of which is connected to the second scan line. Preferably, the first output terminal of the control module is connected to the first input terminal of the privacy module, and the second output terminal of the control module is connected to the second input terminal of the privacy module; preferably, the control module includes a first transistor and a second transistor, the first terminal of the first transistor serves as the first input terminal of the control module, the first terminal of the second transistor is connected to the first terminal of the first transistor, the second terminal of the first transistor serves as the first output terminal of the control module and is connected to the first input terminal of the privacy module; the second terminal of the second transistor serves as the second output terminal of the control module and is connected to the second input terminal of the privacy module.

[0009] In conjunction with the first aspect, in one possible implementation, the privacy module includes: a conventional light-emitting diode (LED) and a privacy LED; the first electrode of the conventional LED serves as the first input terminal of the privacy module and is connected to the first output terminal of the control module, the second electrode of the conventional LED and the second electrode of the privacy LED are connected to a second power supply voltage line, and the conventional LED is used for conventional display; the first electrode of the privacy LED serves as the second input terminal of the privacy module and is connected to the second output terminal of the control module, and the privacy LED is used for privacy display; preferably, the viewing angle of the privacy LED is a preset acute angle or right angle.

[0010] In conjunction with the first aspect, in one possible implementation, the driving module includes: a first driving unit; a first input terminal of the first driving unit is connected to a data line as the first input terminal of the driving module, a second input terminal of the first driving unit is connected to a light emission control line as the second input terminal of the driving module, a third input terminal of the first driving unit is connected to a first scan line as the third input terminal of the driving module, a fourth input terminal of the first driving unit is connected to a second scan line as the fourth input terminal of the driving module, and an output terminal of the first driving unit is connected to a first input terminal of the control module as the output terminal of the driving module; preferably, the first driving unit includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a... The system comprises eight transistors, a ninth transistor, and a second capacitor; the control terminal of the fourth transistor serves as the fourth input terminal of the first driving unit and is connected to the control terminal of the fifth transistor to the second scan line; the first terminal of the fourth transistor serves as the first input terminal of the first driving unit and is connected to the data line; the second terminal of the fourth transistor is connected to the first terminals of the sixth and seventh transistors; the first terminals of the fifth and eighth transistors, the control terminals of the seventh transistor, and one end of the second capacitor are connected; the second terminal of the fifth transistor serves as the output terminal of the first driving unit and is connected to the second terminal of the seventh transistor, the first terminal of the ninth transistor, and the first input terminal of the control module; the control terminal of the sixth transistor serves as the second input terminal of the first driving unit and is connected to the light-emitting control line; the second terminal of the sixth transistor and the other end of the second capacitor are connected to the third power supply voltage line; the control terminal of the eighth transistor serves as the third input terminal of the first driving unit and is connected to the control terminal of the ninth transistor to the first scan line; the second terminals of the eighth and ninth transistors are connected to the first power supply voltage line; preferably, the fourth, fifth, sixth, seventh, eighth, and ninth transistors are of the same type; preferably, the fourth, fifth, sixth, seventh, eighth, and ninth transistors are all P-type thin-film transistors; or, the driving module includes: a second driving unit; the first terminal of the second driving unit... The input terminal serves as the first input terminal of the driving module and is connected to the data line. The second input terminal of the second driving unit serves as the second input terminal of the driving module and is connected to the light emission control line. The third input terminal of the second driving unit serves as the third input terminal of the driving module and is connected to the first scan line. The fourth input terminal of the second driving unit serves as the fourth input terminal of the driving module and is connected to the second scan line. The fifth input terminal of the second driving unit is connected to the fourth scan line. The output terminal of the second driving unit serves as the output terminal of the driving module and is connected to the first input terminal of the control module. Preferably, the second driving unit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a third capacitor.The control terminal of the tenth transistor is connected to the second scan line as the fourth input terminal of the second driving unit. The first terminal of the tenth transistor is connected to the data line as the first input terminal of the second driving unit. The second terminal of the tenth transistor is connected to the first terminals of the eleventh and twelfth transistors. The control terminal of the eleventh transistor, the first terminals of the thirteenth and fourteenth transistors, and the first terminal of the third capacitor are connected. The second terminal of the eleventh transistor is connected to the second terminal of the thirteenth transistor, the first terminal of the fifteenth transistor, and the first input terminal of the control module as the output terminal of the second driving unit. The control terminal of the twelfth transistor is connected to the light emission control line as the second input terminal of the second driving unit. The second terminal of the twelfth transistor is connected to the second terminal of the third capacitor. The control terminal of the thirteenth transistor is connected to the third power supply voltage line; the control terminal of the thirteenth transistor is connected to the first scan line as the fifth input terminal of the second driving unit; the control terminal of the fourteenth transistor is connected to the first scan line as the fourth input terminal of the second driving unit, and the second terminals of the fourteenth and fifteenth transistors are connected to the first power supply voltage line; preferably, the tenth, eleventh, and twelfth transistors are of the same type, the thirteenth, fourteenth, and fifteenth transistors are of the same type, and the tenth and thirteenth transistors are of different types; preferably, the tenth, eleventh, and twelfth transistors are all P-type thin-film transistors, and the thirteenth, fourteenth, and fifteenth transistors are all N-type thin-film transistors.

[0011] Secondly, embodiments of this application provide a privacy control module, the module including any of the privacy control pixel circuits as described in the first aspect, and further including: a timing control module, a shift register, a level conversion module, a multiplexing module, and a display driver chip; one end of the timing control module is connected to an external host, and the other end of the timing control module is connected to one end of the shift register; the timing control module is used to receive privacy area information sent by the external host, and after parsing the privacy area information, sends a privacy parsing signal to the shift register; the privacy area information includes privacy area coordinate data; the shift register... The other end of the bit register is connected to one end of the level conversion module. The shift register is used to transmit the privacy protection parsing information to the level conversion module. The other end of the level conversion module is connected to one end of the multiplexing module. The other end of the multiplexing module is connected to multiple privacy protection signal lines. The level conversion module converts the privacy protection parsing information and transmits it to the multiplexing module so that the multiplexing module can transmit privacy protection signals to the privacy protection signal lines according to the privacy protection parsing information. The display driver chip is connected to the privacy protection control pixel circuit. The display driver chip is used to drive the driver module in the privacy protection control pixel circuit.

[0012] In conjunction with the second aspect, in one possible implementation, the multiplexing module includes: multiple multiplexing units; one end of each multiplexing unit is connected to a level conversion module, and the other end of each multiplexing unit is connected to one of a plurality of privacy protection signal lines; preferably, the multiplexing unit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are of the same type; the control terminals of the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are respectively connected to a timing control module, and the first terminal of the sixteenth transistor, the tenth transistor, and the nineteenth transistor are connected to a timing control module. The first terminals of transistors seven, eighteen, and nineteen are connected to the privacy signal line; the second terminal of transistor sixteen is connected to the high-level signal line, the second terminal of transistor seventeen is connected to the low-level signal line, the second terminal of transistor eighteen is connected to the tri-state signal line, and the second terminal of transistor nineteen is connected to the level conversion signal line corresponding to the level conversion module. The tri-state signal line is used to output a tri-state signal, which is used to control both N-type and P-type thin-film transistors to be off. Preferably, transistors sixteen, seventeen, eighteen, and nineteen are all P-type thin-film transistors.

[0013] Thirdly, embodiments of this application provide a privacy control method applied to a privacy control module as described in the second aspect, comprising: acquiring privacy area information sent by an external host, wherein the privacy area information is coordinate data of a target area selected by the external host, and the number of target areas is at least one; parsing the privacy area information to obtain a target privacy signal; controlling the drive module and the privacy signal line to initialize the privacy module; and performing privacy control on the initialized privacy module according to the target privacy signal.

[0014] In conjunction with the third aspect, in one possible implementation, the method further includes: obtaining the number of regions and the coordinates of the regions corresponding to the target partition; generating anti-spying region information based on the number of regions and the coordinates of the regions; preferably, parsing the anti-spying region information to obtain a target anti-spying signal, including: parsing the anti-spying region information to obtain anti-spying parsing data; and binarizing the anti-spying parsing data to obtain the corresponding target anti-spying signal.

[0015] In conjunction with the third aspect, in one possible implementation, the control driving module and the anti-spy signal line initialize the anti-spy module, including: the control driving module resetting the pixels of the anti-spy module; using a tri-state signal output from the control anti-spy signal line to shut down the internal control module, so that the driving module performs pixel compensation, the tri-state signal being used to control both the first transistor and the second transistor to be in a turned-off state; initializing the anti-spy module according to the pixel reset and pixel compensation; preferably, anti-spy control is performed on the initialized anti-spy module according to the target anti-spy signal, including: outputting the value of the target anti-spy signal through the control anti-spy signal line, the target anti-spy signal being binary data; when the value of the target anti-spy signal is 1 in the binary representation, determining the first... The voltage value corresponding to the node is a high-level signal; based on the high-level signal, it is determined that the first transistor is in a first conducting state and the second transistor is in a first turning-off state; based on the first conducting state, the conventional LED in the privacy module is turned on, and based on the first turning-off state, the privacy LED is turned off; or, when the value of the target privacy signal is 0 in the binarization, the voltage value corresponding to the first node is determined to be a low-level signal; based on the low-level signal, it is determined that the first transistor is in a second turning-off state and the second transistor is in a second conducting state; based on the second turning-off state, the conventional LED in the privacy module is turned off, and based on the second conducting state, the privacy LED is turned on.

[0016] Fourthly, embodiments of this application provide a privacy control device, including: an external host; and, any of the privacy control modules in the second aspect, wherein the privacy control module and the external host are electrically connected.

[0017] The privacy control pixel circuit, privacy control module, method, and apparatus provided in this application include a light-emitting control line, a data line, multiple scan lines, a driving module, a control module, a privacy module, and a privacy signal line. The first input terminal of the driving module is connected to the data line, and the output terminal of the driving module is connected to the first input terminal of the control module. The driving module converts the data signal transmitted by the data line into a pixel driving signal and outputs the pixel driving signal to the control module. The second input terminal of the control module is connected to the privacy signal line, which transmits the received privacy signal to the control module. The control module controls the privacy module to perform privacy display based on the privacy signal and the pixel driving signal. By changing the signal strength received by the privacy signal line, the privacy module can be configured to perform either privacy display or regular display, achieving flexible selection of privacy display and enabling privacy control in any area, thus improving the user experience. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Furthermore, these drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments.

[0019] Figure 1a This is a schematic diagram of the structure of a privacy control pixel circuit provided in Embodiment 1 of this application.

[0020] Figure 1b This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application.

[0021] Figure 2a This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application.

[0022] Figure 2b This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application.

[0023] Figure 3 This is a schematic diagram of a privacy control pixel circuit provided in Embodiment 2 of this application.

[0024] Figure 4 This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 2 of this application.

[0025] Figure 5a This is a schematic diagram of the structure of a privacy control pixel circuit provided in Embodiment 3 of this application.

[0026] Figure 5b This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 3 of this application.

[0027] Figure 5c This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 3 of this application.

[0028] Figure 5d This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 3 of this application.

[0029] Figure 6a This is a timing diagram of odd-numbered frames corresponding to a privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0030] Figure 6b This is a timing diagram of even-numbered frames corresponding to a privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0031] Figure 6cThis is a timing diagram corresponding to another privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0032] Figure 6d This is a timing diagram corresponding to another privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0033] Figure 6e This is a timing diagram corresponding to another privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0034] Figure 6f This is a timing diagram corresponding to another privacy control pixel circuit structure provided in Embodiment 3 of this application.

[0035] Figure 7 This is a schematic diagram of the structure of a privacy control module provided in Embodiment 4 of this application.

[0036] Figure 8 This is a schematic diagram of the structure of a multiplexing module provided in Embodiment 4 of this application.

[0037] Figure 9a This is a timing diagram of odd-numbered frames for a multiplexing module provided in Embodiment 4 of this application.

[0038] Figure 9b This is a timing diagram of even-numbered frames for a multiplexing module provided in Embodiment 4 of this application.

[0039] Figure 10 This is a flowchart illustrating a privacy control method provided in Embodiment 5 of this application.

[0040] Figure 11 This is a flowchart illustrating another privacy control method provided in Embodiment 5 of this application.

[0041] Figure 12 This is a schematic diagram of the structure of a partition of privacy protection area information provided in Embodiment 5 of this application.

[0042] Figure 13 This is a schematic diagram of the structure of a spying target signal provided in Embodiment 5 of this application.

[0043] Figure 14 This is a schematic diagram of the structure of a privacy control device provided in Embodiment Six of this application.

[0044] Explanation of reference numerals in the attached figures: EM Light-emitting control line; Data line; 10 Driver module; 20 Control module; 30 Anti-spy module; PPL Anti-spy signal line; S1 First scan line; S2 Second scan line; S3 Third scan line; S1(n) First scan line of the current row; S2(n) Second scan line of the current row; S3(n) Third scan line of the current row; S1(n+2) First scan line lagging 2 rows; M1 First transistor; M2 Second transistor; M3 Third transistor; C1 First capacitor; K First node; A Second node; Vref Reference power supply voltage; VGL Low-level anti-spy signal; VGH High-level anti-spy signal; 101 First driver unit; 102 Second driver unit; M4 Fourth transistor; M5 Fifth transistor; M6 Sixth transistor; M7 Seventh transistor; M8 Eighth transistor; M9 Ninth transistor; C2 Second capacitor; M10 Tenth transistor; M11 Eleventh transistor; M12 Twelfth transistor; M13 Thirteenth transistor; M14 Fourteenth transistor; M15 Fifteenth transistor; C3 Third capacitor; 200 Timing control module; 300 Shift register; 400 Level conversion module; 500 Multiplexing module; 600 Display driver chip; MUX unit Multiplexing unit; MUX1 Sixteenth transistor; MUX2 Seventeenth transistor; MUX3 Eighteenth transistor; MUX4 Nineteenth transistor; 10000 Privacy protection control device; 2000 Privacy protection control module; AP External host. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention application clearer, the technical solutions in the embodiments of this invention application will be clearly and completely described below in conjunction with the embodiments of this invention application. Obviously, the described embodiments are only some embodiments of this invention application, not all embodiments. Based on the embodiments of this invention application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0046] The terms "comprising" and "having" in the embodiments of this application are used to indicate an open-ended inclusion, meaning that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. Furthermore, the different elements and areas in the drawings are only schematic, therefore this application is not limited to the dimensions or distances shown in the drawings.

[0047] By placing a black matrix (BM) above the OLED device, metallic reflections in non-light-emitting areas can be reduced, the OLED's emission angle can be limited, and the light output rate can be lowered. By changing the relative opening angle between the BM and the OLED, a privacy display effect can be achieved, hence the name "privacy display." Based on this, regular display pixels and privacy display pixels can be obtained. However, current methods achieve fixed privacy, meaning that a particular display is a privacy display, using a full array of privacy display pixels, and remains in privacy mode, unable to switch to normal non-privacy display. Another conventional privacy method allows for switching between regular and privacy display modes. This involves setting two sub-pixels within a designated area of ​​each sub-pixel in the display area: one non-privacy pixel and one privacy pixel. Functionally, this allows switching between two display modes: one is full-screen non-privacy, where only regular display sub-pixels are illuminated; the other is full-screen privacy, where only privacy display sub-pixels are illuminated. This prevents the privacy display function from specifying privacy in designated areas according to the needs of localized privacy in specific environments, thus reducing the user experience.

[0048] To address the issue of inability to provide privacy protection for specific areas, this application proposes a privacy control pixel circuit. By adding a control module and a privacy signal line, when the privacy signal line receives a tri-state signal, the privacy module performs a pixel reset, that is, initializes the sub-pixels lit in the previous frame. When the privacy signal line receives the privacy signal of the pixel in the current scan line, it feeds the privacy signal back to the control module. When the control module selectively selects, it transmits the privacy signal to the privacy module, selecting between privacy display and normal display according to different privacy signals. By changing the privacy signal, the privacy display result is changed, achieving the technical effect of privacy protection for any area.

[0049] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application.

[0050] Example 1 Figure 1a This is a schematic diagram of a privacy control pixel circuit provided in Embodiment 1 of this application. According to the diagram in Figure 1, the privacy control pixel circuit specifically includes an emitting control line EM, a data line Data, and multiple scan lines. The privacy control pixel circuit also includes: The drive module 10, control module 20, privacy module 30, and privacy signal line PPL are included.

[0051] The first input terminal DI1 of the driving module 10 is connected to the data line Data, and the output terminal DO of the driving module 10 is connected to the first input terminal CI1 of the control module 20. The driving module 10 is used to convert the data signal transmitted by the data line Data into a pixel driving signal and output the pixel driving signal to the control module 20.

[0052] The second input terminal CI2 of the control module 20 is connected to the privacy signal line PPL. The privacy signal line PPL is used to transmit the received privacy signal to the control module 20. The control module 20 controls the privacy module 30 to perform privacy display based on the privacy signal and the pixel driving signal.

[0053] In this embodiment, by changing the signal strength received by the privacy signal line, the privacy module can be configured to either display privacy or display normally, thus achieving flexible privacy display selection, enabling privacy control in any area, and improving user experience.

[0054] Figure 1b This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application. Figure 1b As shown, in some embodiments, the driving module 10 further includes a second input terminal DI2, a third input terminal DI3, and a fourth input terminal DI4. The second input terminal DI2 of the driving module 10 is connected to the light emission control line EM, the third input terminal DI3 of the driving module 10 is connected to the first scan line S1, and the fourth input terminal DI4 of the driving module 10 is connected to the second scan line S2.

[0055] Preferably, the control module 20 further includes a third input terminal CI3, which is connected to the light emission control line EM; or, the third input terminal CI3 is connected to the third scan line S3. The first output terminal CO1 of the control module 20 is connected to the first input terminal PI1 of the privacy module 30, and the second output terminal CO2 of the control module 20 is connected to the second input terminal PI2 of the privacy module 30. There are multiple ways to connect the second input terminal of the control module 20, and the specific method can be changed according to requirements. Without increasing the known scan lines of the driving module in the current privacy control pixel circuit, the second input terminal of the control module is connected to the light emission control line. When a scan line is selected to replace the light emission control line, and the signals of the second input terminal DI2 of the driving module and the input terminal of the control module are different, based on the existing scan lines provided by the privacy control pixel circuit hardware, the second input terminal CI2 of the control module is connected to one of the multiple scan lines, ensuring that the signal output by the scan line is different from the signal output by the light emission control line.

[0056] Specifically, the signals received by the privacy signal line generally include three types of signals: a high-level signal, namely the high-level privacy signal VGH; a low-level signal, namely the low-level privacy signal VGL; and a tri-state signal. The high-level signal can be understood as reaching the turn-on voltage threshold of the N-type transistor, namely the high-level privacy signal VGH; the low-level signal can be understood as reaching the turn-on voltage threshold of the P-type transistor, namely the low-level privacy signal VGL; and the tri-state signal can be understood as reaching the turn-off voltage threshold V0 of both the N-type and P-type transistors.

[0057] according to Figure 1a and Figure 1b The provided illustration firstly resets the pixels illuminated in the previous frame within the privacy module under the influence of the light emission control signal and the line scan signal. After the driver module receives the data signal sent from the data line, it performs internal compensation, adjusting the output current of the driver module to regulate the display brightness of the privacy module. At this time, the tri-state signal input on the privacy signal line will not affect the privacy pixels. After the driver module finishes compensation, the magnitude of the privacy signal received by the control module selects between privacy display and normal display. When the control module receives a high-level privacy signal, the corresponding internal circuit is activated, and the normal display pixels connected to the internal conducting device of the control module are illuminated according to the design logic, achieving normal display; when the control module receives a low-level privacy signal, the privacy pixels connected to the internal conducting device of the control module are illuminated, achieving privacy display.

[0058] Optionally, the control logic of the above control module for the privacy module can be modified. That is, when the control module receives a low-level privacy signal, it controls the privacy pixels in the privacy module to light up, so as to realize privacy display; when the control module receives a high-level privacy signal, it controls the regular pixels in the privacy module to light up, so as to realize regular display.

[0059] Furthermore, by changing the magnitude of the privacy signal input to the privacy signal line for the current scan line pixel, privacy display can be implemented for pixels in any area of ​​the display screen, thereby achieving flexible selection of privacy performance.

[0060] Figure 1b The structure of the connection between the third input terminal DI3 of the control module 20 and the light emission control line EM is given, without increasing the number of scan lines currently connected to the driving module, and when the signals of the second input terminal DI2 of the driving module 10 and the third input terminal CI3 of the control module 20 are the same.

[0061] Optionally, without increasing the number of scan lines currently connected to the drive module, the third input terminal CI3 of the control module 20 can be connected to the third scan line. Specifically, Figure 2a This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application. Figure 2aAs shown, in this embodiment, the third scan line lags behind the first scan line S1(n+2) by two scan lines. It can be understood that by having the first scan line, which lags behind by two scan lines, have the same signal relationship with the light emission control line, the same control process as in Figure 1 can be executed, achieving the same technical effect, which will not be elaborated here. Figure 2b This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 1 of this application. Figure 2b As shown, in this embodiment, the third scan line is the third scan line S3 of the current row. It can be understood that by having the same signal relationship between the third scan line S3 of the current row and the light emission control line, the same control process as in Figure 1 can be executed, and the same technical effect can be achieved, which will not be elaborated here.

[0062] The privacy control pixel circuit, privacy control module, method, and apparatus provided in this application include a light-emitting control line, a data line, multiple scan lines, a driving module, a control module, a privacy module, and a privacy signal line. The driving module converts the data signal transmitted by the data line into a pixel driving signal and outputs the pixel driving signal to the control module. The privacy signal line transmits the received privacy signal to the control module, and the control module controls the privacy module to perform privacy display based on the privacy signal and the pixel driving signal. By changing the signal strength received by the privacy signal line, the privacy module can be changed to select between privacy display and regular display, achieving flexible selection of privacy display, realizing privacy control in any area, and improving the user experience.

[0063] Example 2 Figure 3 This is a schematic diagram of a privacy control pixel circuit provided in Embodiment 2 of this application. Figure 3 This description is based on the embodiment shown in Figure 1. Figure 3 The provided diagram shows the specific structure of the privacy control pixel circuit, including: The drive module 10, control module 20, privacy module 30, and privacy signal line PPL are included.

[0064] according to Figure 3 The provided diagram shows that the control module 20 in the privacy control pixel circuit includes a first transistor M1 and a second transistor M2. The control terminals of the first transistor M1 and the second transistor M2 are connected to the first node K and receive the privacy signal transmitted by the privacy signal line PPL. The privacy signal includes a tri-state signal, which is used to control both the first transistor M1 and the second transistor M2 to be in the off state.

[0065] In some embodiments, the control module 20 further includes a third transistor M3, the first end of which is connected to the first node K, and the second end of which serves as the second input terminal of the control module 20 and is connected to the privacy signal line PPL.

[0066] In some embodiments, the control module 20 further includes a first capacitor C1, the first end of which is connected to the first node K, and the second end of which is connected to the first power supply voltage line, i.e., connected to the reference power supply voltage Vref line.

[0067] Understandably, the control terminals of the first transistor M1 and the second transistor M2, the first terminal of the third transistor M3, and the first terminal of the first capacitor C1 are all connected to the first node K. The first terminal of the first transistor M1 serves as the first input terminal of the control module 20. The first terminal of the second transistor M2 is connected to the first terminal of the first transistor M1 and then to the second node A. The second terminal of the first transistor M1 serves as the first output terminal of the control module 20 and is connected to the first input terminal of the privacy module 30. The second terminal of the second transistor M2 serves as the second output terminal of the control module 20 and is connected to the second input terminal of the privacy module 30.

[0068] Optionally, the second terminal of the third transistor M3 is connected to the privacy signal line PPL as the second input terminal of the control module 20. The third transistor M3 is an N-type thin film transistor. The control terminal of the third transistor M3 is connected to the light emission control line EM as the third input terminal of the control module 20. The first transistor M1 and the second transistor M2 are of different types.

[0069] Preferably, the first transistor M1 is an N-type thin-film transistor and the second transistor M2 is a P-type thin-film transistor.

[0070] In some embodiments, the second terminal of the first capacitor C1 is connected to the first power supply voltage line, i.e., the reference power supply voltage Vref line.

[0071] according to Figure 3 The provided diagram shows that during the first cycle, the control line EM outputs a high-level signal, causing the third transistor M3 to conduct. At this time, the privacy signal line PPL inputs a low-level privacy signal VGL or a high-level privacy signal VGH, causing the first transistor M1 or the second transistor M2 to conduct. Through the output signal inside the driving module 10, the pixel in the privacy module 30 connected to the first transistor M1 is reset, or the pixel in the privacy module 30 connected to the second transistor M2 is reset. During the second cycle, the privacy signal line PPL outputs a tri-state signal V0, controlling both the first transistor M1 and the second transistor M2 to remain in the off state. The scanning signal output by the scanning line performs voltage compensation inside the driving module 10 to adjust the output current at the second node A, preparing for the next step of changing the display brightness of the privacy module 30.

[0072] Furthermore, during the third cycle, anti-spy control is activated. When the anti-spy signal line PPL outputs a high-level anti-spy signal VGH, the first transistor M1 is turned on, and the second transistor M2 is turned off, thereby controlling the pixels in the anti-spy module 30 connected to the first transistor M1 to perform normal display; when the anti-spy signal line PPL outputs a low-level anti-spy signal VGL, the first transistor M1 is turned off, and the second transistor M2 is turned on, thereby controlling the pixels in the anti-spy module 30 connected to the second transistor M2 to perform anti-spy display. The control logic can be modified. During the fourth cycle, the light emission control signal is changed to a low-level signal, causing the third transistor M3 to turn off. At this time, the first capacitor C1 connected to the first node K is used to maintain the display state, waiting for the next scan. Figure 3 The provided structure enables flexible privacy control. By simply changing the magnitude of the privacy signal corresponding to the current scan line, privacy display of pixels in any area can be achieved, improving the user experience.

[0073] according to Figure 3 The provided illustration shows that the privacy module 30 in the privacy control pixel circuit includes: A standard LED D1 and a privacy LED D2.

[0074] The first electrode of the conventional LED D1 is connected to the first input terminal of the privacy module 30 and the first output terminal of the control module 20. The second electrode of the conventional LED D1 and the second electrode of the privacy LED D2 are connected to the second power supply voltage line, namely the negative power supply voltage ELVSS line. The conventional LED D1 is used for conventional display.

[0075] The first electrode of the privacy LED D2 is connected to the second input terminal PI2 of the privacy module 30 and the second output terminal CO2 of the control module 20. The privacy LED D2 is used for privacy display.

[0076] Preferably, the viewing angle of the privacy LED D2 is a preset acute angle or right angle.

[0077] The conventional light-emitting diodes and privacy light-emitting diodes mentioned here are both OLED devices.

[0078] Different connection results can be selected by the internal conduction of the control module 20 to achieve different display effects. When the control module 20 is connected to the conventional LED D1, a conventional display can be performed; when the control module 20 is connected to the privacy LED D2, a privacy display is performed.

[0079] according to Figure 3The provided diagram shows that during the first cycle, the control line EM outputs a high-level signal, causing the third transistor M3 to conduct. At this time, the privacy signal line PPL inputs a low-level privacy signal VGL or a high-level privacy signal VGH, causing the first transistor M1 or the second transistor M2 to conduct. The drive module 10 outputs a signal to reset the conventional LED D1 corresponding to the conducting first transistor M1, or to reset the privacy LED D2 connected to the conducting second transistor M2. During the second cycle, the privacy signal line PPL outputs a tri-state signal V0 to keep both the first transistor M1 and the second transistor M2 in the off state. The scan signal output by the scan line performs voltage compensation inside the drive module 10 to adjust the output current at the second node A, preparing for the next step of changing the display brightness of the privacy module 30.

[0080] Furthermore, during the third cycle, privacy control is activated. When the privacy signal line PPL outputs a high-level privacy signal VGH, the first transistor M1 is turned on, and the second transistor M2 is turned off, thereby controlling the conventional LED D1 connected to the first transistor M1 to perform normal display. When the privacy signal line EM outputs a low-level privacy signal VGL, the first transistor M1 is turned off, and the second transistor M2 is turned on, thereby controlling the privacy LED D2 connected to the second transistor M2 to perform privacy display. The control logic can be modified. During the fourth cycle, the light emission control signal is changed to a low-level signal, causing the third transistor M3 to turn off. At this time, the first capacitor C1 connected to the first node K is used to maintain the display state, waiting for the next scan. This achieves flexible privacy control; by simply changing the magnitude of the privacy signal corresponding to the current scan line, privacy display of any pixel area can be achieved, improving the user experience.

[0081] Optionally, Figure 4 This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 2 of this application. Figure 4 Is Figure 2b This introduction is based on the previous one. Figure 4 and Figure 3 The difference is that, Figure 4The third transistor M3 is a P-type thin-film transistor (TFT). The control terminal of the third transistor M3 serves as the third input terminal CI3 of the control module 20 and is connected to the third scan line S3(n) of the current row. By changing the connection of the third transistor's control terminal, without increasing the scan lines already designed in the driver module's hardware structure, the third scan line S3(n) of the current row is selected and connected to the control terminal of the third transistor M3. When the signal output from the third scan line S3(n) of the current row differs from the signal output from the light-emitting control line EM, the same anti-spy control logic for the anti-spy module is achieved using the anti-spy signal output from the anti-spy signal line, thus achieving flexible selection of the anti-spy control area. The specific control process is as follows... Figure 3 The description process is the same, so it will not be repeated here.

[0082] Preferably, see Figure 1~ Figure 4 The structure of the driving module can include a low-temperature polycrystalline silicon (LTPS) pixel driving module.

[0083] The first input terminal of the LTPS pixel driver module is designated as the first input terminal DI1, the second input terminal of the LTPS pixel driver module is designated as the second input terminal DI2, the third input terminal of the LTPS pixel driver module is designated as the third input terminal DI3, the fourth input terminal of the LTPS pixel driver module is designated as the fourth input terminal DI4, and the output terminal of the LTPS pixel driver module is designated as the output terminal DO.

[0084] Specifically, there are various types of LTPS pixel driving modules, with the most common being 1T1C, 2T1C, 3T1C, 4T1C, 7T1C, and 8T1C. Among them, 7T1C indicates that the driving structure contains 7 TFT transistors and 1 capacitor (C). The specific structure is an existing structure and will not be described in detail here.

[0085] Preferably, see Figure 1~ Figure 4 The structure of the driving module may also include a low-temperature polycrystalline oxide (LTPO) pixel driving module.

[0086] The first input terminal of the LTPO pixel driver module is designated as the first input terminal DI1, the second input terminal of the LTPO pixel driver module is designated as the second input terminal DI2, the third input terminal of the LTPO pixel driver module is designated as the third input terminal DI3, the fourth input terminal of the LTPO pixel driver module is designated as the fourth input terminal DI4, and the output terminal of the LTPO pixel driver module is designated as the output terminal DO.

[0087] Specifically, there are several types of LTPO pixel driving modules, with the most common being 2T1C, 3T1C, 7T1C, and 8T1C. Among them, 2T1C indicates that the driving structure includes two TFT transistors and one capacitor (C). The specific structure is an existing structure and will not be described in detail here.

[0088] Example 3 Figure 5a This is a schematic diagram of the structure of a privacy control pixel circuit provided in Embodiment 3 of this application. Figure 5a In Example 2 Figure 3 This introduction is based on [the previous information]. Figure 5a The provided diagram shows that the structure of the privacy control pixel circuit includes: a first driving unit 101, a control module 20, a privacy module 30, and a privacy signal line PPL.

[0089] according to Figure 5a The provided diagram shows that the third transistor M3 in the selected control module is an N-type thin-film transistor (TFT), and the third transistor M3 is connected to the light-emitting control line EM.

[0090] according to Figure 5a The provided illustration shows that the low-temperature polysilicon (LTPS) pixel driving module in the privacy control pixel circuit includes: a first driving unit 101, wherein the first driving unit 101 includes the low-temperature polysilicon (LTPS) pixel driving module.

[0091] The first input terminal of the first driving unit 101 is connected to the data line Data as the first input terminal of the driving module 10. The second input terminal of the first driving unit 101 is connected to the light emission control line EM as the second input terminal of the driving module 10. The third input terminal of the first driving unit 101 is connected to the first scan line S1 as the third input terminal of the driving module 10. The fourth input terminal of the first driving unit 101 is connected to the second scan line S2 as the fourth input terminal of the driving module 10. The output terminal of the first driving unit 101 is connected to the first input terminal of the control module 20 as the output terminal of the driving module 10.

[0092] Preferably, the first driving unit 101 includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a second capacitor C2.

[0093] The control terminal of the fourth transistor M4 is connected to the second scan line S2 as the fourth input terminal of the first driving unit 101 and the control terminal of the fifth transistor M5. The first terminal of the fourth transistor M4 is connected to the data line Data as the first input terminal of the first driving unit 101. The second terminal of the fourth transistor M4 is connected to the first terminal of the sixth transistor M6 and the first terminal of the seventh transistor M7.

[0094] The first terminal of the fifth transistor M5, the first terminal of the eighth transistor M8, the control terminal of the seventh transistor M7, and one terminal of the second capacitor C2 are connected. The second terminal of the fifth transistor M5 serves as the output terminal of the first driving unit 101 and is connected to the second terminal of the seventh transistor M7, the first terminal of the ninth transistor M9, and the first input terminal of the control module 20.

[0095] The control terminal of the sixth transistor M6 is connected to the light-emitting control line EM as the second input terminal of the first driving unit 101. The second terminal of the sixth transistor M6 and the other terminal of the second capacitor C2 are connected to the third power supply voltage line, namely the positive power supply voltage ELVDD line.

[0096] The control terminal of the eighth transistor M8 is connected to the first scan line S1 as the third input terminal of the first driving unit 101. The second terminal of the eighth transistor M8 and the second terminal of the ninth transistor M9 are connected to the first power supply voltage line, i.e., the reference power supply voltage Vref line.

[0097] Preferably, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are of the same type.

[0098] Preferably, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are all P-type thin-film transistors (TFTs).

[0099] The first driving unit 101 is merely one type among many in low-temperature polysilicon (LTPS) pixel driving modules, specifically a modified 7T1C structure. Figure 5a The first driving unit 101 is not described in this document.

[0100] based on Figure 5a Is Figure 3 This explanation is based on [the previous one], and [is related to] Figure 3 The control module and the privacy module have the same internal structure, and the structure and control process of the control module and the privacy module will not be described in detail here.

[0101] Figure 5a and Figure 3 The difference lies in the fact that the driving module is limited to a modified 7T1C structure in the LTPS pixel driving module. The principle is the same as that of a conventional pixel driving circuit, and the driving principle of 7T1C will not be elaborated here.

[0102] according to Figure 5aThe provided diagram shows that during the first cycle, the eighth transistor M8 and the ninth transistor M9 are turned on via the first scan line S1. The first power supply voltage, i.e., the reference power supply voltage Vref, is used to reset the conventional LED D1 via the ninth transistor M9 and the first transistor M1, or the privacy LED is reset via the reference power supply voltage Vref through the ninth transistor M9 and the second transistor M2. In other words, the first cycle initializes the pixels displayed in the previous frame. During the second cycle, the privacy signal line PPL provides a tri-state signal to the third transistor M3, keeping both the first transistor M1 and the second transistor M2 off. The second scan line S2 turns on the fourth transistor M4 and the fifth transistor M5. The voltage on the data line Data compensates the gate voltage of the seventh transistor M7 via the fourth transistor M4, the seventh transistor M7, and the fifth transistor M5.

[0103] Furthermore, during the third cycle, the first scan line S1 and the second scan line S2 keep the fourth transistor M4, fifth transistor M5, sixth transistor M6, eighth transistor M8, and ninth transistor M9 disconnected. A high-level privacy signal VGH is provided to the third transistor M3 via the privacy signal line PPL, causing the first transistor M1 to conduct. This allows the current signal output from the driving module 10 to be transmitted to the conventional LED D1 via the first transistor M1 through the second node A, performing conventional display. Conversely, a low-level privacy signal VGL is provided to the third transistor M3 via the privacy signal line PPL, causing the second transistor M2 to conduct. This allows the current signal output from the driving module 10 to be transmitted to the privacy LED D2 via the second node A through the second transistor M2, performing privacy display, thus achieving privacy control. By changing the level of the privacy signal on the privacy signal line PPL, the pixels in any scan line can be arbitrarily changed, achieving privacy control in any area. During the fourth cycle, the light-emitting control line controls the third transistor M3 to disconnect. At this time, the first capacitor C1 connected to the first node continues to supply power to the conventional light-emitting diode D1 or the privacy light-emitting diode D2.

[0104] In one possible example scenario, Figure 6a This is a timing diagram of odd-numbered frames corresponding to the anti-spy control pixel circuit structure provided in Embodiment 3 of this application. Figure 6b This is a timing diagram of even-numbered frames corresponding to a privacy control pixel circuit structure provided in Embodiment 3 of this application. According to... Figure 6a and Figure 6b The provided timing diagrams are divided into odd-frame timing diagrams and even-frame timing diagrams. The difference lies in the signal of the privacy signal line during the first cycle time period T1.

[0105] In the first cycle period T1: the signal transmitted by the first scan line S1 is at a low level, the eighth transistor M8 and the ninth transistor M9 are turned on, and the first power supply voltage line, i.e., the reference power supply voltage Vref, resets the gate voltage of the seventh transistor M7 through the eighth transistor M8, ensuring that the seventh transistor M7 is turned on in the second cycle period T2. The privacy signal VPPL output by the privacy signal line PPL becomes high or low depending on whether the pixel lit in the previous frame is a regular LED D1 or a privacy LED D2. If the current frame is an odd number, the privacy signal line PPL and the first node K are both at a low level VGL, causing the first transistor M1 to turn off and the second transistor M2 to turn on. The first power supply voltage line, i.e., the reference power supply voltage Vref, resets the anode of the privacy LED D2 through the ninth transistor M9 and the second transistor M2. If the current frame is an even number, the privacy signal line PPL and the first node K are both at a high level privacy signal VGH, the first transistor M1 turns on and the second transistor M2 turns off. The reference power supply voltage Vref resets the first electrode, i.e., the anode, of the conventional LED D1 through the ninth transistor M9 and the first transistor M1.

[0106] During the second cycle period T2: the privacy signal line PPL and the first node K both change to the tri-state signal corresponding to voltage V0, and the first transistor M1 and the second transistor M2 are both turned off. Because the signal transmitted by the first scan line S1 is at a high level, the eighth transistor M8 and the ninth transistor M9 are turned off. The signal transmitted by the second scan line S2 is at a low level, and the fourth transistor M4 and the fifth transistor M5 are turned on. The voltage on the data line Data charges the gate of the seventh transistor M7 through the fourth transistor M4, the seventh transistor M7, and the fifth transistor M5, obtaining the threshold voltage Vth of the seventh transistor M7, and realizing pixel compensation inside the drive module.

[0107] The third period, T3, aims to refresh the voltage at the first node, K. The privacy signal voltage VPPL is written to the first node, K, through the privacy signal line PPL and the third transistor M3. If the privacy signal voltage VPPL is high, the first node, K, displays a high-level privacy signal VGH, indicated by the standard LED D1. If the privacy signal voltage VPPL is low, the first node, K, displays a low-level privacy signal VGL, indicated by the privacy LED D2.

[0108] In the fourth cycle period T4: the light-emitting control line EM outputs a low-level signal, the sixth transistor M6 is turned on and the third transistor M3 is turned off, the privacy module starts to emit light, and the potential at the first node K is maintained by the first capacitor C1 until the next frame arrives.

[0109] Optional, Figure 5b This is a schematic diagram of another privacy control pixel circuit according to Embodiment 3 of this application. Figure 5aThe driving modules in both are identical, employing the first driving unit 101 structure from the low-temperature polysilicon (LTPS) pixel driving module. Figure 5b and Figure 5a The difference is Figure 5b The third transistor in the circuit is a P-type thin-film transistor, and its control terminal is connected to the third scan line S3. This third scan line is understood to be the third scan line of the current row. The specific control process is as follows... Figure 5a They are the same, achieving the same technical effect.

[0110] In one possible example scenario, Figure 6c for Figure 5b The corresponding timing diagram. Based on... Figure 6b The provided diagram can be used for reference. Figure 5b The control timing process is as follows: In the first cycle period T1: the first scan line S1 goes low, the eighth transistor M8 and the ninth transistor M9 are turned on, and the first power supply voltage line, i.e., the reference power supply voltage Vref, resets the gate voltage of the seventh transistor M7 through the eighth transistor M8, ensuring that the seventh transistor M7 is turned on in the second cycle period T2. The third scan line S3 of the current row is high, causing the third transistor M3 to turn off. The voltage at the first node K is still the voltage of the previous frame. The first power supply voltage line, i.e., the reference power supply voltage Vref, resets and initializes the first electrode (anode) of the privacy module through the ninth transistor M9 and the first transistor M1 (or the second transistor M2). Specifically, the device in the privacy module whose first electrode is reset is the device that emitted light in the previous frame.

[0111] During the second cycle period T2: the first scan line S1 is high, and the eighth transistor M8 and the ninth transistor M9 are off. The second scan line S2 is low, and the fourth transistor M4 and the fifth transistor M5 are on. The third scan line S3 of the current row becomes low, and the third transistor M3 is on. The anti-spy signal output voltage VPPL and the voltage V0 at the first node K both become the tri-state signal voltage, causing the first transistor M1 and the second transistor M2 to be off. The voltage on the data line Data charges the gate of the seventh transistor M7 through the fourth transistor M4, the seventh transistor M7, and the fifth transistor M5, obtaining the threshold voltage Vth of the seventh transistor M7, thus realizing internal pixel compensation.

[0112] The purpose of the third cycle period T3 is to refresh the voltage at the first node K. The privacy signal is written to the first node K through the privacy signal line PPL and the third transistor M3. If the privacy signal corresponding to the voltage VPPL is a high-level signal, then the first node K has a high-level privacy signal VGH, and the conventional LED D1 illuminates; if the privacy signal corresponding to the voltage VPPL is a low-level signal, then the first node K has a low-level privacy signal VGL, and the privacy LED D2 illuminates.

[0113] During the fourth cycle period T4: the signal corresponding to the light emission control line EM is at a low level, the sixth transistor M6 is turned on, and the privacy module starts to emit light. When the third scan line S3 of the current row is at a high level, the third transistor M3 is turned off, and the potential at the first node K is maintained by the first capacitor C1 until the next frame arrives.

[0114] It is worth noting that the first scan line S1 mentioned above is the first scan line of the current row, and the second scan line is the second scan line of the current row.

[0115] Figure 5c This is a schematic diagram of another privacy control pixel circuit provided in Embodiment 3 of this application. Figure 5c This is based on Example 2. Figure 5c The provided diagram shows that the structure of the privacy control pixel circuit includes: a second driving unit 102, a control module 20, a privacy module 30, and a privacy signal line PPL.

[0116] according to Figure 5c The provided diagram shows that the third transistor M3 in the selected control module is an N-type thin-film transistor, and the control terminal of the third transistor M3 is connected to the light-emitting control line EM.

[0117] according to Figure 5c The provided illustration shows that the driving module 10 includes a second driving unit 102, wherein the second driving unit 102 includes a low-temperature polycrystalline oxide (LTPO) pixel driving module.

[0118] The first input terminal of the second driving unit 102 is connected to the data line Data as the first input terminal of the driving module 10. The second input terminal of the second driving unit 102 is connected to the light emission control line as the second input terminal of the driving module 10. Specifically, the second input terminal of the second driving unit 102 is connected to the light emission control line EM(n) of the current row as the second input terminal of the driving module 10. The third input terminal of the second driving unit 102 is connected to the first scan line as the third input terminal of the driving module 10. Specifically, the third input terminal of the second driving unit 102 is connected to the first scan line as the third input terminal of the driving module 10. The first input terminal of the second driving unit 102 is connected to the first scan line S1(n) of the current row. The fourth input terminal of the second driving unit 102 is connected to the second scan line as the fourth input terminal of the driving module 10. Specifically, the fourth input terminal of the second driving unit 102 is connected to the second scan line S2(n) of the current row as the fourth input terminal of the driving module 10. The fifth input terminal of the second driving unit 102 is connected to the fourth scan line. Specifically, the fourth scan line is the first scan line S1(n+1) of the next row. The output terminal of the second driving unit 102 is connected to the first input terminal of the control module 20 as the output terminal of the driving module 10.

[0119] Preferably, the second driving unit 102 includes: a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a third capacitor C3.

[0120] The control terminal of the tenth transistor M10 is connected to the second scan line as the fourth input terminal of the second driving unit 102. Specifically, the control terminal of the tenth transistor M10 is connected to the second scan line S2(n) of the current row as the fourth input terminal of the second driving unit 102. The first terminal of the tenth transistor M10 is connected to the data line Data as the first input terminal of the second driving unit 102. The second terminal of the tenth transistor M10 is connected to the first terminal of the eleventh transistor M11 and the first terminal of the twelfth transistor M12.

[0121] The control terminal of the eleventh transistor M11, the first terminal of the thirteenth transistor M13, the first terminal of the fourteenth transistor M14, and the first terminal of the third capacitor C3 are connected. The second terminal of the eleventh transistor M11 serves as the output terminal of the second driving unit 102 and is connected to the second terminal of the thirteenth transistor M13, the first terminal of the fifteenth transistor M15, and the first input terminal of the control module 20.

[0122] The control terminal of the twelfth transistor M12 is connected to the light-emitting control line as the second input terminal of the second driving unit 102. Specifically, the control terminal of the twelfth transistor M12 is connected to the light-emitting control line EM(n) of the current row as the second input terminal of the second driving unit 102. The second terminal of the twelfth transistor M12 and the second terminal of the third capacitor C3 are connected to the third power supply voltage line, namely the positive power supply voltage ELVDD line.

[0123] The control terminal of the thirteenth transistor M13 is connected to the fourth scan line as the fifth input terminal of the second drive unit 102. Specifically, the fourth scan line is the first scan line S1(n+1) of the next row.

[0124] The control terminal of the fourteenth transistor M14 is connected to the first scan line. Specifically, the control terminal of the fourteenth transistor M14 is connected to the first scan line S1(n) of the current row. The control terminal of the fifteenth transistor M15 is connected to the first scan line. Specifically, the control terminal of the fifteenth transistor M15 is connected to the first scan line S1(n) of the current row. The second terminals of the fourteenth transistor M14 and the fifteenth transistor M15 are connected to the first power supply voltage line, i.e., the reference power supply voltage Vref line.

[0125] Preferably, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are of the same type, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are of the same type, and the tenth transistor M10 and the thirteenth transistor M13 are of different types.

[0126] Preferably, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all P-type thin-film transistors (TFTs), and the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are all N-type thin-film transistors (TFTs).

[0127] The transistor mentioned here can be understood as a thin-film transistor (TFT). The control terminal of the transistor mentioned here is the gate of the TFT.

[0128] The second driving unit 102 is merely one type among many in the low-temperature polycrystalline oxide (LTPO) pixel driving module, specifically a second driving unit 102 obtained by modifying the 7T1C structure. Figure 5c The second drive unit 102 is not described in this document.

[0129] based on Figure 5c Is Figure 3 This explanation is based on [the previous one], and [is related to] Figure 3 The control module and the privacy module have the same internal structure, and the structure and control process of the control module and the privacy module will not be described in detail here.

[0130] Figure 5c and Figure 3 The difference lies in the modification of the 7T1C structure in the LTPO pixel driver module. The principle is the same as that of a conventional pixel driver circuit, and the driving principle of 7T1C will not be elaborated here.

[0131] according to Figure 5c The provided diagram shows that during the first cycle, by controlling the fourteenth transistor M14 and the fifteenth transistor M15 to be turned on, the first power supply voltage (i.e., the reference power supply voltage Vref) is used to reset the pixels in the privacy module through the fifteenth transistor M15 and the first transistor M1 or the second transistor M2. During the second cycle, the voltage V0 corresponding to the tri-state signal is output through the privacy signal line, controlling the first and second transistors to remain off. At the same time, under the action of the line scan signal, the fourteenth and fifteenth transistors are turned off, and the tenth, eleventh, and thirteenth transistors are turned on to compensate the voltage at the gate of the eleventh transistor M11. During the third cycle, the tenth transistor M10, the twelfth transistor M12, and the thirteenth transistor M13 are controlled to... 13. Transistors M14 and M15 remain off. When the privacy signal line PPL outputs a high-level privacy signal, the voltage at the first node K is high, controlling the first transistor to conduct, thus executing the conventional LED display. When the corresponding voltage VPPL of the privacy signal line PPL outputs a low-level privacy signal, the voltage at the first node K is low, controlling the second transistor to conduct, thus executing the privacy LED D2 display. During the fourth cycle, the third transistor is turned off, and the display of the privacy module is maintained by the voltage at the first capacitor C1. By changing the magnitude of the corresponding voltage VPPL of the privacy signal, the privacy display result can be changed in any scan line, thereby achieving privacy control in any area and improving the user experience.

[0132] Furthermore, in one possible example scenario, Figure 6d and Figure 6e for Figure 5c The corresponding timing diagram. Figure 6d The timing diagram for odd-numbered frames corresponding to the anti-peeping control pixel circuit structure. Figure 6e The timing diagram for even-numbered frames corresponding to the anti-spy control pixel circuit structure. According to... Figure 6d and Figure 6e The provided diagram can be used for reference. Figure 5c The control timing process is as follows: In the first cycle period T1: the signal transmitted by the first scan line S1(n) of the current row is high, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the first power supply voltage, i.e., the reference power supply voltage Vref, resets the gate voltage of the eleventh transistor M11 through the fourteenth transistor M14, ensuring that M11 is turned on in T2. ​​The signal output by the privacy signal line PPL is either high or low. If the current frame is odd, the privacy signal line PPL and the first node K are both low-level privacy signal VGL, and the reference power supply voltage Vref resets the first electrode (anode) of the privacy OLED; if the current frame is even, the privacy signal line PPL and the first node K are both high-level privacy signal VGH, and the reference power supply voltage Vref resets the first electrode (anode) of the conventional OLED.

[0133] During the second cycle period T2: The anti-spy signal voltage VPPL output by the anti-spy signal line PPL and the voltage V0 at the first node K both change to the tri-state signal voltage V0, causing the first transistor M1 and the second transistor M2 to turn off. Because the signal output by the first scan line S1(n) of the current row is low, the fourteenth transistor M14 and the fifteenth transistor M15 are turned off. The signal output by the first scan line S1(n+1) of the next row is high, and the thirteenth transistor M13 is turned on. The signal output by the second scan line S2(n) of the current row is low, and the tenth transistor M10 is turned on. The voltage on the data line Data charges the gate of the eleventh transistor M11 through the tenth transistor M10, the eleventh transistor M11, and the thirteenth transistor M13, obtaining the threshold voltage Vth of the eleventh transistor M11, thus realizing internal pixel compensation.

[0134] The purpose of the third cycle period T3 is to refresh the voltage at the first node K. The privacy signal line PPL and the third transistor M3 are written to the first node K. If the privacy signal output voltage VPPL is high, then the first node K has a high-level privacy signal VGH, and the conventional LED D1 illuminates; if the privacy signal output voltage VPPL is low, then the first node K has a low-level privacy signal VGL, and the privacy LED D2 illuminates.

[0135] During the fourth cycle period T4: the signal output by the light-emitting control line EM is at a low level, the twelfth transistor M12 is turned on, and the privacy module starts to emit light. The third transistor M3 is turned off, and the potential at the first node K is maintained by the first capacitor C1 until the next frame arrives.

[0136] Optional, Figure 5d This is a schematic diagram of another privacy control pixel circuit according to Embodiment 3 of this application. Figure 5cThe driving modules in both are identical, employing the second driving unit 102 structure from the low-temperature polycrystalline oxide (LTPO) pixel driving module. Figure 5d and Figure 5c The difference is Figure 5d The third transistor in the array is a P-type thin-film transistor (TFT), and the control terminal of the third transistor is connected to the third scan line S3(n) of the current row. The specific control process is as follows: Figure 5c They are the same, achieving the same technical effect.

[0137] Specifically, in one possible example scenario, Figure 6f for Figure 5d The corresponding timing diagram. Based on... Figure 6f The timing control process is illustrated in the provided diagram as follows: In the first cycle period T1: S1(n) goes high, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the reference power supply voltage Vref resets the gate voltage of the eleventh transistor M11 through the fourteenth transistor M14, ensuring that the eleventh transistor M11 is turned on in the second cycle period T2. The signal transmitted by the third scan line S3(n) of the current row is high, and the third transistor M3 is turned off. The voltage at the first node K is still the voltage of the previous frame. The reference power supply voltage Vref resets the first electrode (anode) of the conventional light-emitting diode through the fifteenth transistor M15 and the first transistor M1; or, the reference power supply voltage Vref resets the first electrode (anode) of the privacy LED through the fifteenth transistor M15 and the second transistor M2.

[0138] During the second cycle period T2: Due to the low level of the signal transmitted by the first scan line S1(n) of the current row, the fourteenth transistor M14 and the fifteenth transistor M15 are turned off. The signal transmitted by the third scan line S3(n) of the current row is low, and the third transistor M3 is turned on. The privacy signal of the privacy signal line PPL and the voltage V0 at the first node K are both changed to the three-state signal corresponding to the voltage level V0, and the first transistor M1 and the second transistor M2 are both turned off. S1(n+1) is high, and M13 is turned on. S2(n) is low, and M10 is turned on. The voltage on the data line Data charges the gate of the eleventh transistor M11 through the tenth transistor M10, the eleventh transistor M11, and the thirteenth transistor M13, obtaining the threshold voltage Vth of the eleventh transistor M11, and realizing internal pixel compensation.

[0139] The purpose of the third cycle period T3 is to refresh the voltage at the first node K. The privacy signal line PPL and the third transistor M3 are written to the first node K. If the privacy signal output from the privacy signal line PPL corresponds to a high voltage VPPL, then the first node K displays a high-level privacy signal VGH, and D1 illuminates; if the privacy signal output from the privacy signal line PPL corresponds to a low voltage VPPL, then the first node K displays a low-level privacy signal VGL, and D2 illuminates.

[0140] In the fourth cycle period T4: the signal transmitted by the light-emitting control line EM is low, the twelfth transistor M12 is turned on, and the privacy module starts to emit light. The signal transmitted by the third scan line S3(n) of the current row is high, the third transistor M3 is turned off, and the potential at the first node K is maintained by the first capacitor C1 until the next frame arrives.

[0141] Example 4 Figure 7 This is a schematic diagram of the structure of a privacy control module provided in Embodiment 4 of this application. Figure 7 The description is based on the above embodiments. Figure 7 The provided illustration shows that the privacy control module includes the privacy control pixel circuit 1000 described in the above embodiments, and the structure of the privacy control module further includes: The timing control module 200 (TCON), shift register 300, level shifter 400, multiplexer 500 (MUX), and display driver chip 600 (DDIC) are included.

[0142] One end of the timing control module 200 is connected to the external host 800, and the other end of the timing control module 200 is connected to one end of the shift register 300. The timing control module 200 is used to receive the privacy protection area information sent by the external host 800, and after parsing the privacy protection area information, it sends the privacy protection parsing signal to the shift register 300. The privacy protection area information includes privacy protection area coordinate data.

[0143] The other end of the shift register 300 is connected to one end of the level conversion module 400. The shift register 300 is used to transmit the anti-spying parsing information to the level conversion module 400.

[0144] The other end of the level conversion module 400 is connected to one end of the multiplexing module 500, and the other end of the multiplexing module 500 is connected to multiple privacy signal lines PPL. The level conversion module 400 converts the privacy parsing information and transmits it to the multiplexing module 500, so that the multiplexing module 500 transmits privacy signals to the privacy signal lines PPL according to the privacy parsing information.

[0145] The display driver chip 600 is connected to the privacy control pixel circuit 1000, and the display driver chip 600 is used to drive the driver module 10 in the privacy control pixel circuit 1000.

[0146] according to Figure 7 The provided diagram allows the external host 800 or client to determine the area requiring privacy protection based on the display screen. The privacy protection area is then partitioned to obtain privacy protection area information. The timing control module 200 parses the privacy protection area information to obtain privacy protection parsing information PPD. This information is then converted in the shift register 300 and sent back to the level conversion module 400 to obtain the privacy protection signal. Finally, the privacy protection signal is provided to the privacy protection signal line PPL through the selection of the multiplexing module MUX unit. The privacy protection signal is then used to control the privacy protection module.

[0147] Figure 8 This is a schematic diagram of the structure of a multiplexing module provided in Embodiment 4 of this application. Figure 8 Is Figure 7 This introduction is based on [the previous information]. Figure 8 The provided diagram shows that the structure of the multiplexing module specifically includes: multiple multiplexing units (MUX units).

[0148] Optionally, multiple multiplexing units (MUX units) may have the same structure.

[0149] One end of the multiplexing unit (MUX unit) is connected to the level conversion module 400, and the other end of the multiple multiplexing unit (MUX unit) is connected to one of the multiple privacy signal lines (PPL).

[0150] Preferably, the multiplexing unit (MUX) includes: a sixteenth transistor (MUX1), a seventeenth transistor (MUX2), an eighteenth transistor (MUX3), and a nineteenth transistor (MUX4).

[0151] The sixteenth transistor MUX1, the seventeenth transistor MUX2, the eighteenth transistor MUX3, and the nineteenth transistor MUX4 are of the same type.

[0152] The control terminals of the sixteenth transistor MUX1, the seventeenth transistor MUX2, the eighteenth transistor MUX3, and the nineteenth transistor MUX4 are respectively connected to the timing control module TCON. The first terminals of the sixteenth transistor MUX1, the seventeenth transistor MUX2, the eighteenth transistor MUX3, and the nineteenth transistor MUX4 are connected to the privacy signal line PPL.

[0153] The second terminal of the sixteenth transistor MUX1 is connected to the high-level privacy signal VGH line; the second terminal of the seventeenth transistor MUX2 is connected to the low-level privacy signal VGL line; the second terminal of the eighteenth transistor MUX3 is connected to the tri-state level signal line; and the second terminal of the nineteenth transistor MUX4 is connected to the level conversion signal L / S line corresponding to the level conversion module 400. The tri-state level signal line is used to output the tri-state signal V0, which is used to control both the N-type thin-film transistor (TFT) and the P-type thin-film transistor to be off.

[0154] Preferably, the sixteenth transistor MUX1, the seventeenth transistor MUX2, the eighteenth transistor MUX3, and the nineteenth transistor MUX4 are all P-type thin-film transistors.

[0155] Furthermore, based on the multiple thin-film transistors in the multiplexing unit, when the signals output by the timing control module 200 are different, one of the signals is selected as the anti-spy signal and transmitted to the anti-spy signal line PPL during different periodic periods.

[0156] In one possible example scenario, when the driver module is an LTPO structure, Figure 9a This is a timing diagram of odd-numbered frames for a multiplexing module provided in Embodiment 4 of this application. Figure 9b This is a timing diagram of even-numbered frames for a multiplexing module provided in Embodiment 4 of this application. According to... Figure 9a and Figure 9b The provided diagram shows that during the first period T1 of odd-numbered frames, the timing control module 200 selects the sixteenth transistor MUX1 to be turned on at a low level, providing a high-level privacy signal VGH to the privacy signal line PPL; during the first period T1 of even-numbered frames, the timing control module 200 selects the seventeenth transistor MUX2 to be turned on at a low level, providing a low-level privacy signal VGL to the privacy signal line PPL; during the third period T3, the timing control module 200 selects the eighteenth transistor MUX3 to be turned on, providing a tri-state signal V0 to the privacy signal line PPL; and during the fourth period T4, the timing control module 200 selects the nineteenth transistor MUX4 to be turned on, providing a privacy signal to the privacy signal line PPL.

[0157] This application provides a privacy control module. An external host determines the area to be protected from peeping based on the displayed screen, divides it into partitions, and then transmits the privacy area information obtained from the partitions to a timing control module. The timing control module parses the privacy data to obtain privacy parsing data, stores it, and converts the signal level. The transistor in the multiplexing unit implements timing control, and the privacy signal output from the multiplexed unit is transmitted to the privacy signal line to selectively control the privacy module, thereby achieving the technical effect of privacy protection in any area.

[0158] Example 5 Figure 10 This is a flowchart illustrating a privacy control method provided in Embodiment 5 of this application. Figure 10 This explanation is based on the aforementioned embodiment of the privacy control module. Figure 10 The steps of the privacy control method, as illustrated in the diagram, specifically include: S1001. Obtain the privacy zone information sent by the external host. The privacy zone information is the coordinate data of the target area selected by the external host. The number of target areas is at least 1.

[0159] The privacy protection zone information mentioned here refers to the privacy protection zone data selected after processing by the external host, which can be fed back to the timing control module in any form, such as coordinate data, vector data, or signal set data.

[0160] The target area mentioned here can be understood as the area that needs to be protected from peeping. The number of target areas simply refers to dividing the area that needs to be protected from peeping into separate zones.

[0161] Furthermore, an external host is used to select the area that needs to be protected from peeping in the current environment, and the selected area is used as the target area. Multiple dispersed target areas are combined to obtain the total area that needs to be protected from peeping, and thus the peeping area information is obtained.

[0162] S1002. Analyze the privacy protection area information to obtain the target privacy protection signal.

[0163] The anti-spy target signal mentioned here can be understood as a set of signals that have been processed and have a control function for the area that needs to be protected from peeping.

[0164] Furthermore, after obtaining the area information that needs to be protected from peeping through the timing control module, the area information is parsed and processed. This can be a mapping process of positional relationships, which transforms the specific position information that needs to be protected from peeping into a signal that can control the corresponding pixel. By obtaining the signal, the pixel at the specified position on the corresponding display screen can be displayed in a peeping-proof manner.

[0165] S1003, the control drive module and the anti-spy signal line perform initialization processing on the anti-spy module.

[0166] The initialization process mentioned here can be understood as follows: Figures 5a-5d During the first cycle period, the privacy signal output by the privacy signal line is controlled to be high or low, and the pixels lit up in the previous frame in the privacy module are reset accordingly, that is, the privacy module is initialized.

[0167] Furthermore, after the drive module is turned on internally, the current signal output by the drive module is turned on internally through the control module to reset the pixels in the privacy module connected to the control module, providing a reference signal for the next step of privacy control.

[0168] S1004. Perform anti-spy control on the initialized anti-spy module according to the target anti-spy signal.

[0169] The privacy control mentioned here can be understood as privacy display or regular display.

[0170] Furthermore, after initialization, the privacy module uses the target privacy signal output from the privacy signal line PPL to selectively activate the control module. For example, when the target privacy signal is high, the transistors connected to the regular display pixels in the control module are activated, controlling the privacy module to display normally; when the target privacy signal is low, the transistors connected to the privacy display pixels in the control module are activated, controlling the privacy module to display in the privacy mode. By changing the magnitude of the target privacy signal and the position of the scan lines, privacy control of any area on the display screen can be achieved, improving the user experience.

[0171] This application provides a method for preventing peeping to the screen. An external host determines the peeping area information based on the screen image. After being parsed by a timing control module, a target peeping signal is obtained. After the peeping module is initialized, the target peeping signal is used to control the pixels of the peeping module. By changing the content of the peeping area information, the size of the target peeping signal can be changed, thereby achieving the technical effect of peeping to any area.

[0172] Figure 11 This is a flowchart illustrating another privacy control method provided in Embodiment 5 of this application. Figure 11 Is Figure 10 This introduction is based on [the previous information]. Figure 11 The provided diagram shows that the steps of the privacy control method also include: S1101. Obtain the number of regions and the coordinates of the regions corresponding to the target partition.

[0173] The target partitions are obtained by the external host based on the area to be protected from peeping. Specifically, the external host selects the area to be protected from peeping based on the current playback environment and content of the display screen, and sends this information to the timing control module. The external host then partitions the selected area on the display screen to obtain multiple target partitions, each of which is set as a rectangle.

[0174] S1102. Generate privacy protection area information based on the number of areas and the coordinates of the area locations.

[0175] The partitioning process described in this embodiment does not include the entire display screen; the default area for the entire display screen is the area within the coordinate system. The target partition is selected as the area requiring privacy protection.

[0176] Regarding the process of generating privacy protection area information, the external host selects multiple areas that need privacy protection based on the environment and the content of the displayed screen. Using a rectangular structure, multiple target areas are obtained. The coordinates of the four corners of the rectangle containing each target area are used as data to limit the privacy protection position. The multiple target areas and the coordinates of each target area are fed back to the timing control module as privacy protection area information.

[0177] Furthermore, the number of target areas can be used as the number of partitions. For example, three target areas represent three partitions for the privacy protection area.

[0178] In one possible example scenario, Figure 12 This is a schematic diagram of a two-partition structure for privacy protection area information provided in Embodiment 5 of this application. Figure 12 The given diagram shows that the area requiring privacy protection is divided into two partitions. Partition 1 (area 1 in the diagram) has the following corner coordinates: D1(x1, y1), D1(x2, y2), D1(x3, y3), D1(x4, y4). Partition 2 (area 2 in the diagram) has the following corner coordinates: D2(x1, y1), D2(x2, y2), D2(x3, y3), D2(x4, y4). Other areas are considered normal display areas and are not marked (i.e., area 3 in the diagram, excluding the privacy protection area). The external host feeds back the number of partitions and the corresponding corner coordinates of each partition as privacy protection area information to the timing control module.

[0179] S1105. Obtain the privacy zone information sent by the external host. The privacy zone information is the coordinate data of the target area selected by the external host. The number of target areas is at least one.

[0180] S1106. The privacy protection area information is parsed and processed to obtain privacy protection parsing data.

[0181] S1107. Perform binarization processing on the anti-spying parsing data to obtain the corresponding target anti-spying signal.

[0182] The analysis process described here will not be explained in detail; it is merely a process of transforming and processing the coordinate data contained in the privacy protection area information to obtain data representing the signal magnitude.

[0183] Furthermore, the timing control module parses the information containing the number and specific location coordinates of the privacy zones to obtain data representing the privacy signal. It ensures that the parsed data has the same resolution as the original data and the display screen, achieving a one-to-one correspondence. The parsed privacy data is then binarized into 0 and 1 values. Privacy control rules are set, uniformly setting the data within the privacy zone to 0. That is, when the privacy signal corresponding to the current row pixel is 0, it indicates privacy display. Conversely, the data within the privacy zone can be uniformly set to 1. When the privacy signal corresponding to the current row pixel is 1, it indicates that this pixel requires privacy display.

[0184] In one possible example scenario, Figure 13 This is a schematic diagram of the structure of a spying target signal provided in Embodiment 5 of this application. Figure 13 The provided diagram sets the values ​​in the selected privacy area to 0, sets the privacy target signal to 0 in the two partitions to represent the pixels that need privacy protection, and sets the part with the privacy area removed to 1 as a regular display screen, which is the default regular display.

[0185] Furthermore, Figure 13 The data array consisting of the target privacy signal and the regular display signal corresponding to the central display screen is used as a coordinate analysis data array (Prevent peeping Data, or PPD for short). The timing control module then analyzes the privacy area information to obtain PPD data. Based on the PPD data, reference signals are provided for the next step of privacy control of the corresponding pixels.

[0186] S1108, The control drive module performs pixel reset on the privacy module.

[0187] S1109. The three-state signal output by the control anti-spy signal line is used to shut down the internal control module so that the drive module can perform pixel compensation. The three-state signal is used to control the first transistor and the second transistor to be in the off state.

[0188] S1110. Initialize the privacy module according to pixel reset and pixel compensation.

[0189] The pixel reset mentioned here can be understood as... Figures 5a-5d The control process for the first and second cycle periods mainly implements the initialization process. Please refer to the following for details: Figures 5a-5d The control process for the first and second cycle periods will not be elaborated here.

[0190] S1111: The value of the target anti-spy signal is output by controlling the anti-spy signal line. The target anti-spy signal is binary data.

[0191] Optionally, the binarized data mentioned here is merely a quantitative limitation on the value of the target privacy signal. According to the design requirements of those skilled in the art, it can also be set as other reference signals, with the purpose of achieving differentiated control between privacy display and conventional display, all of which are within the protection scope of this application.

[0192] S1112. When the value of the target anti-spy signal is 1 in the binarization, the voltage value corresponding to the first node is determined to be a high-level signal.

[0193] S1113. Determine that the first transistor is in the first on state based on the high-level signal, and determine that the second transistor is in the first off state.

[0194] S1114. Control the lighting of the conventional LED in the privacy module based on the first on state, and control the privacy LED to be turned off based on the first off state.

[0195] Specifically, corresponding Figures 5a-5d During the third cycle period, and when the nineteenth transistor MUX4 is selected as low level in the multiplexing unit, the privacy signal refers to the PPD data output by the L / S line. When the PPD data is binarized to 1, the first transistor is controlled to turn on, so that the conventional light-emitting diode connected to the first transistor displays and performs conventional display.

[0196] S1115. When the value of the target anti-spy signal is 0 in the binarization, determine that the voltage value corresponding to the first node is a low-level signal.

[0197] S1116. Determine that the first transistor is in the second off state based on the low-level signal, and determine that the second transistor is in the second on state.

[0198] S1117. Based on the second closed state, control the conventional light-emitting diode in the privacy module to be turned off, and based on the second open state, control the light-emitting diode in the privacy module to be turned on.

[0199] Specifically, corresponding Figures 5a-5d During the third cycle period, and when the nineteenth transistor MUX4 is selected as low level in the multiplexing unit, the privacy signal refers to the PPD data output by the L / S line. When the PPD data is binarized to 0, the second transistor is controlled to turn on, so that the privacy LED connected to the second transistor is displayed, and the privacy display is executed.

[0200] Furthermore, by changing the content of the PPD data, the privacy settings for pixels in different scan lines can be optimized, thereby achieving privacy protection in any area and improving the user experience.

[0201] Example 6 Figure 14This is a schematic diagram of the structure of a privacy control device 10000 provided in Embodiment Six of this application. According to... Figure 14 The provided diagram shows that the structure of the privacy control device specifically includes: an external host 800; and, as shown in the diagram. Figures 7-9b The privacy control module 2000 is electrically connected to the external host 800.

[0202] The privacy control device 10000 provided in this embodiment can be as follows: Figure 14 The privacy control device shown can perform the following functions: Figures 10-13 All steps of the privacy control method in China, thereby achieving Figures 10-13 For details on the technical effectiveness of the privacy control method shown, please refer to [link / reference]. Figures 10-13 The relevant descriptions are presented concisely and will not be elaborated upon here.

[0203] Furthermore, in this application, unless otherwise expressly specified and limited, the terms "connected," "linked," "stacked," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A privacy control pixel circuit, characterized in that, The privacy control pixel circuit includes a light emission control line, a data line, and multiple scan lines. The privacy control pixel circuit also includes: Driver module, control module, privacy module, and privacy signal line; The first input terminal of the driving module is connected to the data line, and the output terminal of the driving module is connected to the first input terminal of the control module. The driving module is used to convert the data signal transmitted by the data line into a pixel driving signal and output the pixel driving signal to the control module. The second input terminal of the control module is connected to the privacy signal line, which is used to transmit the received privacy signal to the control module. The control module controls the privacy module to perform privacy display based on the privacy signal and the pixel driving signal.

2. The privacy control pixel circuit according to claim 1, characterized in that, The control module includes: a first transistor and a second transistor; The control terminals of the first transistor and the second transistor are connected to the first node and receive the privacy signal transmitted by the privacy signal line. The privacy signal includes a tri-state signal, which is used to control both the first transistor and the second transistor to be in the off state. Preferably, the control module further includes a third transistor, the first end of which is connected to the first node, and the second end of which serves as the second input terminal of the control module and is connected to the privacy signal line. Preferably, the control module further includes a first capacitor, with a first end of the first capacitor connected to a first node and a second end of the first capacitor connected to a first power supply voltage line.

3. The privacy control pixel circuit according to claim 2, characterized in that, The first transistor is of a different type than the second transistor; Preferably, the first transistor is an N-type thin-film transistor and the second transistor is a P-type thin-film transistor.

4. The privacy control pixel circuit according to claim 1, characterized in that, The control module further includes a third input terminal, which is connected to the light emission control line; or, the third input terminal of the control module is connected to the third scan line. Preferably, the control module includes a third transistor, the control terminal of which is connected to the light emission control line as the third input terminal of the control module; or, the control terminal of the third transistor is connected to the third scan line as the third input terminal of the control module. Preferably, the driving module further includes a second input terminal, a third input terminal, and a fourth input terminal. The second input terminal of the driving module is connected to the light emission control line, the third input terminal of the driving module is connected to the first scan line, and the fourth input terminal of the driving module is connected to the second scan line. Preferably, the first output terminal of the control module is connected to the first input terminal of the privacy module, and the second output terminal of the control module is connected to the second input terminal of the privacy module; Preferably, the control module includes a first transistor and a second transistor, wherein a first terminal of the first transistor serves as a first input terminal of the control module, a first terminal of the second transistor is connected to the first terminal of the first transistor, a second terminal of the first transistor serves as a first output terminal of the control module and is connected to the first input terminal of the privacy module, and a second terminal of the second transistor serves as a second output terminal of the control module and is connected to the second input terminal of the privacy module.

5. The privacy control pixel circuit according to claim 1, characterized in that, The privacy module includes: Conventional LEDs and privacy LEDs; The first electrode of the conventional light-emitting diode is connected to the first output terminal of the control module as the first input terminal of the privacy module, and the second electrode of the conventional light-emitting diode and the second electrode of the privacy light-emitting diode are connected to the second power supply voltage line. The conventional light-emitting diode is used for conventional display. The first electrode of the privacy LED is connected to the second output terminal of the control module as the second input terminal of the privacy module, and the privacy LED is used for privacy display. Preferably, the viewing angle of the privacy LED is a preset acute angle or right angle.

6. The privacy control pixel circuit according to claim 1, characterized in that, The driving module includes: a first driving unit; The first input terminal of the first driving unit is connected to the data line as the first input terminal of the driving module; the second input terminal of the first driving unit is connected to the light emission control line as the second input terminal of the driving module; the third input terminal of the first driving unit is connected to the first scan line as the third input terminal of the driving module; the fourth input terminal of the first driving unit is connected to the second scan line as the fourth input terminal of the driving module; and the output terminal of the first driving unit is connected to the first input terminal of the control module as the output terminal of the driving module. Preferably, the first driving unit includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitor; The control terminal of the fourth transistor is connected to the second scan line as the fourth input terminal of the first driving unit and the control terminal of the fifth transistor. The first terminal of the fourth transistor is connected to the data line as the first input terminal of the first driving unit. The second terminal of the fourth transistor is connected to the first terminal of the sixth transistor and the first terminal of the seventh transistor. The first terminal of the fifth transistor, the first terminal of the eighth transistor, the control terminal of the seventh transistor, and one terminal of the second capacitor are connected. The second terminal of the fifth transistor serves as the output terminal of the first driving unit and is connected to the second terminal of the seventh transistor, the first terminal of the ninth transistor, and the first input terminal of the control module. The control terminal of the sixth transistor is connected to the light-emitting control line as the second input terminal of the first driving unit, and the second terminal of the sixth transistor and the other terminal of the second capacitor are connected to the third power supply voltage line. The control terminal of the eighth transistor is connected to the first scan line as the third input terminal of the first driving unit, and the second terminal of the eighth transistor and the second terminal of the ninth transistor are connected to the first power supply voltage line. Preferably, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are of the same type; Preferably, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all P-type thin-film transistors; or, The driving module includes: a second driving unit; The first input terminal of the second driving unit is connected to the data line as the first input terminal of the driving module; the second input terminal of the second driving unit is connected to the light emission control line as the second input terminal of the driving module; the third input terminal of the second driving unit is connected to the first scan line as the third input terminal of the driving module; the fourth input terminal of the second driving unit is connected to the second scan line as the fourth input terminal of the driving module; the fifth input terminal of the second driving unit is connected to the fourth scan line; and the output terminal of the second driving unit is connected to the first input terminal of the control module as the output terminal of the driving module. Preferably, the second driving unit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a third capacitor; The control terminal of the tenth transistor is connected to the second scan line as the fourth input terminal of the second driving unit, the first terminal of the tenth transistor is connected to the data line as the first input terminal of the second driving unit, and the second terminal of the tenth transistor is connected to the first terminal of the eleventh transistor and the first terminal of the twelfth transistor. The control terminal of the eleventh transistor, the first terminal of the thirteenth transistor, the first terminal of the fourteenth transistor, and the first terminal of the third capacitor are connected. The second terminal of the eleventh transistor serves as the output terminal of the second driving unit and is connected to the second terminal of the thirteenth transistor, the first terminal of the fifteenth transistor, and the first input terminal of the control module. The control terminal of the twelfth transistor is connected to the light-emitting control line as the second input terminal of the second driving unit, and the second terminal of the twelfth transistor and the second terminal of the third capacitor are connected to the third power supply voltage line. The control terminal of the thirteenth transistor is connected to the fourth scan line as the fifth input terminal of the second driving unit; The control terminal of the fourteenth transistor is connected to the first scan line as the fourth input terminal of the second driving unit, and the second terminal of the fourteenth transistor and the second terminal of the fifteenth transistor are connected to the first power supply voltage line. Preferably, the tenth transistor, the eleventh transistor, and the twelfth transistor are of the same type, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are of the same type, and the tenth transistor and the thirteenth transistor are of different types; Preferably, the tenth, eleventh, and twelfth transistors are all P-type thin-film transistors, and the thirteenth, fourteenth, and fifteenth transistors are all N-type thin-film transistors.

7. A privacy control module, the module comprising the privacy control pixel circuit as described in any one of claims 1 to 6, characterized in that, The module also includes: a timing control module, a shift register, a level conversion module, a multiplexing module, and a display driver chip; One end of the timing control module is connected to an external host, and the other end of the timing control module is connected to one end of the shift register. The timing control module is used to receive the privacy protection area information sent by the external host, and after parsing the privacy protection area information, send the privacy protection parsing signal to the shift register. The privacy protection area information includes privacy protection area coordinate data. The other end of the shift register is connected to one end of the level conversion module, and the shift register is used to transmit the anti-spying parsing information to the level conversion module; The other end of the level conversion module is connected to one end of the multiplexing module, and the other end of the multiplexing module is connected to multiple anti-spy signal lines. The level conversion module converts the anti-spy parsing information and transmits it to the multiplexing module, so that the multiplexing module transmits anti-spy signals to the anti-spy signal lines according to the anti-spy parsing information. The display driver chip is connected to the privacy control pixel circuit, and the display driver chip is used to drive the driver module in the privacy control pixel circuit.

8. The privacy control module according to claim 7, characterized in that, The multiplexing module includes: multiple multiplexing units; One end of the multiplexing unit is connected to the level conversion module, and the other end of the multiplexing unit is connected to one of the multiple privacy signal lines; Preferably, the multiplexing unit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are of the same type; The control terminals of the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are respectively connected to the timing control module, and the first terminals of the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor are connected to the privacy signal line. The second terminal of the sixteenth transistor is connected to a high-level signal line, the second terminal of the seventeenth transistor is connected to a low-level signal line, the second terminal of the eighteenth transistor is connected to a tri-state signal line, and the second terminal of the nineteenth transistor is connected to the level conversion signal line corresponding to the level conversion module. The tri-state signal line is used to output a tri-state signal, which is used to control both the N-type thin film transistor and the P-type thin film transistor to be off. Preferably, the sixteenth, seventeenth, eighteenth, and nineteenth transistors are all P-type thin-film transistors.

9. A method for preventing peeping, characterized in that, Applied to the privacy control module as described in claim 7 or 8, comprising: Obtain privacy protection area information sent by an external host, wherein the privacy protection area information is the coordinate data of a target area selected by the external host, and the number of target areas is at least one; The privacy protection area information is analyzed to obtain the target privacy protection signal; The control drive module and the anti-spy signal line perform initialization processing on the anti-spy module; The anti-spy module is subjected to anti-spy control based on the target anti-spy signal after initialization.

10. The method according to claim 9, characterized in that, The method further includes: Obtain the number of regions and the coordinates of the regions corresponding to the target partition, wherein the target partition is obtained by the external host based on the partitioning of the region to be protected from peeping. Anti-spy zone information is generated based on the number of zones and the location coordinates of the zones; Preferably, the step of parsing the privacy protection area information to obtain the target privacy protection signal includes: The privacy protection area information is parsed to obtain privacy protection parsing data; The anti-spying parsing data is binarized to obtain the corresponding target anti-spying signal.

11. The method according to claim 9, characterized in that, The control drive module and the privacy signal line perform initialization processing on the privacy module, including: The control driver module resets the pixels of the privacy module; The control module is shut down by using a three-state signal output from the privacy signal line so that the drive module can perform pixel compensation. The three-state signal is used to control both the first transistor and the second transistor to be in the off state. The privacy module is initialized based on the pixel reset and pixel compensation. Preferably, the anti-spy module is subjected to anti-spy control based on the target anti-spy signal after initialization, including: The value of the target privacy signal is output by controlling the privacy signal line, and the target privacy signal is binary data; When the value of the target anti-spy signal is 1 in the binarization, the voltage value corresponding to the first node is determined to be a high-level signal; Based on the high-level signal, it is determined that the first transistor is in a first on state and the second transistor is in a first off state; The conventional LED in the privacy module is controlled to light up based on the first on state, and the privacy LED is controlled to turn off based on the first off state. or, When the value of the target anti-spy signal is 0 in the binarization, the voltage value corresponding to the first node is determined to be a low-level signal; Based on the low-level signal, it is determined that the first transistor is in a second off state and the second transistor is in a second on state; The privacy module controls the conventional LEDs to be turned off based on the second off state, and controls the privacy LEDs to be turned on based on the second on state.

12. A privacy control device, characterized in that, include: External host; and, The privacy control module according to any one of claims 7 or 8, wherein the privacy control module is electrically connected to the external host.

Images