Data voltage control circuit and display panel

Abstract

The invention discloses a data voltage control circuit and a display panel, and relates to the technical field of display, the circuit comprises a polarity duration determination module, a polarity control signal is accessed to a first end, a data voltage is accessed to a second end, and under the control of the polarity control signal, positive polarity duration data and negative polarity duration data of the data voltage are determined; the first end of the polarity duration comparison module is connected with the third end of the polarity duration determination module, and positive polarity adjustment data and negative polarity adjustment data are respectively determined based on the positive polarity duration data and the negative polarity duration data; the first end of the data voltage adjusting module is connected with the second end of the polarity time length comparison module, the second end of the data voltage adjusting module is connected with data voltage, and the data voltage adjusting module is used for adjusting the positive polarity hopping time length based on the positive polarity adjusting data and adjusting the negative polarity hopping time length based on the negative polarity adjusting data so that the positive polarity hopping time length can be equal to the negative polarity hopping time length. According to the invention, the screen crosstalk is improved by optimizing the design of the data voltage control circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a data voltage control circuit and a display panel. Background Technology

[0002] In LCD (Liquid Crystal Display) displays, to prevent the polarization of liquid crystal molecules, a polarity reversal driving method is usually adopted. That is, the data voltage switches between positive and negative polarities, and the positive polarity transition (such as from low to high) and the negative polarity transition (such as from high to low) should generate coupling charges of equal magnitude and opposite direction to the common electrode voltage, so as to cancel each other out. However, because there are inherent differences in the carrier mobility of different types of thin film transistors, the amount of coupling charge generated during the positive and negative polarity transition cannot be completely canceled out (mainly because the transition time of the two is inconsistent, resulting in the incomplete cancellation of coupling charge), thus forming crosstalk on the display screen.

[0003] Traditional data voltage control circuits adjust the value of the common electrode voltage to completely cancel out the amount of coupled charge generated during the positive and negative polarity transitions. The principle behind this method is to compensate for the difference in carrier mobility between different types of thin-film transistors by adjusting the value of the common electrode voltage. However, this data voltage control method cannot be applied to scenarios where the amount of coupled charge changes due to variations in process, voltage, temperature, etc. Therefore, this data voltage control method is limited by its applicable scenarios. As a result, how to optimize the design of data voltage control circuits to improve screen crosstalk is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] The main objective of this application is to provide a data voltage control circuit and a display panel, which aims to optimize the design of the data voltage control circuit to improve screen crosstalk.

[0005] To achieve the above objectives, this application provides a data voltage control circuit, the data voltage control circuit comprising: A polarity duration determination module, wherein a first terminal of the polarity duration determination module is connected to a polarity control signal, and a second terminal of the polarity duration determination module is connected to a data voltage, and the polarity duration determination module is used to determine the positive polarity duration data and the negative polarity duration data of the data voltage under the control of the polarity control signal; A polarity duration comparison module, wherein the first end of the polarity duration comparison module is connected to the third end of the polarity duration determination module, and the polarity duration comparison module is used to determine positive polarity adjustment data and negative polarity adjustment data based on the positive polarity duration data and the negative polarity duration data, respectively; A data voltage adjustment module is provided, wherein a first terminal of the data voltage adjustment module is connected to a second terminal of the polarity duration comparison module, the second terminal of the data voltage adjustment module is connected to the data voltage, and a third terminal of the data voltage adjustment module is connected to the data voltage terminal of the display panel. The data voltage adjustment module is used to adjust the positive polarity transition duration of the data voltage based on the positive polarity adjustment data, and to adjust the negative polarity transition duration of the data voltage based on the negative polarity adjustment data, so that the positive polarity transition duration is equal to the negative polarity transition duration.

[0006] In one embodiment, the polarity duration determination module includes: A first thin-film transistor, wherein a first terminal of the first thin-film transistor is connected to the data voltage, and a third terminal of the first thin-film transistor is connected to the polarity control signal; A first transition detection unit, wherein a first end of the first transition detection unit is connected to a second end of the first thin-film transistor, and a second end of the first transition detection unit is connected to a first end of the polarity duration comparison module; A second thin-film transistor, wherein the first terminal of the second thin-film transistor is connected to the data voltage, and the third terminal of the second thin-film transistor is connected to the polarity control signal; The second transition detection unit has a first end connected to the second end of the second thin-film transistor, and the second end of the second transition detection unit is connected to the first end of the polarity duration comparison module.

[0007] In one embodiment, both the first transition detection unit and the second transition detection unit include a falling edge transition detection subunit and a rising edge transition detection subunit. The first end of the falling edge transition detection subunit is connected to the first end of the rising edge transition detection subunit and then connected to the second end of the corresponding thin-film transistor. The second end of the falling edge transition detection subunit is connected to the second end of the rising edge transition detection subunit and then connected to the first end of the polarity duration comparison module.

[0008] In one embodiment, the falling edge transition detection subunit includes: A falling-edge trigger, wherein the first terminal of the falling-edge trigger is connected to the second terminal of the corresponding thin-film transistor; A first comparator, wherein the first input terminal of the first comparator is connected to the first terminal of the falling edge trigger, the second input terminal of the first comparator is connected to a first voltage source, and the output terminal of the first comparator is connected to the second terminal of the falling edge trigger; The third thin-film transistor has a first terminal connected to a current source, a third terminal connected to the third terminal of the falling edge trigger, and a second terminal connected to the first terminal of the polarity duration comparison module. A first capacitor, the first end of which is connected to the first end of the polarity duration comparison module, and the second end of which is grounded.

[0009] In one embodiment, when the first terminal of the falling edge trigger receives a falling edge, the third terminal of the falling edge trigger outputs a first level, and when the second terminal of the falling edge trigger receives the first level, the third terminal of the falling edge trigger outputs a second level, wherein the first level and the second level are high level and low level, respectively.

[0010] In one embodiment, the rising edge transition detection subunit includes: A rising edge trigger, wherein the first terminal of the rising edge trigger is connected to the second terminal of the corresponding thin-film transistor; The second comparator has its first input terminal connected to the first terminal of the rising edge flip-flop, its second input terminal connected to a second voltage source, and its output terminal connected to the second terminal of the rising edge flip-flop. A fourth thin-film transistor, wherein the first terminal of the fourth thin-film transistor is connected to a current source, the third terminal of the fourth thin-film transistor is connected to the third terminal of the rising edge trigger, and the second terminal of the fourth thin-film transistor is connected to the first terminal of the polarity duration comparison module. The second capacitor has its first terminal connected to the first terminal of the polarity duration comparison module, and its second terminal grounded.

[0011] In one embodiment, when the first terminal of the rising edge trigger receives a rising edge, the third terminal of the rising edge trigger outputs a first level, and when the second terminal of the rising edge trigger receives the first level, the third terminal of the rising edge trigger outputs a second level, wherein the first level and the second level are high level and low level, respectively.

[0012] In one embodiment, the polarity duration comparison module includes: A buffer, wherein a first end of the buffer is connected to a second end of the first transition detection unit and a second end of the second transition detection unit; A subtractor, wherein the first input terminal of the subtractor is connected to the second terminal of the buffer, and the second input terminal of the subtractor is connected to the third terminal of the buffer, wherein the second terminal of the buffer is used to output the positive polarity duration data of the first transition detection unit, and the third terminal of the buffer is used to output the negative polarity duration data of the second transition detection unit; An error amplifier is provided, with its first terminal connected to the output terminal of the subtractor, and its second and third terminals connected to the first terminal of the data voltage adjustment module. The error amplifier is used to determine the negative polarity adjustment data and the positive polarity adjustment data based on the phase difference duration data determined by the subtractor, wherein the phase difference duration data includes the difference between the negative polarity duration data and the positive polarity duration data.

[0013] In one embodiment, the data voltage adjustment module includes a negative polarity adjustment unit and a positive polarity adjustment unit. The first terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are respectively connected to the second and third terminals of the error amplifier. The second terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage terminal of the display panel. The third terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage. Both the negative polarity adjustment unit and the positive polarity adjustment unit include: A polarity adjuster, wherein a first terminal of the polarity adjuster is connected to the data voltage, and a second terminal of the polarity adjuster is connected to the data voltage terminal of the display panel; A transistor, wherein the first terminal of the transistor is connected to a power supply, and the third terminal of the transistor is connected to the second terminal of the error amplifier or the third terminal of the error amplifier. A grounding resistor, the first end of which is connected to the second end of the transistor and then connected to the switching time adjustment terminal of the negative polarity adjustment unit or the polarity regulator, and the second end of the grounding resistor is grounded.

[0014] Furthermore, to achieve the above objectives, this application also provides a data voltage control method, which is applied to the aforementioned data voltage control circuit, and the data voltage control method includes: Under the control of the polarity control signal, the positive polarity duration data and negative polarity duration data of the data voltage are determined based on the polarity duration determination module, and the positive polarity adjustment data and negative polarity adjustment data are determined respectively in the polarity duration comparison module based on the positive polarity duration data and the negative polarity duration data. Based on the positive polarity adjustment data, the positive polarity transition duration of the data voltage is adjusted in the data voltage adjustment module, and based on the negative polarity adjustment data, the negative polarity transition duration of the data voltage is adjusted in the data voltage adjustment module, so that the positive polarity transition duration is equal to the negative polarity transition duration.

[0015] In one embodiment, the step of determining positive polarity adjustment data and negative polarity adjustment data respectively in the polarity duration comparison module based on the positive polarity duration data and the negative polarity duration data includes: Based on the positive polarity duration data and the negative polarity duration data, the phase difference duration data is determined in the polarity duration comparison module, and positive polarity adjustment data and negative polarity adjustment data are determined based on the phase difference duration data respectively.

[0016] In one embodiment, after the polarity-based duration determination module determines the positive and negative polarity duration data of the data voltage, it includes: Determine the phase difference duration data between the positive polarity duration data and the negative polarity duration data within a preset time frame; When the phase difference duration data exceeds a preset adjustment threshold, positive polarity adjustment data and negative polarity adjustment data are determined based on the phase difference duration data. When the sum of the phase difference duration data is less than or equal to a preset adjustment threshold, positive polarity adjustment data and negative polarity adjustment data are determined based on the sum of the phase difference duration data after the preset time frame ends.

[0017] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the data voltage control circuit described in any of the above claims.

[0018] To optimize the design of the data voltage control circuit and improve screen crosstalk, this application provides a data voltage control circuit. This data voltage control circuit determines the duration adjustment data of positive and negative polarities through a polarity duration determination module and a polarity duration comparison module. Then, after adjusting the duration adjustment data of positive and negative polarities through the data voltage adjustment module, the positive polarity transition duration is made equal to the negative polarity transition duration. This improves the screen crosstalk phenomenon caused by the inconsistency between the positive and negative polarity transition durations by adjusting the positive and negative polarity transition durations. Specifically, the polarity duration determination module has a polarity control signal connected to its first terminal and a data voltage connected to its second terminal. Under the control of the polarity control signal, the polarity duration determination module can determine the positive and negative polarity duration data of the data voltage, meaning it can adjust based on real-time positive and negative polarity durations instead of using fixed adjustment values. Next, the first terminal of the polarity duration comparison module is connected to the third terminal of the polarity duration determination module. This module can determine the positive and negative polarity adjustment data based on the positive and negative polarity duration data, respectively, thus determining the data that needs adjustment between positive and negative polarities. Finally, the positive and negative polarity adjustment data can be transmitted back to the data voltage. The voltage adjustment module can adjust the positive polarity transition time of the data voltage based on the positive polarity adjustment data, and adjust the negative polarity transition time of the data voltage based on the negative polarity adjustment data, so as to achieve a result where the positive polarity transition time equals the negative polarity transition time. This result is then output to the data voltage terminal of the display panel, thereby improving the screen crosstalk phenomenon caused by the inconsistency between the positive and negative polarity transition times. Compared with traditional data voltage control methods, the real-time processing and adjustment method can avoid the phenomenon that it cannot be applied to scenarios where the amount of coupled charge changes due to changes in process, voltage magnitude, temperature, etc., thereby effectively improving the display quality of the display panel applied to this data voltage control circuit by improving the screen crosstalk phenomenon. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural block diagram of the first embodiment of the data voltage control circuit of this application; Figure 2This is a connection diagram of the polarity duration determination module in the data voltage control circuit of this application; Figure 3 This is another connection diagram of the polarity duration determination module in the data voltage control circuit of this application; Figure 4 This is a circuit connection diagram of the falling edge transition detection subunit in the data voltage control circuit of this application; Figure 5 This is a circuit connection diagram of the rising edge transition detection subunit in the data voltage control circuit of this application; Figure 6 This is a circuit connection diagram of the negative polarity adjustment unit in the data voltage control circuit of this application; Figure 7 This is a circuit connection diagram of the positive polarity adjustment unit in the voltage control circuit of this application; Figure 8 This is an equivalent schematic diagram of a bias current control in the voltage control circuit of this application. Figure 9 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0022] Explanation of icon numbers: 10. Polarity Duration Determination Module; 20. Polarity Duration Comparison Module; 30. Data Voltage Adjustment Module; Data1. Data Voltage; Data2. Adjusted Data Voltage; POL. Polarity Control Signal; T1. First Thin-Film Transistor; T2. Second Thin-Film Transistor; 11. First Transition Detection Unit; 12. Second Transition Detection Unit; 21. Buffer; 22. Subtractor; 23. Error Amplifier; RVC. Positive Polarity Duration Data; FVC. Negative Polarity Duration Data; VC. Phase Difference Duration Data; VCP. Positive Polarity Adjustment Data; VCN. Negative Polarity Adjustment Data; Y1. Rising Edge Transition Detection Subunit; Y2. Falling Edge Transition Detection Subunit; 41. Falling Edge Trigger; 4 2. First comparator; T3. Third thin-film transistor; C1. First capacitor; V1. First voltage source; Data-. Negative data voltage; Data+. Positive data voltage; 43. Rising edge trigger; 44. Second comparator; V2. Second voltage source; T4. Fourth thin-film transistor; C2. Second capacitor; IS. Current source; OP+. Positive regulator; OP-. Negative regulator; AVDD. First pull-up voltage; HAVDD. Second pull-up voltage; VCC. Power supply; Q. Transistor; R. Grounding resistor; I. ​​Bias current; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory.

[0023] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0028] In LCD displays, a polarity-reversal driving method is typically used to prevent liquid crystal molecule polarization. This means the data voltage switches between positive and negative polarities, and positive transitions (e.g., from low to high) and negative transitions (e.g., from high to low) generate equal but opposite coupling charges on the common electrode voltage, thus canceling each other out. However, in actual TFT (Thin Film Transistor) manufacturing processes, the inherent difference in carrier mobility between P-type MOS (Metal-Oxide-Semiconductor) and N-type MOS transistors leads to different driving capabilities of the source driver chip's output buffer at high and low output levels. This asymmetry in polarity results in different coupling to the common electrode voltage VCOM. For example, during a positive transition, the PMOS transistor typically dominates charging, but the speed is slower due to the influence of carrier mobility. Conversely, during a negative transition, the NMOS transistor typically dominates discharging, but the speed is faster due to the influence of carrier mobility. Therefore, an asymmetry exists between the rise time (Tr) and fall time (Tf), preventing the coupling charge of the positive and negative transitions to the common electrode voltage VCOM from being completely canceled out. The residual charge creates voltage fluctuations on VCOM, ultimately manifesting as crosstalk on the screen, causing variations in brightness. The problem of incomplete cancellation of coupling charge on the common electrode voltage VCOM due to positive and negative transitions is generally mitigated by optimizing the layout, adding a shielding layer, or adjusting the VCOM value. However, these are passive and fixed compensation measures, unsuitable for scenarios where the coupling charge changes due to variations in manufacturing process, voltage, temperature, etc. In practical applications, the coupling charge of the common electrode voltage VCOM can also change due to manufacturing process, voltage, and temperature. Adjusting the VCOM value may only be applicable to specific manufacturing processes, voltage levels, and temperatures, resulting in poor overall improvement of screen crosstalk.

[0029] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.

[0030] To address the technical deficiencies mentioned above, this application provides a data voltage control circuit and method, as well as a display panel.

[0031] This application provides a data voltage control circuit, referring to... Figure 2 As shown, Figure 2 This is a structural block diagram of a first embodiment of the data voltage control circuit of this application. The data voltage control circuit includes: The polarity duration determination module 10 has a first terminal connected to a polarity control signal POL and a second terminal connected to a data voltage Data1. The polarity duration determination module 10 is used to determine the positive polarity duration data RVC and the negative polarity duration data FVC of the data voltage Data1 under the control of the polarity control signal POL. The polarity duration comparison module 20 has its first end connected to the third end of the polarity duration determination module 10. The polarity duration comparison module 20 is used to determine the positive polarity adjustment data VCP and the negative polarity adjustment data VCN based on the positive polarity duration data RVC and the negative polarity duration data FVC, respectively. For example, this application processes the transition duration and adjusts the transition durations of positive and negative polarities to equal values ​​to completely cancel out the coupling charge quantities in opposite directions, thereby improving screen crosstalk. At this time, under the control of the polarity control signal POL of the polarity duration determination module 10, the positive polarity duration data RVC and the negative polarity duration data FVC of the data voltage Data1 are collected. For example, when the polarity control signal POL is high, it is determined to be a positive polarity data voltage Data+; conversely, when the polarity control signal POL is low, it is determined to be a negative polarity data voltage Data-. The polarity control signal POL can then be provided to a controller, which can identify the high or low state of the polarity control signal POL to determine whether it is a positive polarity data voltage Data+ or a negative polarity data voltage Data-. For example, the polarity control signal POL can be a signal generated internally by the source driver chip, which can control the output polarity. For instance, if the polarity control signal POL is high, it indicates that the output is a positive polarity data voltage Data+, and if the polarity control signal POL is low, it indicates that the output is a negative polarity data voltage Data-. The internal control logic will not be explained in detail here. Furthermore, once the positive polarity data voltage Data+ or the negative polarity data voltage Data- is determined, the duration data of the positive polarity data voltage Data+ or the negative polarity data voltage Data- will be determined in the polarity duration determination module 10. For example, the start and end of the transition of the positive polarity data voltage Data+ or the negative polarity data voltage Data- will be counted to obtain two timing data for the positive and negative polarity transitions. The polarity duration comparison module 20 can then be used to determine the difference between the two timing data, and then determine the positive polarity adjustment data VCP and the negative polarity adjustment data VCN for adjustment. This allows the transition duration of the positive and negative polarity data voltages to be adjusted based on the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, so that the positive polarity transition duration is equal to the negative polarity transition duration, thereby improving the display effect of the display panel.

[0032] For example, the positive polarity duration data RVC and the negative polarity duration data FVC can be the duration of the positive-to-negative polarity transition, or the time value can be converted into other representations, such as converting the time value into a voltage value. The transition duration of the positive-to-negative polarity data voltage can then be adjusted by comparing the voltage values. Since the transition duration ultimately needs to be adjusted, even if it is a defined duration, it must ultimately be converted into a control value, such as a voltage or current value, to control the device and achieve the effect of adjusting the transition duration. Of course, the positive polarity adjustment data VCP and the negative polarity adjustment data VCN can also be designed as count values ​​or voltage / current values, depending on the above situation; this is not limited here.

[0033] The data voltage adjustment module 30 has its first terminal connected to the second terminal of the polarity duration comparison module 20, the second terminal of the data voltage adjustment module 30 connected to the data voltage Data1, and its third terminal connected to the data voltage terminal of the display panel. The data voltage adjustment module 30 is used to adjust the positive polarity transition duration of the data voltage Data1 based on the positive polarity adjustment data VCP, and to adjust the negative polarity transition duration of the data voltage Data1 based on the negative polarity adjustment data VCN, so that the positive polarity transition duration is equal to the negative polarity transition duration.

[0034] In this embodiment, after determining the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, the positive polarity adjustment data VCP and the negative polarity adjustment data VCN are input to the data voltage adjustment module 30. At this time, the data voltage adjustment module 30 can adjust the positive polarity transition duration of the data voltage Data1 and the negative polarity transition duration of the data voltage Data1 according to the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, respectively, so as to realize that the positive polarity transition duration is equal to the negative polarity transition duration, thereby improving the display effect of the display panel. For example, assuming the positive polarity adjustment data VCP is A and the negative polarity adjustment data VCN is B, the positive polarity transition duration of data voltage Data1 will be adjusted by the transition duration corresponding to A, and the negative polarity transition duration of data voltage Data1 will be adjusted by the transition duration corresponding to B, ultimately making the positive polarity transition duration equal to the negative polarity transition duration. The adjusted data voltage Data2 is then output to the data voltage terminal of the display panel. The entire data voltage control circuit can monitor the transition time of the data signal Data1 under positive and negative polarities in real time, and determine the positive polarity adjustment data VCP and negative polarity adjustment data VCN that need to ensure equal transition durations for positive and negative polarities through the polarity duration comparison module 20. Then, the positive polarity adjustment data VCP and negative polarity adjustment data VCN are used to adjust the transition time under positive and negative polarities, ensuring that the transition time remains consistent under all circumstances, thereby eliminating crosstalk caused by VCOM coupling asymmetry.

[0035] Furthermore, in some feasible embodiments, reference is made to Figure 2 , Figure 2 This is a connection diagram of the polarity duration determination module in the data voltage control circuit of this application. The polarity duration determination module 10 includes: The first thin-film transistor T1 has a data voltage Data1 connected to its first terminal and a polarity control signal POL connected to its third terminal. The first transition detection unit 11 has its first end connected to the second end of the first thin film transistor T1, and its second end connected to the first end of the polarity duration comparison module 20. The second thin-film transistor T2 has a first terminal connected to the data voltage Data1 and a third terminal connected to the polarity control signal POL. The second transition detection unit 12 has its first end connected to the second end of the second thin film transistor T2, and its second end connected to the first end of the polarity duration comparison module 20.

[0036] In this embodiment, the polarity duration determination module 10 can use two different types of thin-film transistors to distinguish between positive polarity data voltage Data+ or negative polarity data voltage Data-. Of course, it can also be directly identified by control, that is, a relevant program is designed inside the controller to identify whether it is positive polarity data voltage Data+ or negative polarity data voltage Data-. For example, taking the identification method of two different types of thin-film transistors as an example, assuming that the polarity control signal POL is high, it means that the positive polarity data voltage Data+ is output, and the polarity control signal POL is low, it means that the negative polarity data voltage Data- is output. When the polarity control signal POL outputs a high level, the first thin-film transistor T1 is turned on and the second thin-film transistor T2 is turned off, and then the positive polarity data voltage Data+ in the data voltage Data1 is output to the first transition detection unit 11. The first transition detection unit 11 can be used to detect the transition duration of the positive polarity data voltage Data+, and then the detected transition duration is used as the positive polarity duration data RVC, and subsequent comparison and compensation processing is performed, which is then used as one of the bases for determining the positive polarity adjustment data VCP and the negative polarity adjustment data VCN. When the polarity control signal POL outputs a low level, the first thin-film transistor T1 is turned off and the second thin-film transistor T2 is turned on. This outputs the negative polarity data voltage Data- from the data voltage Data1 to the second transition detection unit 12. The second transition detection unit 12 can then detect the transition duration of the negative polarity data voltage Data-, using the detected transition duration as the negative polarity duration data FVC. This FVC is then used for subsequent comparison and compensation processing, serving as another basis for determining the positive polarity adjustment data VCP and the negative polarity adjustment data VCN. Finally, based on the determined positive polarity duration data RVC and negative polarity duration data FVC, the positive polarity adjustment data VCP and negative polarity adjustment data VCN can be further determined. Ultimately, the original positive and negative polarity transition durations can be adjusted using the positive polarity adjustment data VCP and negative polarity adjustment data VCN to ensure that the adjusted positive and negative polarity transition durations are equal, thereby improving the screen crosstalk problem caused by unequal positive and negative polarity transition durations.

[0037] Furthermore, refer to Figure 3 , Figure 3This is another connection diagram of the polarity duration determination module in the data voltage control circuit of this application. The first transition detection unit 11 and the second transition detection unit 12 each include a falling edge transition detection subunit Y2 and a rising edge transition detection subunit Y1. The first end of the falling edge transition detection subunit Y2 is connected to the first end of the rising edge transition detection subunit Y1 and then connected to the second end of the corresponding thin film transistor (that is, the first end of the falling edge transition detection subunit Y2 in the first transition detection unit 11 is connected to the first end of the rising edge transition detection subunit Y1 and then connected to the second end of the first thin film transistor T1, and the first end of the falling edge transition detection subunit Y2 in the second transition detection unit 12 is connected to the second end of the second thin film transistor T2). The second end of the falling edge transition detection subunit Y2 is connected to the second end of the rising edge transition detection subunit Y1 and then connected to the first end of the polarity duration comparison module 20.

[0038] In this embodiment, both the first transition detection unit 11 and the second transition detection unit 12 include a falling edge transition detection subunit Y2 and a rising edge transition detection subunit Y1. This allows for timing operations on the positive and negative polarity data voltages based on the falling edge transition detection subunit Y2 and the rising edge transition detection subunit Y1. For example, the rising edge transition detection subunit Y1 can be a timer, and this timer can be set to trigger at a low level and end at a high level. That is, the transition duration of the rising edge can be detected based on the rising edge transition detection subunit Y1. Similarly, the falling edge transition detection subunit Y2 can be designed in the same way. This allows for the acquisition of positive polarity duration data (RVC) and negative polarity duration data (FVC) in the first transition detection unit 11 and the second transition detection unit 12, providing a basis for subsequent adjustments. It is worth noting that, at this time, the first transition detection unit 11 and the second transition detection unit 12 can simultaneously use a falling edge transition detection subunit Y2 and a rising edge transition detection subunit Y1. Since the arrival times of positive and negative polarities do not coincide, the rising edge transition detection subunit Y1 and the falling edge transition detection subunit Y2 can be shared. However, it is necessary to determine whether the transition duration returned to the polarity duration comparison module 20 is the transition duration of the positive or negative polarity data voltage. For example, the high or low level of the polarity control signal POL can be used to determine whether the transition duration of the positive or negative polarity data voltage is being collected. That is, by sharing the rising edge transition detection subunit Y1 and the falling edge transition detection subunit Y2, the implementation cost of the first transition detection unit 11 and the second transition detection unit 12 can be reduced.

[0039] For example, refer to Figure 3Taking the rising edge transition detection subunit Y1 detecting the transition duration of the positive polarity data voltage Data+ and the falling edge transition detection subunit Y2 detecting the transition duration of the negative polarity data voltage Data- as an example: In the current frame, the positive polarity data voltage Data+ is detected by the rising edge transition detection subunit Y1, which converts the rising time into positive polarity duration data RVC and outputs it to buffer 21. In the next frame, the negative polarity data voltage Data- is detected by the falling edge transition detection subunit Y2, which converts the falling time into negative polarity duration data FVC and inputs it to buffer 21. Then, using the negative polarity duration data FVC and the positive polarity duration data RVC in buffer 21, the positive polarity adjustment data VCP and the negative polarity adjustment data VCN are determined. Adjustments are then made based on the positive polarity adjustment data VCP and the negative polarity adjustment data VCN to make the positive polarity transition duration equal to the negative polarity transition duration, thereby improving the display effect of the display panel.

[0040] Furthermore, in some other feasible embodiments, reference is made to... Figure 4 , Figure 4 This is a circuit connection diagram of a falling edge transition detection subunit Y2 in the data voltage control circuit of this application. The falling edge transition detection subunit Y2 includes: A falling edge trigger 41 is provided, with its first terminal connected to the second terminal of a corresponding thin-film transistor. For example, the connection between the first terminal of the falling edge trigger 41 and the second terminal of the corresponding thin-film transistor means that when the falling edge trigger 41 detects the transition duration of the negative data voltage Data-, the first terminal of the falling edge trigger 41 is connected to the second terminal of the first thin-film transistor T1, and when the falling edge trigger 41 detects the transition duration of the positive data voltage Data+, the first terminal of the falling edge trigger 41 is connected to the second terminal of the second thin-film transistor T2.

[0041] The first comparator 42 (which can be a common comparator, such as using an operational amplifier for comparison) has its first input terminal connected to the first terminal of the falling edge flip-flop 41, its second input terminal connected to the first voltage source V1, and its output terminal connected to the second terminal of the falling edge flip-flop 41. The third thin-film transistor T3 has its first terminal connected to the current source IS, its third terminal connected to the third terminal of the falling edge trigger 41, and its second terminal connected to the first terminal of the polarity duration comparison module 20. The first capacitor C1 has its first terminal connected to the first terminal of the polarity duration comparison module 20, and its second terminal grounded.

[0042] Furthermore, when the first terminal of the falling edge trigger 41 receives a falling edge, the third terminal of the falling edge trigger 41 outputs a first level, and when the second terminal of the falling edge trigger 41 receives the first level, the third terminal of the falling edge trigger 41 outputs a second level, wherein the first level and the second level are high level and low level, respectively.

[0043] In this embodiment, the falling edge transition detection subunit Y2 is mainly used to detect the duration of the falling edge transition, for example, by directly using a timer to detect the duration of the transition from a high level to a low level. Alternatively, a circuit can be used to replace this time with a voltage value. For example, the falling edge transition detection subunit Y2 includes a falling edge trigger 41, a first comparator 42, a third thin-film transistor T3, and a first capacitor C1. Taking the transition duration detection of the negative polarity data voltage Data- as an example, at the instant the falling edge of the negative polarity data voltage Data- begins, the falling edge trigger 41 detects the instant of the fall and triggers a high-level output to the third thin-film transistor T3, turning on the third thin-film transistor T3, and the current source IS charges the first capacitor C1. When the voltage of the negative polarity data voltage Data- after its drop is equal to the first voltage source V1 input to the first comparator 42, the first comparator 42 outputs a high level to the falling edge trigger 41. The falling edge trigger 41 outputs a low level to the third thin-film transistor T3, which is then turned off. At this time, the first capacitor C1 stops charging, and the final negative polarity duration data FVC is output to the polarity duration comparison module 20. For example, the first voltage source V1 can be 90% of the target voltage. For example, if 5V drops to 0V, the first voltage source V1 can be set to 0.5V. In this case, the first comparator 42 is set to output a low level when the voltage value at the first input terminal of the first comparator 42 is greater than the voltage value at the second input terminal of the first comparator 42, and output a high level when the voltage value at the first input terminal of the first comparator 42 is less than or equal to the voltage value at the second input terminal of the first comparator 42. This allows the transition duration of the negative polarity data voltage Data- to be converted into a voltage value for subsequent direct processing.

[0044] For example, the falling edge trigger 41 can be a multi-signal controller. When the first terminal of the controller receives a falling edge, the third terminal of the falling edge trigger 41 outputs a first level, and when the second terminal of the falling edge trigger 41 receives the first level, the third terminal outputs a second level. The first and second levels are high and low, respectively. That is, the falling edge trigger 41 controls the final output level independently through two different signal inputs. For example, if the falling edge trigger 41 is triggered by a falling edge and outputs a high level, then only the signal at the second terminal of the falling edge trigger 41 needs to be detected for control. Thus, when the second terminal of the falling edge trigger 41 receives a high level, it will output a low level. Alternatively, a logic control chip can be used to implement this. The control logic of this chip is such that one port is set to output a high level when triggered by a falling edge, and the other port outputs a low level when connected to a high level. The correspondence between the output and input signals can be adaptively set according to the actual situation and is not limited here.

[0045] Furthermore, in some other feasible embodiments, reference is made to... Figure 5 , Figure 5 This is a circuit connection diagram of the rising edge transition detection subunit Y1 in the data voltage control circuit of this application. The rising edge transition detection subunit Y1 includes: Rising edge trigger 43, the first terminal of rising edge trigger 43 is connected to the second terminal of the corresponding thin film transistor; The second comparator 44 has its first input terminal connected to the first terminal of the rising edge flip-flop 43, its second input terminal connected to the second voltage source V2, and its output terminal connected to the second terminal of the rising edge flip-flop 43. The fourth thin-film transistor T4 has its first terminal connected to the current source IS, its third terminal connected to the third terminal of the rising edge trigger 43, and its second terminal connected to the first terminal of the polarity duration comparison module 20. The second capacitor C2 has its first terminal connected to the first terminal of the polarity duration comparison module 20, and its second terminal grounded.

[0046] Furthermore, when the first terminal of the rising edge trigger 43 receives a rising edge, the third terminal of the rising edge trigger 43 outputs a first level, and when the second terminal of the rising edge trigger 43 receives the first level, the third terminal of the rising edge trigger 43 outputs a second level, wherein the first level and the second level are high level and low level, respectively.

[0047] In this embodiment, the rising edge transition detection subunit Y1 is mainly used to detect the duration of the rising edge transition, for example, by directly using a timer to detect the duration of the transition from a low level to a high level. Alternatively, a circuit can be used to replace this time with a voltage value. For example, the rising edge transition detection subunit Y1 includes a rising edge trigger 43, a second comparator 44, a fourth thin-film transistor T4, and a second capacitor C2. Taking the transition duration detection of the positive data voltage Data+ as an example, at the instant the rising edge of the positive data voltage Data+ begins, the rising edge trigger 43 detects the instant of the rise and triggers a high-level output to the fourth thin-film transistor T4, turning on the fourth thin-film transistor T4, and the current source IS charges the second capacitor C2. When the voltage of the positive polarity data voltage Data+ rises to the same level as the second voltage source V2 input to the second comparator 44, the second comparator 44 outputs a high level to the rising edge trigger 43. The rising edge trigger 43 outputs a low level to the fourth thin-film transistor T4, which then turns off. At this time, the charging of the second capacitor C2 stops, and the final positive polarity duration data RVC is output to the polarity duration comparison module 20. For example, the second voltage source V2 can be 90% of the target voltage. For instance, if the voltage drops from 0V to 5V, the second voltage source V2 can be set to 4.5V. In this case, the second comparator 44 is configured to output a high level when the voltage value at its first input is greater than the voltage value at its second input, and to output a low level when the voltage value at its first input is less than or equal to the voltage value at its second input. This allows the transition duration of the positive polarity data voltage Data+ to be converted into a voltage value for subsequent direct processing.

[0048] For example, the rising edge trigger 43 can be a multi-signal controller. When the first terminal of the controller receives a rising edge, the third terminal of the rising edge trigger 43 outputs a first level, and when the second terminal of the rising edge trigger 43 receives the first level, the third terminal outputs a second level. The first level and the second level are high and low, respectively. That is, the rising edge trigger 43 uses two different signal inputs to independently control the different final output levels. For example, if the rising edge trigger 43 is triggered by a rising edge and outputs a high level, then only the signal at the second terminal of the rising edge trigger 43 needs to be detected for control. Thus, when the second terminal of the rising edge trigger 43 receives a high level, it will output a low level. Of course, this can also be implemented using a logic control chip. The control logic of this logic control chip is such that one port is set to output a high level when triggered by a rising edge, and the other port outputs a low level when connected to a high level. The correspondence between the output and input signals can be adaptively set according to the actual situation and is not limited here.

[0049] It should be noted that, assuming the first transition detection unit 11 and the second transition detection unit 12 simultaneously use a falling edge transition detection subunit Y2 and a rising edge transition detection subunit Y1, then adaptive selection of the second voltage source V2 and the first voltage source V1 is required. For example, different second voltage sources V2 and V1 can be selected based on the polarity control signal POL. That is, the second voltage source V2 and the first voltage source V1 are respectively the second voltage source V2 and the first voltage source V1 for detecting the transition duration of the positive polarity data voltage Data+, and the second voltage source V2 and the first voltage source V1 for detecting the transition duration of the negative polarity data voltage Data-. Then, a two-to-one device is used to connect the second voltage source V2 and the first voltage source V1 for detecting the transition duration of the positive polarity data voltage Data+ or the second voltage source V2 and the first voltage source V1 for detecting the transition duration of the negative polarity data voltage Data-. The control signal of this two-to-one device can be set to the polarity control signal POL.

[0050] Another point worth noting is that the input voltages of the two comparators can also be the low-level voltage values ​​in the positive voltage waveform and the high-level voltage values ​​in the negative voltage waveform. For example, if the positive voltage waveform is +E and 0, and the negative voltage waveform is -F and -E, where E is greater than F, then the input voltages of the two comparators are 0 and -F, respectively. In this case, the transition edge detection subunits on the output side of T1 and T2 can be shared. For example, when the positive polarity changes to negative polarity, the start time is the start time of the falling edge, and the end time is when it falls to -F. However, if the transition edge detection subunit detects a rising edge after the negative voltage, then the actual duration of the positive polarity change to negative polarity should be the start time of the falling edge minus the detection of -F, plus the time from -F to -E. This ensures the accuracy of the overall time detection. The time from -F to -E can be directly compensated based on the result of "the transition edge detection subunit detecting a rising edge" and used as the latest duration data of the positive polarity change to negative polarity, ensuring the accuracy of subsequent adjustments.

[0051] Furthermore, in some other feasible embodiments, the polarity duration comparison module 20 includes: Buffer 21, the first end of which is connected to the second end of the first transition detection unit 11 and the second end of the second transition detection unit 12; Subtractor 22, the first input terminal of subtractor 22 is connected to the second terminal of buffer 21, the second input terminal of subtractor 22 is connected to the third terminal of buffer 21, wherein the second terminal of buffer 21 is used to output the positive polarity duration data RVC of the first transition detection unit 11, and the third terminal of buffer 21 is used to output the negative polarity duration data FVC of the second transition detection unit 12; Error amplifier 23 has its first terminal connected to the output terminal of subtractor 22, and its second and third terminals connected to the first terminal of data voltage adjustment module 30. Error amplifier 23 is used to determine the negative polarity adjustment data VCN and the positive polarity adjustment data VCP output from the second terminal of error amplifier 23 based on the phase difference duration data VC determined by subtractor 22. The phase difference duration data VC includes the difference between the negative polarity duration data FVC and the positive polarity duration data RVC.

[0052] In this embodiment, refer to Figure 3 After receiving the positive polarity duration data RVC and the negative polarity duration data FVC, the buffer 21 inputs the positive polarity duration data RVC and the negative polarity duration data FVC to the subtractor 22, thereby determining that the output of the subtractor 22 is the phase difference duration data VC, which includes the difference between the negative polarity duration data FVC and the positive polarity duration data RVC. For example, the buffer 21 can be a single voltage buffer, outputting two non-synchronized positive polarity duration data RVC and negative polarity duration data FVC to the subtractor 22. Alternatively, the buffer 21 can be a combination of a controller and a voltage source, determining the negative polarity duration data FVC and the positive polarity duration data RVC, and then controlling the voltage source to output the negative polarity duration data FVC and the positive polarity duration data RVC to the subtractor 22. Other processing methods are also possible, which will not be described in detail here. Ultimately, because the phase difference duration data VC is relatively small, it can be input into error amplifier 23 to amplify it. This allows for the output of positive polarity adjustment data VCP and negative polarity adjustment data VCN based on the phase difference duration data VC. Finally, the transition duration between positive and negative polarities is adjusted based on the positive and negative polarity adjustment data VCP and VCN to make the positive polarity transition duration equal to the negative polarity transition duration, thereby improving the display effect of the display panel.

[0053] For example, the positive polarity adjustment data VCP and negative polarity adjustment data VCN can be determined using preset rules based on the phase difference duration data VC. For instance, if the phase difference duration data VC is G (the positive polarity duration data RVC is larger than the negative polarity duration data FVC), then the positive polarity adjustment data VCP can be set to -G / 2 and the negative polarity adjustment data VCN can be set to G / 2. Of course, the positive polarity adjustment data VCP can also be set to -G, and the negative polarity adjustment data VCN can also be set to G, as long as the adjusted positive polarity transition duration is equal to the negative polarity transition duration.

[0054] Furthermore, in some other feasible embodiments, the data voltage adjustment module 30 includes a negative polarity adjustment unit and a positive polarity adjustment unit. The first terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are respectively connected to the second terminals and the third terminals of the error amplifier 23. The second terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage terminal of the display panel. The third terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage. Both the negative polarity adjustment unit and the positive polarity adjustment unit include: A polarity adjuster (which can be a common BUFFER module) is used. The first end of the polarity adjuster is connected to the data voltage, and the second end of the polarity adjuster is connected to the data voltage terminal of the display panel. Transistor Q, the first terminal of transistor Q is connected to power supply VCC, and the third terminal of transistor Q is connected to the second terminal of error amplifier 23 or the third terminal of error amplifier 23. The grounding resistor R is connected to the second terminal of the transistor Q, and then to the switching time adjustment terminal of the polarity regulator. The second terminal of the grounding resistor R is grounded.

[0055] In this embodiment, the data voltage adjustment module 30 includes a negative polarity adjustment unit and a positive polarity adjustment unit. The first terminals of the negative and positive polarity adjustment units are respectively connected to the second and third terminals of the error amplifier 23. The second terminals of the negative and positive polarity adjustment units are connected to the data voltage terminal of the display panel. The third terminals of the negative and positive polarity adjustment units are connected to the data voltage Data1. The negative and positive polarity adjustment units can change the internal pull-up and pull-down bias current I according to the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, thereby changing the driving capability of the data voltage Data1 output signal to change the duration of its voltage transition, ultimately making the transition duration of its rising and falling edges consistent. For example, refer to... Figure 6 , Figure 6 This is a circuit connection diagram of the negative polarity adjustment unit in the data voltage control circuit of this application. The input of the negative polarity adjustment unit is the negative polarity data voltage Data-, and the output is the negative polarity data voltage portion of the adjusted data voltage Data2. Further details can be found in... Figure 7 , Figure 7This is a circuit connection diagram of the positive polarity adjustment unit in the data voltage control circuit of this application. The input of the positive polarity adjustment unit is the positive polarity data voltage Data+, and the output is the positive polarity data voltage part of the adjusted data voltage Data2. Finally, the two together can form the adjusted data voltage Data2. It is worth noting that, taking positive polarity as an example, the first pull voltage AVDD and the second pull voltage HAVDD are the voltages of the positive polarity regulator OP+. Taking negative polarity as an example, ground and the second pull voltage HVADD are the voltages of the negative polarity regulator OP-. The entire driving process can be a common driving process and is not limited here.

[0056] For example, both the negative polarity adjustment unit and the positive polarity adjustment unit include a bias current processing circuit. The main function of the bias current processing circuit is to adjust the bias current I based on the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, as shown in the reference. Figure 8 , Figure 8This is an equivalent schematic diagram of bias current control in the data voltage control circuit of this application. The positive polarity adjustment data VCP and the negative polarity adjustment data VCN are controlled in the linear region by controlling the transistor Q. This allows the on-resistance of the transistor Q to be different under different voltages of the positive polarity adjustment data VCP and the negative polarity adjustment data VCN, thereby controlling the bias current I. Based on the different bias currents I, the driving capability of the data voltage Data1 output signal is changed, so as to change the duration of its voltage transition. For example, under the same bias current I, the positive polarity transition time can be controlled to be equal to the negative polarity transition time. Of course, it is also possible to control the positive polarity transition time to be equal to the negative polarity transition time under different bias currents I. For example, the positive polarity transition time is t1 under bias current S1 and the positive polarity transition time is t1 under bias current S2. That is, the positive polarity transition time is equal to the negative polarity transition time. Then, the positive polarity adjustment data VCP and the negative polarity adjustment data VCN can be adjusted based on the relationship between bias current S1 and bias current S2. At this time, the principle of the bias current processing circuit is that the larger the input positive polarity adjustment data VCP and negative polarity adjustment data VCN, the smaller the bias current I. Of course, at this time, only one of the positive polarity adjustment data VCP and negative polarity adjustment data VCN can be determined, and the other can be directly set to 0. Thus, only the one duration that needs to be compensated is compensated. Of course, other logic can also be used, which will not be explained one by one. For example, the bias current still needs to be considered. The first sum of the bias current S11 of the positive polarity adjustment data VCP and the bias current S12 of the device itself under positive polarity needs to satisfy the relationship between bias current S1 and bias current S2, along with the second sum of the bias current S21 of the negative polarity adjustment data VCN and the bias current S22 of the device itself under negative polarity. This ensures that the positive polarity transition time equals the negative polarity transition time. In the most extreme case, the relationship between bias current S1 and bias current S2 is 1:1, in which case the first and second sums must be equal. Of course, other control methods can also be used, such as other parameters that can change the driving capability to adjust the transition time, or directly using related algorithms or hardware to adjust the transition time. This is not limited here.

[0057] It is worth noting that all the hardware components in the above embodiments of this application can be implemented using related software programs, as long as the software programs are designed to satisfy the above control logic. Of course, the hardware components in the above embodiments can also be equivalently replaced by devices with the same or similar control logic.

[0058] In summary, to optimize the design of the data voltage control circuit and improve screen crosstalk, this application provides a data voltage control circuit. This data voltage control circuit determines the duration adjustment data of positive and negative polarities through a polarity duration determination module and a polarity duration comparison module. Then, after adjusting the duration using the positive and negative polarity duration adjustment data through the data voltage adjustment module, the positive polarity transition duration is made equal to the negative polarity transition duration. This improves the screen crosstalk phenomenon caused by the inconsistency between the positive and negative polarity transition durations by adjusting the positive and negative polarity transition durations. Specifically, the polarity duration determination module has a polarity control signal connected to its first terminal and a data voltage connected to its second terminal. Under the control of the polarity control signal, the polarity duration determination module can determine the positive and negative polarity duration data of the data voltage, meaning it can adjust based on real-time positive and negative polarity durations instead of using fixed adjustment values. Next, the first terminal of the polarity duration comparison module is connected to the third terminal of the polarity duration determination module. This module can determine the positive and negative polarity adjustment data based on the positive and negative polarity duration data, respectively, thus determining the data that needs adjustment between positive and negative polarities. Finally, the positive and negative polarity adjustment data can be transmitted back to the data voltage. The voltage adjustment module can adjust the positive polarity transition time of the data voltage based on the positive polarity adjustment data, and adjust the negative polarity transition time of the data voltage based on the negative polarity adjustment data, so as to achieve a result where the positive polarity transition time equals the negative polarity transition time. This result is then output to the data voltage terminal of the display panel, thereby improving the screen crosstalk phenomenon caused by the inconsistency between the positive and negative polarity transition times. Compared with traditional data voltage control methods, the real-time processing and adjustment method can avoid the phenomenon that it cannot be applied to scenarios where the amount of coupled charge changes due to changes in process, voltage magnitude, temperature, etc., thereby effectively improving the display quality of the display panel applied to this data voltage control circuit by improving the screen crosstalk phenomenon.

[0059] Furthermore, based on the above embodiments of the data voltage control circuit, an embodiment of the data voltage control method of this application is proposed. The data voltage control method is applied to the above-mentioned data voltage control circuit, and the data voltage control method includes: Step S10: Under the control of the polarity control signal, the positive polarity duration data and negative polarity duration data of the data voltage are determined based on the polarity duration determination module, and the positive polarity adjustment data and negative polarity adjustment data are determined respectively in the polarity duration comparison module based on the positive polarity duration data and negative polarity duration data. Step S20: Based on the positive polarity adjustment data, the positive polarity transition duration of the data voltage is adjusted in the data voltage adjustment module, and based on the negative polarity adjustment data, the negative polarity transition duration of the data voltage is adjusted in the data voltage adjustment module, so that the positive polarity transition duration is equal to the negative polarity transition duration.

[0060] In this embodiment, when polarity reversal is required, it can be determined based on the polarity control signal (i.e., the polarity control signal is actually a flag signal for polarity reversal). Then, based on the polarity control signal, the corresponding part in the polarity duration determination module is controlled to work, thereby enabling the acquisition of positive and negative polarity duration data in the data voltage. The positive and negative polarity duration data are the voltages when the polarity changes from positive to negative and vice versa, respectively. The corresponding positive and negative polarity adjustment data can be determined in the polarity duration comparison module based on the positive and negative polarity duration data. Assuming the AV voltage corresponds to the duration of A1S, the difference between the positive and negative polarity duration data can be directly determined. Based on this difference, the positive and negative polarity adjustment data can be adaptively matched. That is, the difference between the matched positive and negative polarity adjustment data is the inverse of the difference between the positive and negative polarity duration data. Therefore, the positive polarity transition duration of the data voltage can be adjusted based on the positive polarity adjustment data, and the negative polarity transition duration of the data voltage in the data voltage adjustment module can be adjusted based on the negative polarity adjustment data, thus achieving a balance between the positive and negative polarity transition durations. For example, the adjustment method could involve driving various polarity adjustment units based on different voltage values, and then adjusting the durations based on these units to improve screen crosstalk by ensuring consistency between the positive and negative polarity durations.

[0061] In one embodiment, the step of determining positive polarity adjustment data and negative polarity adjustment data respectively in the polarity duration comparison module based on positive polarity duration data and negative polarity duration data includes: Based on the positive and negative polarity duration data, the phase difference duration data is determined in the polarity duration comparison module, and the positive and negative polarity adjustment data are determined based on the phase difference duration data respectively.

[0062] In this embodiment, after determining the positive and negative polarity duration data, the difference in duration data is determined in the polarity duration comparison module. Based on this difference in duration data, the positive and negative polarity adjustment data can then be determined. For example, if the difference between the positive and negative polarity duration data is 5 (meaning 5 represents 5 time units), the positive polarity adjustment data can be directly set to -5, and the negative polarity adjustment data to 0. Other settings are also possible; the core principle is that adjusting the negative and positive polarity data voltages in the data voltages will result in the positive polarity transition duration equal to the negative polarity transition duration.

[0063] Furthermore, after the polarity duration determination module determines the positive and negative polarity duration data of the data voltage, it includes: Determine the phase difference between the positive and negative duration data within a preset time frame; When the difference in duration data exceeds a preset adjustment threshold, positive and negative adjustment data are determined based on the difference in duration data. If the difference in duration data is less than or equal to the preset adjustment threshold, then after the preset time frame ends, positive and negative polarity adjustment data are determined based on the difference in duration data.

[0064] For example, since polarity switching typically involves multiple switching events within a very short time, to avoid the problem of devices failing to react promptly or repeatedly adjusting in both directions, a preset time frame can be introduced. This allows the entire adjustment period to be adjusted within the length of a single time frame. For instance, the time frame could be the length of a normal A-frame, and not adjusting within the A-frame duration would not significantly affect the display. Furthermore, by determining the sum of the difference in duration between the positive and negative polarity duration data within the preset time frame—that is, by adding the values ​​of each positive and negative polarity duration data—the sum of the difference in duration within the entire time frame is obtained. For example, if the differences within the A-frame are 10, -5, and -6, the final determined sum of the difference in duration should be -1. After the preset time frame ends, adjustments can be made based on this final determined sum of the difference in duration, using it as the difference in duration data in the above embodiment. This transforms the situation requiring adjustments to three or at least three data signals into a situation requiring only one adjustment, thereby significantly reducing the complexity and frequency of adjustments. In another embodiment, if the differences within frame A are 8, 7, and 6, the final determined sum of the phase difference duration data should be 29. However, the difference is determined to have accumulated to 21 in the first two frames. Assuming that a display device will experience a significant display problem when the difference between the positive and negative polarity duration data is 15, a preset adjustment threshold can be set in the range of approximately 15. If it is found that the accumulated value within the preset time frame has reached or is about to reach the range of approximately 15, the positive and negative polarity adjustment data can be determined directly based on the sum of the phase difference duration data. That is, after flipping the positive and negative polarities in the second frame within frame A, adjustments are made based on the sum of the phase difference duration data to avoid display problems caused by the sum of the entire phase difference duration data exceeding the preset adjustment threshold.

[0065] It is worth noting that real-time differences can also be accumulated directly. Then, within a certain range before the accumulated difference reaches the preset adjustment threshold, a process is executed to determine the positive and negative polarity adjustment data based on the accumulated difference. The reason for setting the entire value within a certain range before the preset adjustment threshold is that it is unclear whether it needs to be accumulated or decreased in the next step. To avoid the problem of exceeding the preset adjustment threshold directly after accumulation, this setting can be used.

[0066] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the data voltage control circuit described in any of the above claims.

[0067] In addition, this application also provides a display device. Please refer to... Figure 9 , Figure 9This is a schematic diagram of the display device involved in the embodiments of this application. Specifically, the display device in the embodiments of this application may be a device that uses a locally running data voltage control method.

[0068] like Figure 9 As shown, the display device in this embodiment may include: the data voltage control circuit described above; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0069] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0070] Those skilled in the art will understand that Figure 9 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0071] like Figure 9 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a data voltage control program.

[0072] exist Figure 9 In the display device shown, the processor 1001 can be used to call the data voltage control program stored in the memory 1005 and execute the steps of the data voltage control method as described above.

[0073] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0074] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0075] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0076] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A data voltage control circuit, characterized in that, The data voltage control circuit includes: A polarity duration determination module, wherein a first terminal of the polarity duration determination module is connected to a polarity control signal, and a second terminal of the polarity duration determination module is connected to a data voltage, and the polarity duration determination module is used to determine the positive polarity duration data and the negative polarity duration data of the data voltage under the control of the polarity control signal; A polarity duration comparison module, wherein the first end of the polarity duration comparison module is connected to the third end of the polarity duration determination module, and the polarity duration comparison module is used to determine positive polarity adjustment data and negative polarity adjustment data based on the positive polarity duration data and the negative polarity duration data, respectively; A data voltage adjustment module is provided, wherein a first terminal of the data voltage adjustment module is connected to a second terminal of the polarity duration comparison module, the second terminal of the data voltage adjustment module is connected to the data voltage, and a third terminal of the data voltage adjustment module is connected to the data voltage terminal of the display panel. The data voltage adjustment module is used to adjust the positive polarity transition duration of the data voltage based on the positive polarity adjustment data, and to adjust the negative polarity transition duration of the data voltage based on the negative polarity adjustment data, so that the positive polarity transition duration is equal to the negative polarity transition duration.

2. The data voltage control circuit as described in claim 1, characterized in that, The polarity duration determination module includes: A first thin-film transistor, wherein a first terminal of the first thin-film transistor is connected to the data voltage, and a third terminal of the first thin-film transistor is connected to the polarity control signal; A first transition detection unit, wherein a first end of the first transition detection unit is connected to a second end of the first thin-film transistor, and a second end of the first transition detection unit is connected to a first end of the polarity duration comparison module; A second thin-film transistor, wherein the first terminal of the second thin-film transistor is connected to the data voltage, and the third terminal of the second thin-film transistor is connected to the polarity control signal; The second transition detection unit has a first end connected to the second end of the second thin-film transistor, and the second end of the second transition detection unit is connected to the first end of the polarity duration comparison module.

3. The data voltage control circuit as described in claim 2, characterized in that, Both the first transition detection unit and the second transition detection unit include a falling edge transition detection subunit and a rising edge transition detection subunit. The first end of the falling edge transition detection subunit is connected to the first end of the rising edge transition detection subunit and then connected to the second end of the corresponding thin film transistor. The second end of the falling edge transition detection subunit is connected to the second end of the rising edge transition detection subunit and then connected to the first end of the polarity duration comparison module.

4. The data voltage control circuit as described in claim 3, characterized in that, The falling edge transition detection subunit includes: A falling-edge trigger, wherein the first terminal of the falling-edge trigger is connected to the second terminal of the corresponding thin-film transistor; A first comparator, wherein the first input terminal of the first comparator is connected to the first terminal of the falling edge trigger, the second input terminal of the first comparator is connected to a first voltage source, and the output terminal of the first comparator is connected to the second terminal of the falling edge trigger; The third thin-film transistor has a first terminal connected to a current source, a third terminal connected to the third terminal of the falling edge trigger, and a second terminal connected to the first terminal of the polarity duration comparison module. A first capacitor, the first end of which is connected to the first end of the polarity duration comparison module, and the second end of which is grounded.

5. The data voltage control circuit as described in claim 4, characterized in that, When a falling edge is received at the first terminal of the falling edge trigger, the third terminal of the falling edge trigger outputs a first level. When the first level is received at the second terminal of the falling edge trigger, the third terminal of the falling edge trigger outputs a second level, wherein the first level and the second level are high level and low level, respectively.

6. The data voltage control circuit as described in claim 3, characterized in that, The rising edge transition detection subunit includes: A rising edge trigger, wherein the first terminal of the rising edge trigger is connected to the second terminal of the corresponding thin-film transistor; The second comparator has its first input terminal connected to the first terminal of the rising edge flip-flop, its second input terminal connected to a second voltage source, and its output terminal connected to the second terminal of the rising edge flip-flop. A fourth thin-film transistor, wherein the first terminal of the fourth thin-film transistor is connected to a current source, the third terminal of the fourth thin-film transistor is connected to the third terminal of the rising edge trigger, and the second terminal of the fourth thin-film transistor is connected to the first terminal of the polarity duration comparison module. The second capacitor has its first terminal connected to the first terminal of the polarity duration comparison module, and its second terminal grounded.

7. The data voltage control circuit as described in claim 6, characterized in that, When a rising edge is received at the first terminal of the rising edge trigger, the third terminal of the rising edge trigger outputs a first level. When the first level is received at the second terminal of the rising edge trigger, the third terminal of the rising edge trigger outputs a second level. The first level and the second level are high level and low level, respectively.

8. The data voltage control circuit as described in claim 2, characterized in that, The polarity duration comparison module includes: A buffer, wherein a first end of the buffer is connected to a second end of the first transition detection unit and a second end of the second transition detection unit; A subtractor, wherein the first input terminal of the subtractor is connected to the second terminal of the buffer, and the second input terminal of the subtractor is connected to the third terminal of the buffer, wherein the second terminal of the buffer is used to output the positive polarity duration data of the first transition detection unit, and the third terminal of the buffer is used to output the negative polarity duration data of the second transition detection unit; An error amplifier is provided, with its first terminal connected to the output terminal of the subtractor, and its second and third terminals connected to the first terminal of the data voltage adjustment module. The error amplifier is used to determine the negative polarity adjustment data and the positive polarity adjustment data based on the phase difference duration data determined by the subtractor, wherein the phase difference duration data includes the difference between the negative polarity duration data and the positive polarity duration data.

9. The data voltage control circuit as described in claim 8, characterized in that, The data voltage adjustment module includes a negative polarity adjustment unit and a positive polarity adjustment unit. The first terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are respectively connected to the second and third terminals of the error amplifier. The second terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage terminal of the display panel. The third terminals of the negative polarity adjustment unit and the positive polarity adjustment unit are connected to the data voltage. Both the negative polarity adjustment unit and the positive polarity adjustment unit include: A polarity adjuster, wherein the first end of the polarity adjuster is connected to the data voltage, and the second end of the polarity adjuster is connected to the data voltage terminal of the display panel; A transistor, wherein the first terminal of the transistor is connected to a power supply, and the third terminal of the transistor is connected to the second terminal of the error amplifier or the third terminal of the error amplifier. A grounding resistor, the first end of which is connected to the second end of the transistor and then connected to the switching time adjustment terminal of the polarity regulator, and the second end of the grounding resistor is grounded.

10. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a data voltage control circuit as described in any one of claims 1 to 9.

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