Silicon carbide multilevel conversion control method and system based on embedded micro-channel heat dissipation

Abstract

This invention relates to the field of semiconductor heat dissipation control technology, specifically a silicon carbide multilevel converter control method and system based on embedded microchannel heat dissipation. The method includes: calculating the thermal wake coupling potential index of each SiC power transistor under the current power level based on an embedded flow path thermal wake coupling risk assessment strategy; dynamically evaluating the local thermal boundaries of all power modules in the multilevel system based on the thermal wake coupling potential index to obtain a first set of thermally hazardous module modes; obtaining real-time fluctuation tracking data involving fluid transport characteristics to construct an electro-current coupling analysis model; outputting the heat dissipation uniformity of each power module based on this model; outputting the deviation ratio of module thermal aging; and performing carrier phase shift compensation control on the carrier scheduling sequence of the multilevel converter based on the deviation ratio. This invention solves the problem in the prior art of being unable to perceive the physical delay of the thermal pulse generated by the upstream switching transistor propagating in the microchannel.

Description

Technical Field

[0001] This invention relates to the field of semiconductor heat dissipation control technology, and is a silicon carbide multilevel conversion control method and system based on embedded microchannel heat dissipation. Background Technology

[0002] As the requirements for power density and reliability continue to rise in applications such as high-power-density inverters and high-voltage vehicle main drives, silicon carbide multilevel converters have become the mainstream technology due to their advantages of high voltage resistance, low loss and high frequency. However, the area of ​​silicon carbide chips is only one-fifth to one-tenth of that of silicon devices with equivalent power, resulting in a discontinuous increase in local power consumption density. To achieve efficient heat dissipation, an embedded microchannel structure is introduced, allowing the coolant to flow directly through the micron-level channels at the bottom of the chip. Unlike the thermal inertia of external heat sinks, this tightly coupled structure almost unfilters the rapid and high-frequency switching loss pulses of silicon carbide devices to the coolant. In a multilevel topology, the switching transistors corresponding to different levels are physically distributed at different positions in a serial or parallel microchannel. The transient thermal pulses generated by the upstream switching transistors will propagate downstream via the coolant as a thermal tail, interfering with the intrinsic heat dissipation conditions of the downstream power transistors. Furthermore, when the multilevel converter uses high-frequency carrier superposition control, the extremely high-frequency switching pulses generated by the silicon carbide devices will induce extremely high-frequency microscopic phase transition cycles in the coolant near the microchannel wall, thereby forming periodic microbubbles. These bubbles migrate and accumulate in the flow channel, causing the downstream power transistors under high load conditions to face the risk of sudden local overheating or even damage due to the coolant being isolated by the gas film.

[0003] Traditional multilevel control methods typically rely on steady-state temperature feedback or simple derating protection, making it difficult for existing technologies to simultaneously guarantee the heat dissipation performance and long-term operational reliability of silicon carbide multilevel converters under high-frequency, high-power-density operating conditions. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] The technical problem to be solved by the present invention is that, in the prior art, the physical delay of the thermal pulse generated by the upstream switching transistor propagating in the microchannel cannot be detected. The present invention proposes a silicon carbide multilevel conversion control method and system based on embedded microchannel heat dissipation.

[0006] To achieve the above objectives, the technical solution of the silicon carbide multilevel conversion control method based on embedded microchannel heat dissipation of the present invention includes the following steps:

[0007] S1: Real-time extraction of real-time loss and power consumption data of SiC power modules in each phase bridge arm of the multilevel converter, pressure gradient at the microchannel inlet, and flow behavior status data;

[0008] S2: Import the data into the embedded flow path thermal wake coupling risk assessment strategy, and calculate the thermal wake coupling potential index of each SiC power transistor under the current level condition.

[0009] S3: Based on the thermal wake coupling potential index, perform local thermal boundary dynamic evaluation on all power modules in the multilevel system to obtain the first thermally hazardous module mode set, and dynamically adjust the thermal risk warning baseline of the corresponding bridge arm.

[0010] S4: Perform thermal pulse propagation path tracking on the flow channels associated with all power transistors in the first thermal hazard module mode set to obtain real-time fluctuation tracking data involving fluid transport characteristics;

[0011] S5: Construct an electro-current coupling analysis model, import the thermal wake coupling potential index and the real-time fluctuation tracking data into the model, and output the heat dissipation balance of each power module;

[0012] S6: Import the heat dissipation uniformity into the junction temperature gradient lifetime fluctuation analysis model, output the deviation ratio of module thermal aging, and perform carrier phase shift compensation control on the carrier scheduling sequence of the multilevel converter according to the deviation ratio.

[0013] Preferably, in S2, the embedded flow path thermal wake coupling risk assessment strategy includes: a flow path crosstalk thermal effect assessment sub-strategy and a gate power consumption delay assessment sub-strategy;

[0014] The specific sub-strategy for evaluating the crosstalk thermal effect of the flow channel is as follows:

[0015] S21: Extract the coolant flow rate of each sub-channel within the embedded microchannel at the current sampling point, as well as the transient heat flux per unit area generated by the multi-level spatiotemporal arrangement, where the number of channel branches is... During the observation period, the total number of heat sources for SiC power transistors within the same subchannel is: , The subscript is the heat source index;

[0016] S22: with the first The power transistor is used as the evaluation center; the calculation is performed on the [number]th [transistor]. The path between each hot spot location and the coolant inlet is calculated simultaneously, along with the remaining coolant flow rate downstream of the same streamline. The axial flow path distances of each power tube from the center of the heat source constitute the set of downstream heat wake transfer distances. , , For set The total amount of data in the middle, For set index, For the first The axial flow path distance of each power transistor in the upstream thermal radiation field;

[0017] S23: Based on S21-S22, calculate and obtain the channel disturbance thermal factor, specifically: ;

[0018] in, Indicates the first The cumulative intensity of thermal wake generated by upstream level loss in each power transistor; For the first The average switching loss power of each upstream power transistor during the observation period; For upstream heat source to the first The axial flow path distance of each power transistor; The thermal conductivity of the coolant; For reference temperature difference; This represents the single-channel cross-sectional area of ​​the microchannel.

[0019] Preferably, the gate power consumption delay evaluation sub-strategy specifically includes:

[0020] S24: with the first Each power transistor serves as the physical evaluation center. Based on the topology logic of the multilevel converter circuit, the remaining... The high-frequency switching operation timestamp of the power unit and the first The time interval between power transistors;

[0021] S25: Set a critical thermal accumulation threshold for the SiC chip surface. Select transistors in the above power units whose transient junction temperature rise rate is greater than or equal to the preset critical threshold, and record their corresponding loss trigger sequence timestamps to form a set of loss pulse peak sequences. , , For set The total number of medium and high frequency thermal pulses For set index, For the first The peak power moment is generated by a single SiC switch;

[0022] S26: Based on S24-S25, calculate and obtain the gate behavior thermal accumulation factor, specifically: ;

[0023] in, The number of flow channel branches, Indicates the first Thermal response hysteresis stress of individual cells in multi-level switching sequences; For the first The center moment of the rising edge of the conduction of the individual switching transistor; The thermal diffusion time constant of the embedded microchannel wall material;

[0024] S27: Based on S21-S26, calculate the thermal wake coupling potential index. The specific formula is as follows: ;

[0025] in, For the first The thermal wake coupling potential index of each power transistor, with a value range of [value missing]. The larger the value, the more significant the thermal wake coupling effect is to the power transistor under the current operating conditions, and the higher the thermal risk. and Based on the local Reynolds number within the microchannel The dynamically set weight allocation coefficients satisfy... ;

[0026] Preferably, in S3, the dynamic evaluation of the local thermal boundary includes: obtaining the thermal wake coupling potential index of all power chips in the same heat dissipation branch under the current converter carrier phase shift period, arranging all potential indices in descending order, and taking the median value of the sequence as the real-time dynamic heat dissipation baseline. The set of power chips whose potential index exceeds the heat dissipation baseline is marked as the first thermal hazard module mode set, and a thermal risk warning signal is sent to the drive controller to dynamically increase the thermal risk monitoring sampling frequency of the bridge arm.

[0027] The total number of sets is , This is the index of the first thermal hazard module mode set.

[0028] Preferably, S4 includes the following specific steps:

[0029] S41: Perform microfluidic high-frequency sampling and tracking on each SiC unit to be evaluated and its connected embedded flow channel in the first thermal hazard module mode set, including: triggering a real-time flow control diagnostic sequence during the follow-through period of the multi-level conversion cycle.

[0030] S42: Extract real-time fluctuation tracking data. When the standard deviation of the propagation delay of the thermal wake at the downstream pressure measuring point exceeds the preset threshold value for 5 consecutive times, trigger the operation of the electric-current coupling analysis model and execute step S5. Otherwise, maintain the original monitoring frequency. The preset threshold value is set according to twice the standard deviation of the propagation delay under steady-state conditions.

[0031] Preferably, S5 includes the following specific steps:

[0032] S51: Construct an electro-current coupling analysis model to describe the dynamic relationship between carrier phase shift angle and fluid heat transfer hysteresis;

[0033] S52: Potential Index Importing fluctuation tracking data into the model to calculate heat dissipation uniformity The formula is: ;

[0034] in, For the first The heat dissipation uniformity of a high-heat-load chip, with a value range of [value range missing]. to A higher value indicates more balanced heat dissipation. The cross-channel fluid interference coefficient has a value ranging from 0.8 to 1.2. The subscript is the index of the sequence number of the interference signal. Indicates the first The high-frequency loss and power consumption value captured this time; This represents the average energy of the data collected from the aforementioned five thermal events; The fluid turbulence decay time constant; For the first The upstream thermal wake propagation delay corresponding to each wafer For the first The propagation delay corresponding to the secondary interference signal; For the first The cumulative intensity of thermal wake corresponding to each crystal cell; It is the average value of the thermal wake coupling potential index of all cells in the first thermal hazard module mode set.

[0035] Preferably, in S6, the junction temperature gradient lifetime fluctuation analysis model is as follows:

[0036] in, The ratio of fluctuation in heat dissipation uniformity; This represents the total number of thermal monitoring units over a given time period. This serves as an index for the unit time period of thermal monitoring. Indicates the first During the aging and decay monitoring period, the first The heat dissipation balance of each switching transistor; and These represent the maximum and minimum values ​​of heat dissipation uniformity for each level module in the entire system; The thermal convection time interval for each level arm of the converter based on the carrier phase difference is defined as the product of the phase difference of the switching action of adjacent level arms and the carrier period.

[0037] In S6, the carrier phase shift compensation control includes:

[0038] Maximum aging risk value of preset heat dissipation uniformity fluctuation ratio When the fluctuation rate of heat dissipation uniformity of any detected switching transistor is... Exceeding the maximum aging risk value At this point, the system returns to the underlying driver logic, re-extracts the original sequence signal from the driver instruction corresponding to that level, and performs carrier preprocessing on the sequence signal, including: filtering out electromagnetic noise interference from the power circuit, suppressing high-order harmonic components of the system, and dynamically extracting the effective current component using a fast Fourier transform algorithm, before connecting it to the embedded channel thermal wake co-controller; in this controller, the thermal seek time delay ratio is first calculated. ,in For the first The propagation delay of the upstream thermal wake of each power transistor. The average flow rate of the coolant within the microchannels. The time interval between the switching action of the upstream interference source transistor and the switching action of the power transistor;

[0039] Then according to Deviation from ideal value The degree of compensation is determined by dynamically calculating the carrier phase shift compensation angle using a proportional-integral controller. The details are as follows:

[0040] ;

[0041] in, This is the proportionality coefficient, and its value range is... to ; The integral coefficient has a range of values ​​of 1. to ; The reference time constant is set to the carrier period.

[0042] The compensation angle This is superimposed on the carrier phase corresponding to the power transistor, increasing the thermal seek time delay ratio. Approaching This achieves spatiotemporal decoupling between the thermal pulse peak and the high-loss operation of the downstream switching transistor, and is based on the compensated heat dissipation balance. The degree of improvement was repeatedly confirmed to verify whether the heat source of the device and the center of the thermal wake of the flow path had been decoupled.

[0043] In S6, the compensation control further includes:

[0044] When the heat dissipation uniformity fluctuation ratio Less than or equal to the maximum aging risk value When the system is confirmed to be in a stable operating state, the thermal fatigue thermogram distribution of each phase switch in the multi-level system is visualized in real time on the control terminal. Simultaneously, a corresponding three-dimensional image of the thermal stress density gradient is generated by combining the level position and the thermal wake coupling potential index, enabling hardware-level graded thermal early warning. The hardware-level graded thermal early warning is based on the heat dissipation uniformity... The risk level is divided into ranges of values, and the switching frequency or output power of the corresponding switching transistor is dynamically adjusted by the drive controller to reduce the derating operation.

[0045] In addition, the silicon carbide multilevel conversion control system based on embedded microchannel heat dissipation of the present invention includes the following modules:

[0046] The module includes a synchronous sampling module for thermal-electric parameters, a module for assessing the coupling potential of thermal wake, a module for dynamic thermal boundary delineation, a module for wave velocity matching and flow tracking, a module for electro-current coupling analysis, and a module for frequency modulation compensation.

[0047] Thermo-electric parameter synchronous sampling module is used to extract real-time loss and flow channel monitoring data of bridge arms at different levels;

[0048] The thermal wake coupling potential assessment module is used to quantitatively assess the interference risk of high-frequency switching pulses of SiC chips on downstream heat dissipation capabilities by calculating the channel perturbation thermal factor and the gate behavior thermal accumulation factor.

[0049] The thermal boundary dynamic division module establishes a dynamic screening baseline based on the thermal wake coupling potential distribution and divides high-risk heat-affected groups.

[0050] The wave velocity matching flow tracking module locates the downstream monitoring point of the microchannel where the high-heat-risk module is located based on its physical coordinates, and captures abnormal values ​​of propagation delay fluctuations caused by the thermal wake effect.

[0051] The electro-current coupling analysis module constructs an electro-current coupling analysis model and outputs the heat dissipation uniformity.

[0052] The frequency modulation compensation module calculates the PWM phase shift offset of each level transistor based on the lifetime fluctuation ratio and the thermal search delay ratio. It optimizes the thermal balance of the chip surface through dynamic phase shift, thereby completing the system thermal balance control.

[0053] Compared with the prior art, the technical effects of the present invention are as follows:

[0054] First, this invention constructs a thermal wake coupling potential index, integrating channel geometry parameters, coolant properties, upstream heat source power, and downstream switching timing into a unified risk assessment index. Furthermore, based on propagation delay fluctuations triggering electro-current coupling analysis, it achieves a quantitative assessment of the heat dissipation uniformity of each power transistor. Simultaneously, this invention ensures that the upstream thermal pulse reaches the downstream transistor precisely at its own high-loss operating moment, eliminating the risk of localized overheating caused by thermal peak superposition. This fully releases the heat dissipation potential of the embedded microchannel, maintaining a stable heat transfer mass ratio between the coolant and the chip surface even under the extreme conditions of high frequency and high power density in silicon carbide devices, effectively suppressing microbubble accumulation and liquid film breakage induced by thermal wake crosstalk. A deeper benefit of this invention lies in overcoming the problem of uneven device lifetime caused by the inherent topology of multilevel converters. Through continuous monitoring of heat dissipation uniformity and junction temperature gradient lifetime fluctuation analysis, this invention introduces the lifetime aging deviation ratio as a feedback quantity into carrier phase shift compensation, achieving dynamic rebalancing of thermal stress in power transistors at different locations. This enables the system to adaptively adjust the heat load distribution of each switch transistor, leveling out its lattice aging rate, thereby extending the overall lifespan of the multilevel converter. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0056] Figure 1 This is a flowchart illustrating the silicon carbide multilevel conversion control method based on embedded microchannel heat dissipation according to the present invention.

[0057] Figure 2 This is a schematic diagram of the silicon carbide multilevel conversion control system based on embedded microchannel heat dissipation of the present invention. Detailed Implementation

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0060] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0061] Example 1:

[0062] like Figure 1 As shown, the silicon carbide multilevel conversion control method based on embedded microchannel heat dissipation in this embodiment of the invention is as follows: Figure 1 As shown, the specific steps include the following:

[0063] S1: Connect the sensor group of the microchannel heat dissipation system and the multilevel drive control monitoring port to extract real-time loss and power consumption data of SiC power modules in each phase bridge arm of the multilevel converter, pressure gradient at the microchannel inlet, and flow behavior status data in real time.

[0064] S2: Import the data into the embedded flow path thermal wake coupling risk assessment strategy, and calculate the thermal wake coupling potential index of each SiC power transistor under the current level condition; wherein, the thermal wake refers to the coupling phenomenon in which the heat generated by the upstream power transistor is carried downstream by the coolant and affects the heat dissipation conditions of the downstream power transistor.

[0065] In S2, the embedded flow path thermal wake coupling risk assessment strategy includes: a flow path crosstalk thermal effect assessment sub-strategy and a gate power consumption delay assessment sub-strategy;

[0066] The specific sub-strategy for evaluating the crosstalk thermal effect of the flow channel is as follows:

[0067] S21: Extract the coolant flow rate of each sub-channel within the embedded microchannel at the current sampling point, as well as the transient heat flux per unit area generated by the multi-level spatiotemporal arrangement, where the number of channel branches is... During the observation period, the total number of heat sources for SiC power transistors within the same subchannel is: , The subscript is the heat source index;

[0068] S22: with the first The power transistor is used as the evaluation center; the calculation is performed on the [number]th [transistor]. The path between each hot spot location and the coolant inlet is calculated simultaneously, along with the remaining coolant flow rate downstream of the same streamline. The axial flow path distances of each power tube from the center of the heat source constitute the set of downstream heat wake transfer distances. , , For set The total amount of data in the middle, For set index, For the first The axial flow path distance of each power transistor in the upstream thermal radiation field;

[0069] S23: Based on S21-S22, calculate and obtain the channel disturbance thermal factor, specifically:

[0070] ;

[0071] in, Indicates the first The cumulative intensity of thermal wake generated by upstream level loss in each power transistor; For the first The average switching loss power of each upstream power transistor during the observation period; For upstream heat source to the first The axial flow path distance of each power transistor; Thermal conductivity of the coolant, in units of ; For reference temperature difference, the value is taken as follows: ; This represents the single-channel cross-sectional area of ​​the microchannel.

[0072] The gate power consumption delay evaluation sub-strategy specifically includes:

[0073] S24: with the first Each power transistor serves as the physical evaluation center. Based on the topology logic of the multilevel converter circuit, the remaining... The high-frequency switching operation timestamp of the power unit and the first The time interval between power transistors;

[0074] S25: Set a critical thermal accumulation threshold for the SiC chip surface. Select transistors in the above power units whose transient junction temperature rise rate is greater than or equal to the preset critical threshold, and record their corresponding loss trigger sequence timestamps to form a set of loss pulse peak sequences. , , For set The total number of medium and high frequency thermal pulses For set index, For the first The peak power moment is generated by a single SiC switch;

[0075] S26: Based on S24-S25, calculate and obtain the gate behavior thermal accumulation factor, specifically:

[0076] ;

[0077] in, The number of flow channel branches, Indicates the first Thermal response hysteresis stress of individual cells in multi-level switching sequences; For the first The center moment of the rising edge of the conduction of the individual switching transistor; The thermal diffusion time constant of the embedded microchannel wall material is given, with a value range of [value range missing]. to ;

[0078] S27: Based on S21-S26, calculate the thermal wake coupling potential index. The specific formula is as follows: ;

[0079] in, For the first The thermal wake coupling potential index of each power transistor, with a value range of [value missing]. The larger the value, the more significant the thermal wake coupling effect is to the power transistor under the current operating conditions, and the higher the thermal risk. and Based on the local Reynolds number within the microchannel The dynamically set weight allocation coefficients satisfy... ;

[0080] when hour, , ;when hour, , .

[0081] S3: Based on the thermal wake coupling potential index, perform local thermal boundary dynamic evaluation on all power modules in the multilevel system to obtain the first thermally hazardous module mode set, and dynamically adjust the thermal risk warning baseline of the corresponding bridge arm.

[0082] In S3, the dynamic assessment of the local thermal boundary includes: obtaining the thermal wake coupling potential index of all power chips in the same heat dissipation branch under the current converter carrier phase shift period, arranging all potential indices in descending order, and taking the median value of the sequence as the real-time dynamic heat dissipation baseline. The set of power chips whose potential index exceeds the heat dissipation baseline is designated as the first thermal hazard module mode set, and a thermal risk warning signal is sent to the drive controller to dynamically increase the thermal risk monitoring sampling frequency of this bridge arm; wherein, the total number of sets is , This is the index of the first thermal hazard module mode set.

[0083] S4: Perform thermal pulse propagation path tracking on the flow channels associated with all power transistors in the first thermal hazard module mode set to obtain real-time fluctuation tracking data involving fluid transport characteristics;

[0084] S4 includes the following specific steps:

[0085] S41: Perform microfluidic high-frequency sampling and tracking on each SiC unit to be evaluated and its connected embedded flow channel in the first thermal hazard module mode set, including: triggering a real-time flow control diagnostic sequence during the follow-through period of the multi-level conversion cycle.

[0086] S42: Extract real-time fluctuation tracking data. When the standard deviation of the propagation delay of the thermal wake at the downstream pressure measuring point exceeds the preset threshold value for 5 consecutive times, trigger the operation of the electric-current coupling analysis model and execute step S5. Otherwise, maintain the original monitoring frequency. The preset threshold value is set according to twice the standard deviation of the propagation delay under steady-state conditions.

[0087] Furthermore, the real-time fluctuation tracking data includes: thermal wake propagation delay, dynamic local viscosity, microchannel surface shear stress, wall temperature distribution parameters, and fluid Reynolds number. .

[0088] S5: Construct an electro-current coupling analysis model, import the thermal wake coupling potential index and the real-time fluctuation tracking data into the model, and output the heat dissipation balance of each power module;

[0089] S5 includes the following specific steps:

[0090] S51: Construct an electro-current coupling analysis model to describe the dynamic relationship between carrier phase shift angle and fluid heat transfer hysteresis;

[0091] S52: Potential Index Importing fluctuation tracking data into the model to calculate heat dissipation uniformity The formula is: ;

[0092] in, For the first The heat dissipation uniformity of a high-heat-load chip, with a value range of [value range missing]. to A higher value indicates more balanced heat dissipation. The cross-channel fluid interference coefficient has a value ranging from 0.8 to 1.2. The subscript is the index of the sequence number of the interference signal. Indicates the first The high-frequency loss and power consumption value captured this time; This represents the average energy of the data collected from the aforementioned five thermal events; The fluid turbulence decay time constant has a value range of 1. to ; For the first The upstream thermal wake propagation delay corresponding to each wafer For the first The propagation delay corresponding to the secondary interference signal; For the first The cumulative intensity of thermal wake corresponding to each crystal cell; It is the average value of the thermal wake coupling potential index of all cells in the first thermal hazard module mode set.

[0093] S6: Import the heat dissipation uniformity into the junction temperature gradient lifetime fluctuation analysis model, output the deviation ratio of module thermal aging, and perform carrier phase shift compensation control on the carrier scheduling sequence of the multilevel converter according to the deviation ratio.

[0094] In S6, the junction temperature gradient lifetime fluctuation analysis model is as follows: ;

[0095] in, The ratio of fluctuation in heat dissipation uniformity; This represents the total number of thermal monitoring units over a given time period. This serves as an index for thermal monitoring unit time periods. The duration of each thermal monitoring unit time period is an integer multiple of the carrier cycle, ranging from 10 to 100 carrier cycles. Indicates the first During the aging and decay monitoring period, the first The heat dissipation balance of each switching transistor;

[0096] and These represent the maximum and minimum values ​​of heat dissipation uniformity for each level module in the entire system; The thermal convection time interval for each level arm of the converter based on the carrier phase difference is defined as the product of the phase difference of the switching action of adjacent level arms and the carrier period.

[0097] In S6, the carrier phase shift compensation control includes:

[0098] Maximum aging risk value of preset heat dissipation uniformity fluctuation ratio When the fluctuation rate of heat dissipation uniformity of any detected switching transistor is... Exceeding the maximum aging risk value When the time comes, return to the underlying logic of the driver, re-extract the original sequence signal in the driver instruction corresponding to the level, and perform carrier preprocessing on the sequence signal, including: filtering out electromagnetic noise interference in the power circuit, suppressing high-order harmonic components of the system, dynamically extracting the effective current component through the fast Fourier algorithm, and connecting to the embedded channel thermal wake co-controller.

[0099] In this controller, the heat search time-delay ratio is first calculated. ,in For the first The propagation delay of the upstream thermal wake of each power transistor. The average flow rate of the coolant within the microchannels. The time interval between the switching action of the upstream interference source transistor and the switching action of the power transistor;

[0100] It should be noted that the heat search time-delay ratio mentioned in this article Defined as the ratio of the upstream thermal wake propagation delay to the downstream power transistor switching time interval, this value is used to quantify the timing coupling between the thermal pulse and switching losses. It should also be noted that, ideally, the peak value of the thermal pulse should be staggered from the switching time of the downstream power transistor; therefore, the control objective is to minimize the thermal wake-up delay. Deviating as far from 1.0 as possible; this embodiment uses a PI controller to control the deviation. Adjusting to a non-zero value aims to achieve timing decoupling.

[0101] Then according to Deviation from ideal value The degree of compensation is determined by dynamically calculating the carrier phase shift compensation angle using a proportional-integral controller. The details are as follows:

[0102] ;

[0103] in, This is the proportionality coefficient, and its value range is... to ; The integral coefficient has a range of values ​​of 1. to ; The reference time constant is set to the carrier period; the compensation angle is... This is superimposed on the carrier phase corresponding to the power transistor, increasing the thermal seek time delay ratio. Approaching This achieves spatiotemporal decoupling between the thermal pulse peak and the high-loss operation of the downstream switching transistor, and is based on the compensated heat dissipation balance. The degree of improvement was repeatedly confirmed to verify whether the heat source of the device and the center of the thermal wake of the flow path had been decoupled.

[0104] In S6, the compensation control further includes:

[0105] When the heat dissipation uniformity fluctuation ratio Less than or equal to the maximum aging risk value When the system is confirmed to be in a stable operating state, the thermal fatigue thermogram distribution of each phase switch in the multi-level system is visualized in real time on the control terminal. Simultaneously, a corresponding three-dimensional image of the thermal stress density gradient is generated by combining the level position and the thermal wake coupling potential index, enabling hardware-level graded thermal early warning. The hardware-level graded thermal early warning is based on the heat dissipation uniformity... The risk level is divided into ranges of values, and the switching frequency or output power of the corresponding switching transistor is dynamically adjusted by the drive controller to reduce the derating operation.

[0106] Example 2:

[0107] like Figure 2 As shown, the silicon carbide multilevel conversion control system based on embedded microchannel heat dissipation in this embodiment of the invention is as follows: Figure 2 As shown, it includes the following modules:

[0108] The module includes a synchronous sampling module for thermal-electric parameters, a module for assessing the coupling potential of thermal wake, a module for dynamic thermal boundary delineation, a module for wave velocity matching and flow tracking, a module for electro-current coupling analysis, and a module for frequency modulation compensation.

[0109] Thermo-electric parameter synchronous sampling module is used to extract real-time loss and flow channel monitoring data of bridge arms at different levels;

[0110] The thermal wake coupling potential assessment module is used to quantitatively assess the interference risk of high-frequency switching pulses of SiC chips on downstream heat dissipation capabilities by calculating the channel perturbation thermal factor and the gate behavior thermal accumulation factor.

[0111] The thermal boundary dynamic division module establishes a dynamic screening baseline based on the thermal wake coupling potential distribution and divides high-risk heat-affected groups.

[0112] The wave velocity matching flow tracking module locates the downstream monitoring point of the microchannel where the high-heat-risk module is located based on its physical coordinates, and captures abnormal values ​​of propagation delay fluctuations caused by the thermal wake effect.

[0113] The electro-current coupling analysis module constructs an electro-current coupling analysis model and outputs the heat dissipation uniformity.

[0114] The frequency modulation compensation module calculates the PWM phase shift offset of each level transistor based on the lifetime fluctuation ratio and the thermal search delay ratio. It optimizes the thermal balance of the chip surface through dynamic phase shift, thereby completing the system thermal balance control.

[0115] Example 3:

[0116] This embodiment provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0117] The processor executes the aforementioned silicon carbide multilevel switching control method based on embedded microchannel heat dissipation by calling the computer program stored in memory.

[0118] This electronic device can vary considerably depending on its configuration or performance. It may include one or more Central Processing Units (CPUs) and one or more memories, wherein the memory stores at least one computer program, which is loaded and executed by the processor to implement the silicon carbide multilevel converter control method based on embedded microchannel heat dissipation provided in the above-described embodiment. The electronic device may also include other components for implementing its functions; for example, it may have wired or wireless network interfaces and input / output interfaces for data input and output. Details will not be elaborated upon in this embodiment.

[0119] Example 4:

[0120] This embodiment proposes a computer-readable storage medium on which an erasable and rewritable computer program is stored.

[0121] When the computer program runs on the computer device, it causes the computer device to execute the aforementioned silicon carbide multilevel conversion control method based on embedded microchannel heat dissipation.

[0122] For example, computer-readable storage media can be read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0123] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0124] It should be understood that determining B based on A does not mean determining B solely based on A; it also means determining B based on A and / or other information.

[0125] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired network and / or wireless network. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives (SSDs).

[0126] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0127] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0128] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only one method, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0129] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0130] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0131] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0132] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for silicon carbide multilevel inverter control based on embedded microchannel cooling, characterized by, The method includes: S1: Real-time extraction of real-time loss and power consumption data of SiC power modules in each phase bridge arm of the multilevel converter, pressure gradient at the microchannel inlet, and flow behavior status data; S2: Import the data into the embedded flow path thermal wake coupling risk assessment strategy, and calculate the thermal wake coupling potential index of each SiC power transistor under the current level condition. S3: Based on the thermal wake coupling potential index, perform local thermal boundary dynamic evaluation on all power modules in the multilevel system to obtain the first thermally hazardous module mode set, and dynamically adjust the thermal risk warning baseline of the corresponding bridge arm. S4: Perform thermal pulse propagation path tracking on all power transistor-related flow channels in the first thermal hazard module mode set to obtain real-time fluctuation tracking data involving fluid transport characteristics; S5: Construct an electric-current coupling analysis model, import the thermal wake coupling potential index and the real-time fluctuation tracking data into the model, and output the heat dissipation balance of each power module; S6: Import the heat dissipation uniformity into the junction temperature gradient lifetime fluctuation analysis model, output the deviation ratio of module thermal aging, and perform carrier phase shift compensation control on the carrier scheduling sequence of the multilevel converter according to the deviation ratio.

2. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 1, characterized in that, In S2, the embedded flow path thermal wake coupling risk assessment strategy includes: a flow path crosstalk thermal effect assessment sub-strategy and a gate power consumption delay assessment sub-strategy; The specific sub-strategy for evaluating the crosstalk thermal effect of the flow channel is as follows: S21: Extract the coolant flow rate of each sub-channel within the embedded microchannel at the current sampling point, as well as the transient heat flux per unit area generated by the multi-level spatiotemporal arrangement; within the observation period, the total number of SiC power transistor heat sources in the same sub-channel is... , The subscript is the heat source index; S22: with the first The power transistor is used as the evaluation center; the calculation is performed on the [number]th [transistor]. The path between each hot spot location and the coolant inlet is calculated simultaneously, along with the remaining coolant flow rate downstream of the same streamline. The axial flow path distances of each power tube from the center of the heat source constitute the set of downstream heat wake transfer distances. , , For set The total amount of data in the middle, For set index, For the first The axial flow path distance of each power transistor in the upstream thermal radiation field; S23: Based on S21-S22, calculate and obtain the channel disturbance thermal factor, specifically: ； in, Indicates the first The cumulative intensity of thermal wake generated by upstream level loss in each power transistor; For the first The average switching loss power of each upstream power transistor during the observation period; For upstream heat source to the first The axial flow path distance of each power transistor; The thermal conductivity of the coolant; For reference temperature difference; This represents the single-channel cross-sectional area of ​​the microchannel.

3. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 2, characterized in that, The gate power consumption delay evaluation sub-strategy specifically includes: S24: with the first Each power transistor serves as the physical evaluation center. Based on the topology logic of the multilevel converter circuit, the remaining... The high-frequency switching operation timestamp of the power unit and the first The time interval between power transistors; S25: Set a critical thermal accumulation threshold for the SiC chip surface. Select transistors in the above power units whose transient junction temperature rise rate is greater than or equal to the preset critical threshold, and record their corresponding loss trigger sequence timestamps to form a set of loss pulse peak sequences. , , For set The total number of medium and high frequency thermal pulses For set index, For the first The peak power moment is generated by a single SiC switch; S26: Based on S24-S25, calculate and obtain the gate behavior thermal accumulation factor, specifically: ； in, The number of flow channel branches, Indicates the first Thermal response hysteresis stress of individual cells in multi-level switching sequences; For the first The center moment of the rising edge of the conduction of the individual switching transistor; The thermal diffusion time constant of the embedded microchannel wall material; S27: Based on S21-S26, calculate the thermal wake coupling potential index. The specific formula is as follows: ; in, For the first The thermal wake coupling potential index of each power transistor, with a value range of [value missing]. The larger the value, the more significant the thermal wake coupling effect is to the power transistor under the current operating conditions, and the higher the thermal risk. and Based on the local Reynolds number within the microchannel The dynamically set weight allocation coefficients satisfy... .

4. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 3, characterized in that, In S3, the dynamic assessment of the local thermal boundary includes: obtaining the thermal wake coupling potential index of all power chips in the same heat dissipation branch under the current converter carrier phase shift period, arranging all potential indices in descending order, and taking the median value of the sequence as the real-time dynamic heat dissipation baseline. The set of power chips whose potential index exceeds the heat dissipation baseline is marked as the first thermal hazard module mode set, and a thermal risk warning signal is sent to the drive controller to dynamically increase the thermal risk monitoring sampling frequency of the bridge arm. The total number of sets is , This is the index of the first thermal hazard module mode set.

5. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 4, characterized in that, S4 includes the following specific steps: S41: Perform microfluidic high-frequency sampling and tracking on each SiC unit to be evaluated and its connected embedded flow channel in the first thermal hazard module mode set, including: triggering a real-time flow control diagnostic sequence during the follow-through period of the multi-level conversion cycle. S42: Extract real-time fluctuation tracking data. When the standard deviation of the propagation delay fluctuation of the downstream pressure measuring point exceeds the preset threshold value for 5 consecutive times, trigger the operation of the electric-current coupling analysis model and execute step S5. Otherwise, maintain the original monitoring frequency. The preset threshold value is set according to twice the standard deviation of the propagation delay under steady-state conditions.

6. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 5, characterized in that, S5 includes the following specific steps: S51: Construct an electro-current coupling analysis model to describe the dynamic relationship between carrier phase shift angle and fluid heat transfer hysteresis; S52: Potential Index Importing fluctuation tracking data into the model to calculate heat dissipation uniformity The formula is: ; in, For the first The heat dissipation uniformity of a high-heat-load chip, with a value range of [value range missing]. to A higher value indicates more balanced heat dissipation. The cross-channel fluid interference coefficient has a value ranging from 0.8 to 1.

2. The subscript is the index of the sequence number of the interference signal. Indicates the first The high-frequency loss and power consumption value captured this time; This represents the average energy of the data collected from the aforementioned five thermal events; The fluid turbulence decay time constant; For the first The upstream thermal wake propagation delay corresponding to each wafer For the first The propagation delay corresponding to the secondary interference signal; For the first The cumulative intensity of thermal wake corresponding to each crystal cell; It is the average value of the thermal wake coupling potential index of all cells in the first thermal hazard module mode set.

7. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 6, characterized in that, In S6, the junction temperature gradient lifetime fluctuation analysis model is as follows: ; in, The ratio of fluctuation in heat dissipation uniformity; This represents the total number of thermal monitoring units over a given time period. This serves as an index for the unit time period of thermal monitoring. Indicates the first During the aging and decay monitoring period, the first The heat dissipation balance of each switching transistor; and These represent the maximum and minimum values ​​of heat dissipation uniformity for each level module in the entire system; The thermal convection time interval for each level arm of the converter based on the carrier phase difference is defined as the product of the phase difference of the switching action of adjacent level arms and the carrier period.

8. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 7, characterized in that, In S6, the carrier phase shift compensation control includes: Maximum aging risk value of preset heat dissipation uniformity fluctuation ratio When the fluctuation rate of heat dissipation uniformity of any detected switching transistor is... Exceeding the maximum aging risk value When the time comes, return to the underlying logic of the driver, re-extract the original sequence signal in the driver instruction corresponding to the level, and perform carrier preprocessing on the sequence signal, including: filtering out electromagnetic noise interference in the power circuit, suppressing high-order harmonic components of the system, and dynamically extracting the effective current component through the fast Fourier algorithm, and connecting it to the embedded channel thermal wake co-controller. In this controller, the heat search time-delay ratio is first calculated. ,in For the first The propagation delay of the upstream thermal wake of each power transistor. The average flow rate of the coolant within the microchannels. The time interval between the switching action of the upstream interference source transistor and the switching action of the power transistor; Then according to Deviation from ideal value The degree of compensation is determined by dynamically calculating the carrier phase shift compensation angle using a proportional-integral controller. The details are as follows: ； in, This is the proportionality coefficient, and its value range is... to ; The integral coefficient has a range of values ​​of 1. to ; The reference time constant is set to the carrier period. The compensation angle This is superimposed on the carrier phase corresponding to the power transistor, increasing the thermal seek time delay ratio. Approaching This achieves spatiotemporal decoupling between the thermal pulse peak and the high-loss operation of the downstream switching transistor, and is based on the compensated heat dissipation balance. The degree of improvement was repeatedly confirmed to verify whether the heat source of the device and the center of the thermal wake of the flow path had been decoupled.

9. The silicon carbide multi-level conversion control method based on embedded microchannel heat dissipation according to claim 8, characterized in that, In S6, the compensation control further includes: When the heat dissipation uniformity fluctuation ratio Less than or equal to the maximum aging risk value When the system is confirmed to be in a stable operating state, the thermal fatigue thermogram distribution of each phase switch in the multi-level system is visualized in real time on the control terminal. Simultaneously, a corresponding three-dimensional image of the thermal stress density gradient is generated by combining the level position and the thermal wake coupling potential index, enabling hardware-level graded thermal early warning. The hardware-level graded thermal early warning is based on the heat dissipation uniformity... The risk level is divided into ranges of values, and the switching frequency or output power of the corresponding switching transistor is dynamically adjusted by the drive controller to achieve derated operation.

10. A silicon carbide multilevel converter control system based on embedded microchannel heat dissipation, used to implement the silicon carbide multilevel converter control method based on embedded microchannel heat dissipation as described in any one of claims 1-9, characterized in that, The system includes the following modules: The module includes a synchronous sampling module for thermal-electric parameters, a module for assessing the coupling potential of thermal wake, a module for dynamic thermal boundary delineation, a module for wave velocity matching and flow tracking, a module for electro-current coupling analysis, and a frequency modulation compensation module. Thermo-electric parameter synchronous sampling module is used to extract real-time loss and flow channel monitoring data of bridge arms at different levels; The thermal wake coupling potential assessment module is used to quantitatively assess the interference risk of high-frequency switching pulses of SiC chips on downstream heat dissipation capabilities by calculating the channel perturbation thermal factor and the gate behavior thermal accumulation factor. The thermal boundary dynamic division module establishes a dynamic screening baseline based on the thermal wake coupling potential distribution and divides high-risk heat-affected groups. The wave velocity matching flow tracking module locates the downstream monitoring point of the microchannel where the high-heat-risk module is located based on its physical coordinates, and captures abnormal values ​​of propagation delay fluctuations caused by the thermal wake effect. The electro-current coupling analysis module constructs an electro-current coupling analysis model and outputs the heat dissipation uniformity. The frequency modulation compensation module calculates the PWM phase shift offset of each level transistor based on the lifetime fluctuation ratio and the thermal search delay ratio. It optimizes the thermal balance of the chip surface through dynamic phase shift and completes the system thermal balance control.

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