A high-gain, gain-adjustable low-noise amplifier
By designing a DC blocking capacitor circuit and a gain control unit, combined with current multiplexing and source negative feedback structure, the fixed gain and area problems of traditional low-noise amplifiers are solved, realizing a high-gain, adjustable low-noise amplifier that can adapt to dynamic gain requirements and save circuit area and power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING ZHONGKE MICROELECTRONICS CO LTD
- Filing Date
- 2026-01-19
- Publication Date
- 2026-05-26
AI Technical Summary
Traditional low-noise amplifiers have fixed gain and cannot adapt to dynamic gain requirements. They also require the introduction of an additional balun structure, resulting in a large chip area and making it impossible to achieve adjustable high gain and high power efficiency.
A DC blocking capacitor circuit, a first-stage and a second-stage amplifier circuit, and a gain control unit are used to achieve high gain through current reuse and source negative feedback structure. The feedback depth is adjusted by using a MOS transistor array to achieve adjustable gain, thus eliminating the balun structure.
It achieves a high-gain, adjustable, low-noise amplifier, saving circuit area and power consumption, adapting to different signal strength requirements, and realizing single-ended input to dual-ended output.
Smart Images
Figure CN122092809A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency integrated circuit technology, and more specifically, to a high-gain, gain-adjustable, low-noise amplifier. Background Technology
[0002] The low-noise amplifier (LNO) is the first module in a wireless receiver, responsible for amplifying the weak signal received by the antenna for processing by subsequent circuits. Due to its crucial role in the receiving system, its performance significantly impacts the overall system performance. With the increasing demand for integration in the electronics field, the design of LNOs has become increasingly important, focusing on performance optimizations such as high gain, low power consumption, high linearity, and low noise. Furthermore, considering the automatic gain control system in the receiver's low-power design, gain adjustability must also be considered in the design of the LNO.
[0003] like Figure 1 The traditional two-stage common-source cascaded amplifier structure is shown, where M1 and M2 are the first and second stage amplifier transistors, respectively, R1 and R2 are the output loads of M1 and M2, respectively, and gm1 and gm2 are the transconductances of M1 and M2, respectively. The DC gain of this two-stage common-source cascaded amplifier is the product of the gains of the two stage amplifier transistors, gm1*R1*gm2*R2.
[0004] Traditional two-stage common-source cascaded amplifiers have single-ended inputs and outputs, requiring the introduction of a balun to achieve differential output, which may occupy a large chip area; moreover, the circuit design is fixed gain and lacks adjustability, making it unable to adapt to dynamic gain requirements. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides a high-gain, adjustable-gain, low-noise amplifier that can provide adjustable high gain while achieving balun-free single-ended input to dual-ended output conversion, saving circuit area and power consumption.
[0006] As a first aspect of the present invention, a high-gain, gain-adjustable low-noise amplifier is provided. The high-gain, gain-adjustable low-noise amplifier includes a DC-blocking capacitor circuit, a first-stage amplifier circuit, and a second-stage amplifier circuit. The second-stage amplifier circuit includes an amplifying transistor and a gain control unit. One end of the DC-blocking capacitor circuit is connected to a radio frequency signal, and the other end of the DC-blocking capacitor circuit is connected to the input terminal of the first-stage amplifier circuit. The output terminal of the first-stage amplifier circuit is connected to the input terminal of the second-stage amplifier circuit. The gain control unit is connected between the input terminal and the output terminal of the amplifying transistor. The DC blocking capacitor circuit is used to input the radio frequency signal; The first-stage amplifier circuit is used to initially amplify the radio frequency signal to output the initially amplified radio frequency signal; The second-stage amplifier circuit is used to further amplify the initially amplified radio frequency signal to output a further amplified radio frequency signal; wherein, the gain control unit is used to adjust the closed-loop gain of the second-stage amplifier circuit.
[0007] Furthermore, the DC blocking capacitor circuit includes a DC blocking capacitor C1, one end of which is connected to the radio frequency signal RFin, and the other end of which is connected to the input terminal of the first stage amplifier circuit.
[0008] Furthermore, the first-stage amplifier circuit includes a bias current source I. B1 The circuit consists of an NMOS transistor M1, a PMOS transistor M2, resistors R1 and R2; wherein the gate terminal of the NMOS transistor M1 is connected to the other end of the DC blocking capacitor C1, the gate terminal of the PMOS transistor M2, and one end of resistor R1; the drain terminal of the NMOS transistor M1 is connected to the drain terminal of the PMOS transistor M2, the other end of resistor R1, and the input terminal of the second-stage amplifier circuit; the source terminal of the NMOS transistor M1 is connected to one end of resistor R2; the other end of resistor R2 is grounded (GND); and the source terminal of the PMOS transistor M2 is connected to the bias current source I. B1 One end is connected; the bias current source I B1 The other end is connected to the power supply VDD.
[0009] Furthermore, the bias current source I B1 The first-stage amplifier circuit is provided with DC bias, and the NMOS transistor M1 and PMOS transistor M2 share the bias current source I. B1 The bias current; the NMOS transistor M1 and PMOS transistor M2 form a current-multiplexed common-source amplifier structure; the resistor R1 provides the gate bias voltage for the NMOS transistor M1 and PMOS transistor M2, and the resistor R2 serves as the negative feedback resistor for the NMOS transistor M1; wherein, the radio frequency signal output by the DC blocking capacitor circuit enters through the gate terminals of the NMOS transistor M1 and PMOS transistor M2, is initially amplified by the NMOS transistor M1 and PMOS transistor M2, and is output to the second-stage amplifier circuit through the drain terminals of the NMOS transistor M1 and PMOS transistor M2.
[0010] Furthermore, the second-stage amplifier circuit includes a gain control unit and a bias current source I. B2 and NMOS transistor M3; wherein, the gate terminal of the NMOS transistor M3 is connected to the drain terminal of the NMOS transistor M1, the drain terminal of the PMOS transistor M2, the other end of the resistor R1, the output terminal of the gain control unit, and the non-inverting output terminal OUTP of the low-noise amplifier; the drain terminal of the NMOS transistor M3 is connected to the bias current source I. B2One end of the NMOS transistor M3 is connected to the input terminal of the gain control unit and the inverting output terminal OUTN of the low-noise amplifier; the source terminal of the NMOS transistor M3 is grounded to GND; the bias current source I... B2 The other end is connected to the power supply VDD.
[0011] Furthermore, the bias current source I B2 The second-stage amplifier circuit is provided with a DC bias; the gate terminal of the NMOS transistor M3 is connected to the output terminal of the first-stage amplifier circuit to further amplify the pre-amplified RF signal and output the re-amplified RF signal through the inverting output terminal OUTN of the low-noise amplifier; wherein the pre-amplified RF signal is output through the non-inverting output terminal OUTP of the low-noise amplifier.
[0012] Furthermore, the gain control unit includes a resistor R3 and a MOS transistor array, wherein the MOS transistor array is connected in parallel with the resistor R3, and the MOS transistor array includes NMOS transistors M connected in parallel. C1 NMOS transistor M C2 and NMOS transistor M C3 Among them, one end of the resistor R3 and the NMOS transistor M C1 The drain of the NMOS transistor M C2 The drain terminal and NMOS transistor M C3 The drain terminal of the resistor R3 serves as the input terminal of the gain control unit and is connected to the drain terminal of the NMOS transistor M3; the other end of the resistor R3 and the NMOS transistor M... C1 The source end, NMOS transistor M C2 The source terminal and NMOS transistor M C3 The source terminal serves as the output terminal of the gain control unit and is connected to the gate terminal of the NMOS transistor M3; the NMOS transistor M... C1 The gate terminal and control voltage V C1 Connection; the NMOS transistor M C2 The gate terminal and control voltage V C2 Connection; the NMOS transistor M C3 The gate terminal and control voltage V C3 connect; The gain control unit serves as the negative feedback resistor for the NMOS transistor M3, and together with the NMOS transistor M3, they form a common-source amplifier structure with resistive negative feedback.
[0013] Furthermore, by controlling the voltage to control the on or off of the NMOS transistors in the MOS transistor array, the equivalent impedance of the gain control unit is changed, thereby adjusting the closed-loop gain of the second-stage amplifier circuit.
[0014] The high-gain, gain-adjustable, low-noise amplifier provided by this invention has the following advantages: First, without using an additional balun structure, a pseudo-differential output structure is adopted to achieve single-ended input to double-ended output; Second, a current reuse structure is used in the first-stage amplifier circuit, and the gate parallel resistor achieves self-biasing, eliminating the need for external bias voltage. Moreover, the current reuse makes the basic gain significantly higher than that of the traditional common-source amplifier structure. Third, source negative feedback is used in the first-stage amplifier circuit to suppress the nonlinearity of the amplifier tube, and a gain control unit with feedback function is introduced to be connected between the gate and drain terminals of the second-stage amplifier tube to jointly suppress the nonlinearity of the circuit. Fourth, the fixed resistance of the gain control unit and the dynamic switching of the MOS switch array can achieve adjustable gain to meet the reception requirements of different signal strengths. Attached Figure Description
[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.
[0016] Figure 1 This is the circuit diagram of a traditional two-stage common-source cascaded amplifier.
[0017] Figure 2 The circuit diagram of the high-gain, gain-adjustable, low-noise amplifier provided by the present invention. Detailed Implementation
[0018] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a high-gain, gain-adjustable, low-noise amplifier proposed according to the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0020] In explaining this invention, it should be noted that the terms "installation," "connection," and "linking" should be interpreted broadly unless otherwise specified. For example, a connection can be a fixed connection, a connection through a special interface, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0021] This embodiment provides a high-gain, gain-adjustable, low-noise amplifier, such as... Figure 2 As shown, the high-gain, gain-adjustable low-noise amplifier includes a DC blocking capacitor circuit 11, a first-stage amplifier circuit 12, and a second-stage amplifier circuit 13. The second-stage amplifier circuit 13 includes an amplifying tube and a gain control unit 14. One end of the DC blocking capacitor circuit 11 is connected to the radio frequency signal, and the other end of the DC blocking capacitor circuit 11 is connected to the input terminal of the first-stage amplifier circuit 12. The output terminal of the first-stage amplifier circuit 12 is connected to the input terminal of the second-stage amplifier circuit 13. The gain control unit 14 is connected between the input and output terminals of the amplifying tube. The DC blocking capacitor circuit 11 is used to input the radio frequency signal; The first-stage amplifier circuit 12 is used to initially amplify the radio frequency signal to output the initially amplified radio frequency signal; The second-stage amplifier circuit 13 is used to amplify the initially amplified radio frequency signal again to output a re-amplified radio frequency signal; wherein, the gain control unit 14 is used to adjust the closed-loop gain of the second-stage amplifier circuit 13.
[0022] Preferably, the DC blocking capacitor circuit 11 includes a DC blocking capacitor C1, one end of which is connected to the radio frequency signal RFin, and the other end of which is connected to the input terminal of the first stage amplifier circuit 12.
[0023] Preferably, the first-stage amplifier circuit 12 includes a bias current source I. B1The circuit consists of an NMOS transistor M1, a PMOS transistor M2, resistors R1 and R2; wherein the gate terminal of the NMOS transistor M1 is connected to the other end of the DC blocking capacitor C1, the gate terminal of the PMOS transistor M2, and one end of resistor R1; the drain terminal of the NMOS transistor M1 is connected to the drain terminal of the PMOS transistor M2, the other end of resistor R1, and the input terminal of the second-stage amplifier circuit 13; the source terminal of the NMOS transistor M1 is connected to one end of resistor R2; the other end of resistor R2 is grounded (GND); and the source terminal of the PMOS transistor M2 is connected to the bias current source I. B1 One end is connected; the bias current source I B1 The other end is connected to the power supply VDD.
[0024] Preferably, the bias current source I B1 The first-stage amplifier circuit 12 is provided with DC bias, and the NMOS transistor M1 and PMOS transistor M2 share the bias current source I. B1 The bias current; the NMOS transistor M1 and PMOS transistor M2 form a current-multiplexed common-source amplifier structure; the resistor R1 provides the gate bias voltage for the NMOS transistor M1 and PMOS transistor M2, and the resistor R2 serves as the negative feedback resistor for the NMOS transistor M1. The source negative feedback suppresses the nonlinearity of the amplifier transistor and improves the linearity of the circuit; wherein, the radio frequency signal output by the DC blocking capacitor circuit 11 enters through the gate terminals of the NMOS transistor M1 and PMOS transistor M2, is initially amplified by the NMOS transistor M1 and PMOS transistor M2, and is output to the second-stage amplifier circuit 13 through the drain terminals of the NMOS transistor M1 and PMOS transistor M2.
[0025] It should be noted that NMOS transistor M1 is the first common-source amplifier transistor, PMOS transistor M2 is the second common-source amplifier transistor, resistor R1 is the gate parallel resistor, resistor R2 is the source negative feedback resistor, the gate terminals of NMOS transistor M1 and PMOS transistor M2 serve as the input terminals of the first-stage amplifier circuit 12, and the drain terminals of NMOS transistor M1 and PMOS transistor M2 serve as the output terminals of the first-stage amplifier circuit 12. The first-stage amplifier circuit 12 adopts a current-reused source negative feedback common-source amplifier structure, which is used to receive the input signal, perform preliminary low-noise amplification of the input signal, achieve high gain by current reuse while saving circuit area and power consumption, and improve linearity through source negative feedback, while providing the amplified signal to the input terminal of the second-stage amplifier circuit 13.
[0026] Preferably, the second-stage amplifier circuit 13 includes a gain control unit 14 and a bias current source I. B2and NMOS transistor M3; wherein, the gate terminal of the NMOS transistor M3 is connected to the drain terminal of the NMOS transistor M1, the drain terminal of the PMOS transistor M2, the other end of the resistor R1, the output terminal of the gain control unit 14, and the non-inverting output terminal OUTP of the low noise amplifier; the drain terminal of the NMOS transistor M3 is connected to the bias current source I. B2 One end of the NMOS transistor M3 is connected to the input terminal of the gain control unit 14 and the inverting output terminal OUTN of the low-noise amplifier; the source terminal of the NMOS transistor M3 is grounded to GND; the bias current source I... B2 The other end is connected to the power supply VDD.
[0027] Preferably, the bias current source I B2 The second-stage amplifier circuit 13 is provided with a DC bias; the gate terminal of the NMOS transistor M3 is connected to the output terminal of the first-stage amplifier circuit 12 to further amplify the pre-amplified RF signal, and the re-amplified RF signal is output through the inverting output terminal OUTN of the low-noise amplifier; wherein, the pre-amplified RF signal is output through the non-inverting output terminal OUTP of the low-noise amplifier to achieve pseudo-differential output.
[0028] It should be noted that the second-stage amplifier circuit 13 adopts a common-source amplifier structure with resistive negative feedback to amplify the signal in the final stage, and performs pseudo-differential output from the gate and drain terminals to realize single-ended input to dual-ended output, suppress common-mode noise and adapt to the subsequent differential circuit.
[0029] Preferably, the gain control unit 14 includes a resistor R3 and a MOS transistor array, wherein the MOS transistor array is connected in parallel with the resistor R3, and the MOS transistor array includes NMOS transistors M connected in parallel. C1 NMOS transistor M C2 and NMOS transistor M C3 Among them, one end of the resistor R3 and the NMOS transistor M C1 The drain of the NMOS transistor M C2 The drain terminal and NMOS transistor M C3 The drain terminal of the resistor R3 serves as the input terminal of the gain control unit 14 and is connected to the drain terminal of the NMOS transistor M3; the other end of the resistor R3 and the NMOS transistor M3 are connected to the input terminal of the gain control unit 14. C1 The source end, NMOS transistor M C2 The source terminal and NMOS transistor M C3 The source terminal serves as the output terminal of the gain control unit 14 and is connected to the gate terminal of the NMOS transistor M3; the NMOS transistor M... C1 The gate terminal and control voltage V C1 Connection; the NMOS transistor M C2 The gate terminal and control voltage V C2Connection; the NMOS transistor M C3 The gate terminal and control voltage V C3 Connection; when V C When it is high, NMOS transistor M C When conducting, the channel resistance is at a low level; when V C When it is low, NMOS transistor M C When the circuit is turned off, the channel resistance is high. The MOS transistor array and resistor R3 are connected in parallel under different control voltages, resulting in different feedback resistance values. This changes the closed-loop gain of the second-stage amplifier circuit 13 and adjusts the overall gain of the circuit.
[0030] The input terminal of the gain control unit 14 is connected to the drain terminal of the NMOS transistor M3, and the output terminal is connected to the gate terminal of the NMOS transistor M3. The gain control unit 14 serves as the negative feedback resistor of the NMOS transistor M3, and together with the NMOS transistor M3, they form a common-source amplifier structure with resistive negative feedback.
[0031] Preferably, the turn-on or turn-off of the NMOS transistors in the MOS transistor array is controlled by controlling the voltage, thereby changing the equivalent impedance of the gain control unit 14, changing the feedback depth, and adjusting the amplification gain of the second-stage amplifier circuit 13.
[0032] In one alternative embodiment, the high-gain, gain-adjustable low-noise amplifier has an eight-level adjustable gain between 23dB and 43dB, an operating current of 645uA, and a P1dB of -23dBm at the lowest gain.
[0033] like Figure 2 As shown, the high-gain, gain-adjustable, low-noise amplifier provided in this embodiment operates as follows: (1) In the first-stage amplifier circuit 12, M1 and M2 form a current multiplexing structure, and the bias current source I is biased. B1 DC bias is provided for M1 and M2. The input RF signal RFin, after DC isolation by C1, is input to the gates of M1 and M2. M1 and M2 act as amplifier transistors, simultaneously amplifying the RF signal RFin input at the gate terminals twice, significantly improving the gain of the first-stage amplifier, and outputting it from the drain terminal to the second-stage amplifier circuit 13. The parallel resistor R1 between the gates of M1 and M2 provides a low-impedance path for 1 / f noise. The 1 / f noise voltage at the gates of M1 and M2 is shunt to ground through resistor R1, reducing the superposition of this noise voltage on the gate input signal and optimizing the noise performance of the circuit. The source negative feedback resistor R2 stabilizes the transconductance of M1 and M2, suppressing nonlinear distortion. The current multiplexing structure achieves high gain in the first stage while saving circuit area and power consumption.
[0034] (2) The drain terminals of M1 and M2 serve as the output terminals of the first-stage amplifier circuit 12, loading the pre-amplified radio frequency signal onto the gate of M3. At the same time, the pre-amplified radio frequency signal is output from the output terminal OUTP. M3 further amplifies the pre-amplified radio frequency signal, and its drain terminal outputs a re-amplified radio frequency signal. This re-amplified radio frequency signal is out of phase with the radio frequency signal input to the gate terminal of M3.
[0035] (3) The gain control unit 14 samples the radio frequency signal from the drain terminal of M3 and sends it back to the gate terminal of M3 to cancel part of the input radio frequency signal, thereby changing the actual input radio frequency signal and the actual output radio frequency signal of M3. The actual output radio frequency signal of M3 is led out from the output terminal OUTN. The gain control unit 14 reduces the theoretical amplification gain of the second-stage amplifier circuit 13, but effectively improves the circuit linearity and output voltage stability; (4) The core logic of the gain control unit 14 is to change the equivalent impedance of the feedback network by switching the MOSFETs in the MOSFET array on and off, thereby changing the feedback depth; among which, When the control voltage V C1 ~V C3 When all are at high level, all MOS transistors in the MOS transistor array are turned on. Since the equivalent resistance of the turned-on MOS transistors is extremely small, the equivalent impedance of the feedback network is minimized, the feedback depth is minimized, and the closed-loop gain of the second-stage amplifier circuit 13 is minimized. When the control voltage V C1 ~V C3 When one of them is low and the other two are high, one MOSFET is turned off and the other two are turned on. Since the equivalent resistance of the turned-off MOSFET is large, the equivalent impedance of the feedback network increases, the feedback depth increases, and the closed-loop gain of the second-stage amplifier circuit 13 increases. When the control voltage V C1 ~V C3 When two of them are at low level and the other one is at high level, two MOSFETs are turned off and one MOSFET is turned on, causing the equivalent impedance of the feedback network to continue to increase and the feedback depth to continue to increase. As a result, the closed-loop gain of the second-stage amplifier circuit 13 continues to rise. When the control voltage V C1 ~V C3 When all are at low level, all MOSFETs are turned off, resulting in the maximum equivalent impedance of the feedback network and the maximum feedback depth, thus maximizing the closed-loop gain of the second-stage amplifier circuit 13. By controlling V C1 ~V C3 By switching the number of MOSFETs turned on at different levels, multiple equivalent impedances can be formed, enabling multi-stage amplification gain adjustment.
[0036] The high-gain, adjustable-gain low-noise amplifier provided in this embodiment includes a two-stage amplifier circuit and a gain control unit. The first-stage amplifier circuit is a current-reused source-negative feedback common-source amplifier structure. Current reuse saves circuit area and power consumption, and the source-level negative feedback resistor can improve linearity. The second-stage amplifier circuit adopts a resistive negative feedback common-source amplifier structure to further amplify the signal. The feedback section, i.e., the gain control unit, is connected between the gate and drain of the common-source amplifier transistor and consists of a fixed-value resistor and a MOSFET switch array connected in parallel. By controlling the conduction or cutoff of the MOSFETs, the resistance value of the feedback section can be changed to achieve multi-stage gain adjustment to adapt to output requirements. This invention is applied to the initial signal amplification in wireless receivers, providing adjustable high gain while meeting matching requirements.
[0037] The high-gain, low-noise amplifier provided by this invention uses current multiplexing to save circuit area and power consumption. The source-level negative feedback resistor can improve the linearity of the amplifier tube. The feedback unit composed of a fixed resistance value and a MOS switch array in parallel can change the feedback depth to adjust the circuit gain. It can achieve single-ended input and double-ended output without using an additional balun structure. The overall circuit achieves adjustable high gain while optimizing layout area and power consumption.
[0038] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A high-gain, gain-adjustable, low-noise amplifier, characterized in that, The high-gain, gain-adjustable low-noise amplifier includes a DC blocking capacitor circuit (11), a first-stage amplifier circuit (12), and a second-stage amplifier circuit (13). The second-stage amplifier circuit (13) includes an amplifying tube and a gain control unit (14). One end of the DC blocking capacitor circuit (11) is connected to the radio frequency signal, and the other end of the DC blocking capacitor circuit (11) is connected to the input terminal of the first-stage amplifier circuit (12). The output terminal of the first-stage amplifier circuit (12) is connected to the input terminal of the second-stage amplifier circuit (13). The gain control unit (14) is connected between the input and output terminals of the amplifying tube. The DC blocking capacitor circuit (11) is used to input the radio frequency signal; The first stage amplifier circuit (12) is used to initially amplify the radio frequency signal to output the initially amplified radio frequency signal; The second-stage amplifier circuit (13) is used to amplify the pre-amplified radio frequency signal again to output the amplified radio frequency signal; wherein, the gain control unit (14) is used to adjust the closed-loop gain of the second-stage amplifier circuit (13).
2. The high-gain, gain-adjustable, low-noise amplifier according to claim 1, characterized in that, The DC blocking capacitor circuit (11) includes a DC blocking capacitor C1, one end of which is connected to the radio frequency signal RFin, and the other end of which is connected to the input terminal of the first stage amplifier circuit (12).
3. The high-gain, gain-adjustable, low-noise amplifier according to claim 2, characterized in that, The first stage amplifier circuit (12) includes a bias current source I. B1 The circuit consists of an NMOS transistor M1, a PMOS transistor M2, resistors R1 and R2; wherein the gate of the NMOS transistor M1 is connected to the other end of the DC blocking capacitor C1, the gate of the PMOS transistor M2, and one end of resistor R1; the drain of the NMOS transistor M1 is connected to the drain of the PMOS transistor M2, the other end of resistor R1, and the input terminal of the second-stage amplifier circuit (13); the source of the NMOS transistor M1 is connected to one end of resistor R2; the other end of resistor R2 is grounded (GND); and the source of the PMOS transistor M2 is connected to the bias current source I. B1 One end is connected; the bias current source I B1 The other end is connected to the power supply VDD.
4. A high-gain, gain-adjustable, low-noise amplifier according to claim 3, characterized in that, The bias current source I B1 The first-stage amplifier circuit (12) is provided with DC bias, and the NMOS transistor M1 and PMOS transistor M2 share the bias current source I. B1 The bias current; the NMOS transistor M1 and PMOS transistor M2 form a current-multiplexed common-source amplifier structure; the resistor R1 provides the gate bias voltage for the NMOS transistor M1 and PMOS transistor M2, and the resistor R2 serves as the negative feedback resistor for the NMOS transistor M1; wherein, the radio frequency signal output by the DC blocking capacitor circuit (11) enters from the gate terminals of the NMOS transistor M1 and PMOS transistor M2, is initially amplified by the NMOS transistor M1 and PMOS transistor M2, and is output to the second-stage amplifier circuit (13) from the drain terminals of the NMOS transistor M1 and PMOS transistor M2.
5. A high-gain, gain-adjustable, low-noise amplifier according to claim 3, characterized in that, The second-stage amplifier circuit (13) includes a gain control unit (14) and a bias current source I. B2 and NMOS transistor M3; wherein, the gate terminal of the NMOS transistor M3 is connected to the drain terminal of the NMOS transistor M1, the drain terminal of the PMOS transistor M2, the other end of the resistor R1, the output terminal of the gain control unit (14), and the non-inverting output terminal OUTP of the low noise amplifier; the drain terminal of the NMOS transistor M3 is connected to the bias current source I B2 One end of the NMOS transistor M3 is connected to the input terminal of the gain control unit (14) and the inverting output terminal OUTN of the low-noise amplifier; the source terminal of the NMOS transistor M3 is grounded to GND; the bias current source I B2 The other end is connected to the power supply VDD.
6. A high-gain, gain-adjustable, low-noise amplifier according to claim 5, characterized in that, The bias current source I B2 The second stage amplifier circuit (13) is provided with DC bias; the gate terminal of the NMOS transistor M3 is connected to the output terminal of the first stage amplifier circuit (12) to amplify the pre-amplified radio frequency signal again, and output the re-amplified radio frequency signal through the inverting output terminal OUTN of the low noise amplifier; wherein the pre-amplified radio frequency signal is output through the non-inverting output terminal OUTP of the low noise amplifier.
7. A high-gain, gain-adjustable, low-noise amplifier according to claim 5, characterized in that, The gain control unit (14) includes a resistor R3 and a MOS transistor array, wherein the MOS transistor array is connected in parallel with the resistor R3, and the MOS transistor array includes parallel NMOS transistors M. C1 NMOS transistor M C2 and NMOS transistor M C3 Among them, one end of the resistor R3 and the NMOS transistor M C1 The drain of the NMOS transistor M C2 The drain terminal and NMOS transistor M C3 The drain terminal of the resistor R3 serves as the input terminal of the gain control unit (14) and is connected to the drain terminal of the NMOS transistor M3; the other end of the resistor R3 and the NMOS transistor M3 are connected to the input terminal of the gain control unit (14) and the input terminal of the gain control unit (14). C1 The source end, NMOS transistor M C2 The source terminal and NMOS transistor M C3 The source terminal serves as the output terminal of the gain control unit (14) and is connected to the gate terminal of the NMOS transistor M3; the NMOS transistor M C1 The gate terminal and control voltage V C1 Connection; the NMOS transistor M C2 The gate terminal and control voltage V C2 Connection; the NMOS transistor M C3 The gate terminal and control voltage V C3 connect; The gain control unit (14) serves as the negative feedback resistor for the NMOS transistor M3, and together with the NMOS transistor M3, they form a common-source amplifier structure with resistive negative feedback.
8. A high-gain, gain-adjustable, low-noise amplifier according to claim 7, characterized in that, By controlling the voltage to control the NMOS transistors in the MOS transistor array to turn on or off, the equivalent impedance of the gain control unit (14) is changed, thereby adjusting the closed-loop gain of the second-stage amplifier circuit (13).