Semiconductor devices

Abstract

This disclosure relates to a semiconductor device. A semiconductor device capable of reducing power consumption is provided. An nMOS transistor MNo receives an external power supply voltage Vcc at its drain and outputs an internal power supply voltage Vdd from its source. A charge pump circuit CP receives the external power supply voltage Vcc and generates a boost power supply voltage Vcp higher than the external power supply voltage Vcc. A reference voltage generation circuit VREFG1 uses a replica nMOS transistor MNr formed using the same fabrication process as the nMOS transistor MNo to generate a first reference voltage Vref1 reflecting changes in the characteristics of the nMOS transistor MNo. A voltage regulator circuit VREGb applies a gate voltage VGn determined based on the first reference voltage Vref1 to the gate of the nMOS transistor MNo.

Description

Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-204922, filed on November 25, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device, such as a semiconductor device including a power supply circuit. Background Technology

[0003] The publicly available technologies are listed below.

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-171076

[0005] Patent document 1 discloses a semiconductor device including a switching regulator and a linear regulator. When an input voltage is applied, the switching regulator is set to a stop state, and the linear regulator is set to an operating state. After the input voltage is applied, the switching regulator is controlled to switch from the stop state to the operating state. Summary of the Invention

[0006] In recent years, particularly for ICs (integrated circuits) used in small devices such as smartphones and tablets—in other words, for semiconductor devices—there has been a demand to reduce the number of terminals and miniaturize the package. However, reducing the number of terminals and miniaturizing the package leads to reduced heat dissipation capabilities. Therefore, it is desirable to suppress heat generation by reducing the power consumption of semiconductor devices.

[0007] On the other hand, as shown in Patent Document 1, semiconductor devices typically use linear regulators or LDO (Low Dropout) regulators to generate an internal power supply voltage lower than the external power supply voltage. Logic circuits within the semiconductor device operate at this internal power supply voltage. However, a relatively high external power supply voltage is required for the proper operation of an LDO regulator. This high external power supply voltage can become a bottleneck for reducing power consumption.

[0008] The embodiments described below are proposed in view of these problems, and other problems and novel features will become apparent from the description and drawings in this specification.

[0009] A semiconductor device according to one embodiment receives an external power supply voltage and includes a power supply circuit and a load circuit. The power supply circuit generates an internal power supply voltage having a voltage value lower than the external power supply voltage, which is supplied to the load circuit. The power supply circuit includes an n-channel output transistor, a charge pump circuit, a reference voltage generation circuit, and a voltage regulator circuit. The output transistor receives the external power supply voltage at its drain and outputs the internal power supply voltage from its source. The charge pump circuit receives the external power supply voltage and generates a boosted power supply voltage higher than the external power supply voltage. The reference voltage generation circuit is supplied with the boosted power supply voltage and uses a replicated transistor formed using the same manufacturing process as the output transistor to generate a first reference voltage reflecting changes in the characteristics of the output transistor. The voltage regulator circuit is supplied with the boosted power supply voltage and applies a gate voltage determined based on the first reference voltage to the gate of the output transistor.

[0010] According to this embodiment, the power consumption of semiconductor devices can be reduced. Attached Figure Description

[0011] Figure 1A This is a block diagram illustrating an example configuration of a semiconductor device according to one embodiment.

[0012] Figure 1B This is a schematic diagram showing an example of an external view of a semiconductor device according to one embodiment.

[0013] Figure 2 It shows the basis Figure 1A The circuit diagram is an example of the power supply circuit configuration in the comparison example.

[0014] Figure 3 It shows the basis Figure 2 A schematic diagram showing examples of voltage values ​​at each node of the external power supply voltage.

[0015] Figure 4 It is shown Figure 2 A diagram illustrating an example of a problem.

[0016] Figure 5 It shows the basis Figure 1A A circuit diagram illustrating an example configuration of a power supply circuit in one embodiment.

[0017] Figure 6A It is shown Figure 5 A schematic diagram illustrating the voltage relationships at each node in the diagram.

[0018] Figure 6B It shows the basis Figure 5 A schematic diagram showing examples of voltage values ​​at each node of the external power supply voltage.

[0019] Figure 7It is shown in Figure 5 A timing diagram showing examples of voltages or currents occurring at each node in the diagram.

[0020] Figure 8 It is shown Figure 5 The circuit diagram shows an example of a modified configuration around the charge pump circuit.

[0021] Figure 9A It is shown Figure 1A The circuit diagram is an example of a configuration for a general power supply circuit.

[0022] Figure 9B It is shown Figure 9A The circuit diagram shows an example of the configuration of the amplifier circuit in the example.

[0023] Figure 10 It is shown Figure 9A and Figure 9B A diagram illustrating an example of a problem.

[0024] Figure 11 It is shown that... Figure 10 Sequence diagrams for examples of different problems. Detailed Implementation

[0025] In the following embodiments, for convenience, the description may be divided into multiple parts or embodiments where necessary; however, unless otherwise specified, they are not unrelated to each other, and one may be related to another as a part or the whole of an example of modification, detail, supplementary description, etc. Furthermore, in the following embodiments, when referring to the number of elements, etc. (including quantity, value, amount, range, etc.), unless otherwise specified and clearly limited in principle to a specific number, it is not limited to that specific number and may be not less than or equal to that specific number.

[0026] Furthermore, in the embodiments below, constituent elements (including element steps, etc.) are not necessarily necessary unless otherwise specifically stated and explicitly considered necessary in principle. Similarly, in the embodiments below, when referring to the shape, positional relationship, etc. of components, unless otherwise specifically stated and explicitly considered not to be so in principle, it includes those parts that are substantially approximate or similar to these shapes, etc. This also applies to the numerical values ​​and ranges mentioned above.

[0027] Furthermore, in the following embodiments, p-channel MOSFETs (metal-oxide-semiconductor field-effect transistors) and n-channel MOSFETs are referred to as pMOS transistors and nMOS transistors, respectively. In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are given the same reference numerals, and repeated descriptions thereof are omitted.

[0028] (Configuration of semiconductor devices)

[0029] Figure 1A This is a block diagram illustrating an example configuration of a semiconductor device according to one embodiment. Figure 1B This is a schematic diagram showing an example of an external view of a semiconductor device according to one embodiment. Figure 1A The semiconductor device DEV shown is, for example, a system-on-a-chip (SoC) with a semiconductor chip CHP or a microcontroller. The semiconductor device DEV includes internal units interconnected via a bus BS. Furthermore, the semiconductor device DEV includes a power supply circuit PWG and a clock generation circuit CKG. Each of these components is formed on a single semiconductor chip CHP.

[0030] Internal units include, for example, a processor (PRC), volatile memory (RAM), and non-volatile memory (NVM). Additionally, internal units include an amplifier unit (AMPU), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a driver unit (DRVU), a PWM (pulse width modulation) unit (PWMU), a serial-to-parallel interface (SPI), and various peripheral circuits (PERI).

[0031] Volatile memory (RAM) is, for example, SRAM (Static Random Access Memory). Non-volatile memory (NVM) is, for example, flash memory. The processor (PRC) includes a CPU (Central Processing Unit) and may also include a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit). The processor (PRC) executes a predetermined program, such as a control program for an external system, copied from the non-volatile memory (NVM) to the volatile memory (RAM).

[0032] For example, semiconductor device DEV control includes an external system of sensors and actuators. In this case, the amplifier unit (AMPU) receives the detection signal (i.e., analog signal) from the sensor and amplifies the input analog signal. The analog-to-digital converter (ADC) converts the signal amplified by the AMPU into a digital signal. The processor (PRC) receives the digital signal via the bus (BS), and thereby receives the detection signal from the sensor, and generates an operation signal corresponding to the detection signal.

[0033] Then, the processor PRC outputs the generated operation signal to the digital-to-analog converter (DAC) or the PWM unit (PWMU) via the bus BS to control the actuator. In this process, the DAC converts the digital signal, which is the operation signal input, into an analog signal. The driver unit DRVU drives the actuator based on the analog signal from the DAC. Alternatively, the PWM unit PWMU generates a PWM signal based on the duty cycle command value, which is the operation signal input, and uses the PWM signal to drive the actuator.

[0034] The serial-to-parallel interface (SPI) uses serial-to-parallel conversion to perform predetermined digital communication with external systems. Various peripheral circuits (PERI) provide additional functions required to control external systems. The clock generation circuit CKG generates a reference clock signal based on an external crystal oscillator (not shown), and then generates a clock signal CK based on the reference clock signal using a PLL (phase-locked loop) circuit, etc. The clock generation circuit CKG supplies the generated clock signal CK to the logic circuit represented by the processor PRC.

[0035] As will be described in detail later, the power supply circuit PWG receives an external power supply voltage Vcc and generates various power supply voltages with predetermined values, including an internal power supply voltage Vdd for the load circuit. The internal power supply voltage Vdd has a lower voltage value than the external power supply voltage Vcc. The load circuit is either a logic circuit or an analog circuit. Figure 1A In the example shown, the logic circuitry primarily corresponds to the processor PRC, but may also correspond to volatile memory RAM, serial-to-parallel interface SPI, or PWM unit PWMU, etc. Analog circuitry may correspond to, for example, amplifier unit AMPU, analog-to-digital converter ADC, and digital-to-analog converter DAC, etc.

[0036] Figure 1A The semiconductor device DEV shown can be configured in, for example... Figure 1B The package shown. Figure 1B Examples of planar configurations of a semiconductor device DEV and examples of cross-sectional configurations of a semiconductor device DEV between A-A' are shown. Figure 1B In this process, solder balls BL, used as package terminals, are formed on the semiconductor chip CHP via a wiring layer WL. The wiring layer WL connects the electrode pads of the semiconductor chip CHP to the solder balls BL. Such a package is called CSP (Chip Scale Package), WLP (Wafer Scale Package), or WLCSP (Wafer Scale CSP), etc.

[0037] In particular, in semiconductor devices (DEVs) used in small devices such as smartphones and tablets, packages with fewer terminals and smaller dimensions, such as CSPs, are typically used instead of QFPs (Quad Flat Packages). As a specific example, Figure 1A and Figure 1B The semiconductor device DEV shown is an IC used in OIS (Optical Image Stabilizer). In this case, the semiconductor device DEV is mounted in a small space surrounding a small module that includes the camera lens.

[0038] In particular, when using packages similar to CSPs, heat dissipation may be reduced compared to packages using heat dissipation components such as bonding wires or lead frames. Furthermore, the mounting space of the package is often located in areas where heat dissipation is difficult to achieve. Therefore, it is desirable to reduce the power consumption of the semiconductor device DEV to suppress heat generation. Additionally, the external power supply voltage Vcc is supplied, for example, by a battery. To extend the battery's operating time while reducing the power consumption of the semiconductor device DEV, a lower lower limit for the external power supply voltage Vcc is desirable. In the method of the embodiments described later, a power supply circuit PWG that satisfies this requirement is shown.

[0039] (Regarding the power supply circuit (general configuration))

[0040] Before describing the power supply circuit according to this embodiment, a general power supply circuit will be described first. Figure 9A It is shown Figure 1A The circuit diagram shows an example configuration of the general power supply circuit PWG. Figure 9B It is shown Figure 9A The circuit diagram shows an example configuration of the amplifier circuit AMP in the example. Figure 9A The power supply circuit PWGx shown includes a reference voltage generation circuit VREFGx and a voltage regulator circuit VREGx. The reference voltage generation circuit VREFGx is configured with a bandgap reference circuit. The reference voltage generation circuit VREFGx generates, for example, a reference voltage Vref of 1.2V.

[0041] The voltage regulator circuit VREGx is a linear regulator or LDO regulator. The VREGx circuit includes an amplifier circuit AMP and a pMOS transistor MPo as the output transistor. The pMOS transistor MPo receives an external power supply voltage Vcc at its source and outputs an internal power supply voltage Vdd from its drain. The amplifier circuit AMP compares the internal power supply voltage Vdd with a reference voltage Vref and uses negative feedback to control the gate voltage VGp of the pMOS transistor MPo, so that the internal power supply voltage Vdd is closer to the reference voltage Vref.

[0042] As a result, an internal power supply voltage of approximately 1.2V, Vdd, is generated. This internal power supply voltage Vdd is then supplied to the load circuit, LDC. Figure 1A As shown, the load circuit LDC is a logic or analog circuit formed on the semiconductor chip CHP. A relatively large load current Iload flows through the load circuit LDC. Therefore, the pMOS transistor MPo has a high current drive capability, i.e., a large gate width (W).

[0043] like Figure 9BAs shown, the amplifier circuit AMP is supplied with an external power supply voltage Vcc (with the ground power supply voltage GND as a reference), thus forming an nMOS input differential amplifier circuit. The amplifier circuit AMP includes pMOS transistors MP1 and MP2, and nMOS transistors MN1 to MN3. nMOS transistors MN1 and MN2 form the differential input pair of the differential amplifier circuit. nMOS transistor MN1 receives the reference voltage Vref as its negative input. nMOS transistor MN2 receives the internal power supply voltage Vdd as its positive input.

[0044] pMOS transistors MP1 and MP2 form a current mirror circuit and serve as the load current source for the differential amplifier circuit. PMOS transistor MP2 is configured as a diode connection. The common drain node of pMOS transistor MP1 and nMOS transistor MN1 becomes the positive output node of the differential amplifier circuit. At this positive output node, a gate voltage VGp is ​​generated to pMOS transistor MPo, which acts as the output transistor. nMOS transistor MN3 is connected to the common source node of nMOS transistors MN1 and MN2 and serves as the tail current source for the differential amplifier circuit.

[0045] Here, the source-drain voltage VdsN of nMOS transistors MN1 to MN3 may need to be, for example, about 0.5V or greater, to stabilize the differential amplifier circuit. Furthermore, based on threshold voltages, the gate-source voltage VgsP and therefore the source-drain voltage VdsP of pMOS transistor MP2 may need to be, for example, 0.7V or greater. In this case, the external supply voltage Vcc may need to be 1.7V (=0.5V). (2 + 0.7) or larger.

[0046] Figure 10 It shows Figure 9A and Figure 9B A diagram illustrating an example of a problem. Figure 10 An example is shown based on the value of the internal power supply voltage Vdd according to the external power supply voltage Vcc. For example... Figure 9B As shown, in order for the amplifier circuit AMP to operate normally, a lower limit voltage Vmin1 of approximately 1.7V needs to be set for the external power supply voltage Vcc. Therefore, as Figure 10 As shown, even if the target value of the internal power supply voltage Vdd is low, for example, 1.2V, an external power supply voltage Vcc of 1.7V or higher is required. This high external power supply voltage Vcc can become a bottleneck, (A) making it difficult to reduce the power consumption of the semiconductor device DEV.

[0047] Figure 11 It is shown that... Figure 10 Sequence diagrams for examples of different problems. Figure 11 It shows Figure 9B The waveforms of the load current Iload, internal power supply voltage Vdd, gate voltage VGp, and gate current IGp are shown in the figure. Figure 11 As shown, when the load current Iload increases or decreases rapidly, the internal power supply voltage Vdd decreases or increases instantaneously. The amplifier circuit AMP rapidly suppresses fluctuations in the internal power supply voltage Vdd by rapidly decreasing or increasing the gate voltage VGp in response to the instantaneous decrease or increase of the internal power supply voltage Vdd.

[0048] Here, in order to rapidly decrease or increase the gate voltage VGp, i.e., to rapidly discharge or charge the large gate capacitance, the amplifier circuit AMP needs to rapidly pass a large discharge current Idg or charging current Icg (as the gate current IGp). Therefore, (B) the amplifier circuit AMP may consume a relatively large amount of power. Furthermore, the transistors constituting the amplifier circuit AMP require relatively high current drive capability, i.e., a relatively large gate width (W). As a result, (C) the amplifier circuit AMP may have relatively high power consumption.

[0049] (Regarding power supply circuits (comparative examples))

[0050] Next, a description of a power supply circuit according to a comparative example, considering prior to the power supply circuit according to the embodiment, will be given. Figure 2 It shows the basis Figure 1A The circuit diagram is an example of the configuration of the power supply circuit PWG in the comparison example. Figure 2 The power supply circuit PWGa shown includes an nMOS transistor MNo as an output transistor and a drive circuit DVa that drives the nMOS transistor MNo.

[0051] Thus, in Figure 2 In this context, nMOS transistor MNo is used instead. Figure 9A The pMOS transistor MPo shown is used as the output transistor. The nMOS transistor MNo receives the external power supply voltage Vcc at its drain and outputs the internal power supply voltage Vdd from its source. In other words, the nMOS transistor MNo constitutes a source follower circuit. If the current drive capability is the same, using an nMOS transistor instead of a pMOS transistor can reduce the circuit area.

[0052] The driving circuit DVa includes a charge pump circuit CP, a charge pump control circuit CPCTa, a current source CSa, a Zener diode Dz, and a resistive voltage divider circuit RDIV. The charge pump circuit CP receives the external power supply voltage Vcc and generates a boost power supply voltage Vcp that is higher than the external power supply voltage Vcc. The resistive voltage divider circuit RDIV generates a detection voltage Vdet that reflects the boost power supply voltage Vcp by resistively dividing the boost power supply voltage Vcp.

[0053] The current source CSa and the Zener diode Dz are connected in series between the external power supply voltage Vcc and the ground power supply voltage GND. This generates a Zener voltage Vz at one end of the Zener diode Dz. The Zener voltage Vz is a reference voltage for determining the value of the boosted power supply voltage Vcp. The charge pump control circuit CPCTa compares the detected voltage Vdet with the Zener voltage Vz. Based on the comparison result, the charge pump control circuit CPCTa controls the charge pump circuit CP to be active or inactive using the enable signal ENcp.

[0054] Specifically, when "Vdet < Vz", the charge pump control circuit CPCT activates the charge pump circuit CP, and when "Vdet > Vz", the charge pump control circuit CPCT deactivates the charge pump circuit CP. This maintains the boosted power supply voltage Vcp at a predetermined value determined by the resistive voltage division ratio of the resistive voltage division circuit RDIV and the Zener voltage Vz. The nMOS transistor MNo, which is the output transistor, receives the boosted power supply voltage Vcp generated in this way as the gate voltage VGn. The nMOS transistor MNo then outputs a voltage obtained by reducing the gate-source voltage VgsN from the gate voltage VGn as the internal power supply voltage Vdd.

[0055] Figure 3 is a schematic diagram showing an example of the voltage value at each node corresponding to Figure 2 the external power supply voltage Vcc in Figure 3 shows an example of the voltage values of the boosted power supply voltage Vcp, the internal power supply voltage Vdd, and the Zener voltage Vz. As Figure 3 shown, by using the Figure 2 power supply circuit PWGa shown, the lower limit voltage Vmin2 of the external power supply voltage Vcc can be reduced to the required internal power supply voltage Vdd, for example, about 1.2V. In this example, the lower limit voltage Vmin2 is 1.3V, which is lower than Figure 10 the lower limit voltage Vmin1 shown, for example, 1.7V.

[0056] In the range above this lower limit voltage Vmin2, based on a Zener voltage Vz of about 0.9V and a resistive voltage division ratio of about 1 / 2, the boosted power supply voltage Vcp is maintained at, for example, 1.8V. The nMOS transistor MNo inputs this boosted power supply voltage Vcp of about 1.8V as the gate voltage VGn, and outputs a voltage obtained by reducing the gate-source voltage VgsN by about 0.6V as the internal power supply voltage Vdd.

[0057] Figure 4 is a schematic diagram showing an example of Figure 2 the problem in Figure 4An example illustrating the timing variations of the boost supply voltage Vcp and the internal supply voltage Vdd is shown. The charge pump circuit CP typically generates the boost supply voltage Vcp by alternately repeating charging and boosting operations on the capacitor. Therefore, the boost supply voltage Vcp typically includes a ripple voltage ΔVrpl. Furthermore, the gate-source voltage VgsN of the nMOS transistor MNo may experience voltage fluctuations ΔVgs depending on manufacturing tolerances or temperature variations, such as ±50mV to ±200mV.

[0058] As a result, the internal power supply voltage Vdd may experience a voltage fluctuation ΔVdd(ΔVrpl) corresponding to the ripple voltage ΔVrpl. Furthermore, the internal power supply voltage Vdd may also experience a voltage fluctuation ΔVdd(ΔVgs) corresponding to the voltage fluctuation ΔVgs of the gate-source voltage VgsN. This makes it difficult to... Figure 2 The method in the comparison example shown determines the internal power supply voltage Vdd with high precision.

[0059] (Regarding the power supply circuit (example))

[0060] Figure 5 It shows the basis Figure 1A A circuit diagram illustrating an example configuration of the power supply circuit PWG in one embodiment. Figure 5 The power supply circuit PWGb shown receives an external power supply voltage Vcc and generates an internal power supply voltage Vdd, which is lower than the external power supply voltage Vcc. The power supply circuit PWGb includes an nMOS transistor MNo as an output transistor and a drive circuit DVb that controls the nMOS transistor MNo. Figure 2 In this case, the nMOS transistor MNo receives the external power supply voltage Vcc at its drain and outputs the internal power supply voltage Vdd from its source. On the other hand, the drive circuit DVb has the same characteristics as... Figure 2 Different configurations are available.

[0061] The drive circuit DVb includes a charge pump circuit CP, a charge pump control circuit CPCTb, two reference voltage generation circuits VREFG1 and VREFG2, and a voltage regulator circuit VREGb. The charge pump circuit CP receives an external power supply voltage Vcc and generates a boost power supply voltage Vcp that is higher than the external power supply voltage Vcc. The charge pump control circuit CPCTb uses, for example, an enable signal ENcp to control the charge pump circuit CP to be in an active or inactive state.

[0062] The reference voltage generation circuit VREFG2 is, for example, a bandgap reference circuit BGR, which generates a second reference voltage Vref2 that is not temperature-dependent. On the other hand, the boost supply voltage Vcp is supplied to the reference voltage generation circuit VREFG1. The reference voltage generation circuit VREFG1 includes a replica transistor (specifically an nMOS transistor MNr), which is formed using the same manufacturing process as the output transistor (which is an nMOS transistor MNr). In general, the reference voltage generation circuit VREFG1 uses the replica transistor, which is an nMOS transistor MNr, to generate a first reference voltage Vref1 that reflects the characteristic changes of the output transistor.

[0063] In detail, the reference voltage generation circuit VREFG1 includes, in addition to the nMOS transistor MNr, a current source CS and an amplifier circuit (first amplifier circuit) AMP1. The current source CS is supplied with a boost supply voltage Vcp at one end and generates a reference current Iref to flow through the nMOS transistor MNr. The current source CS is, for example, constructed as a pMOS transistor-type current mirror circuit including a pMOS transistor MPC as a mirror transistor. The nMOS transistor MNr is configured as a diode connection. The nMOS transistor MNr generates a gate-source voltage VgsR between the commonly connected drain and gate-source terminals by allowing the reference current Iref to flow between the drain and source.

[0064] Amplifier circuit AMP1 is supplied with a boost power supply voltage Vcp. Amplifier circuit AMP1 applies a second reference voltage Vref2 from reference voltage generation circuit VREFG2 to the source of nMOS transistor MNr. Specifically, amplifier circuit AMP1 is, for example, constructed by a voltage follower circuit that takes the second reference voltage Vref2 as a positive input. This voltage follower circuit applies an output voltage of the same magnitude as the second reference voltage Vref2 to the source of nMOS transistor MNr. Amplifier circuit AMP1 uses, for example, a voltage follower circuit such as... Figure 9B The differential amplifier circuit shown is configured as follows. Therefore, in order to ensure stable operation of the amplifier circuit AMP1, a boost supply voltage Vcp of, for example, 1.7V or greater is required.

[0065] A first reference voltage Vref1 is generated at the gate and drain of the nMOS transistor MNr. Specifically, the reference voltage generation circuit VREFG1 generates the first reference voltage Vref1 by adding the gate-source voltage VgsR generated in the nMOS transistor MNr to a second reference voltage Vref2. The second reference voltage Vref2 is set to 1.2V, for example, based on a target value of the internal power supply voltage Vdd. Based on the threshold voltage value of the nMOS transistor MNr and the value of the reference current Iref, the gate-source voltage VgsR is set to approximately 0.6V. In this case, the first reference voltage Vref1 becomes approximately 1.8V.

[0066] The boost supply voltage Vcp is supplied to the voltage regulator circuit VREGb. In general, the voltage regulator circuit VREGb applies a gate voltage VGn, determined based on a first reference voltage Vref1, to the gate of the output transistor (which is an nMOS transistor MNo). Specifically, the voltage regulator circuit VREGb includes a drive transistor (which is a pMOS transistor MPd), an amplifier circuit AMP2, and a discharge transistor, namely the nMOS transistor MNdg.

[0067] The pMOS transistor MPd forms a source-drain path between the boost supply voltage Vcp and the gate of the output transistor (which is the nMOS transistor MNo). The amplifier circuit AMP2 performs negative feedback control on the gate voltage VGp of the pMOS transistor MPd to make the error between the gate voltage VGn of the nMOS transistor MNo (which is also the drain voltage of the pMOS transistor MPd) and the first reference voltage Vref1 close to zero.

[0068] The discharge transistor (which is an nMOS transistor MNdg) responds to the discharge command signal DG, causing the gate voltage VGn of the nMOS transistor MNo to discharge to the ground supply voltage GND. The amplifier circuit AMP2, for example, uses... Figure 9B The differential amplifier circuit shown is similar to that of amplifier circuit AMP1. A boost supply voltage Vcp, for example, 1.7V or higher, is required to stabilize the operation of amplifier circuit AMP2.

[0069] Using this voltage regulator circuit VREGb, a gate voltage VGn, for example approximately 1.8V, is applied to the gate of the output transistor (which is an nMOS transistor MNo), based on a first reference voltage Vref1. The value of the internal supply voltage Vdd becomes the value obtained by subtracting the gate-source voltage VgsN of the nMOS transistor MNo from the gate voltage VGn. For example, when the gate-source voltage VgsN is approximately 0.6V, the internal supply voltage Vdd becomes approximately 1.2V.

[0070] Specifically, depending on the value of the required load current Iload, the nMOS transistor MNo has a sufficiently high current drive capability, i.e., a sufficiently large gate width (W). In this case, the overdrive voltage Vov (=VgsN-Vth) generated based on the load current Iload can be, for example, 0.1V or less. When the threshold voltage (Vth) of the nMOS transistor MNo is approximately 0.5V, the gate-source voltage VgsN can be approximately 0.6V.

[0071] The charge pump control circuit CPCTb controls the charge pump circuit CP, ensuring that the boost supply voltage Vcp is above the lower limit voltage and below the upper limit voltage. The lower limit voltage of the boost supply voltage Vcp is the higher of the following two voltages. The first voltage is the voltage required for stable operation of amplifier circuits AMP1 and AMP2 as described above, for example, 1.7V. The second voltage is the required gate voltage VGn, which is the target internal supply voltage Vdd (for example, 1.2V) plus the gate-source voltage VgsN (for example, 0.6V). In other words, for the pMOS transistor MPd to operate properly, the relationship "Vcp > VGn" must be satisfied.

[0072] Furthermore, the gate-source voltage VgsN can be appropriately varied based on the threshold voltage (Vth) and size settings of the nMOS transistor MNo. Correspondingly, the lower limit voltage of the boost supply voltage Vcp can also be changed. Alternatively, the upper limit voltage of the boost supply voltage Vcp can be determined, for example, by considering the transistor's power dissipation and breakdown voltage. When the boost supply voltage Vcp reaches the upper limit voltage, the charge pump control circuit CPCTb uses the enable signal ENcp to deactivate the charge pump circuit CP.

[0073] Figure 6A It is shown Figure 5 A schematic diagram illustrating the voltage relationship of each node in the diagram. Figure 6A In this configuration, the second reference voltage Vref2 is set to, for example, 1.2V. The first reference voltage Vref1 is set to, for example, 1.8V by adding the gate-source voltage VgsR of the replica transistor (MNr) to the second reference voltage Vref2. Therefore, the gate voltage VGn of the output transistor (MNo) also becomes 1.8V. Due to the voltage drop of the gate-source voltage VgsN of the output transistor (MNo) relative to the gate voltage VGn, the internal power supply voltage Vdd becomes 1.2V.

[0074] In this example, the boost supply voltage Vcp is 2.4V. For example... Figure 6AAs shown, a predetermined ripple voltage ΔVrpl is superimposed on a boost power supply voltage Vcp based on 2.4V, etc. However, due to the rectification effect of the current source CS and the rectification effect of the amplifier circuit AMP1 that constitutes the voltage follower circuit, even if the boost power supply voltage Vcp includes the ripple voltage ΔVrpl, the reference voltage generation circuit VREFG1 can generate a stable first reference voltage Vref1.

[0075] Similarly, due to the rectification effect of the amplifier circuit AMP2 with its negative feedback configuration, the voltage regulator circuit VREGb can generate a stable gate voltage VGn even if the boost supply voltage Vcp includes a ripple voltage ΔVrpl. As a result, the output transistor (MNo) can generate a stable internal supply voltage Vdd. That is, it can suppress ripple voltages such as... Figure 4 The internal power supply voltage Vdd is shown as the voltage fluctuation ΔVdd(ΔVrpl) based on the ripple voltage ΔVrpl.

[0076] The nMOS transistor MNr (which is the replica transistor) is configured with a gate width (W) of 1 / K of that of the nMOS transistor MNo (which is the output transistor). Therefore, the reference current Iref from the current source CS is also set to a value of 1 / K of the assumed load current Iload for the load circuit LDC. The value of K is 10 or greater, and can be on the order of 100 or 1000. The assumed load current Iload is, for example, the average current or rated current expected in the load circuit LDC.

[0077] Using this parameter setting, if the gate-source voltage VgsN of the nMOS transistor MNo changes due to manufacturing deviations or temperature variations, the gate-source voltage VgsR of the nMOS transistor MNr will similarly change. As a result, the state of "VgsR = VgsN" can be maintained relative to various variation factors, and therefore the value of the internal power supply voltage Vdd can be determined by the value of the second reference voltage Vref2. This allows for suppression of… Figure 4 The diagram shows the voltage fluctuation ΔVdd (ΔVgs) of the internal power supply voltage Vdd caused by manufacturing variations or temperature changes in the nMOS transistor MNr. Furthermore, it reduces the area overhead associated with the nMOS transistor MNr and the current source CS.

[0078] Figure 6B It shows the basis Figure 5 A schematic diagram illustrating an example of the voltage value of each node in the external power supply voltage Vcc. (See diagram for example.) Figure 6B As shown, by using Figure 5 The power supply circuit PWGb shown can reduce the external power supply voltage Vcc required to generate the internal power supply voltage Vdd of 1.2V to a lower limit voltage Vmin2 of approximately 1.3V, similar to... Figure 3 In this case, the external power supply voltage Vcc can be obtained from... Figure 10 The lower limit voltage Vmin1, shown as approximately 1.7V, is reduced to a lower limit voltage Vmin2 of approximately 1.3V. Note that the lower limit voltage Vmin2 can also be set to a value close to 1.2V, depending on the gate width (W) of the output transistor (MNo).

[0079] and Figure 10 Unlike other situations, reducing the external power supply voltage Vcc in this way can reduce the power consumption of the semiconductor device DEV. Furthermore, when the external power supply voltage Vcc is supplied from a battery, the battery's operating time can be extended. Note that in... Figure 6B In this circuit, based on the boost ratio of the charge pump circuit CP, the boost power supply voltage Vcp increases as the external power supply voltage Vcc increases. Furthermore, when the boost power supply voltage Vcp exceeds the lower limit of the aforementioned boost power supply voltage Vcp, the gate voltage VGn is set to 1.8V, etc.

[0080] Figure 7 It is shown in Figure 5 A timing diagram showing examples of voltages or currents occurring at each node in the diagram. Figure 7 It shows Figure 5 Waveform examples of load current Iload, internal power supply voltage Vdd, gate voltage VGn, gate voltage VGp, and gate current IGn and IGp. (Example provided) Figure 7 As shown, when the load current Iload increases, the internal power supply voltage Vdd decreases slightly depending on the current drive capability of the nMOS transistor MNo. On the other hand, the voltage regulator circuit VREGb generates the gate voltage VGn in an open-loop manner. Therefore, with... Figure 11 In the case of [other conditions], the gate voltage VGn is constant. Therefore, the gate voltage VGp is ​​also constant.

[0081] When the gate voltages VGn and VGp are constant, the gate currents IGn and IGp are both approximately zero. That is, compared with... Figure 11 Unlike other amplifiers, AMP2 does not require high current drive capability because the gate current IGp is ​​approximately zero. Furthermore, AMP2 does not require a high-speed response. As a result, the power consumption of AMP2 can be reduced. Additionally, AMP2 can operate stably with a boost supply voltage Vcp that has low current supply capability, without the need for an external supply voltage Vcc. Furthermore, the circuit area of ​​AMP2 can be reduced. Note that similar effects apply to amplifier AMP1.

[0082] (Example of modifications around a charge pump circuit)

[0083] Figure 8 It is shown Figure 5 The circuit diagram shows an example of a modified configuration around the charge pump circuit CP. Figure 8 The configuration around the extracted and displayed charge pump circuit CP is shown. Figure 8 In addition to the charge pump circuit CP and the charge pump control circuit CPCTc, a switch SW1 is also provided. The charge pump control circuit CPCTc compares the external power supply voltage Vcc with a predetermined lower limit voltage VcpMIN of the boost power supply voltage Vcp. Then, when the external power supply voltage Vcc exceeds the lower limit voltage VcpMIN, the charge pump control circuit CPCTc uses the enable signal ENcp to deactivate the charge pump circuit CP.

[0084] When the external power supply voltage Vcc exceeds the lower limit voltage VcpMIN, switch SW1 connects node Nvcc of the external power supply voltage Vcc to node Nvcp of the boost power supply voltage Vcp. In this example, when the charge pump circuit CP is deactivated, the charge pump control circuit CPCTc controls switch SW1 to turn on. As a result, the boost power supply voltage Vcp is replaced by the external power supply voltage Vcc. Note that if the external power supply voltage Vcc does not exceed the lower limit voltage VcpMIN, the charge pump circuit CP is controlled to be active, and switch SW1 is controlled to be open.

[0085] By using this configuration, the charge pump circuit CP can remain inactive when the external supply voltage Vcc is sufficiently high, thereby further reducing the power consumption of the semiconductor device DEV. Note that the switch SW1 can be configured, for example, using a pMOS transistor. The charge pump control circuit CPCTc can be configured with, for example, a comparator that compares the external supply voltage Vcc, which is divided by resistors, with a lower limit voltage VcpMIN corresponding to the resistor division ratio.

[0086] (Other modification examples)

[0087] exist Figure 5 In this circuit, the pMOS transistor MPd is used as the drive transistor in the voltage regulator circuit VREGb. However, an nMOS transistor can also be used instead of the pMOS transistor. In this case, the amplifier circuit AMP2 is configured as a pMOS input differential amplifier circuit, instead of... Figure 9B The circuit shown is an nMOS input differential amplifier.

[0088] In addition, Figure 5The power supply circuit PWGb shown is configured to make the second reference voltage Vref2 equal to the internal power supply voltage Vdd. However, a constant voltage difference between the second reference voltage Vref2 and the internal power supply voltage Vdd can also be provided by feeding back the value of the internal power supply voltage Vdd, which is divided by resistors, to the amplifier circuit AMP2.

[0089] (Main effects of the embodiments)

[0090] As described above, the semiconductor device according to one embodiment uses an n-channel output transistor constituting a source follower circuit to generate an internal power supply voltage based on an external power supply voltage. This allows the external power supply voltage to be reduced to the same level as the internal power supply voltage, thereby reducing power consumption in the semiconductor device. Furthermore, a reference voltage generation circuit and a voltage regulator circuit are provided to generate the gate voltage of the output transistor. These circuits generate the gate voltage in an open-loop manner, thus requiring no current drive capability. As a result, power consumption in the reference voltage generation circuit and the voltage regulator circuit can also be reduced.

[0091] Although the invention has been specifically described based on embodiments, the invention is not limited to the described embodiments and various modifications can be made without departing from its essence. For example, the described embodiments are detailed for the purpose of clearly explaining the invention and are not necessarily limited to including all described configurations. A portion of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of another embodiment may be added to the configuration of one embodiment. Furthermore, a portion of the configuration of each embodiment may be added, deleted, or replaced with other configurations.

Claims

1. A semiconductor device comprising: a power supply circuit that receives an external power supply voltage and generates an internal power supply voltage having a voltage value lower than the external power supply voltage; and a load circuit to which the internal power supply voltage is supplied; wherein the power supply circuit includes: an n-channel output transistor that receives the external power supply voltage at a drain and outputs the internal power supply voltage from a source; a charge pump circuit that receives the external power supply voltage and generates a boosted power supply voltage higher than the external power supply voltage; a reference voltage generation circuit that is supplied with the boosted power supply voltage and has a replica transistor formed by the same manufacturing process as the output transistor, and generates a first reference voltage that reflects a characteristic variation of the output transistor using the replica transistor; and a voltage regulator circuit that is supplied with the boosted power supply voltage and applies a gate voltage determined based on the first reference voltage to a gate of the output transistor.

2. The semiconductor device according to claim 1, wherein a gate width of the replica transistor is 1 / K of a gate width of the output transistor, and a value of K is 10 or more.

3. The semiconductor device according to claim 2, wherein the replica transistor is configured to be diode-connected, and wherein the reference voltage generation circuit further includes a current source that generates a reference current flowing through the replica transistor, and the reference voltage generation circuit generates the first reference voltage by adding a gate-source voltage generated in the replica transistor to a second reference voltage that does not vary with temperature.

4. The semiconductor device according to claim 3, wherein the reference current is set to a value of 1 / K of a load current assumed for the load circuit.

5. The semiconductor device according to claim 3, wherein the reference voltage generation circuit includes a first amplifier circuit to which the boosted power supply voltage is supplied, and wherein the first amplifier circuit receives the second reference voltage and applies a voltage of the same magnitude as the second reference voltage to a source of the replica transistor.

6. The semiconductor device according to claim 1, wherein the voltage regulator circuit includes: a drive transistor that forms a source-drain path between the boosted power supply voltage and the gate of the output transistor; and a second amplifier circuit that performs negative feedback control of a gate voltage of the drive transistor to make an error between the gate voltage of the output transistor and the first reference voltage close to zero.

7. The semiconductor device according to claim 1, further comprising: a charge pump control circuit that deactivates the charge pump circuit when the external power supply voltage exceeds a predetermined lower limit voltage of the boosted power supply voltage; and a switching element that connects a node of the external power supply voltage to a node of the boosted power supply voltage when the external power supply voltage exceeds the lower limit voltage of the boosted power supply voltage. ​ ​

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