A single-sided input buffer and a fully differential input buffer

Abstract

This application discloses a single-sided input buffer and a fully differential input buffer, relating to the field of input buffer technology. The first input terminal of an operational amplifier serves as the single-sided output terminal of the single-sided input buffer, and the second input terminal of the operational amplifier serves as the single-sided input terminal of the single-sided input buffer. A connection is established between the second terminal of a first switch and the input terminal of an inverting amplifier, such that when the first switch is turned on, the gain coefficient setting of the inverting amplifier resets the first output terminal of the operational amplifier to a common-mode voltage signal. The common-mode voltage signal is based on this signal, and the gain coefficient of the inverting amplifier is adjusted and varied accordingly, reducing the input buffer's requirement for the operational amplifier's output swing and eliminating the need to follow the slope changes of the operational amplifier's input signal. This achieves a balance between wide swing and high gain while reducing the impact of different input voltages on the gain, improving linearity across the entire input range.

Description

Technical Field

[0001] This application relates to the field of input buffer technology, and in particular to a single-sided input buffer and a fully differential input buffer. Background Technology

[0002] The input buffer structure consists of an operational amplifier and a switched capacitor circuit. The output swing of the operational amplifier varies with the input signal. The operational amplifier in the input buffer needs to output a wide-swing signal, capable of swinging from the lowest to the highest voltage of the power supply. However, the high gain of the operational amplifier relies on the internal transistors operating in the saturation region with a small output voltage variation range. If the operational amplifier is allowed to output a wide swing, the internal transistors leave the saturation region and enter the linear region, leading to a significant drop in the op-amp's gain. Once the op-amp's gain decreases, the accuracy and linearity of the input buffer deteriorate. The requirement for a wide swing limits the high gain of the op-amp, and consequently, the accuracy of the input buffer.

[0003] Therefore, how to achieve a balance between wide swing and high precision while minimizing the impact of different input voltages on the gain in order to improve the linearity across the entire input range is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a single-sided input buffer and a fully differential input buffer to solve the problem of poor compatibility between wide swing and high precision of input buffers.

[0005] To solve the above-mentioned technical problems, this application provides a single-sided input buffer, including an operational amplifier, a first switched capacitor circuit, and a second switched capacitor circuit; The first and second input terminals of the operational amplifier correspond to the single-sided output and single-sided input terminals of the single-sided input buffer, respectively; the first input terminal of the operational amplifier is connected to the output terminal of the inverting amplifier, the first terminal of the first switched capacitor circuit, and the first terminal of the second switched capacitor circuit; the first and second output terminals of the operational amplifier are respectively connected to the common-mode voltage signal through clamping switches. The first switched capacitor circuit is connected to the power supply voltage signal and the first output terminal of the operational amplifier through a first complementary clock control switch; the second switched capacitor circuit is connected to the common-mode voltage signal and the first terminal of the first switch through a second complementary clock control switch; the second terminal of the first switch is connected to the input terminal of the inverting amplifier, so that the output swing range of the operational amplifier can be determined by the relationship between the common-mode voltage signal and the gain coefficient of the inverting amplifier and the changing voltage signal in the switching state formed by the first complementary clock control switch, the second complementary clock control switch and the clamping switch.

[0006] On one hand, the first switched capacitor circuit includes a first capacitor, a second capacitor, and a first complementary clock control switch, wherein the first complementary clock control switch includes a first sub-complementary clock control switch corresponding to the first capacitor and a second sub-complementary clock control switch corresponding to the second capacitor; the first sub-complementary clock control switch includes a second switch and a third switch, and the second sub-complementary clock control switch includes a fourth switch and a fifth switch; The first terminal of the first capacitor and the first terminal of the second capacitor are both connected to the first input terminal of the operational amplifier; the second terminal of the first capacitor is connected to the first terminal of the second switch and the first terminal of the third switch; the second terminal of the second capacitor is connected to the first terminal of the fourth switch and the first terminal of the fifth switch. The second terminal of the second switch and the second terminal of the fifth switch are both connected to the first output terminal of the operational amplifier; the second terminal of the third switch is connected to the power supply voltage signal, and the second terminal of the fourth switch is connected to the ground signal; wherein, the sum of the voltage values ​​corresponding to the power supply voltage signal and the ground signal is equal to the voltage value corresponding to the common mode voltage signal.

[0007] On the other hand, the second switched capacitor circuit includes a third capacitor, a fourth capacitor, and a second complementary clock control switch, wherein the second complementary clock control switch includes a third sub-complementary clock control switch corresponding to the third capacitor and a fourth sub-complementary clock control switch corresponding to the fourth capacitor; the third sub-complementary clock control switch includes a sixth switch and a seventh switch, and the fourth sub-complementary clock control switch includes an eighth switch and a ninth switch. The first terminal of the third capacitor and the first terminal of the fourth capacitor are both connected to the first input terminal of the operational amplifier; the second terminal of the third capacitor is connected to the first terminal of the sixth switch and the first terminal of the seventh switch; the second terminal of the fourth capacitor is connected to the first terminal of the eighth switch and the first terminal of the ninth switch. The second terminal of the sixth switch and the second terminal of the ninth switch are both connected to the first terminal of the first switch; the second terminal of the seventh switch and the second terminal of the eighth switch are both connected to a common-mode voltage signal.

[0008] On the other hand, the first switched capacitor circuit includes a fifth capacitor and a first complementary clock control switch, wherein the first complementary clock control switch includes a fifth sub-complementary clock control switch corresponding to the fifth capacitor, and the fifth sub-complementary clock control switch includes a tenth switch and an eleventh switch. The first terminal of the fifth capacitor is connected to the first input terminal of the operational amplifier; the second terminal of the fifth capacitor is connected to the first terminal of the tenth switch and the first terminal of the eleventh switch; the second terminal of the tenth switch is connected to the first output terminal of the operational amplifier; the second terminal of the eleventh switch is connected to a power supply voltage signal; wherein, the voltage value corresponding to the power supply voltage signal is equal to the voltage value corresponding to the common-mode voltage signal.

[0009] On the other hand, the operating states of the single-sided input buffer include four switching states that cycle sequentially: In the first switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the seventh switch, and the ninth switch are controlled to close, and the first switch, the third switch, the fourth switch, the clamping switch, the sixth switch, and the eighth switch are controlled to open. When the change in the input voltage signal of the buffer is the first voltage signal, the change in the output voltage signal of the first output terminal of the operational amplifier is determined to be the first voltage signal by utilizing the virtual short characteristic of the operational amplifier, so as to determine the change in the voltage signal at the first switch as the first voltage signal. In the second switch state formed by the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the sixth switch, and the eighth switch are controlled to open, and the first switch, the third switch, the fourth switch, the clamping switch, the seventh switch, and the ninth switch are controlled to close. The voltage change at the single-sided output terminal of the buffer is determined to be obtained from the relationship between the gain coefficient of the inverting amplifier and the change corresponding to the change in the voltage signal. Furthermore, the voltage signal at the first output terminal of the operational amplifier is reset to the common-mode voltage signal by turning on the clamping switch. In the third switch state formed by the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the sixth switch, and the eighth switch are controlled to close, and the first switch, the third switch, the fourth switch, the clamping switch, the seventh switch, and the ninth switch are controlled to open. This determines that the input voltage at the first input terminal of the operational amplifier in its initial state is equal to the output voltage at the output terminal of the buffer, and this is obtained from the relationship between the input voltage at the input terminal of the buffer, the gain coefficient of the inverting amplifier, and the change in the corresponding voltage signal. When the voltage signals at the first input terminal and the first output terminal of the operational amplifier reach equilibrium, the output voltage at the output terminal of the buffer, the first input terminal of the operational amplifier, the second input terminal of the operational amplifier, and the output voltage at the input terminal of the buffer are all equal. The output voltage at the first output terminal of the operational amplifier is determined by the common-mode voltage signal and the relationship between the gain coefficient of the inverting amplifier and the changing voltage signal. In the fourth switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the seventh switch, and the ninth switch are controlled to open, and the first switch, the third switch, the fourth switch, the clamping switch, the sixth switch, and the eighth switch are controlled to close, thereby determining that the output voltage of the first output terminal of the operational amplifier, the input voltage of the first input terminal of the operational amplifier, the voltage at the inverting amplifier, and the common-mode voltage are equal.

[0010] On the other hand, it also includes a controller; the controller is connected to the first output terminal of the operational amplifier and is used to reset the output voltage of the first output terminal of the operational amplifier to the common-mode voltage signal.

[0011] On the other hand, when the first complementary clock control switch, the second complementary clock control switch, and the clamping switch are all MOS transistors, each switch is an NMOS transistor; the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, and the ninth switch correspond to the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, and the ninth switch transistor, respectively; the clamping switch includes a twelfth switch transistor and a thirteenth switch transistor; the gate of each switch transistor is connected to the corresponding control signal; The drain of the first switching transistor is connected to the drain of the sixth switching transistor and the drain of the ninth switching transistor, and the source of the first switching transistor is connected to the input terminal of the inverting amplifier. The drain of the second switching transistor is connected to the first output terminal of the operational amplifier, and the source of the second switching transistor is connected to the second terminal of the first capacitor. The drain of the third switch is connected to the power supply voltage signal, and the source of the third switch is connected to the second terminal of the first capacitor. The drain of the fourth switch is connected to a ground signal, and the source of the fourth switch is connected to the second terminal of the second capacitor. The drain of the fifth switching transistor is connected to the first output terminal of the operational amplifier, and the source of the fifth switching transistor is connected to the second terminal of the second capacitor. The source of the sixth switch is connected to the second terminal of the third capacitor, and the source of the ninth switch is connected to the second terminal of the fourth capacitor. The drains of the seventh and eighth switching transistors are both connected to a common-mode voltage signal; the source of the seventh switching transistor is connected to the second terminal of the third capacitor, and the source of the eighth switching transistor is connected to the second terminal of the fourth capacitor. The source of the twelfth switch is connected to the first output terminal of the operational amplifier, and the source of the thirteenth switch is connected to the second output terminal of the operational amplifier; the drain of the twelfth switch is connected to the drain of the thirteenth switch and is connected to a common-mode voltage signal.

[0012] On the other hand, it also includes the sampling capacitor; The first terminal of the sampling capacitor is connected to the single-sided output terminal of the single-sided input buffer, the first input terminal of the operational amplifier, and the first terminals of the first switched capacitor circuit and the second switched capacitor circuit respectively; the second terminal of the sampling capacitor is grounded. The sampling capacitor is used to receive the output voltage of the single-sided output terminal of the single-sided input buffer for sampling processing.

[0013] On the other hand, the first capacitor and the second capacitor have the same capacitance value; the third capacitor and the fourth capacitor have the same capacitance value; Alternatively, the first complementary clock control switch, the second complementary clock control switch, and the clamping switch may be of the same type, namely, a single-pole single-throw switch or a switching transistor.

[0014] To solve the above-mentioned technical problems, this application also provides a fully differential input buffer, which is composed of two single-sided input buffers as described above; the first output terminal of the operational amplifier in one single-sided input buffer is connected to the first output terminal of the operational amplifier in the other single-sided input buffer; the second output terminal of the operational amplifier in one single-sided input buffer is connected to the second output terminal of the operational amplifier in the other single-sided input buffer.

[0015] This application provides a single-sided input buffer. Firstly, the first input terminal of an operational amplifier serves as the single-sided output terminal of the buffer, and the second input terminal serves as the single-sided input terminal. Compared to conventional input buffers, the output terminal of the operational amplifier serves as the output terminal, and its output voltage equals the input voltage. Using the inverting input terminal of the operational amplifier as the buffer's output essentially utilizes the open-loop virtual short characteristic of the operational amplifier, allowing the voltage at the inverting input terminal to follow that of the non-inverting input terminal, thus achieving buffering. In large-signal, high-bandwidth scenarios, the output stage is prone to problems such as insufficient slew rate and nonlinear distortion. Directly using the internal inverting input terminal of the operational amplifier as the output avoids the nonlinearity of the output stage, significantly improving signal fidelity in high-precision, wide-amplitude applications. It reduces the parasitic parameters and noise introduction of external components, resulting in a higher phase margin in the feedback loop and better stability under high-frequency and high-capacitive loads. Secondly, the first input terminal of the operational amplifier is connected to the output terminal of the directional amplifier, and the first terminals of the first and second switched capacitor circuits. The first switched capacitor circuit is connected to the power supply voltage signal and the first output terminal of the operational amplifier via a first complementary clock control switch. The second switched capacitor circuit is connected to the common-mode voltage signal and the first terminal of the first switch via a second complementary clock control switch. The purpose of the connection relationship of the first switched capacitor circuit is to obtain the relationship between the common-mode voltage signal corresponding to the power supply voltage signal, so that the voltage signal at the location of the first switched capacitor circuit is the same as the first output terminal of the operational amplifier, and is a common-mode voltage signal. The purpose of the connection relationship of the second switched capacitor circuit is to obtain the voltage difference between the voltage signals at the first output terminal and the first input terminal of the operational amplifier. This connection relationship, via the second terminal of the first switch connected to the input terminal of the inverting amplifier, ensures that when the first switch is turned on, the gain coefficient of the inverting amplifier changes, and when the input signal of the buffer changes, the corresponding change in the output voltage of the buffer also changes, thereby resetting the first output terminal of the operational amplifier to the common-mode voltage signal. Finally, by controlling the relationship between the gain coefficient of the inverting amplifier and the changing voltage signal, the output swing range of the operational amplifier is controlled within the change in voltage signal corresponding to the switching cycle of the switching states formed by the first complementary clock control switch, the second complementary clock control switch, and the clamping switch. The common-mode voltage signal is adjusted based on this signal by controlling the gain coefficient of the inverting amplifier and setting the changing voltage signal. This reduces the requirements of the input buffer for the operational amplifier's output swing, eliminating the need to follow the slope change of the operational amplifier's input signal and reducing the impact of different output swings on the linearity of the input buffer. This achieves a balance between wide swing and high gain while reducing the impact of different input voltages on the gain and improving linearity across the entire input range.

[0016] In addition, this application also provides a fully differential input buffer, which has the same beneficial effects as the single-sided input buffer described above. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This application provides a schematic diagram of the structure of a single-sided input buffer; Figure 2 This is a schematic diagram of a conventional input buffer. Figure 3 This is a schematic diagram showing the curve of the operational amplifier swing versus the input signal in a conventional input buffer operational amplifier structure. Figure 4 A schematic diagram of another single-sided input buffer provided in an embodiment of this application; Figure 5 A timing diagram showing four switching states is provided in an embodiment of this application; Figure 6 This application provides a schematic diagram of a circuit switch being turned on in a first switching state, as provided in an embodiment of the present application. Figure 7 This application provides a schematic diagram of a circuit switch in a second switching state. Figure 8 This application provides a schematic diagram of a circuit switch in a third switching state. Figure 9 This application provides a schematic diagram of a circuit switch in a fourth switching state. Figure 10 This application provides a schematic diagram illustrating the change in the input signal of the operational amplifier output swing, as shown in the embodiments of this application. Figure 11 This is a schematic diagram of the input-output correspondence curves of an input buffer provided in an embodiment of this application; Figure 12 This is a schematic diagram of a single-sided input buffer provided in another embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] The core of this application is to provide a single-sided input buffer and a fully differential input buffer to solve the problem of poor compatibility between wide swing and high precision of input buffers.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As a bridge between the external input signal and the internal modulator, the input buffer's performance directly limits the upper limit of the overall analog-to-digital converter (ADC) performance. Input buffers typically require a wide input range, some even requiring rail-to-rail connections. This places high demands on the output swing of the operational amplifier in traditional input buffer structures, while simultaneously ensuring the linearity of the input buffer's accuracy under different input signals. The single-sided input buffer provided in this application solves these technical problems.

[0023] Figure 1 A schematic diagram of a single-sided input buffer provided in this application is shown below. Figure 1 As shown, it includes an operational amplifier U1, a first switched capacitor circuit 1, and a second switched capacitor circuit 2; The first and second input terminals of operational amplifier U1 correspond to the single-sided output terminal (VOUTP) and single-sided input terminal (VINP) of the single-sided input buffer, respectively; the first input terminal (VI-) of operational amplifier U1 is connected to the output terminal of the inverting amplifier, the first terminal of the first switched capacitor circuit 1 and the first terminal of the second switched capacitor circuit 2; the first output terminal (VO+) and the second output terminal (VO-) of operational amplifier U1 are respectively connected to the common-mode voltage signal VCM through clamping switch 5. The first switched capacitor circuit 1 is connected to the power supply voltage signal and the first output terminal (VO+) of the operational amplifier U1 through the first complementary clock control switch 3; the second switched capacitor circuit 2 is connected to the common-mode voltage signal and the first terminal of the first switch S1 through the second complementary clock control switch 4; the second terminal of the first switch S1 is connected to the input terminal of the inverting amplifier A1. In the switching state formed by the first complementary clock control switch 3, the second complementary clock control switch 4 and the clamping switch 5, the output swing range of the operational amplifier U1 is determined by the relationship between the common-mode voltage signal and the gain coefficient of the inverting amplifier A1 and the changing voltage signal.

[0024] Specifically, Figure 2 This is a schematic diagram of a conventional input buffer, such as... Figure 2 As shown, the circuit consists of two states: sampling and holding. In the sampling state, Φ1 is closed, Φ1P is closed, and Φ2 is open. Sampling capacitors CS1 and CS2 sample the input signals VINP and VINN, and the operational amplifier is not operating at this time. Subsequently, Φ1P opens first, followed by Φ1, which opens and Φ2 closes, and the circuit enters the holding state. At this time, CS1 and CS2 act as feedback capacitors, and the operational amplifier operates. By utilizing the charge conservation at the bottom plate of the sampling capacitor in the two states, the following equation can be derived, where V_CM is the set common-mode voltage of the bottom plate sampling: ; (1) ; (2) Subtracting formula (2) from formula (1) yields formula (3): .

[0025] The differential output voltage increases with the increase of the differential input voltage, indicating that this structure requires a high output swing of the operational amplifier. If the input buffer has a large input range, the operational amplifier is also required to have a wide output swing. Figure 3 This is a schematic diagram showing the operational amplifier swing versus the input signal in a conventional input buffer operational amplifier structure, as shown below. Figure 3 As shown, the output time of the operational amplifier changes with the input time of the operational amplifier, which in turn affects the input time orientation of the input buffer. A larger input time orientation corresponds to a larger output swing range of the operational amplifier.

[0026] Traditional input buffer structures consist of switched capacitor circuits and operational amplifiers. Often, the output of the operational amplifier is the output of the input buffer, and its output voltage equals its input voltage. In this embodiment, as... Figure 1As shown, the first input terminal of the operational amplifier serves as the single-sided output terminal of the single-sided input buffer, and the second input terminal of the operational amplifier serves as the single-sided input terminal. The first input terminal of the operational amplifier is connected to the output terminal of the inverting amplifier, and the first terminals of the first and second switched-capacitor circuits. The number and connection relationships of the components in the first and second switched-capacitor circuits differ. The two switched-capacitor circuits utilize the discrete-time structure of switches and capacitors to replace the resistors in traditional circuits, forming filtering, amplification, and integration functional modules within the operational amplifier structure, achieving high-precision and easily integrated signal processing. The first and second output terminals of the operational amplifier are respectively connected to the common-mode voltage signal via clamping switches. Regarding the clamping switches, when the circuit enters the sampling or reset phase, the clamping switches close, clamping both output terminals of the operational amplifier to the common-mode voltage signal. This forces the output common-mode voltage of the operational amplifier to be fixed at VCM, allowing the transistors inside the operational amplifier to return to a known and stable operating point at the beginning of each sampling cycle. Without this clamping, the op-amp's output common-mode voltage might drift with the input signal, causing the transistor's operating point to deviate from its optimal region, or even enter the nonlinear region. When the switch is closed, VO+ and VO- are forcibly pulled to VCM, ensuring that the op-amp is in a zero-differential-voltage initial state at the start of each cycle. In switched-capacitor circuits, the switching action introduces charge injection errors. Clamping the output to VCM (a low-impedance reference node) allows the charge injected when the switch is open to be absorbed by the large capacitor VCM, without affecting the op-amp's input signal. This effectively reduces the op-amp's DC offset and 1 / f noise. The action of this clamping switch is complementary to the clock-controlled switch of the preceding switched capacitor. During the clock-controlled switch sampling phase, the clamping switch is closed, and the output is clamped to VCM, allowing the capacitor to stably sample the difference between the input signal and VCM. During the clock-controlled switch hold phase, the clamping switch is open, and the op-amp enters negative feedback mode, amplifying and outputting the sampled signal.

[0027] The first switched-capacitor circuit connects to the power supply voltage signal and the first output terminal of the operational amplifier via a first complementary clock control switch. The second switched-capacitor circuit connects to the common-mode voltage signal and the first terminal of the first switch via a second complementary clock control switch. Both switched-capacitor circuits use complementary clock control to switch between sampling and transmission / hold states. The first switched-capacitor circuit is internally connected to the power supply voltage signal, which can be a differential signal and a reference ground signal, or both of which are common-mode reference signals.

[0028] Regarding the settings of the first switch and the inverting amplifier, the closing and opening of the first switch affects the conduction and turn-off of the inverting amplifier. The inverting amplifier provides controllable negative gain, negative impedance, negative feedback components, and phase difference components, which are algebraically superimposed with the signal from the first switched capacitor circuit at the virtual ground summation node of the op-amp to achieve the output voltage change of the input buffer.

[0029] In the switching states comprised of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the output swing range of the operational amplifier is determined by the relationship between the common-mode voltage signal and the gain coefficient of the inverting amplifier and the changing voltage signal. This is based on the various switches of the input buffer, which, in conjunction with chopping, are divided into four states. The output swing range is achieved through combinations of the closed and open states of the complementary clock control switches.

[0030] This application provides a single-sided input buffer. Firstly, the first input terminal of an operational amplifier serves as the single-sided output terminal of the buffer, and the second input terminal serves as the single-sided input terminal. Compared to conventional input buffers, the output terminal of the operational amplifier serves as the output terminal, and its output voltage equals the input voltage. Using the inverting input terminal of the operational amplifier as the buffer's output essentially utilizes the open-loop virtual short characteristic of the operational amplifier, allowing the voltage at the inverting input terminal to follow the voltage at the non-inverting input terminal, thus achieving buffering. In large-signal, high-bandwidth scenarios, the output stage is prone to problems such as insufficient slew rate and nonlinear distortion. Directly using the internal inverting input terminal of the operational amplifier as the output avoids the nonlinearity of the output stage, significantly improving signal fidelity in high-precision, wide-amplitude applications. It reduces the parasitic parameters and noise introduction of external components, resulting in a higher phase margin in the feedback loop and better stability under high-frequency and high-capacitive loads. Secondly, the first input terminal of the operational amplifier is connected to the output terminal of the directional amplifier, and the first terminals of the first and second switched capacitor circuits. The first switched capacitor circuit is connected to the power supply voltage signal and the first output terminal of the operational amplifier via a first complementary clock control switch. The second switched capacitor circuit is connected to the common-mode voltage signal and the first terminal of the first switch via a second complementary clock control switch. The purpose of the connection relationship of the first switched capacitor circuit is to obtain the relationship between the common-mode voltage signal corresponding to the power supply voltage signal, so that the voltage signal at the location of the first switched capacitor circuit is the same as the first output terminal of the operational amplifier, and is a common-mode voltage signal. The purpose of the connection relationship of the second switched capacitor circuit is to obtain the voltage difference between the voltage signals at the first output terminal and the first input terminal of the operational amplifier. This connection relationship, via the second terminal of the first switch connected to the input terminal of the inverting amplifier, ensures that when the first switch is turned on, the gain coefficient of the inverting amplifier changes, and when the input signal of the buffer changes, the corresponding change in the output voltage of the buffer also changes, thereby resetting the first output terminal of the operational amplifier to the common-mode voltage signal. Finally, by controlling the relationship between the gain coefficient of the inverting amplifier and the changing voltage signal, the output swing range of the operational amplifier is controlled within the change in voltage signal corresponding to the switching cycle of the switching states formed by the first complementary clock control switch, the second complementary clock control switch, and the clamping switch. The common-mode voltage signal is adjusted based on this signal by controlling the gain coefficient of the inverting amplifier and setting the changing voltage signal. This reduces the requirements of the input buffer for the operational amplifier's output swing, eliminating the need to follow the slope change of the operational amplifier's input signal and reducing the impact of different output swings on the linearity of the input buffer. This achieves a balance between wide swing and high gain while reducing the impact of different input voltages on the gain and improving linearity across the entire input range.

[0031] In some embodiments, such as Figure 1As shown, the first switched capacitor circuit 1 includes a first capacitor C1, a second capacitor C2 and a first complementary clock control switch 3, wherein the first complementary clock control switch 3 includes a first sub-complementary clock control switch corresponding to the first capacitor C1 and a second sub-complementary clock control switch corresponding to the second capacitor C2; the first sub-complementary clock control switch includes a second switch S2 and a third switch S3, and the second sub-complementary clock control switch includes a fourth switch S4 and a fifth switch S5. The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are both connected to the first input terminal of the operational amplifier U1; the second terminal of the first capacitor C1 is connected to the first terminal of the second switch S2 and the first terminal of the third switch S3; the second terminal of the second capacitor C2 is connected to the first terminal of the fourth switch S4 and the first terminal of the fifth switch S5. The second terminal of the second switch S2 and the second terminal of the fifth switch S5 are both connected to the first output terminal of the operational amplifier U1; the second terminal of the third switch S3 is connected to the power supply voltage signal, and the second terminal of the fourth switch S4 is connected to the ground signal; wherein, the sum of the voltage values ​​corresponding to the power supply voltage signal and the ground signal is equal to the voltage value corresponding to the common mode voltage signal.

[0032] The first switched-capacitor circuit includes two capacitors and a first complementary clock control switch. The first complementary clock control switch includes a first sub-complementary clock control switch and a second sub-complementary clock control switch corresponding to the two capacitors. Each sub-complementary clock control switch includes two switches connected as follows: the first terminals of the first and second capacitors are both connected to the first input terminal of the operational amplifier; the second terminal of the first capacitor is connected to the first terminals of the second and third switches; the second terminal of the second capacitor is connected to the first terminals of the fourth and fifth switches; the second terminals of the second and fifth switches are both connected to the first output terminal of the operational amplifier; the second terminal of the third switch is connected to the power supply voltage signal, and the second terminal of the fourth switch is connected to the ground signal.

[0033] The internal connection relationship of the first switched capacitor circuit provided in this embodiment ensures that the output common-mode voltage of the fully differential operational amplifier is stabilized at the voltage value corresponding to the common-mode voltage signal, so as to ensure the normal amplification and processing of the differential signal.

[0034] In other embodiments, Figure 4 A schematic diagram of another single-sided input buffer provided in an embodiment of this application is shown below. Figure 4 As shown, the first switched capacitor circuit 1 includes a fifth capacitor C5 and a first complementary clock control switch 3, wherein the first complementary clock control switch 3 includes a fifth sub-complementary clock control switch corresponding to the fifth capacitor C5, and the fifth sub-complementary clock control switch includes a tenth switch S10 and an eleventh switch S11. The first terminal of the fifth capacitor C5 is connected to the first input terminal of the operational amplifier U1; the second terminal of the fifth capacitor C5 is connected to the first terminal of the tenth switch S10 and the first terminal of the eleventh switch S11; the second terminal of the tenth switch S10 is connected to the first output terminal of the operational amplifier U1; the second terminal of the eleventh switch S11 is connected to the power supply voltage signal; wherein, the voltage value corresponding to the power supply voltage signal is equal to the voltage value corresponding to the common mode voltage signal.

[0035] Specifically, unlike the connection relationship in the above embodiments, the first switched capacitor circuit in this embodiment contains only one capacitor, and its complementary clock control switch has two switches corresponding to the fifth sub-complementary clock control switch. This corresponds to the switching path of one capacitor in the above embodiments. The same power supply voltage signal as the common-mode voltage signal is connected to the second terminal of the eleventh switch.

[0036] The simplified single-capacitor structure provided in this embodiment within the first switched capacitor circuit samples only one output, which, in conjunction with the common-mode voltage signal, reflects the common-mode signal. This simplifies timing, reduces one capacitor and one set of switches, saves chip area, and reduces parasitic capacitance and process complexity. Only the switching timing of a single capacitor needs to be controlled, eliminating the need for strict synchronization of the non-overlapping clocks of the two capacitors, thus reducing the design difficulty of the digital control logic.

[0037] In some embodiments, such as Figure 1 As shown, the second switched capacitor circuit 2 includes a third capacitor C3, a fourth capacitor C4, and a second complementary clock control switch 4. The second complementary clock control switch 4 includes a third sub-complementary clock control switch corresponding to the third capacitor C3 and a fourth sub-complementary clock control switch corresponding to the fourth capacitor C4. The third sub-complementary clock control switch includes a sixth switch S6 and a seventh switch S7, and the fourth sub-complementary clock control switch includes an eighth switch S8 and a ninth switch S9. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are both connected to the first input terminal of the operational amplifier U1; the second terminal of the third capacitor C3 is connected to the first terminal of the sixth switch S6 and the first terminal of the seventh switch S7; the second terminal of the fourth capacitor C4 is connected to the first terminal of the eighth switch S8 and the first terminal of the ninth switch S9. The second terminal of the sixth switch S6 and the second terminal of the ninth switch S9 are both connected to the first terminal of the first switch; the second terminal of the seventh switch S7 and the second terminal of the eighth switch S8 are both connected to the common-mode voltage signal.

[0038] like Figure 1As shown, the second switched-capacitor circuit includes two capacitors and a second complementary clock control switch. The second complementary clock control switch includes a third sub-complementary clock control switch and a fourth sub-complementary clock control switch corresponding to the two capacitors. Each sub-complementary clock control switch includes two switches, connected as follows: the first terminals of the third and fourth capacitors are both connected to the first input terminal of the operational amplifier; the second terminal of the third capacitor is connected to the first terminals of the sixth and seventh switches; the second terminal of the fourth capacitor is connected to the first terminals of the eighth and ninth switches; the second terminals of the sixth and ninth switches are both connected to the first terminal of the first switch; and the second terminals of the seventh and eighth switches are both connected to a common-mode voltage signal.

[0039] The third and fourth capacitors are connected to the common-mode node of the operational amplifier's output for sampling, storing the superimposed charge of the common-mode voltage and the operational amplifier's offset voltage. If the input is switched to the first input of the operational amplifier, the stored charge is injected into the summing node, generating a correction voltage equal in magnitude but opposite in polarity to the offset voltage, thereby canceling the operational amplifier's input offset.

[0040] In this embodiment, the internal device connections of the second switched capacitor, in conjunction with the inverting amplifier, provide an inverted reference path, ensuring that the injected calibration charge is precisely out of phase with the offset voltage, thus achieving a more stable offset suppression effect. Using switched capacitor technology, no additional resistors or amplifier quiescent current are required; dynamic power consumption is only generated during clock transitions, making it ideal for low-power, high-precision analog front-ends.

[0041] Furthermore, the operating state of the single-sided input buffer in any of the foregoing embodiments can be divided into four sequentially cycling switching control states. Figure 5 A timing diagram for four switching states is provided in an embodiment of this application, such as... Figure 5 As shown, the switch is on and off in four states, and the four states form a cycle.

[0042] In the first switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second, fifth, seventh, and ninth switches are controlled to close, and the first, third, fourth, clamping, sixth, and eighth switches are controlled to open. When the change in the input voltage signal of the buffer is the first voltage signal, the change in the output voltage signal of the first output terminal of the operational amplifier is determined to be the first voltage signal by utilizing the virtual short characteristic of the operational amplifier, so as to determine the change in the voltage signal at the first switch as the first voltage signal.

[0043] Figure 6 This application provides a schematic diagram of a circuit switch in a first switching state, as shown in the embodiment of the present application. Figure 6As shown, the loop forms negative feedback. When the change in the input voltage signal VINP of the buffer is equal to the first voltage signal, utilizing the characteristic that capacitor voltage cannot change abruptly, and due to the virtual short of the operational amplifier, the lower plate of the fourth capacitor is connected to the common-mode voltage signal, and the upper plate is connected to the output of the inverting amplifier. At this time, the circuit is in the offset sampling stage, and the voltage difference stored on the fourth capacitor is VI1-Vcm. When the lower plate of the fourth capacitor is switched to the first input terminal VOUTP of the operational amplifier, and the upper plate remains connected to VI1, the circuit enters the negative feedback offset calibration stage. The voltage Vc across the fourth capacitor = voltage of the upper plate - voltage of the lower plate. At the instant of clock transition, the charge cannot change abruptly, and its voltage difference cannot change abruptly either. Therefore, VI1-VOUTP = VI1-VCM. When negative feedback is entered, the second input terminal of the operational amplifier increases by ΔV. According to the virtual short characteristic, the inverting input terminal VOUTP will also increase by ΔV, that is: VO+=VCM. At this time, VO+=VCM+ΔV. Similarly, the voltage at VI1 also increases by ΔV. Since the lower plate of capacitor C4 is connected to VCM in state four, the voltage at VI1 is VCM+ΔV.

[0044] In the second switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second, fifth, sixth, and eighth switches are opened, and the first, third, fourth, clamping, seventh, and ninth switches are closed. The voltage change at the single-sided output terminal of the buffer is determined to be obtained from the relationship between the gain coefficient of the inverting amplifier and the change corresponding to the voltage signal. Furthermore, the voltage signal at the first output terminal of the operational amplifier is reset to the common-mode voltage signal by turning on the clamping switch.

[0045] Specifically, Figure 7 This application provides a schematic diagram of a circuit switch in a second switching state, as shown in the embodiment of the present application. Figure 7 As shown, in state two, the switch connected to the inverting amplifier A1 is turned on. Since the input voltage VI1 of the amplifier increases by ΔV at this time, assuming the gain of the inverting amplifier is... Then the voltage change at the VOUTP terminal is: ; (4) At this time, the first output terminal of the operational amplifier is reset to VCM.

[0046] In the third switch state, which consists of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second, fifth, sixth, and eighth switches are closed, and the first, third, fourth, clamping, seventh, and ninth switches are opened. This ensures that the input voltage at the first input terminal of the operational amplifier in its initial state is equal to the output voltage at the output terminal of the buffer, and this is determined by the relationship between the input voltage at the input terminal of the buffer, the gain coefficient of the inverting amplifier, and the change in the voltage signal. When the voltage signals at the first input terminal and the first output terminal of the operational amplifier reach equilibrium, the output voltage at the output terminal of the buffer, the first input terminal of the operational amplifier, the second input terminal of the operational amplifier, and the output voltage at the input terminal of the buffer are all equal. The output voltage at the first output terminal of the operational amplifier is determined by the common-mode voltage signal and the relationship between the gain coefficient of the inverting amplifier and the voltage signal.

[0047] Specifically, Figure 8 This application provides a schematic diagram of a circuit switch in a third switching state, as shown in the embodiment of the present application. Figure 8 As shown, in state three, due to the initial state: ; (5) At this point, due to the differential voltage at the input of the operational amplifier, VO+ and VI- increase until they reach equilibrium. In the equilibrium state, VOUT = VI- = VI+ = VINP. .

[0048] In the fourth switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second, fifth, seventh, and ninth switches are controlled to open, and the first, third, fourth, clamping, sixth, and eighth switches are controlled to close, thus determining that the output voltage at the first output terminal of the operational amplifier, the input voltage at the first input terminal of the operational amplifier, the voltage at the inverting amplifier, and the common-mode voltage are equal.

[0049] Figure 9 This application provides a schematic diagram of a circuit switch in a fourth switching state, as shown in the embodiment of the present application. Figure 9 As shown, in state four, the situation is the same as in state two. Therefore, states one, two, three, and four form a cycle. In states one and three, VOUTP = VINP, and VOUTP serves as the output of this input buffer, which is then sampled at the next stage sampling capacitor.

[0050] The four switching states provided in this embodiment are designed to greatly reduce the output swing required by the operational amplifier under the same input conditions, solve the problem of the input buffer being constrained under low voltage conditions, and reduce the impact of different output swings on the linearity of the input buffer.

[0051] In some embodiments, a controller is also included; the controller is connected to the first output terminal of the operational amplifier and is used to reset the output voltage of the first output terminal of the operational amplifier to a common-mode voltage signal.

[0052] Specifically, in state three, a reset setting is used to reset to the common-mode voltage signal, ensuring that the operational amplifier's output time varies with the operational amplifier's output time. Figure 10 This application provides a schematic diagram illustrating the change in the input signal of the operational amplifier output swing, as shown in the embodiment of the present application. Figure 10 As shown, in the third state, after being directly reset to the common-mode voltage signal, the cycle repeats, so that the output swing of the operational amplifier is only proportional to the change in the input signal within the cycle, which can be controlled by the gain of the inverting amplifier in the structure. Figure 11 A schematic diagram of the input-output correspondence curves of an input buffer provided in an embodiment of this application is shown below. Figure 11 As shown, the output voltage of the input buffer changes with the input voltage of the input buffer.

[0053] This embodiment provides a method to output a reset signal to a common-mode voltage signal via the controller, thereby resetting the input buffer in state three. This reduces the impact of different output swings on the linearity of the input buffer and avoids the inability to balance the wide swing and high precision of the input buffer due to changes in output swing.

[0054] In some embodiments, the first complementary clock control switch, the second complementary clock control switch, and the clamping switch are of the same type, namely, a single-pole single-throw switch or a switching transistor.

[0055] Specifically, a single-pole single-throw switch is essentially an ideal switch, free from parasitics, delays, and charge injection. A single-pole single-throw switch implemented using an N-channel metal-oxide-semiconductor (NMOS) or P-channel metal-oxide-semiconductor (PMOS) transistor is a physical component in an actual chip and exhibits parasitic capacitance, on-resistance, charge injection, and clock feedthrough.

[0056] Different types of switches (such as single-pole single-throw versus other types, NMOS versus PMOS) introduce different parasitic capacitances and resistances. Using switches of the same type ensures a high degree of matching of parasitic parameters across branches, preventing signal distortion or a decrease in common-mode rejection ratio (CMRR) due to parasitic differences. This is particularly important for the common-mode feedback and offset calibration modules of fully differential op-amps.

[0057] Switched-capacitor circuits rely on non-overlapping clocks to ensure that the sampling and feedback phases of the capacitors do not overlap. Switches of the same type (such as MOSFETs made of the same process) have consistent turn-on / turn-off delays, ensuring that all switches operate precisely on the same clock edge. If the switch types are different, the delay difference will cause clock overlap, leading to charge crosstalk between capacitors and compromising the stability of the feedback loop.

[0058] All switches provided in this embodiment are of the same type, and all switch types are kept consistent in order to ensure the symmetry of circuit performance, timing consistency and charge injection matching.

[0059] In some embodiments, Figure 12 A schematic diagram of a single-sided input buffer provided in another embodiment of this application is shown below. Figure 12 As shown, when the switching types of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch are MOS transistors, each switch is an NMOS transistor; the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, and the ninth switch correspond to the first switching transistor NM1, the second switching transistor NM2, the third switching transistor NM3, the fourth switching transistor NM4, the fifth switching transistor NM5, the sixth switching transistor NM6, the seventh switching transistor NM7, the eighth switching transistor NM8, and the ninth switching transistor NM9, respectively; the clamping switch includes the twelfth switching transistor NM12 and the thirteenth switching transistor NM13; the gate of each switching transistor is connected to the corresponding control signal CTRL; The drain of the first switch NM1 is connected to the drain of the sixth switch NM6 and the drain of the ninth switch NM9, and the source of the first switch NM1 is connected to the input terminal of the inverting amplifier A1. The drain of the second switching transistor NM2 is connected to the first output terminal of the operational amplifier U1, and the source of the second switching transistor NM2 is connected to the second terminal of the first capacitor C1. The drain of the third switching transistor NM3 is connected to the power supply voltage signal, and the source of the third switching transistor NM3 is connected to the second terminal of the first capacitor C1. The drain of the fourth switch NM4 is connected to the ground signal, and the source of the fourth switch NM4 is connected to the second terminal of the second capacitor C2. The drain of the fifth switching transistor NM5 is connected to the first output terminal of the operational amplifier U1, and the source of the fifth switching transistor NM5 is connected to the second terminal of the second capacitor C2. The source of the sixth switch NM6 is connected to the second terminal of the third capacitor C3, and the source of the ninth switch NM9 is connected to the second terminal of the fourth capacitor C4. The drains of the seventh switch NM7 and the eighth switch NM8 are both connected to a common-mode voltage signal; the source of the seventh switch NM7 is connected to the second terminal of the third capacitor C3, and the source of the eighth switch NM8 is connected to the second terminal of the fourth capacitor C4. The source of the twelfth switch NM12 is connected to the first output terminal of the operational amplifier U1, and the source of the thirteenth switch NM13 is connected to the second output terminal of the operational amplifier U1; the drain of the twelfth switch NM12 is connected to the drain of the thirteenth switch NM13 and is connected to a common-mode voltage signal.

[0060] Specifically, if an NMOS transistor is used as the switching transistor, the corresponding control signals can all be sent by the controller. Figure 5 The timing diagram sends corresponding control signals at different times to control the corresponding switching transistors to turn on and off, achieving conduction in four states. The specific on / off states for different states have been analyzed in the above embodiments regarding when to turn on, and will not be repeated here. The settings can be adjusted according to actual conditions.

[0061] The embodiment provides a method for turning on and off using MOS switches. Switches of the same type can ensure a high degree of matching of parasitic parameters in each branch, avoiding signal distortion or a decrease in common-mode rejection ratio (CMRR) due to parasitic differences.

[0062] In some embodiments, such as Figure 1 As shown, it also includes a sampling capacitor CS; The first terminal of the sampling capacitor CS is connected to the single-sided output terminal of the single-sided input buffer, the first input terminal of the operational amplifier U1, and the first terminals of the first switched capacitor circuit 1 and the second switched capacitor circuit 2 respectively; the second terminal of the sampling capacitor CS is grounded. The sampling capacitor CS is used to receive the output voltage of the single-sided output terminal of the single-sided input buffer for sampling processing.

[0063] Specifically, the sampling capacitor is configured to take into account the output voltage of the single-sided output terminal of the single-ended input buffer, which will be used for sampling in subsequent application scenarios. The corresponding connection relationship is as follows: the first terminal of the sampling capacitor is connected to the single-sided output terminal of the single-ended input buffer, the first input terminal of the operational amplifier, and the first terminal of the first switched capacitor circuit and the second switched capacitor circuit respectively; the second terminal of the sampling capacitor is grounded.

[0064] The sampling capacitor provided in this embodiment is used for sampling the output of the subsequent input buffer at the sampling capacitor to enrich the diversity of application scenarios.

[0065] In some embodiments, the first capacitor and the second capacitor have the same capacitance value; the third capacitor and the fourth capacitor have the same capacitance value.

[0066] Specifically, symmetrical processing of differential signals is achieved through capacitor matching, thereby suppressing common-mode noise, canceling non-ideal effects, and improving the accuracy and stability of the circuit. Combined with... Figure 1 Specifically, the capacitance values ​​of the first and second capacitors are crucial to ensure accurate and symmetrical averaging of the differential output. Otherwise, common-mode voltage extraction will introduce errors, causing common-mode feedback to fail. Under ideal matching, the differential signal components will cancel each other out at the summing node, with only the common-mode component entering the feedback path. If the capacitors are mismatched, the differential signal will leak into the common-mode feedback loop, leading to differential gain fluctuations and signal distortion.

[0067] The identical capacitance values ​​of the third and fourth capacitors ensure symmetrical and equal injection of calibration charges from both paths, guaranteeing precise cancellation of offset voltage. Otherwise, residual offset would be introduced. As an auxiliary unit for the main common-mode feedback, the symmetrical C3 and C4 ensure balanced compensation for common-mode voltage fluctuations, preventing common-mode voltage shifts or oscillations caused by capacitor mismatch. During clock switching, the matched capacitors exhibit perfectly synchronized charge transfer speed and magnitude, ensuring synchronization between calibration actions and the main circuit timing, avoiding asynchronous noise and timing errors.

[0068] The capacitance values ​​of the four capacitors provided in this embodiment, along with the symmetrical capacitor structure, effectively suppress common-mode interference, significantly improving the circuit's immunity to power supply noise and environmental interference. Matched capacitors and switches can offset most charge injection and clock feedthrough effects, thereby reducing the circuit's offset voltage and noise level. When differential signals are transmitted in the symmetrical capacitor network, amplitude or phase errors are not introduced due to mismatch, ensuring signal fidelity.

[0069] Furthermore, this application also provides a fully differential input buffer, which is composed of two of the above-mentioned single-sided input buffers; the first output terminal of the operational amplifier in one single-sided input buffer is connected to the first output terminal of the operational amplifier in the other single-sided input buffer; and the second output terminal of the operational amplifier in one single-sided input buffer is connected to the second output terminal of the operational amplifier in the other single-sided input buffer.

[0070] For a description of the fully differential input buffer provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the single-sided input buffer described above.

[0071] Furthermore, this application also provides a digital-to-analog converter, including the aforementioned fully differential input buffer.

[0072] For an introduction to the digital-to-analog converter provided in this application, please refer to the above method embodiments. This application will not repeat the details here, but it has the same beneficial effects as the fully differential input buffer described above.

[0073] The foregoing has provided a detailed description of a single-sided input buffer and a fully differential input buffer provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0074] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A single-sided input buffer, characterized in that, Includes an operational amplifier, a first switched capacitor circuit, and a second switched capacitor circuit; The first and second input terminals of the operational amplifier correspond to the single-sided output and single-sided input terminals of the single-sided input buffer, respectively; the first input terminal of the operational amplifier is connected to the output terminal of the inverting amplifier, the first terminal of the first switched capacitor circuit, and the first terminal of the second switched capacitor circuit; the first and second output terminals of the operational amplifier are respectively connected to the common-mode voltage signal through clamping switches. The first switched capacitor circuit is connected to the power supply voltage signal and the first output terminal of the operational amplifier through a first complementary clock control switch; the second switched capacitor circuit is connected to the common-mode voltage signal and the first terminal of the first switch through a second complementary clock control switch; the second terminal of the first switch is connected to the input terminal of the inverting amplifier, so that the output swing range of the operational amplifier can be determined by the relationship between the common-mode voltage signal and the gain coefficient of the inverting amplifier and the changing voltage signal in the switching state formed by the first complementary clock control switch, the second complementary clock control switch and the clamping switch.

2. The single-sided input buffer according to claim 1, characterized in that, The first switched capacitor circuit includes a first capacitor, a second capacitor, and a first complementary clock control switch, wherein the first complementary clock control switch includes a first sub-complementary clock control switch corresponding to the first capacitor and a second sub-complementary clock control switch corresponding to the second capacitor; the first sub-complementary clock control switch includes a second switch and a third switch, and the second sub-complementary clock control switch includes a fourth switch and a fifth switch; The first terminal of the first capacitor and the first terminal of the second capacitor are both connected to the first input terminal of the operational amplifier; the second terminal of the first capacitor is connected to the first terminal of the second switch and the first terminal of the third switch; the second terminal of the second capacitor is connected to the first terminal of the fourth switch and the first terminal of the fifth switch. The second terminal of the second switch and the second terminal of the fifth switch are both connected to the first output terminal of the operational amplifier; the second terminal of the third switch is connected to the power supply voltage signal, and the second terminal of the fourth switch is connected to the ground signal; wherein, the sum of the voltage values ​​corresponding to the power supply voltage signal and the ground signal is equal to the voltage value corresponding to the common mode voltage signal.

3. The single-sided input buffer according to claim 2, characterized in that, The second switched capacitor circuit includes a third capacitor, a fourth capacitor, and a second complementary clock control switch, wherein the second complementary clock control switch includes a third sub-complementary clock control switch corresponding to the third capacitor and a fourth sub-complementary clock control switch corresponding to the fourth capacitor; the third sub-complementary clock control switch includes a sixth switch and a seventh switch, and the fourth sub-complementary clock control switch includes an eighth switch and a ninth switch; The first terminal of the third capacitor and the first terminal of the fourth capacitor are both connected to the first input terminal of the operational amplifier; the second terminal of the third capacitor is connected to the first terminal of the sixth switch and the first terminal of the seventh switch; the second terminal of the fourth capacitor is connected to the first terminal of the eighth switch and the first terminal of the ninth switch. The second terminal of the sixth switch and the second terminal of the ninth switch are both connected to the first terminal of the first switch; the second terminal of the seventh switch and the second terminal of the eighth switch are both connected to a common-mode voltage signal.

4. The single-sided input buffer according to claim 1, characterized in that, The first switched capacitor circuit includes a fifth capacitor and a first complementary clock control switch, wherein the first complementary clock control switch includes a fifth sub-complementary clock control switch corresponding to the fifth capacitor, and the fifth sub-complementary clock control switch includes a tenth switch and an eleventh switch. The first terminal of the fifth capacitor is connected to the first input terminal of the operational amplifier; the second terminal of the fifth capacitor is connected to the first terminal of the tenth switch and the first terminal of the eleventh switch; the second terminal of the tenth switch is connected to the first output terminal of the operational amplifier; the second terminal of the eleventh switch is connected to a power supply voltage signal; wherein, the voltage value corresponding to the power supply voltage signal is equal to the voltage value corresponding to the common-mode voltage signal.

5. The single-sided input buffer according to claim 3, characterized in that, The single-sided input buffer operates in four sequentially cycling states: In the first switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the seventh switch, and the ninth switch are controlled to close, and the first switch, the third switch, the fourth switch, the clamping switch, the sixth switch, and the eighth switch are controlled to open. When the change in the input voltage signal of the buffer is the first voltage signal, the change in the output voltage signal of the first output terminal of the operational amplifier is determined to be the first voltage signal by utilizing the virtual short characteristic of the operational amplifier, so as to determine the change in the voltage signal at the first switch as the first voltage signal. In the second switch state formed by the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the sixth switch, and the eighth switch are controlled to open, and the first switch, the third switch, the fourth switch, the clamping switch, the seventh switch, and the ninth switch are controlled to close. The voltage change at the single-sided output terminal of the buffer is determined to be obtained from the relationship between the gain coefficient of the inverting amplifier and the change corresponding to the change in the voltage signal. Furthermore, the voltage signal at the first output terminal of the operational amplifier is reset to the common-mode voltage signal by turning on the clamping switch. In the third switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the sixth switch, and the eighth switch are controlled to close, and the first switch, the third switch, the fourth switch, the clamping switch, the seventh switch, and the ninth switch are controlled to open. It is determined that the input voltage of the first input terminal of the operational amplifier in the initial state is equal to the output voltage of the output terminal of the buffer, and is obtained from the relationship between the input voltage of the input terminal of the buffer, the gain coefficient of the inverting amplifier, and the change in the corresponding amount of the changing voltage signal. When the voltage signals at the first input terminal and the first output terminal of the operational amplifier reach a balanced state, the output voltage at the output terminal of the buffer, the output voltage at the first input terminal of the operational amplifier, the output voltage at the second input terminal of the operational amplifier, and the output voltage at the input terminal of the buffer are all equal. The output voltage at the first output terminal of the operational amplifier is determined by the common-mode voltage signal and the relationship between the gain coefficient of the inverting amplifier and the changing voltage signal. In the fourth switch state consisting of the first complementary clock control switch, the second complementary clock control switch, and the clamping switch, the second switch, the fifth switch, the seventh switch, and the ninth switch are controlled to open, and the first switch, the third switch, the fourth switch, the clamping switch, the sixth switch, and the eighth switch are controlled to close, thereby determining that the output voltage of the first output terminal of the operational amplifier, the input voltage of the first input terminal of the operational amplifier, the voltage at the inverting amplifier, and the common-mode voltage are equal.

6. The single-sided input buffer according to claim 5, characterized in that, It also includes a controller; the controller is connected to the first output terminal of the operational amplifier and is used to reset the output voltage of the first output terminal of the operational amplifier to the common-mode voltage signal.

7. The single-sided input buffer according to claim 3, characterized in that, When the first complementary clock control switch, the second complementary clock control switch, and the clamping switch are all MOS transistors, each switch is an NMOS transistor; the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, and the ninth switch correspond to the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, and the ninth switch transistor, respectively; the clamping switch includes a twelfth switch transistor and a thirteenth switch transistor; the gate of each switch transistor is connected to the corresponding control signal; The drain of the first switching transistor is connected to the drain of the sixth switching transistor and the drain of the ninth switching transistor, and the source of the first switching transistor is connected to the input terminal of the inverting amplifier. The drain of the second switching transistor is connected to the first output terminal of the operational amplifier, and the source of the second switching transistor is connected to the second terminal of the first capacitor. The drain of the third switch is connected to the power supply voltage signal, and the source of the third switch is connected to the second terminal of the first capacitor. The drain of the fourth switch is connected to a ground signal, and the source of the fourth switch is connected to the second terminal of the second capacitor. The drain of the fifth switching transistor is connected to the first output terminal of the operational amplifier, and the source of the fifth switching transistor is connected to the second terminal of the second capacitor. The source of the sixth switch is connected to the second terminal of the third capacitor, and the source of the ninth switch is connected to the second terminal of the fourth capacitor. The drains of the seventh and eighth switching transistors are both connected to a common-mode voltage signal; the source of the seventh switching transistor is connected to the second terminal of the third capacitor, and the source of the eighth switching transistor is connected to the second terminal of the fourth capacitor. The source of the twelfth switch is connected to the first output terminal of the operational amplifier, and the source of the thirteenth switch is connected to the second output terminal of the operational amplifier; the drain of the twelfth switch is connected to the drain of the thirteenth switch and is connected to a common-mode voltage signal.

8. The single-sided input buffer according to any one of claims 1 to 7, characterized in that, It also includes the sampling capacitor; The first terminal of the sampling capacitor is connected to the single-sided output terminal of the single-sided input buffer, the first input terminal of the operational amplifier, and the first terminals of the first switched capacitor circuit and the second switched capacitor circuit respectively; the second terminal of the sampling capacitor is grounded. The sampling capacitor is used to receive the output voltage of the single-sided output terminal of the single-sided input buffer for sampling processing.

9. The single-sided input buffer according to claim 3, characterized in that, The first capacitor and the second capacitor have the same capacitance value; the third capacitor and the fourth capacitor have the same capacitance value; Alternatively, the first complementary clock control switch, the second complementary clock control switch, and the clamping switch may be of the same type, namely, a single-pole single-throw switch or a switching transistor.

10. A fully differential input buffer, characterized in that, It is composed of two single-sided input buffers as described in any one of claims 1 to 9; the first output terminal of the operational amplifier in one single-sided input buffer is connected to the first output terminal of the operational amplifier in the other single-sided input buffer; the second output terminal of the operational amplifier in one single-sided input buffer is connected to the second output terminal of the operational amplifier in the other single-sided input buffer.

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