A charge transfer based switched capacitor circuit

Abstract

The application discloses a switch capacitor circuit based on charge transfer, a sampling control end of a sampling clock generation circuit is electrically connected with a sampling switch control end of a sampling switch capacitor array; a control end of a transfer driving array is connected with a driving control circuit, and the driving control circuit controls on-off of each switch of the transfer driving array; an output end of the transfer driving array is electrically connected with a storage switch capacitor array, cyclic sampling is continuously carried out through the sampling clock generation circuit and the sampling switch capacitor array, and the voltage value sampled cyclically is transferred to the storage switch capacitor array through the transfer driving array; an output end of the storage switch capacitor array is electrically connected with a quantization circuit; a quantization readout control circuit receives readout data of the quantization circuit, and outputs the data to an off-chip through serial output. The circuit can avoid the contradiction between the sampling depth and the analog bandwidth, significantly improve the bandwidth of an analog bus, and increase the sampling depth of the switch capacitor array.

Description

Technical Field

[0001] This invention relates to the field of waveform digitization electronics technology, and more particularly to a switched capacitor circuit based on charge transfer. Background Technology

[0002] Waveform digitization electronics is a key development direction for front-end electronics in future particle physics experiments, playing a vital role in various particle physics studies such as gamma-ray detection, time-of-flight detection systems, and neutrino experiments. By analyzing the waveform output by the detector, all the physical information contained within it can be obtained. The analog waveform signal generated by the detector is converted into digital waveform data via an ADC (analog-to-digital converter), and then fitted, interpolated, and discriminated by a digital signal processing system to extract the time information contained in the waveform. Traditional waveform digitization schemes typically employ high-speed ADCs, which suffer from low integration, high cost, and high power consumption, and their efficiency is limited as the sampling rate increases.

[0003] To address the aforementioned issues, existing technologies have proposed a waveform digitization method for application-specific integrated circuits (ASICs) based on switched-capacitor arrays (SCA). This method employs a "simulation-first, digital-later" strategy, using a switched-capacitor matrix to sample analog signals at high speed, followed by digitization using a slow, high-precision ADC, thus reconciling the conflict between high-speed sampling and high-precision analog-to-digital conversion. This technology offers advantages such as high sampling rate, low power consumption, high channel integration, and low cost, making it particularly suitable for high-precision time measurement applications. For traditional switched-capacitor arrays, the highest possible sampling rate is typically required to capture the leading edge of fast signals, and the largest possible sampling depth is needed to increase the signal width that can be acquired in a single sample. However, a larger sampling depth requires more switched capacitors on the input bus, which significantly reduces the bandwidth of the input analog bus, thereby limiting the rise time of the input signal. Therefore, while ensuring a high sampling rate for SCA (Switched Capacitor Array) ASICs, the sampling depth and analog bandwidth of the SCA are often contradictory specifications.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a charge-transfer based switched-capacitor circuit to solve the aforementioned technical problems in the prior art. The circuit of this invention can circumvent the contradiction between sampling depth and analog bandwidth. By reducing the number of switched capacitors connected to the analog bus, the bandwidth of the analog bus is significantly improved; and by increasing the number of storage capacitors, the sampling depth of the switched-capacitor array is significantly increased.

[0006] The objective of this invention is achieved through the following technical solution: A switched-capacitor circuit based on charge transfer, the switched-capacitor circuit comprising a sampling clock generation circuit, a sampling switched-capacitor array, a charge transfer drive array, a drive control circuit, a storage switched-capacitor array, a quantization circuit, and a quantization readout control circuit, wherein: The sampling control terminal of the sampling clock generation circuit is electrically connected to the sampling switch control terminal of the sampling switch capacitor array; The output of the sampling switched capacitor array is electrically connected to the transport drive array; The control terminal of the transport drive array is connected to the drive control circuit, which controls the on / off state of each switch in the transport drive array. The output of the transport drive array is electrically connected to the storage switched capacitor array. The sampling clock generation circuit and the sampling switched capacitor array continuously perform cyclic sampling, and the cyclically sampled voltage values ​​are transferred to the storage switched capacitor array through the transport drive array. The output of the storage switched capacitor array is electrically connected to the quantization circuit; the voltage value stored in the storage switched capacitor array is quantized multiple times according to the storage order under the action of the quantization circuit, converting the analog voltage value into a digital code value. The quantization readout control circuit is electrically connected to the quantization circuit, controls the quantization circuit to perform quantization, receives the readout data from the quantization circuit, and outputs the data serially to an external device.

[0007] Compared with the prior art, the circuit provided by the present invention can avoid the contradiction between sampling depth and analog bandwidth. By reducing the number of switched capacitors connected to the analog bus, the bandwidth of the analog bus is significantly improved. By increasing the number of storage capacitors, the sampling depth of the switched capacitor array is significantly increased. This solution is applicable to the digital readout application of detector waveforms in SCA. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a switched capacitor circuit based on charge transfer provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the transport drive array described in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the first-stage driver in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of the second-stage driver according to an embodiment of the present invention; Figure 5 This is a timing diagram of the control signal for the sampling switch capacitor sampling switch provided in an embodiment of the present invention; Figure 6 This is a timing diagram of the control signals for driving the switched capacitor and the switch provided in an embodiment of the present invention; Figure 7 The timing diagram of control signals for each switch of the first-stage driver provided in this embodiment of the invention; Figure 8 The timing diagram of the control signals of each switch of the second-stage driver provided in the embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0011] First, the following explanations are provided for the terms that may be used in this article: The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0012] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0013] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0014] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0015] like Figure 1 The diagram shown is a schematic representation of a charge-transfer based switched-capacitor circuit according to an embodiment of the present invention. The switched-capacitor circuit includes a sampling clock generation circuit, a sampling switched-capacitor array, a charge transfer drive array, a drive control circuit, a storage switched-capacitor array, a quantization circuit, and a quantization readout control circuit, wherein: The sampling control terminal of the sampling clock generation circuit is electrically connected to the sampling switch control terminal of the sampling switch capacitor array; in this specific implementation, the sampling rate is set to 10 GHz, and the interval between the clock pulses generated by the sampling clock generation circuit is 100 ps. The output of the sampling switched capacitor array is electrically connected to the transport drive array; The control terminal of the transport drive array is connected to the drive control circuit, which controls the on / off state of each switch in the transport drive array. The output of the transport drive array is electrically connected to the storage switched capacitor array. The sampling clock generation circuit and the sampling switched capacitor array continuously perform cyclic sampling, and the cyclically sampled voltage values ​​are transferred to the storage switched capacitor array through the transport drive array. The output of the storage switched capacitor array is electrically connected to the quantization circuit; the voltage value stored in the storage switched capacitor array is quantized multiple times according to the storage order under the action of the quantization circuit, converting the analog voltage value into a digital code value. The quantization readout control circuit is electrically connected to the quantization circuit, controls the quantization circuit to perform quantization, receives the readout data from the quantization circuit, and outputs the data serially to an external device.

[0016] like Figure 1 As shown, in order to allow the transport drive array sufficient time to transport charge, the sampling switched capacitor array is divided into four groups. During the sampling process of the other three groups of sampling switched capacitor arrays, each group of sampling switched capacitor arrays is connected to the transport drive array to transport charge. Each sampling switched capacitor array consists of multiple sampling switched capacitor units. Each sampling switched capacitor unit includes: a sampling capacitor and a sampling switch, wherein: One end of the sampling capacitor is grounded, and the other end is electrically connected to the sampling switch and the transport drive array; The other end of the sampling switch is electrically connected to the analog bus.

[0017] For example, each sampling switched capacitor array can consist of 16 sampling capacitor units, with each sampling time being 1.6 ns, and the total sampling time for the four groups is ΔT = 6.4 ns.

[0018] like Figure 2 The diagram shown is a structural schematic of the transport drive array according to an embodiment of the present invention. The transport drive array consists of a first-stage driver, a drive switched capacitor unit, and a second-stage driver, wherein: The input terminal of the first-stage driver is electrically connected to a sampling capacitor, and the output terminal is electrically connected to multiple driving switched capacitor units. Each drive switch capacitor unit includes a drive switch and a drive capacitor; wherein, one end of the drive capacitor is grounded, and the other end is electrically connected to the drive switch and the second stage driver, and the other end of the drive switch is electrically connected to the output terminal of the first stage driver. The input of the second-stage driver is electrically connected to a driving capacitor, and the output is electrically connected to an array of multiple storage switched capacitors. For example, 64 first-stage drivers can be set up, with the input of each driver electrically connected to a sampling capacitor and the output of each driver electrically connected to 8 driving switched capacitor units; the input of each second-stage driver is electrically connected to a driving capacitor and the output of each driver is electrically connected to a 32-cell storage switched capacitor array.

[0019] like Figure 3 The diagram shown is a schematic representation of the structure of the first-stage driver according to an embodiment of the present invention. The first-stage driver consists of a PMOS transistor, a current mirror, and two reset switches, wherein: The gate of the PMOS transistor is electrically connected to the sampling capacitor; the source is electrically connected to one end of the drive switch, one end of the first reset switch, and one end of the first current mirror; the drain is electrically connected to one end of the second reset switch. The other end of the first current mirror is connected to a power source; The other end of the first reset switch is electrically connected to a fixed voltage level (V_BASE); the other end of the second reset switch is grounded. like Figure 4 The diagram shown is a schematic representation of the structure of the second-stage driver according to an embodiment of the present invention. The second-stage driver consists of an NMOS transistor, a current mirror, and two reset switches, wherein: The gate of the NMOS transistor is electrically connected to the drive capacitor; the source is electrically connected to one end of the storage switch, one end of the third reset switch, and one end of the second current mirror; the drain is electrically connected to one end of the fourth reset switch. The other end of the second current mirror is grounded; The other end of the third reset switch is grounded; the other end of the fourth reset switch is connected to the power supply.

[0020] In practice, turning on the first-stage driver is equivalent to turning off the first reset switch corresponding to the first-stage driver and turning off the second reset switch; turning off the first-stage driver is equivalent to turning off the first reset switch corresponding to the first-stage driver and turning off the second reset switch. When the second-stage driver is turned on, it is equivalent to the third reset switch corresponding to the second-stage driver being turned off and the fourth reset switch being turned on; when the second-stage driver is turned off, it is equivalent to the third reset switch corresponding to the second-stage driver being turned on and the fourth reset switch being turned off.

[0021] In specific implementation, the process by which the drive control circuit controls the on / off state of each switch in the transport drive array is as follows: S1. Multiple sets of sampling switched capacitor arrays are sampled sequentially and cyclically. During the sampling process of a certain set of sampling switched capacitor arrays, the first-stage driver connected to it is kept closed. After the sampling of the set of sampling switched capacitor arrays is completed, the first-stage driver connected to it is turned on until the next sampling begins and the first-stage driver is turned off. S2. During the first stage driver's operation, the drive switch of one drive switching capacitor connected to the output terminal of the first stage driver is kept closed, while the drive switches of other drive switching capacitors connected to the first stage driver are opened. After the first stage driver is turned off, the drive switches that were opened at this time are opened, and the drive switches of the next drive switching capacitor are closed in sequence. S3. When the drive switch of the driving capacitor is closed, the second-stage driver connected to the drive switch is turned off; after the drive switch of the driving capacitor is turned off, the second-stage driver connected to the drive switch is turned on until the next time the drive switch is closed, the second-stage driver is turned off. S4. During the second-stage driver's operation, the storage switch of one storage switch capacitor array connected to the output terminal of the second-stage driver remains closed, while the storage switches of other storage switch capacitor arrays connected to the output terminal of the second-stage driver are open. After the second-stage driver is turned off, the storage switches of the currently open storage switch capacitor arrays are opened, and the storage switches of the next storage switch capacitor array are closed in sequence.

[0022] For example, such as Figure 5 The diagram shown is a timing diagram of the control signal for the sampling switch capacitor sampling switch provided in an embodiment of the present invention. Figure 6 The diagram shown is a timing diagram of the control signals for driving the switched capacitor and the switch provided in an embodiment of the present invention. Figure 7 The diagram shown is a timing diagram of the control signals for each switch of the first-stage driver provided in an embodiment of the present invention. Figure 8The figures shown are timing diagrams of the control signals for each switch in the second-stage driver provided in an embodiment of the present invention. The timing diagrams in Figures 5 and 6 illustrate the control process of the drive control circuit, and the timing diagrams in Figures 7 and 8 illustrate the control signal process for moving each switch in the drive array, specifically including: 1. In the timing diagram of Figure 5, WR[1:64] represents the control signal of the sampling switch, which is divided into four groups: WR[1:16], WR[17:32], WR[33:48], and WR[49:64]. Multiple groups of sampling switch capacitor arrays are sampled sequentially and cyclically. During the sampling process of a certain group of sampling switch capacitor arrays, the first-stage driver connected to it remains closed. Figure 7 As shown, RST=0, which is equivalent to the first reset switch corresponding to the first-stage driver being closed and the second reset switch being open; after this set of sampling switch capacitor arrays completes sampling, the first-stage driver connected to it is turned on, RST=1, which is equivalent to the first reset switch corresponding to the first-stage driver being open and the second reset switch being closed, until the driver is turned off before the next sampling begins, RST=0. 2. During the first-stage driver's operation, the drive switch of one of the drive switching capacitors connected to its output terminal is kept closed, while the drive switches of the other drive switching capacitors connected to it are open. In the timing diagram of Figure 6, SWI_PIPE[0:7] represents the control signal of the drive switch. As shown in Figure 7, one of SWI_PIPE[X] in SWI_PIPE[0:7] is 1, and the rest are 0. After the first-stage driver is turned off, the drive switch that was turned on at this time is opened, and the drive switch of the next drive switching capacitor is closed in sequence. SWI_PIPE[X+1]=1, and the rest are 0. 3. In the timing diagram of Figure 6, SWI_PIPE[0:7] represents the control signal of the drive switch. When the drive switch of a certain drive switch capacitor is closed, that is, when SWI_PIPE[X]=1, the second-stage driver connected to it is turned off, as shown in Figure 8, RST=0, which is equivalent to the third reset switch corresponding to the second-stage driver being closed and the fourth reset switch being open; after the drive switch of this drive switch capacitor is turned off, the second-stage driver connected to it is turned on, RST=1, which is equivalent to the third reset switch corresponding to the second-stage driver being open and the fourth reset switch being closed, until the second-stage driver is turned off before the next drive switch is closed, RST=0; 4. During the second-stage driver's operation, the storage switch of one of the storage switch capacitor arrays connected to its output terminal is kept closed, while the storage switches of the other storage switch capacitor arrays connected to its output terminal are opened, as shown in Figure 8. SWI_STOR[1:32] represents the control signal of the storage switch. One of SWI_STOR[Y] in SWI_STOR[1:32] is 1, and the rest are 0. After the second-stage driver is closed, the storage switch that was opened at this time is opened, and the storage switch of the next storage switch capacitor array is closed in sequence. SWI_STOR[Y+1]=1, and the rest are 0.

[0023] Furthermore, in a specific implementation, the storage switched capacitor array is composed of multiple storage switched capacitor units, each storage switched capacitor unit including: a storage capacitor, a storage switch, and a quantization switch, wherein: One end of the storage capacitor is grounded, and the other end is electrically connected to the storage switch and the quantization switch; The other end of the storage switch is electrically connected to the output of the second-stage driver; The other end of the quantization switch is electrically connected to the quantization circuit.

[0024] Furthermore, the quantization circuit consists of multiple quantization units, for example, 128 quantization units can be set. Each quantization unit includes: a quantization driver and a single-slope analog-to-digital converter (ADC), wherein: The input terminal of the quantization driver is electrically connected to one end of the quantization switch of multiple memory switched capacitor arrays, and the output terminal is electrically connected to the input terminal of the single-slope analog-to-digital converter (ADC). In specific implementation, each quantization driver can be configured with 128 memory switched capacitor units. The output of the single-slope analog-to-digital converter (ADC) is electrically connected to the input of the quantization readout control circuit.

[0025] The quantization readout control circuit is connected to the control terminal of the quantization switch of the storage switched capacitor array and the switch control terminal of the quantization driver. It is used to control the quantization start and stop of the quantization circuit and to convert the quantization data transmitted by the quantization circuit into data signals on the serial bus and output them to the off-chip.

[0026] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0027] This invention also provides a computer storage medium that stores multiple instructions adapted for loading and execution by a processor to drive the control process of a control circuit.

[0028] In summary, the circuit described in this embodiment of the invention innovatively proposes a pipelined transport drive scheme. This design avoids the contradiction between the sampling depth and analog bandwidth of the SCA (Switched Capacitor Array). By reducing the number of switched capacitors connected to the analog bus, the bandwidth of the analog bus is significantly improved; and by increasing the number of storage capacitors, the sampling depth of the SCA is significantly increased. This scheme is applicable to digital readout applications of switched capacitor array detector waveforms, such as signal acquisition from various detectors in particle physics experiments, gamma-ray telescopes used in astronomical observations, and related fields in PET (Positive Electron Microscopy) instruments in medical imaging.

[0029] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A switched capacitor circuit based on charge transfer, characterized in that, The switched capacitor circuit includes a sampling clock generation circuit, a sampling switched capacitor array, a transport drive array, a drive control circuit, a storage switched capacitor array, a quantization circuit, and a quantization readout control circuit, wherein: The sampling control terminal of the sampling clock generation circuit is electrically connected to the sampling switch control terminal of the sampling switch capacitor array; The output of the sampling switched capacitor array is electrically connected to the transport drive array; The control terminal of the transport drive array is connected to the drive control circuit, which controls the on / off state of each switch in the transport drive array. The output of the transport drive array is electrically connected to the storage switched capacitor array. The sampling clock generation circuit and the sampling switched capacitor array continuously perform cyclic sampling, and the cyclically sampled voltage values ​​are transferred to the storage switched capacitor array through the transport drive array. The output of the storage switched capacitor array is electrically connected to the quantization circuit; the voltage value stored in the storage switched capacitor array is quantized multiple times according to the storage order under the action of the quantization circuit, converting the analog voltage value into a digital code value. The quantization readout control circuit is electrically connected to the quantization circuit, controls the quantization circuit to perform quantization, receives the readout data from the quantization circuit, and outputs the data serially to an external device.

2. The switched capacitor circuit based on charge transfer according to claim 1, characterized in that, The sampling switched capacitor array is divided into four groups. During the sampling process of the other three groups of sampling switched capacitor arrays, each group of sampling switched capacitor arrays is connected to the transfer drive array to transfer charge. Each sampling switched capacitor array consists of multiple sampling switched capacitor units. Each sampling switched capacitor unit includes: a sampling capacitor and a sampling switch, wherein: One end of the sampling capacitor is grounded, and the other end is electrically connected to the sampling switch and the transport drive array; The other end of the sampling switch is electrically connected to the analog bus.

3. The switched capacitor circuit based on charge transfer according to claim 1, characterized in that, The transport drive array consists of a first-stage driver, a drive switched capacitor unit, and a second-stage driver, wherein: The input terminal of the first-stage driver is electrically connected to a sampling capacitor, and the output terminal is electrically connected to multiple driving switched capacitor units. Each drive switch capacitor unit includes a drive switch and a drive capacitor; wherein, one end of the drive capacitor is grounded, and the other end is electrically connected to the drive switch and the second stage driver, and the other end of the drive switch is electrically connected to the output terminal of the first stage driver. The input of the second-stage driver is electrically connected to a driving capacitor, and the output is electrically connected to an array of multiple storage switching capacitors.

4. The switched capacitor circuit based on charge transfer according to claim 3, characterized in that, The first-stage driver consists of a PMOS transistor, a current mirror, and two reset switches, wherein: The gate of the PMOS transistor is electrically connected to the sampling capacitor; the source is electrically connected to one end of the drive switch, one end of the first reset switch, and one end of the first current mirror; the drain is electrically connected to one end of the second reset switch. The other end of the first current mirror is connected to a power source; The other end of the first reset switch is electrically connected to a fixed voltage level; the other end of the second reset switch is grounded. The second-stage driver consists of an NMOS transistor, a current mirror, and two reset switches, wherein: The gate of the NMOS transistor is electrically connected to the drive capacitor; the source is electrically connected to one end of the storage switch, one end of the third reset switch, and one end of the second current mirror; the drain is electrically connected to one end of the fourth reset switch. The other end of the second current mirror is grounded; The other end of the third reset switch is grounded; the other end of the fourth reset switch is connected to the power supply.

5. The switched capacitor circuit based on charge transfer according to claim 3, characterized in that, The process by which the drive control circuit controls the on / off state of each switch in the transport drive array is as follows: S1. Multiple sets of sampling switched capacitor arrays are sampled sequentially and cyclically. During the sampling process of a certain set of sampling switched capacitor arrays, the first-stage driver connected to it is kept closed. After the sampling of the set of sampling switched capacitor arrays is completed, the first-stage driver connected to it is turned on until the next sampling begins and the first-stage driver is turned off. S2. During the first stage driver's operation, the drive switch of one drive switching capacitor connected to the output terminal of the first stage driver is kept closed, while the drive switches of other drive switching capacitors connected to the first stage driver are opened. After the first-stage driver is turned off, the currently open drive switch is disconnected, and the drive switch of the next drive switch capacitor is closed in sequence. S3. When the drive switch of the driving capacitor is closed, the second-stage driver connected to the drive switch is turned off. After the drive switch for the drive capacitor is turned off, the second-stage driver connected to the drive switch is turned on until the drive switch is turned off again. S4. During the second-stage driver's operation, the storage switch of one storage switched capacitor array connected to the output of the second-stage driver remains closed, while the storage switches of other storage switched capacitor arrays connected to the output of the second-stage driver are open. After the second-stage driver is turned off, the storage switch of the storage switch capacitor array that is currently open is disconnected, and the storage switch of the next storage switch capacitor array is closed in sequence.

6. The switched capacitor circuit based on charge transfer according to claim 4, characterized in that, When the first-stage driver is turned on, it is equivalent to the first reset switch corresponding to the first-stage driver being turned off and the second reset switch being turned on. When the first-stage driver is turned off, it is equivalent to the first reset switch corresponding to the first-stage driver being closed and the second reset switch being open. When the second-stage driver is turned on, it is equivalent to the third reset switch corresponding to the second-stage driver being turned off and the fourth reset switch being turned on. When the second-stage driver is turned off, it is equivalent to the third reset switch corresponding to the second-stage driver being closed and the fourth reset switch being open.

7. The switched capacitor circuit based on charge transfer according to claim 1, characterized in that, The storage switched capacitor array consists of multiple storage switched capacitor units, each storage switched capacitor unit including: a storage capacitor, a storage switch, and a quantization switch, wherein: One end of the storage capacitor is grounded, and the other end is electrically connected to the storage switch and the quantization switch; The other end of the storage switch is electrically connected to the output of the second-stage driver; The other end of the quantization switch is electrically connected to the quantization circuit.

8. The switched capacitor circuit based on charge transfer according to claim 7, characterized in that, The quantization circuit consists of multiple quantization units, each quantization unit including: a quantization driver and a single-slope analog-to-digital converter (ADC), wherein: The input terminal of the quantization driver is electrically connected to one end of the quantization switch of the multiple storage switched capacitor array, and the output terminal is electrically connected to the input terminal of the single-slope analog-to-digital converter (ADC). The output of the single-slope analog-to-digital converter (ADC) is electrically connected to the input of the quantization readout control circuit.

9. The switched capacitor circuit based on charge transfer according to claim 8, characterized in that, The quantization readout control circuit is connected to the control terminal of the quantization switch of the storage switched capacitor array and the switch control terminal of the quantization driver. It is used to control the quantization start and stop of the quantization circuit and to convert the quantization data transmitted by the quantization circuit into data signals on the serial bus and output them to the off-chip.

10. A computer storage medium, characterized in that, The computer storage medium stores multiple instructions adapted for loading and execution by a processor of the control process of claim 5.

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