Comparator circuit and image sensor

Abstract

This invention provides a comparator circuit and an image sensor, belonging to the field of electronic circuit technology. The image sensor includes at least: a current mirror, a ramp-coupled input transistor, a pixel-coupled input transistor, and a current source input transistor; a ramp reset transistor and a pixel reset transistor; the current mirror includes a first mirror branch and a second mirror branch; a first mirror branch load controller and a second mirror branch load controller, allowing the first mirror branch load controller to connect to the first mirror branch and allowing the second mirror branch load controller to connect to the second mirror branch; wherein, when the comparator circuit is reset, when the first reset signal is high, the first and second mirror branch load controllers are connected or disconnected from the circuit, reducing the on-state voltage drop of the first and second mirror branches. The comparator circuit and image sensor provided by this invention can balance the comparator's noise performance while increasing the maximum input swing.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and specifically relates to a comparator circuit and an image sensor. Background Technology

[0002] An image sensor is a chip that converts light signals into electrical signals. An image sensor includes a pixel array and a pixel analog-to-digital converter (ADC). The pixel array outputs pixel voltages, and the ADC converts these pixel voltages into digital signals. The ADC includes a ramp generator, a comparator, and a counter.

[0003] Comparators typically employ a two-stage structure. To ensure noise performance, the channel length of the load transistor in the comparator is set to be relatively large. When the channel length of the load transistor is large, the gate-source voltage of the load transistor is large, and the self-reset voltage is low. The comparator's comparison start voltage is the self-reset voltage, and a low self-reset voltage will significantly limit the maximum input swing. Summary of the Invention

[0004] The purpose of this invention is to provide a comparator circuit and an image sensor that can solve the problem of not being able to simultaneously achieve both the noise performance and the maximum input swing of a comparator.

[0005] To achieve the above objectives, the present invention provides a comparator circuit, the comparator circuit including a first-stage comparator, and the first-stage comparator including: The system comprises a current mirror, a ramp-coupled input transistor, a pixel-coupled input transistor, and a current source input transistor. The first mirror branch of the current mirror, the ramp-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The second mirror branch of the current mirror, the pixel-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The control terminal of the ramp-coupled input transistor receives a ramp voltage, and the control terminal of the pixel-coupled input transistor receives a pixel voltage. A ramp reset transistor and a pixel reset transistor are provided. The ramp reset transistor is connected in series between the control terminal of the ramp coupled input transistor and the common terminal of the ramp coupled input transistor and the first mirror branch. The pixel reset transistor is connected in series between the control terminal of the pixel coupled input transistor and the common terminal of the pixel coupled input transistor and the second mirror branch. Both the ramp reset transistor and the pixel reset transistor are controlled by a first reset signal. The first mirror branch load controller and the second mirror branch load controller allow the first mirror branch load controller to connect to the first mirror branch and allow the second mirror branch load controller to connect to the second mirror branch. When the comparator circuit is reset, if the first reset signal is high, the first mirror branch load controller and the second mirror branch load controller are connected or disconnected from the circuit, thereby reducing the on-state voltage drop of the first mirror branch and the second mirror branch.

[0006] In one embodiment of the present invention, the first mirror branch includes a first load transistor connected in series between the voltage source and the ramp coupling input transistor, and the second mirror branch includes a second load transistor connected in series between the voltage source and the pixel coupling input transistor.

[0007] In one embodiment of the present invention, the first mirror branch load controller includes a third load transistor and a first control switch, wherein the third load transistor is connected in series with the first load transistor and the first control switch is connected in parallel with the third load transistor; the second mirror branch load controller includes a fourth load transistor and a second control switch, wherein the fourth load transistor is connected in series with the second load transistor and the second control switch is connected in parallel with the fourth load transistor.

[0008] In one embodiment of the present invention, when the comparator circuit is reset, when the first reset signal is high, the first control switch and the second control switch are closed, so that the third load transistor and the fourth load transistor are short-circuited; after the first reset signal is pulled low, the first control switch and the second control switch are opened, so that the third load transistor is connected to the first mirror branch and the fourth load transistor is connected to the second mirror branch.

[0009] In one embodiment of the present invention, the comparator circuit includes a second-stage comparator, and the second-stage comparator includes: A common-source transistor and an output control transistor are connected in series between the voltage source and the ground terminal. The control terminal of the common-source transistor is electrically connected to the output terminal of the first-stage comparator. The control terminal of the output control transistor is grounded through an energy storage capacitor. An output reset transistor is connected in series with the control terminal of the output control transistor and the common terminal of the output control transistor and the common source transistor, and the output reset transistor is controlled by a second reset signal.

[0010] In one embodiment of the present invention, the second-stage comparator further includes a common-source transconductance regulating transistor and a third control switch. The common-source transconductance regulating transistor is connected in series with the common-source transistor, and the third control switch is connected in parallel with the common-source transconductance regulating transistor. When the second reset signal is high, the third control switch is disconnected, so that the common-source transconductance regulating transistor is connected to the second-stage comparator.

[0011] In one embodiment of the present invention, the first mirror branch load controller includes a fifth load transistor and a fourth control switch, wherein the fifth load transistor is connected in series with the first load transistor and the fourth control switch is connected in parallel with the first load transistor; the second mirror branch load controller includes a sixth load transistor and a fifth control switch, wherein the sixth load transistor is connected in series with the second load transistor and the fifth control switch is connected in parallel with the second load transistor.

[0012] In one embodiment of the present invention, when the comparator circuit is reset, when the first reset signal is high, the fourth control switch and the fifth control switch are closed, so that the first load transistor is connected to the first mirror branch and the second load transistor is connected to the second mirror branch; after the first reset signal is pulled low, the fourth control switch and the fifth control switch are then opened, so that the first load transistor is connected to the first mirror branch and the second load transistor is connected to the second mirror branch.

[0013] In one embodiment of the present invention, the first mirror branch load controller includes a seventh load transistor and a sixth control switch, wherein the seventh load transistor and the sixth control switch are connected in series and then connected in parallel to the first load transistor; the second mirror branch load controller includes an eighth load transistor and a seventh control switch, wherein the eighth load transistor and the seventh control switch are connected in series and then connected in parallel to the second load transistor.

[0014] In one embodiment of the present invention, when the comparator circuit is reset, when the first reset signal is high, the sixth control switch and the seventh control switch are closed, so that the seventh load transistor is connected to the first mirror branch and the eighth load transistor is connected to the second mirror branch; after the first reset signal is pulled low, the sixth control switch and the seventh control switch are then disconnected, so that the seventh load transistor and the eighth load transistor are disconnected from the circuit.

[0015] In one embodiment of the present invention, the first mirror branch load control device includes a first resistor and an eighth control switch, the first resistor and the eighth control switch being connected in series and then connected in parallel to the first load transistor; the second mirror branch load control device includes a second resistor and a ninth control switch, the second resistor and the ninth control switch being connected in series and then connected in parallel to the second load transistor.

[0016] In one embodiment of the present invention, when the comparator circuit is reset, when the first reset signal is high, the eighth control switch and the ninth control switch are closed, so that the first resistor is connected to the first mirror branch and the second resistor is connected to the second mirror branch; after the first reset signal is pulled low, the eighth control switch and the ninth control switch are then disconnected, so that the first resistor and the second resistor are disconnected from the circuit.

[0017] The present invention also provides an image sensor, comprising at least: A pixel array, including an effective pixel region, wherein the effective pixel region outputs an effective pixel voltage; A ramp generator that generates a ramp voltage; The comparator as described in any of the above embodiments, wherein the pixel voltage is input to the control terminal of the pixel-coupled input transistor, and the ramp voltage is input to the control terminal of the ramp-coupled input transistor; and A counter, electrically connected to the output of the comparator, counts the pixel voltage.

[0018] In summary, the comparator circuit and image sensor provided by this invention, through a control switch, allow the load transistors to be two or more external load transistors connected in series or parallel during the comparator's self-reset phase, thereby achieving a lower gate-source voltage during self-reset. After reset, the control switch restores the multiple external load transistors to the preset load transistor dimensions, meeting the noise performance requirements during quantization. By controlling the connection or disconnection of multiple load transistors through the control switch, a large input swing can be achieved while maintaining consistent performance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic block diagram of the structure of an image sensor in one embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram of the comparator in one embodiment of the present invention when the load transistor is not split.

[0022] Figure 3 This is a circuit diagram of a comparator in one embodiment of the present invention when a load transistor is split into two load transistors connected in series.

[0023] Figure 4This is a timing diagram of the comparator control when a load transistor is split into two series-connected load transistors in one embodiment of the present invention.

[0024] Figure 5 This is a circuit diagram of a comparator in one embodiment of the present invention, in which a load transistor is split into two series-connected load transistors and a common-source transistor is split.

[0025] Figure 6 This is a control timing diagram in one embodiment of the present invention when a load transistor is split into two series-connected load transistors and a common-source transistor is split.

[0026] Figure 7 This is a circuit diagram of a comparator in one embodiment of the present invention when a load transistor is split into two load transistors connected in series.

[0027] Figure 8 This is a circuit diagram of a comparator with two additional load transistors connected in parallel in one embodiment of the present invention.

[0028] Figure 9 This is a control timing diagram of the comparator when two additional load transistors are connected in parallel in one embodiment of the present invention.

[0029] Figure 10 A circuit diagram of a comparator with two additional parallel resistors connected to the load transistor in one embodiment of the present invention. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0032] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] Please see Figure 1 As shown, in one embodiment of the present invention, the image sensor includes a pixel array and a pixel analog-to-digital converter circuit. The pixel array includes pixels arranged in an array, and each pixel includes a photodiode (PD) and a pixel voltage readout circuit 101. The photodiode (PD) converts an optical signal into an electrical signal and stores it. The pixel voltage readout circuit 101 reads the electrical signal and outputs the pixel voltage VPIX. The pixel analog-to-digital converter circuit converts the read pixel voltage VPIX into a digital signal.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, the pixel voltage readout circuit 101 includes a transmission transistor M1, a reset transistor M2, a source follower transistor M3, and a row select transistor M4. The transmission transistor M1 is connected in series between a photodiode PD and a floating diffusion region FD, controlling the transfer of charge from the photodiode PD to the floating diffusion region FD. The reset transistor M2 is connected in series between the pixel region voltage and the floating diffusion region FD, controlling the reset process of the floating diffusion region FD. The source follower transistor M3 and the row select transistor M4 are connected in series between the pixel region voltage and the ground terminal GND. The control terminal of the source follower transistor M3 is electrically connected to the floating diffusion region FD, and the control terminal of the row select transistor M4 is controlled by the row select signal SEL. Together, they achieve row-by-row selective readout of the pixel. Furthermore, a pixel current source CL can be provided in the peripheral circuit. The pixel current source CL is connected in series between part of the row select transistors M4 and the ground terminal GND, providing a stable current for pixel readout.

[0035] Please see Figure 1 As shown, in one embodiment of the present invention, the ramp generator 201 generates a ramp voltage VRAMP. One end of the comparator 202 receives the pixel voltage VPIX output from the pixel array, and the other end receives the ramp voltage VRAMP generated by the ramp generator 201. The comparator 202 compares the pixel voltage VPIX and the ramp voltage VRAMP. A counter 203 is electrically connected to the output of the comparator 202. The counter 203 counts the pixel voltage VPIX when the pixel voltage VPIX and the ramp voltage VRAMP flip, thus achieving analog-to-digital conversion of the pixel voltage VPIX.

[0036] Please see Figure 2As shown, in some embodiments, the comparator circuit employs a two-stage structure. To optimize the comparator's noise performance, the original load transistors PM11 and PM12 in the first-stage comparator and the original common-source transistor PM13 in the second-stage comparator are configured with larger channel lengths. Therefore, the channel width-to-length ratio (W / L) of the original load transistors PM11 and PM12 in the first-stage comparator and the original common-source transistor PM13 in the second-stage comparator is smaller, resulting in a larger gate-source voltage for the original load transistors PM11 and PM12 in the first-stage comparator. When the comparator is reset, the reset voltage at the two input terminals of the first-stage comparator is obtained using the following formula: VINrst=VIPrst=VDD-VGS_PM11.

[0037] Where VINrst is the reset voltage at one input of the first-stage comparator, VIPrst is the reset voltage at the other input of the first-stage comparator, VDD is the voltage source, and VGS_PM11 is the gate-source voltage of the original load transistor PM11 in the first-stage comparator.

[0038] At this point, the maximum input swing of the comparator is obtained using the following formula: Vmax=VDD-VGS_PM11-VGS_NM1-VDSAT0.

[0039] in, Vmax is the maximum input swing of the comparator, VDD is the voltage source, VGS_PM11 is the gate-source voltage of the original load transistor PM11 in the first stage comparator, VGS_NM1 is the gate-source voltage of the pixel-coupled input transistor NM1, and VDSAT0 is the minimum saturation voltage drop of the current source input transistor NM0.

[0040] As can be seen from the formula for the maximum input swing of the comparator, the maximum input swing is related to the gate-source voltage of the original load transistor in the first-stage comparator. Increasing the channel length of the original load transistor to improve noise performance also increases the gate-source voltage of the original load transistors PM11 and PM12, thus reducing the maximum input swing of the comparator. Increasing the maximum input swing by decreasing the channel length of the original load transistor sacrifices the comparator's noise performance. This application provides a comparator circuit and image sensor that can increase the maximum input swing without sacrificing noise performance.

[0041] Please see Figures 3 to 10As shown, in one embodiment of the present invention, a comparator circuit is provided, including a first-stage comparator and a second-stage comparator. The first-stage comparator includes a current mirror, a ramp-coupled input transistor NM1 and a pixel-coupled input transistor NM2, a ramp reset transistor RST1 and a pixel reset transistor RST2, a current source input transistor NM0, and a first mirror branch load controller and a second mirror branch load controller. The first mirror branch of the current mirror, the ramp-coupled input transistor NM1, and the current source input transistor NM0 are connected in series between a voltage source VDD and ground GND. The second mirror branch of the current mirror, the pixel-coupled input transistor NM2, and the current source input transistor NM0 are also connected in series between a voltage source VDD and ground GND. The control terminal of the ramp-coupled input transistor NM1 receives a ramp voltage VRAMP, and the control terminal of the pixel-coupled input transistor NM2 receives a pixel voltage VPIX. Ramp reset transistor RST1 is connected in series between the control terminal of ramp coupled input transistor NM1 and the common terminal of ramp coupled input transistor NM1 and the first mirror branch. Pixel reset transistor RST2 is connected in series between the control terminal of pixel coupled input transistor NM2 and the common terminal of pixel coupled input transistor NM2 and the second mirror branch. Both pixel reset transistor RST2 and ramp reset transistor RST1 are controlled by the first reset signal rst1. This allows the load controller of the first mirror branch to connect to the first mirror branch, and allows the load controller of the second mirror branch to connect to the second mirror branch. When the comparator circuit is reset, when the first reset signal rst1 is high, the load controllers of the first and second mirror branches are connected or disconnected from the circuit, reducing the on-state voltage drop of the first and second mirror branches. In addition to the first mirror branch load controller and the second mirror branch load controller, the first mirror branch includes at least the first load transistor PM1, and the first load transistor PM1 is connected in series between the voltage source VDD and the ramp-coupled input transistor NM1. The second mirror branch includes at least the second load transistor PM2, and the second load transistor PM2 is connected in series between the voltage source VDD and the pixel-coupled input transistor NM2.

[0042] Please see Figures 3 to 10 As shown, in one embodiment of the present invention, the second-stage comparator includes a common-source transistor PM9, an output control transistor NM3, and an output reset transistor RST3. PM9 and NM3 are connected in series between the voltage source VDD and the ground terminal GND. The control terminal of PM9 is electrically connected to the output terminal of the first-stage comparator, and the control terminal of NM3 is grounded through a storage capacitor C3. The output reset transistor RST3 is connected in series between the control terminal of NM3 and the common terminal of NM3 and PM9, and is controlled by a second reset signal rst2.

[0043] For details, please refer to Figures 3 to 10As shown, in a specific embodiment of the present invention, the first load transistor PM1 and the second load transistor PM2 in the first-stage comparator are PMOS transistors, while the ramp-coupled input transistor NM1, the pixel-coupled input transistor NM2, and the current source input transistor NM0 are NMOS transistors. The ramp reset transistor RST1 and the pixel reset transistor RST2 are arbitrary type digital control switches, and the first mirror branch load control device and the second mirror branch load control device are set according to requirements. In the second-stage comparator, the common-source transistor PM9 is a PMOS transistor, the output control transistor NM3 is an NMOS transistor, and the output reset transistor RST3 is an arbitrary type digital control switch.

[0044] Please see Figures 3 to 10 As shown, in a specific embodiment of the present invention, in the first-stage comparator, the source of the first load transistor PM1 is electrically connected to the voltage source VDD, the drain of the first load transistor PM1 is directly or indirectly electrically connected to the drain of the ramp-coupled input transistor NM1, the source of the ramp-coupled input transistor NM1 is electrically connected to the drain of the current source input transistor NM0, and the source of the current source input transistor NM0 is electrically connected to the ground terminal GND. A ramp reset transistor RST1 is connected in parallel between the drain and gate of the ramp-coupled input transistor NM1. A first coupling capacitor C1 is also connected in series at the control terminal of the ramp-coupled input transistor NM1, and the ramp voltage VRAMP is input to the control terminal of the ramp-coupled input transistor NM1 through the first coupling capacitor C1. The source of the second load transistor PM2 is electrically connected to the voltage source VDD, the drain of the second load transistor PM2 is directly or indirectly electrically connected to the drain of the pixel-coupled input transistor NM2, and the source of the pixel-coupled input transistor NM2 is electrically connected to the drain of the current source input transistor NM0. The pixel reset transistor RST2 is connected in parallel between the drain and gate of the pixel coupled input transistor NM2. A second coupling capacitor C2 is also connected in series at the control terminal of the pixel coupled input transistor NM2, and the pixel voltage VPIX is input to the control terminal of the pixel coupled input transistor NM2 through the second coupling capacitor C2.

[0045] Please see Figures 3 to 10 As shown, in a specific embodiment of the present invention, in the first-stage comparator, the source of the common-source transistor PM9 is electrically connected to the voltage source VDD, and the drain of the common-source transistor PM9 is directly or indirectly electrically connected to the drain of the output control transistor NM3. The drain of the output control transistor NM3 is electrically connected to the ground terminal GND. The output reset transistor RST3 is connected in series between the drain and gate of the output control transistor NM3.

[0046] Please refer to the combination Figure 2 and Figure 3As shown, in one embodiment of the present invention, the first mirror branch load control device includes a third load transistor PM3 and a first control switch SW1. The third load transistor PM3 is connected in series with the first load transistor PM1, and the first control switch SW1 is connected in parallel with the third load transistor PM3. The second mirror branch load control device includes a fourth load transistor PM4 and a second control switch SW2. The fourth load transistor PM4 is connected in series with the second load transistor PM2, and the second control switch SW2 is connected in parallel with the fourth load transistor PM4. The first control switch SW1 controls whether the third load transistor PM3 is connected to the first mirror branch, and the second control switch SW2 controls whether the fourth load transistor PM4 is connected to the second mirror branch. At this time, the channel width of the first load transistor PM1 and the third load transistor PM3 is equal to the channel width of the original load transistor PM11, the total transconductance of the first load transistor PM1 and the third load transistor PM3 is equal to the transconductance of the original load transistor PM11, and the sum of the channel length of the first load transistor PM1 and the channel length of the third load transistor PM3 is equal to the channel length of the original load transistor PM11. The channel widths of the second load transistor PM2 and the fourth load transistor PM4 are equal to the channel width of the original load transistor PM12. The total transconductance of the second load transistor PM2 and the fourth load transistor PM4 is equal to the transconductance of the original load transistor PM12. The sum of the channel lengths of the second load transistor PM2 and the fourth load transistor PM4 is equal to the channel length of the original load transistor PM12. This is equivalent to splitting the original load transistor into two load transistors along its channel length. Therefore, three or more load transistors can also be set in each mirror branch, which is equivalent to splitting the original load transistor into three or more load transistors along its channel length.

[0047] Please see Figure 3 and Figure 4 As shown, in a specific embodiment of the present invention, the third load transistor PM3 and the fourth load transistor PM4 are PMOS transistors, and the first control switch SW1 and the second control switch SW2 are arbitrary type digital control switches, controlled by the switch control signal SW. At this time, the source of the third load transistor PM3 is electrically connected to the drain of the first load transistor PM1, and the drain of the third load transistor PM3 is electrically connected to the drain of the ramp-coupled input transistor NM1. The first control switch SW1 is connected in series between the source and drain of the third load transistor PM3. The source of the fourth load transistor PM4 is electrically connected to the drain of the second load transistor PM2, and the drain of the fourth load transistor PM4 is electrically connected to the drain of the pixel-coupled input transistor NM2. The second control switch SW2 is connected in series between the source and drain of the fourth load transistor PM4.

[0048] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, when the comparator circuit is reset, the first reset signal rst1 is set high, and after the second stage comparator is reset through the second reset signal rst2, the first control switch SW1 and the second control switch SW2 are closed, short-circuiting the third load transistor PM3 and the fourth load transistor PM4. After pulling the first reset signal rst1 low, the first control switch SW1 and the second control switch SW2 are then opened, connecting the third load transistor PM3 to the first mirror branch and the fourth load transistor PM4 to the second mirror branch. During the subsequent comparison of the pixel voltage VPIX and the ramp voltage VRAMP, the first control switch SW1 and the second control switch SW2 are always kept open, thus maintaining the noise performance of the subsequent comparator. Therefore, during the reset process of the first stage comparator, the reset voltage at the two input terminals of the first stage comparator is obtained by the following formula: VINrst=VIPrst=VDD-VGS_PM1.

[0049] Wherein, VINrst is the reset voltage at one input of the first-stage comparator, VIPrst is the reset voltage at the other input of the first-stage comparator, VDD is the voltage source, and VGS_PM1 is the gate-source voltage of the first load transistor PM1.

[0050] At this point, the maximum input swing of the comparator is obtained using the following formula: Vmax=VDD-VGS_PM1-VGS_NM1-VDSAT0.

[0051] in, Vmax is the maximum input swing of the comparator, VDD is the voltage source, VGS_PM1 is the gate-source voltage of the first load transistor PM1, VGS_NM1 is the gate-source voltage of the ramp-coupled input transistor NM1, and VDSAT0 is the minimum saturation voltage drop of the current source input transistor NM0.

[0052] VGS_PM1 and VGS_PM11 represent the on-state voltage drops of the first and second mirror branches under different conditions. Compared to the original load transistor PM11 in the first-stage comparator, due to the reduced channel length, VGS_PM1 < VGS_PM11, thus the maximum input swing of the comparator is... Vmax increases. During the subsequent comparison of pixel voltage VPIX and ramp voltage VRAMP, the first control switch SW1 and the second control switch SW2 are always kept open, ensuring that the comparator's noise performance remains the same as the original comparator.

[0053] Please see Figure 5 and Figure 6As shown, in another embodiment of the present invention, based on the arrangement of a third load transistor PM3 and a first control switch SW1 in the first mirror branch, and a fourth load transistor PM4 and a second control switch SW2 in the second mirror branch, a common-source transconductance regulator PM10 and a third control switch SW3 are arranged in the second-stage comparator. The common-source transconductance regulator PM10 is connected in series with the common-source transistor PM9, and its gate is electrically connected to the output of the first-stage comparator. The third control switch SW3 is connected in parallel with the common-source transconductance regulator PM10, and controls whether the common-source transconductance regulator PM10 is connected to the second-stage comparator. The channel widths of the common-source transistor PM9 and the common-source transconductance regulating transistor PM10 are equal to the channel width of the original common-source transistor PM13. The total transconductance of the common-source transistor PM9 and the common-source transconductance regulating transistor PM10 is equal to the transconductance of the original common-source transistor PM13. The sum of the channel lengths of the common-source transistor PM9 and the common-source transconductance regulating transistor PM10 is equal to the channel length of the original common-source transistor PM13. This is equivalent to splitting the original common-source transistor PM13 into two transistors along its channel length. Therefore, three or more transistors can also be used in the second-stage comparator.

[0054] Please see Figure 5 and Figure 6 As shown, in another specific embodiment of the present invention, the common-source transconductance regulating transistor PM10 is, for example, a PMOS transistor. The source of the common-source transconductance regulating transistor PM10 is electrically connected to the drain of the common-source transistor PM9, and the drain of the common-source transconductance regulating transistor PM10 is electrically connected to the drain of the output control transistor NM3.

[0055] Please see Figure 5 and Figure 6 As shown, in another specific embodiment of the present invention, the third control switch SW3, the second control switch SW2, and the first control switch SW1 are controlled by the same switch control signal SW. When the second reset signal rst2 is high, the third control switch SW3 is disconnected, allowing the common-source transconductance regulating transistor PM10 to be connected to the second-stage comparator. Specifically, after simultaneously setting the first reset signal rst1 and the second reset signal rst2 high, the switch control signal SW is set high, simultaneously short-circuiting the third load transistor PM3, the fourth load transistor PM4, and the common-source transconductance regulating transistor PM10. This increases the maximum input swing of the comparator. Vmax, while changing the flip point of the second-stage comparator.

[0056] Please refer to the combination Figure 3 and Figure 7As shown, in another embodiment of the present invention, the first mirror branch load control device includes a fifth load transistor PM5 and a fourth control switch SW4. The fifth load transistor PM5 is connected in series with the first load transistor PM1, and the fourth control switch SW4 is connected in parallel with the first load transistor PM1. The second mirror branch load control device includes a sixth load transistor PM6 and a fifth control switch SW5. The sixth load transistor PM6 is connected in series with the second load transistor PM2, and the fifth control switch SW5 is connected in parallel with the second load transistor PM2. The fourth control switch SW4 controls whether the first load transistor PM1 is connected to the first mirror branch, and the fifth control switch SW5 controls whether the second load transistor PM2 is connected to the second mirror branch. The fifth load transistor PM5 is identical in type and connection to the third load transistor PM3, and the sixth load transistor PM6 is identical in type and connection to the fourth load transistor PM4, which is equivalent to only modifying the positions of the first control switch SW1 and the second control switch SW2 in the first embodiment.

[0057] Please refer to the combination Figure 3 , Figure 4 and Figure 7 As shown, in another embodiment of the present invention, when the comparator circuit is reset, the first reset signal rst1 is set high, and after the second stage comparator is reset through the second reset signal rst2, the fourth control switch SW4 and the fifth control switch SW5 are closed, short-circuiting the fifth load transistor PM5 and the sixth load transistor PM6. After the first reset signal rst1 is pulled low, the fourth control switch SW4 and the fifth control switch SW5 are then opened, connecting the fifth load transistor PM5 to the first mirror branch and the sixth load transistor PM6 to the second mirror branch. During the subsequent comparison of the pixel voltage VPIX and the ramp voltage VRAMP, the fourth control switch SW4 and the fifth control switch SW5 are always kept open, thus maintaining the noise performance of the subsequent comparator.

[0058] Please see Figure 8 and Figure 9As shown, in another embodiment of the present invention, the first mirror branch load control device includes a seventh load transistor PM7 and a sixth control switch SW6. The seventh load transistor PM7 and the sixth control switch SW6 are connected in series and then connected in parallel to the first load transistor PM1. The second mirror branch load control device includes an eighth load transistor PM8 and a seventh control switch SW7. The eighth load transistor PM8 and the seventh control switch SW7 are connected in series and then connected in parallel to the second load transistor PM2. The sixth control switch SW6 controls whether the seventh load transistor PM7 is connected to the first mirror branch, and the sixth control switch SW7 controls whether the eighth load transistor PM8 is connected to the second mirror branch. At this time, the channel width of the first load transistor PM1 is equal to the channel width of the original load transistor PM11, the transconductance of the first load transistor PM1 is equal to the transconductance of the original load transistor PM11, and the channel length of the first load transistor PM1 is equal to the channel length of the original load transistor PM11. The channel width of the second load transistor PM2 is equal to the channel width of the original load transistor PM12, the transconductance of the second load transistor PM2 is equal to the transconductance of the original load transistor PM12, and the channel length of the second load transistor PM2 is equal to the channel length of the original load transistor PM12. The channel length and width of the seventh load transistor PM7 and the eighth load transistor PM8 are determined by the actual simulation requirements and can be related to the first load transistor PM1 / second load transistor PM2 or not. This is equivalent to adding two additional load transistors to the original load transistors. Therefore, three or more load transistors can also be set in each mirror branch, which is equivalent to connecting two or more additional load transistors in parallel to the original load transistors.

[0059] Please see Figure 8 and Figure 9 As shown, in another specific embodiment of the present invention, the seventh load transistor PM7 and the eighth load transistor PM8 are PMOS transistors, and the sixth control switch SW6 and the seventh control switch SW7 are arbitrary type digital control switches, controlled by the switch control signal SW. In this case, the source of the seventh load transistor PM7 is electrically connected to the voltage source VDD, and the drain of the seventh load transistor PM7 is electrically connected to the drain of the ramp-coupled input transistor NM1 through the sixth control switch SW6. The source of the eighth load transistor PM8 is electrically connected to the voltage source VDD, and the drain of the eighth load transistor PM8 is electrically connected to the drain of the pixel-coupled input transistor NM2 through the seventh control switch SW7.

[0060] Please see Figure 8 and Figure 9As shown, in another embodiment of the present invention, when the comparator circuit is reset, the first reset signal rst1 is set high, and after the second stage comparator is reset through the second reset signal rst2, the sixth control switch SW6 and the seventh control switch SW7 are turned on, so that the seventh load transistor PM7 and the eighth load transistor PM8 are connected to the circuit. After the first reset signal rst1 is pulled low, the sixth control switch SW6 and the seventh control switch SW7 are turned off, so that the seventh load transistor PM7 and the eighth load transistor PM8 are disconnected from the circuit. During the subsequent comparison of the pixel voltage VPIX and the ramp voltage VRAMP, the sixth control switch SW6 and the seventh control switch SW7 are always kept in the off state, that is, to maintain the noise performance of the subsequent comparator. Therefore, during the reset process of the first stage comparator, the reset voltage of the two input terminals of the first stage comparator is obtained by the following formula: VINrst=VIPrst=VDD-VGS_eff.

[0061] Where VINrst is the reset voltage at one input of the first-stage comparator, VIPrst is the reset voltage at the other input of the first-stage comparator, VDD is the voltage source, and VGS_eff is the gate-source voltage of the first load transistor PM1 and the seventh load transistor PM7 connected in parallel in the first-stage comparator.

[0062] At this point, the maximum input swing of the comparator is obtained using the following formula: Vmax=VDD-VGS_eff-VGS_NM1-VDSAT0.

[0063] in, Vmax is the maximum input swing of the comparator, VDD is the voltage source, VGS_eff is the gate-source voltage of the first load transistor PM1 and the seventh load transistor PM7 connected in parallel in the first stage comparator, VGS_NM1 is the gate-source voltage of the ramp-coupled input transistor NM1, and VDSAT0 is the saturation voltage drop of the current source input transistor NM0.

[0064] VGS_eff and VGS_PM11 represent the on-state voltage drops of the first and second mirror branches under different conditions. Compared to the original load transistor PM11 in the first-stage comparator, due to the increased channel width, VGS_eff < VGS_PM11, thus the maximum input swing of the comparator is... Vmax increases. During the subsequent comparison of pixel voltage VPIX and ramp voltage VRAMP, the sixth control switch SW6 and the seventh control switch SW7 are always kept open, ensuring that the comparator's noise performance remains the same as the original comparator.

[0065] Please combine Figure 8 and Figure 10As shown, in another embodiment of the present invention, the first mirror branch load control device includes a first resistor R1 and an eighth control switch SW8. The first resistor R1 and the eighth control switch SW8 are connected in series and then connected in parallel to the first load transistor PM1. The second mirror branch load control device includes a second resistor R2 and a ninth control switch SW9. The second resistor R2 and the ninth control switch SW9 are connected in series and then connected in parallel to the second load transistor PM2. The eighth control switch SW8 controls whether the first resistor R1 is connected to the first mirror branch, and the ninth control switch SW9 controls whether the second resistor R2 is connected to the second mirror branch. Its principle is the same as that of connecting the seventh load transistor PM7 and the eighth load transistor PM8 in parallel.

[0066] Please combine Figures 8 to 10 As shown, in another embodiment of the present invention, when the comparator circuit is reset, the first reset signal rst1 is set high, and after the second stage comparator is reset through the second reset signal rst2, the eighth control switch SW8 and the ninth control switch SW9 are closed, so that the first resistor R1 is connected to the first mirror branch and the second resistor R2 is connected to the second mirror branch. After the first reset signal rst1 is pulled low, the eighth control switch SW8 and the ninth control switch SW9 are then opened, so that the first resistor R1 and the second resistor R2 are disconnected from the circuit. During the subsequent comparison of the pixel voltage VPIX and the ramp voltage VRAMP, the sixth control switch SW6 and the seventh control switch SW7 are always kept open, that is, the noise performance of the subsequent comparator is maintained.

[0067] In summary, the comparator circuit and image sensor provided by this invention include a first-stage comparator and a second-stage comparator. The first-stage comparator comprises a current mirror, a ramp-coupled input transistor, a pixel-coupled input transistor, and a current source input transistor. The first mirror branch of the current mirror, the ramp-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The second mirror branch of the current mirror, the pixel-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The control terminal of the ramp-coupled input transistor receives a ramp voltage, and the control terminal of the pixel-coupled input transistor receives a pixel voltage. A ramp reset transistor and a pixel reset transistor are also included, with the ramp reset transistor connected in series between the control terminal of the ramp-coupled input transistor and the ramp voltage. Between the coupling input transistor and the common terminal of the first mirror branch, the pixel reset transistor is connected in series between the control terminal of the pixel coupling input transistor and the common terminal of the pixel coupling input transistor and the second mirror branch, and the ramp reset transistor and the pixel reset transistor are controlled by a first reset signal; and a first mirror branch load controller and a second mirror branch load controller, allowing the first mirror branch load controller to connect to the first mirror branch, and allowing the second mirror branch load controller to connect to the second mirror branch; wherein, when the comparator circuit is reset, when the first reset signal is high, the first mirror branch load controller and the second mirror branch load controller are connected or disconnected from the circuit, reducing the on-state voltage drop of the first mirror branch and the second mirror branch. The second-stage comparator includes a common-source transistor and an output control transistor, which are connected in series between the voltage source and the ground terminal. The control terminal of the common-source transistor is electrically connected to the output terminal of the first-stage comparator. The control terminal of the output control transistor is grounded through an energy storage capacitor. An output reset transistor is connected in series between the control terminal of the output control transistor and the common terminal of the output control transistor and the common-source transistor. The output reset transistor is controlled by a second reset signal.

[0068] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A comparator circuit, characterized in that, The comparator circuit includes a first-stage comparator, and the first-stage comparator includes: The system comprises a current mirror, a ramp-coupled input transistor, a pixel-coupled input transistor, and a current source input transistor. The first mirror branch of the current mirror, the ramp-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The second mirror branch of the current mirror, the pixel-coupled input transistor, and the current source input transistor are connected in series between a voltage source and a ground terminal. The control terminal of the ramp-coupled input transistor receives a ramp voltage, and the control terminal of the pixel-coupled input transistor receives a pixel voltage. A ramp reset transistor and a pixel reset transistor are provided. The ramp reset transistor is connected in series between the control terminal of the ramp coupled input transistor and the common terminal of the ramp coupled input transistor and the first mirror branch. The pixel reset transistor is connected in series between the control terminal of the pixel coupled input transistor and the common terminal of the pixel coupled input transistor and the second mirror branch. Both the ramp reset transistor and the pixel reset transistor are controlled by a first reset signal. The first mirror branch load controller and the second mirror branch load controller allow the first mirror branch load controller to connect to the first mirror branch and allow the second mirror branch load controller to connect to the second mirror branch. When the comparator circuit is reset, if the first reset signal is high, the first mirror branch load controller and the second mirror branch load controller are connected or disconnected from the circuit, thereby reducing the on-state voltage drop of the first mirror branch and the second mirror branch.

2. The comparator circuit according to claim 1, characterized in that, The first mirror branch includes a first load transistor connected in series between the voltage source and the ramp-coupled input transistor. The second mirror branch includes a second load transistor connected in series between the voltage source and the pixel-coupled input transistor.

3. A comparator circuit according to claim 2, characterized in that, The first mirror branch load controller includes a third load transistor and a first control switch. The third load transistor is connected in series with the first load transistor, and the first control switch is connected in parallel with the third load transistor. The second mirror branch load controller includes a fourth load transistor and a second control switch. The fourth load transistor is connected in series with the second load transistor, and the second control switch is connected in parallel with the fourth load transistor.

4. A comparator circuit according to claim 3, characterized in that, When the comparator circuit is reset, when the first reset signal is high, the first control switch and the second control switch are closed, short-circuiting the third load transistor and the fourth load transistor; after the first reset signal is pulled low, the first control switch and the second control switch are opened, connecting the third load transistor to the first mirror branch and the fourth load transistor to the second mirror branch.

5. A comparator circuit according to claim 1, characterized in that, The comparator circuit includes a second-stage comparator, and the second-stage comparator includes: A common-source transistor and an output control transistor are connected in series between the voltage source and the ground terminal. The control terminal of the common-source transistor is electrically connected to the output terminal of the first-stage comparator. The control terminal of the output control transistor is grounded through an energy storage capacitor. An output reset transistor is connected in series with the control terminal of the output control transistor and the common terminal of the output control transistor and the common source transistor, and the output reset transistor is controlled by a second reset signal.

6. A comparator circuit according to claim 5, characterized in that, The second-stage comparator also includes a common-source transconductance regulator and a third control switch. The common-source transconductance regulator is connected in series with the common-source transistor, and the third control switch is connected in parallel with the common-source transconductance regulator. When the second reset signal is high, the third control switch is disconnected, so that the common-source transconductance regulator is connected to the second-stage comparator.

7. A comparator circuit according to claim 2, characterized in that, The first mirror branch load controller includes a fifth load transistor and a fourth control switch. The fifth load transistor is connected in series with the first load transistor, and the fourth control switch is connected in parallel with the first load transistor. The second mirror branch load controller includes a sixth load transistor and a fifth control switch. The sixth load transistor is connected in series with the second load transistor, and the fifth control switch is connected in parallel with the second load transistor.

8. A comparator circuit according to claim 7, characterized in that, When the comparator circuit is reset, when the first reset signal is high, the fourth control switch and the fifth control switch are closed, so that the first load transistor is connected to the first mirror branch and the second load transistor is connected to the second mirror branch; after the first reset signal is pulled low, the fourth control switch and the fifth control switch are opened, so that the first load transistor is connected to the first mirror branch and the second load transistor is connected to the second mirror branch.

9. A comparator circuit according to claim 2, characterized in that, The first mirror branch load controller includes a seventh load transistor and a sixth control switch. The seventh load transistor and the sixth control switch are connected in series and then connected in parallel to the first load transistor. The second mirror branch load controller includes an eighth load transistor and a seventh control switch. The eighth load transistor and the seventh control switch are connected in series and then connected in parallel to the second load transistor.

10. A comparator circuit according to claim 9, characterized in that, When the comparator circuit is reset, when the first reset signal is high, the sixth control switch and the seventh control switch are closed, so that the seventh load transistor is connected to the first mirror branch and the eighth load transistor is disconnected from the second mirror branch; after the first reset signal is pulled low, the sixth control switch and the seventh control switch are then disconnected, so that the seventh load transistor and the eighth load transistor are disconnected from the circuit.

11. A comparator circuit according to claim 2, characterized in that, The first mirror branch load controller includes a first resistor and an eighth control switch. The first resistor and the eighth control switch are connected in series and then connected in parallel to the first load transistor. The second mirror branch load controller includes a second resistor and a ninth control switch. The second resistor and the ninth control switch are connected in series and then connected in parallel to the second load transistor.

12. A comparator circuit according to claim 11, characterized in that, When the comparator circuit is reset, when the first reset signal is high, the eighth control switch and the ninth control switch are closed, so that the first resistor is connected to the first mirror branch and the second resistor is connected to the second mirror branch. After pulling the first reset signal low, the eighth control switch and the ninth control switch are then disconnected, so that the first resistor and the second resistor are disconnected from the circuit.

13. An image sensor, characterized in that, At least including: A pixel array, including an effective pixel region, wherein the effective pixel region outputs an effective pixel voltage; A ramp generator that generates a ramp voltage; The comparator as described in any one of claims 1 to 12, wherein the pixel voltage is input to the control terminal of the pixel-coupled input transistor, and the ramp voltage is input to the control terminal of the ramp-coupled input transistor; and A counter, electrically connected to the output of the comparator, counts the pixel voltage.

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