A method and system for online control of the uniformity of electrical properties within a wafer plane
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- QINGDAO UNIV OF SCI & TECH
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-26
Smart Images
Figure CN122094469A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and specifically to a method and system for online control of the uniformity of electrical properties within a wafer plane. Background Technology
[0002] In the semiconductor manufacturing field, as process nodes continue to shrink to the nanoscale, the uniformity of the electrical performance of devices within the wafer surface has become a key factor restricting yield and product performance. During the process, due to uneven airflow, temperature, and plasma distribution within the equipment chamber, as well as physical differences between the wafer's edges and center, critical parameters such as film thickness, doping concentration, and key dimensions exhibit complex spatial distribution fluctuations on the wafer surface. These minute fluctuations in front-end process parameters, accumulated and amplified by subsequent process steps, ultimately cause significant mismatches in core electrical characteristics such as transistor threshold voltage and drive current across different regions of the wafer. This mismatch not only reduces the overall performance and reliability of the chip, but also directly leads to functional failure in products with extremely high consistency requirements, such as memory and analog circuits.
[0003] Currently, the industry's commonly used uniformity control methods mainly rely on post-processing detection and passive adjustments. Specifically, offline electrical testing is typically performed after a batch of wafers has completed all or all critical process steps, and performance distribution trends are analyzed through statistical data. Engineers then make tentative adjustments to global process parameters (such as average implantation dose and annealing temperature) for subsequent batches based on this lag data and long-accumulated empirical models. This method has several inherent drawbacks: First, it relies on batch-to-batch feedback and cannot intervene in real-time on individual wafers being processed, essentially a "lock-the-barrel" approach. Second, the adjustment strategy is global and uniform, unable to achieve fine-grained local compensation for different locations on the wafer, making it difficult to cope with complex spatial non-uniformity patterns. Finally, it heavily relies on expert experience, resulting in long adjustment cycles, low efficiency, and a lack of agile adaptability to new products and processes. Therefore, there is an urgent need for a new method and system that can perform online, real-time, and spatially adaptive control to achieve proactive and precise control of wafer-level electrical performance uniformity.
[0004] Therefore, existing technologies still need further development. Summary of the Invention
[0005] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a method and system for online control of the uniformity of electrical properties within a wafer surface, so as to solve the problems existing in the prior art.
[0006] To achieve the above-mentioned technical objectives, according to a first aspect of the present invention, the present invention provides a method for online control of the uniformity of electrical properties within a wafer plane, comprising: S100. During wafer fabrication, key process parameters at multiple locations within the wafer surface are obtained; S200. The key process parameters are input into a pre-trained machine learning model to predict the estimated electrical performance at different locations within the wafer plane. The machine learning model is configured to model the spatial correlation between different locations within the wafer plane. S300. Based on the difference between the estimated electrical performance and the target electrical performance, generate a space-adaptive process formula for differentiated process compensation in different regions of the wafer. S400. Based on the space-adaptive process formulation, adjust at least one process parameter in subsequent process steps to actively correct electrical performance deviations within the wafer plane.
[0007] Specifically, the machine learning model is a graph neural network, in which different locations on the wafer are modeled as nodes of a graph, and spatial or process relationships between locations are modeled as edges of the graph.
[0008] Specifically, the training process of the graph neural network incorporates historical wafer data from different process batches or different product models to enhance the model's generalization ability under different process conditions.
[0009] Specifically, the method further includes: training an agent using a reinforcement learning algorithm, wherein the agent dynamically makes decisions and outputs the spatially adaptive process recipe based on the current wafer process parameters and the prediction results of the graph neural network.
[0010] Specifically, the reward function of the reinforcement learning algorithm is constructed based on the modified uniformity index of the actual electrical performance of the wafer, so as to guide the learning direction of the agent.
[0011] Specifically, the key process parameters include at least one of the following: film thickness, key dimensions, and doping concentration, measured by an integrated metering unit.
[0012] Specifically, the generation of space-adaptive process formulations includes: generating differentiated doping compensation formulations or differentiated stress application formulations for different regions of the wafer.
[0013] Specifically, adjusting at least one process parameter in subsequent process steps includes performing the differentiated process compensation by adjusting at least one of the following methods: adjusting the mask pattern in the photolithography process, adjusting the implantation dose and energy in the ion implantation process, or adjusting the temperature and time in the annealing process.
[0014] Specifically, the pre-trained machine learning model is a model built on a meta-learning framework, which can be quickly and adaptively fine-tuned based on a small amount of initial measurement data from the current wafer.
[0015] According to a second aspect of the present invention, an online control system for the uniformity of electrical properties within a wafer surface is provided, comprising: The parameter acquisition module is configured to acquire key process parameters at multiple locations within the wafer surface during wafer fabrication. The performance prediction module has a built-in machine learning model configured to receive the key process parameters and predict the estimated electrical performance at different locations within the wafer surface. The machine learning model is configured to model the spatial correlation between different locations within the wafer surface. The recipe generation module is configured to generate a spatially adaptive process recipe for differentiated process compensation in different regions of the wafer based on the difference between the estimated electrical performance and the target electrical performance. The process execution module is configured to adjust at least one process parameter in subsequent process steps based on the space-adaptive process recipe, so as to actively correct electrical performance deviations within the wafer plane.
[0016] Beneficial effects: The online control method and system for uniformity of in-plane electrical properties of wafers based on machine learning models provided by this invention can bring significant multi-level beneficial effects compared with the prior art.
[0017] First, this invention represents a fundamental shift from "offline batch feedback" to "online single-wafer feedforward," constructing a real-time intelligent closed loop. By directly acquiring key process parameters during manufacturing and utilizing a pre-trained model to predict final performance in real time, the system can generate and execute compensation formulas before the current wafer flows into the next process step. This completely eliminates the time lag of traditional methods, enabling real-time perception and immediate suppression of process fluctuations, and greatly improving manufacturing agility and controllability.
[0018] Secondly, by introducing machine learning models with spatial modeling capabilities, especially graph neural networks, this invention can accurately capture and quantify the complex relationships and interactions between process parameters at different locations on the wafer. This makes the prediction of performance distribution no longer independent of individual points, but a holistic and accurate extrapolation based on the spatial topology, with prediction accuracy far exceeding that of traditional statistical models, laying a reliable data foundation for generating scientifically effective compensation strategies.
[0019] Furthermore, this invention integrates advanced decision-making algorithms such as reinforcement learning into the control closed loop, enabling the system to automatically learn and optimize compensation strategies. Through interaction with the environment, the intelligent agent autonomously explores the optimal spatial compensation scheme for various non-uniformity patterns. Its decision-making transcends the limitations of fixed rules and the boundaries of human experience, achieving automation and optimization of the control process. This improves uniformity while ensuring the pass rate of product performance.
[0020] Furthermore, the solution of this invention has good compatibility and feasibility with existing semiconductor production line equipment. Its data comes from standard integrated metering units, and control commands can be directly issued to programmable process equipment (such as ion implanters and annealing equipment). No modification to core hardware is required; the functionality can be achieved mainly through software and intelligent algorithm upgrades. The industry adoption threshold is low, and the practical value is high.
[0021] Finally, by incorporating few-shot learning techniques such as meta-learning, the system of this invention exhibits strong adaptive capabilities. When faced with new product introductions or process drift, it can rapidly fine-tune the model using minimal data, quickly adapting to new manufacturing scenarios. This solves a core bottleneck in the application of artificial intelligence in data-scarce advanced manufacturing, enabling the system to possess continuous evolutionary capabilities and broad applicability. Attached Figure Description
[0022] Figure 1 This is a flowchart illustrating the method for online control of the uniformity of electrical properties within a wafer plane provided in a specific embodiment of the present invention. Figure 2 This is a schematic diagram of the system composition of the online control system for the uniformity of electrical properties within a wafer plane provided in a specific embodiment of the present invention. Detailed Implementation
[0023] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.
[0024] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.
[0025] Please see Figure 1 This invention provides a method for online control of the uniformity of electrical properties within a wafer plane, comprising: S100. During wafer fabrication, acquire key process parameters at multiple locations within the wafer surface.
[0026] It should be further explained that this method begins with online measurements at a specific wafer fabrication site, such as after ion implantation or rapid thermal annealing. Integrated optical metrology units (such as ellipsometers) or electrical metrology units (such as four-probe testers) are used to acquire parameters such as film thickness and sheet resistance according to a pre-set spatial sampling plan (e.g., a polar coordinate grid with the wafer center as the origin, selecting four azimuth angle points at radii of 0mm, 75mm, and 145mm, respectively, for a total of nine measurement points). These parameters constitute the initial feature vector for each sampling point.
[0027] S200. The key process parameters are input into a pre-trained machine learning model to predict the estimated electrical performance at different locations within the wafer plane. The machine learning model is configured to model the spatial correlation between different locations within the wafer plane.
[0028] It should be further explained that this step inputs the feature set of all sampling points on the entire wafer into a pre-trained machine learning model. The core capability of this model lies in its internal structure, which can identify and utilize the spatial dependencies between different measurement points on the wafer. For example, the film thickness at one point may affect the stress distribution in its adjacent areas during subsequent heat treatment, thereby affecting the final threshold voltage (Vth). Based on this spatial correlation pattern, the model outputs the estimated electrical performance for each point, such as saturation current (Idsat) or threshold voltage (Vth).
[0029] S300. Based on the difference between the estimated electrical performance and the target electrical performance, generate a space-adaptive process formula for differentiated process compensation in different regions of the wafer.
[0030] It should be further explained that this step compares the predicted performance distribution map of the entire wafer with an idealized, uniform target performance distribution map to calculate the performance deviation of each region (the wafer can be divided into multiple concentric rings or sector partitions). Based on this deviation, a decision algorithm generates a compensation recipe, which is not a single global value, but a spatial distribution function, such as a "dose compensation map," which explicitly indicates that region A on the wafer needs a 2% increase in implantation dose and region B needs a 1% decrease in dose.
[0031] S400. Based on the space-adaptive process formulation, adjust at least one process parameter in subsequent process steps to actively correct electrical performance deviations within the wafer plane.
[0032] It should be further explained that the formula generated in the above steps is converted into control instructions executable by downstream process equipment (such as a scanning ion implanter). By controlling the scanning speed of the ion implanter and the residence time of the beam at different positions on the wafer, spatially differentiated adjustments of the dosage are achieved, thereby physically altering the doping concentration distribution and actively correcting electrical performance deviations.
[0033] Understandably, this method constructs a complete intelligent closed loop from "online monitoring" to "spatial prediction" to "feedforward compensation," replacing the traditional passive mode that relies on post-event electrical testing and inter-batch experience adjustments. By utilizing the spatial correlation model built into the machine learning model, it can more accurately predict the propagation effect of process fluctuations on the wafer, thereby generating more scientific and refined local compensation instructions. This not only improves the performance uniformity of a single wafer but also achieves real-time proactive suppression of process fluctuations, improving the process window and production yield.
[0034] Specifically, the machine learning model is a graph neural network, in which different locations on the wafer are modeled as nodes of a graph, and spatial or process relationships between locations are modeled as edges of the graph.
[0035] It should be further explained that the specific construction method of a Graph Neural Network (GNN) is as follows: each measurement point is treated as a node. Node feature vectors It can be represented as ,in For film thickness, For thin-film resistors, For critical dimensions (if they can be measured in this step). and Here are the polar coordinates of the point. Edges are constructed based on the principle of spatial proximity: for each node... Calculate its Euclidean distance to all other nodes on the wafer. ,like Then at node and Establish an undirected edge between them Distance threshold The preferred value is 50mm to 80mm. The rationale for choosing this range is that, on a 300mm wafer, this distance effectively covers the typical correlation lengths caused by process fluctuations due to spin coating, uneven thermal field distribution, etc., capturing meaningful spatial correlations while avoiding the introduction of noise and increased computational complexity from connecting excessively distant irrelevant nodes. Each edge can be assigned an initial weight. ,in For the scale parameter, preferably .
[0036] Furthermore, a Graph Attention Network (GAT) layer is used for message passing. In each layer, for each node... and its neighboring nodes Calculate the attention coefficient ,in It is a learnable weight matrix. It is an attention vector. This indicates a splicing operation; the negative slope parameter of Leaky ReLU is preferably 0.2. Then, the nodes... The update feature is After multiple layers of such aggregation, the final node representation is input into a fully connected layer to regress and predict electrical performance values. .
[0037] Understandably, by employing graph neural networks, particularly GAT, the wafer's topology is explicitly incorporated into the model, enabling the model to autonomously learn the strength and direction of influences between different locations (through attention coefficients). This approach, compared to treating the wafer as a set of independent points or simply using coordinates as features in neural networks, better reflects the physical nature of process variations in semiconductor manufacturing (which possesses spatial continuity), thus enabling more accurate and reliable predictions.
[0038] Specifically, the training process of the graph neural network incorporates historical wafer data from different process batches or product models to enhance the model's generalization ability under different process conditions. It should be further noted that the training dataset consists of multiple "sub-datasets," each corresponding to a specific process batch or product model (e.g., batch 001 of product A, batch 002 of product B). Each sample is a pair... ,in It is a graph constructed using the aforementioned method. This is the measured electrical performance vector at the corresponding location. To improve the model's generalization ability, domain adversarial training is introduced during training. The specific steps are as follows: In the feature extractor of GNN (i.e., the final node representation) After that, two prediction heads are connected in parallel: a main task head (regressor) is used for prediction. A domain discriminator (classifier) is used to determine node features. From which batch or product area does it originate? The training objective is to minimize the loss of the main task. Simultaneously maximize the loss of the neighborhood discriminator (That is, to prevent the discriminator from distinguishing the source of features), this is achieved through a gradient reversal layer during backpropagation. The total loss function is... ,in This is a tradeoff coefficient, with an optimal value of 0.5 to 1.5. The rationale for choosing this range is the need to balance performance prediction accuracy with feature-domain invariance; a value that is too low (<0.5) would result in a loss of accuracy. This can lead to insufficient domain invariance, and an excessively high value (>1.5) may impair the performance of the main task. The model uses the Adam optimizer with an initial learning rate of 0.001 and a batch size of 32. It stops after the total loss converges or the maximum number of iterations (e.g., 500) is reached.
[0039] Understandably, by fusing multi-source data and employing domain adversarial training, the feature representations learned by the model are forced to be "domain invariant," meaning that interference from batch- or product-specific variations is eliminated, retaining only process features that are fundamentally causally related to electrical performance. This significantly enhances the model's predictive stability and accuracy when encountering new batches or new products in a production environment, reducing the cost of model maintenance and retraining.
[0040] Specifically, the method further includes: training an agent using a reinforcement learning algorithm, wherein the agent dynamically makes decisions and outputs the spatially adaptive process recipe based on the current wafer process parameters and the prediction results of the graph neural network.
[0041] It should be further noted that the training of the reinforcement learning agent is an offline process. The environment simulator is built based on historical data or process simulation (TCAD), and its state... It consists of two parts: one is the current (simulated) wafer process parameter diagram. Secondly, GNN for Predictive performance distribution .action Defined as a spatial modulation factor for a standard process formulation. For example, for ion implantation dosage, It can be a dimension A vector (e.g., M=5, representing 5 concentric annular partitions), where each element , which represents the dose adjustment factor for the corresponding partition.
[0042] Furthermore, the agent is trained using the Proximal Policy Optimization (PPO) algorithm. Its policy network... It is a multilayer perceptron, and the input is the state. The agent aggregates features (e.g., a graph-level representation obtained by pooling the node features output by a GNN), and the output consists of parameters (mean and variance) defining the action probability distribution (e.g., a Gaussian distribution). In each simulation, the agent selects actions according to the policy. The environment simulator applies this action (i.e., press...). Modulate the dosage and simulate subsequent process steps and final electrical performance to calculate the reward. Then proceed to the next state (Simulating the next wafer).
[0043] Furthermore, the PPO algorithm maximizes the alternative objective function with clipping. To update the policy network parameters ,in For probability ratios, It is the advantage function calculated through generalized advantage estimation (GAE). This is the cutting parameter, with a preferred value of 0.2. It's the discount factor in PPO. Optimal value: 0.99, GAE parameter 0.95 is preferred. These values were chosen to balance long-term and current rewards and to ensure the stability of strategy updates.
[0044] Understandably, training the agent through reinforcement learning solves the mapping problem from complex prediction results to optimal compensation decisions. Through trial and error with the environment (simulated process), the agent autonomously learns which optimal spatial compensation strategy to adopt when facing various non-uniformity patterns, thereby automating and optimizing the decision-making process.
[0045] Specifically, the reward function of the reinforcement learning algorithm is constructed based on the modified uniformity index of the actual electrical performance of the wafer, so as to guide the learning direction of the agent.
[0046] It should be further explained that the reward function The specific design is as follows: in: The simulated electrical properties within the wafer (e.g., after applying a compensation formula) are obtained. The standard deviation of ) This is the target standard deviation value that is expected to be achieved, for example, it can be set to 90% of the historical best value; First item The direct reward is an improvement in uniformity, with a positive reward given when the actual standard deviation is less than the target value. The preferred value is 10; Second item It is a reward for meeting the average target. It is an indicator function, when the average performance Higher than the lower limit of specifications At that time, this item is Otherwise, it is 0. The preferred value is 5; Third item This is the worst-case scenario reward, where even the worst-case performance is above the lower limit of the specification. At that time, this item is Otherwise, it is 0. The preferred value is 3.
[0047] Further, choose The rationale is that the primary goal is to improve uniformity, followed by ensuring average performance is acceptable, and finally ensuring all points are acceptable. This weighting guides the agent to prioritize exploring strategies with optimal uniformity while also considering the acceptance rate constraint. If improved uniformity leads to unacceptable performance, the reward will be penalized.
[0048] Understandably, this reward function quantifies complex production objectives (high uniformity, high yield) into a computable scalar signal, effectively guiding the policy search direction of the reinforcement learning agent. It ensures that the learned policy not only pursues extreme uniformity but also meets the rigid requirements of actual production for the absolute value of device performance, avoiding the creation of technically effective but commercially unfeasible compensation schemes.
[0049] Specifically, the key process parameters include at least one of the following: film thickness, key dimensions, and doping concentration, measured by an integrated metering unit.
[0050] It should be further noted that the film thickness is preferably measured using a multi-wavelength ellipsometer integrated within the reaction chamber of the deposition or annealing equipment, by measuring the amplitude ratio of the polarized light after reflection. and phase difference The thickness value can be derived from a pre-established optical model (such as the Cauchy model) with a measurement accuracy of up to 0.1 angstroms.
[0051] Furthermore, the measurement of critical dimensions preferably employs an optical scattering (OCD) instrument integrated next to the photolithography or etching equipment. By analyzing the diffraction spectrum and matching it with a pre-calculated spectral library, three-dimensional morphology parameters such as linewidth and sidewall angle are obtained, and the measurement repeatability (3σ) can reach 0.1 nm.
[0052] Furthermore, direct online measurement of doping concentration is difficult, and it is usually reflected indirectly through its electrical characterization—thin-film resistance. Using a non-contact four-probe tester integrated within the vacuum transmission chamber of an ion implanter or annealing equipment, the voltage drop generated when four collinear probes induce current on the wafer surface is measured, according to the formula... Calculate the resistance of a thin film ,in For voltage, For the current. Then, based on the known implantation type and energy, using ion implantation models (such as Pearson IV distribution) or table lookup methods, the current is determined. This is correlated with the activated carrier concentration. In practice, at least one parameter can be selected for measurement based on the main influencing parameters of the current process step. For example, after polysilicon gate etching, the critical dimension is critical; after source / drain ion implantation, the sheet resistance is critical.
[0053] Understandably, clearly defining these core, directly or indirectly measurable process parameters provides a clear technical path for data acquisition. These parameters are the most direct precursor variables determining the final MOSFET electrical performance (such as threshold voltage and drive current). Accurate online measurement of these high-value parameters provides high-quality, highly relevant input for subsequent intelligent prediction, ensuring the reliability of the fundamental data for the entire closed-loop control system.
[0054] Specifically, the generation of space-adaptive process formulations includes: generating differentiated doping compensation formulations or differentiated stress application formulations for different regions of the wafer.
[0055] It should be further explained that the process of generating the differentiated doping compensation formula is as follows: First, based on the predicted performance deviation distribution map (e.g., (Higher areas), combined with the process knowledge base (which stores information such as " With channel doping concentration The corresponding curve (the performance deviation is converted into the required doping concentration adjustment) is used to convert the performance deviation into the required doping concentration adjustment. ,in These are the coordinates on the wafer surface.
[0056] Then, based on the ion implantation model, the doping concentration is adjusted. Convert to the corresponding ion implantation dose adjustment amount The final product is a digitized two-dimensional dose compensation map. For differentiated stress application formulations, such as tensile stress for NMOS devices and compressive stress for PMOS devices, if the predicted electron mobility of an NMOS region is insufficient, the formulation generation module calculates the required increase in tensile stress for that region. Based on the model in the process knowledge base regarding the relationship between the thickness / internal stress of the contact hole etch stop layer (CESL) and the effective stress applied to the channel, the following will be implemented: This is converted into the target thickness or target gas flow rate ratio of the region in the CESL deposition process, generating a spatially distributed set of control instructions.
[0057] Understandably, by specifically implementing the compensation formula onto doping and stress—the two most core and effective performance modulation methods—this invention's regulation possesses profound physical significance and powerful effects. By inversely mapping the predicted "electrical performance deviation" into executable "process parameter adjustment amounts," a seamless bridge is achieved from the virtual information space to the physical manufacturing space. This enables intelligent decision-making to directly drive the process equipment to produce the required, customized material property changes, thereby precisely correcting device performance.
[0058] Specifically, adjusting at least one process parameter in subsequent process steps includes performing the differentiated process compensation by adjusting at least one of the following methods: adjusting the mask pattern in the photolithography process, adjusting the implantation dose and energy in the ion implantation process, or adjusting the temperature and time in the annealing process.
[0059] It should be further explained that the specific implementation of using adjustments to the mask pattern in the photolithography process to perform differential doping compensation is as follows: Based on the generated dose compensation map This is converted into a graphical transmittance distribution of a correction reticle. The conversion relationship is as follows: This compensation mask can be a gray-tone mask or a half-tone mask, with the transmittance of different areas varying continuously or in steps. In the ion implantation process, the wafer first undergoes exposure and development of a standard pattern through the master mask to form a photoresist pattern.
[0060] Then, using this compensation mask, a second "compensation exposure" is performed without replacing the wafer. The light dose distribution during the compensation exposure is shown. ,in The exposure energy is used. Ultimately, the total light dose received at each point on the wafer (or the equivalent photoresist removal rate) is the sum of the two exposures, thus achieving spatial modulation of the dose during ion implantation because the number of ions passing through photoresist of different thicknesses varies.
[0061] Furthermore, adjusting the ion implantation dose and energy is even more direct: for ion implanters with beam scanning and precise wafer stepping control capabilities, the control system will receive... The spectrum was calculated in real time into ion beam current density. and wafer stage scanning speed The matching relationship makes the coordinates Injection dose at the site The settings are met. Adjusting the annealing temperature and time can be achieved using a multi-zone rapid thermal annealing (RTA) device. Different heating zones on the device can have their power independently controlled, thereby creating different temperature distributions along the wafer's radial direction. This allows for differentiated adjustment of doping activation rate and stress relaxation in different regions.
[0062] It is understood that this invention provides various specific physical execution paths that interface with existing mature process equipment. These methods do not invent entirely new equipment, but rather represent innovative combinations and intelligent control of the functions of existing high-precision equipment. This demonstrates the feasibility and industrial integration of this invention, enabling semiconductor factories to upgrade and transform existing production lines to achieve the intelligent uniformity control described in this invention, significantly reducing implementation barriers and costs.
[0063] Specifically, the pre-trained machine learning model is a model built on a meta-learning framework, which can be quickly and adaptively fine-tuned based on a small amount of initial measurement data from the current wafer.
[0064] It should be further explained that the specific implementation steps of the Model-Independent Meta-Learning (MAML) framework are as follows: During the meta-training phase, a large number of tasks are constructed from historical multi-product data. Each task corresponds to a specific process context (such as a product model), and the support set for that task contains... Complete wafer data in this scenario (process parameter diagram) and measured electrical performance The query set contains several additional pieces for testing. Ideally, 3 to 5 pieces should be used. This small sample size is chosen to simulate a data-scarce scenario during New Product Introduction (NPI). The goal of MAML is to find a set of initial model parameters. This makes it possible to sample new tasks from the task distribution. ,Model Using only this new task Update each support sample with a small number of gradient steps (inner loop). Then, the loss on the query set. Minimum. The inner loop update formula is: ,in The inner loop learning rate is preferably 0.01. The outer loop (meta-update) updates the learning rate using gradient descent. : ,in It is the outer loop learning rate, preferably 0.001.
[0065] Furthermore, when deployed on the production line, when encountering a completely new product model, the system first uses the model name previously used. Using the data from three completed wafers as the support set, the pre-trained meta-model is trained. Perform 1 to 5 inner loop gradient updates to quickly obtain the optimal model adapted to this new product. This finely tuned model was then used to provide services for subsequent wafers of the same type.
[0066] Understandably, the introduction of meta-learning endows the model with powerful "few-shot learning" and "rapid adaptation" capabilities. This enables the intelligent control system of this invention to quickly understand the characteristics of new processes or new products using minimal initial production data (3-5 wafers), just like a human engineer, and to provide accurate predictions and decisions. This solves the core bottleneck of applying AI models in semiconductor manufacturing, a scenario characterized by high data acquisition costs and rapid product iteration, making the system both agile and economical for practical use.
[0067] Please see Figure 2 The present invention provides another embodiment, which provides an online control system for the uniformity of electrical properties within a wafer plane. The online control system for the uniformity of electrical properties within a wafer plane includes: (1) Parameter acquisition module 100, configured to acquire key process parameters at multiple locations within the wafer surface during wafer processing. It should be further explained that the parameter acquisition module 100 is physically composed of a group of sensors deployed in the chambers or transmission paths of key process equipment (such as coating and developing machines, etching machines, and ion implanters), for example, an integrated ellipsomerometer, an integrated scatterometer, and an integrated four-probe station. These sensors are connected to the upper-level control system via a device communication bus (such as SECS / GEM) to upload measurement data in real time.
[0068] (2) Performance prediction module 200, which has a pre-set machine learning model configured to receive the key process parameters and predict the estimated electrical performance at different locations within the wafer surface. The machine learning model is configured to model the spatial correlation between different locations within the wafer surface.
[0069] It should be further explained that the performance prediction module 200 is deployed on the edge computing server or cloud server in the workshop. Its core is an inference engine (such as an engine optimized using TensorRT) loaded with a pre-trained graph neural network model file. This module receives raw data from the parameter acquisition module through the workshop network (such as Ethernet), organizes the data into a graph structure according to a preset graph construction protocol, performs forward inference calculations, and passes the prediction results (usually a list containing coordinates and predicted values) to the recipe generation module.
[0070] (3) Recipe generation module 300, configured to generate a spatially adaptive process recipe for different regions on the wafer to perform differentiated process compensation based on the difference between the estimated electrical performance and the target electrical performance.
[0071] It should be further noted that the recipe generation module 300 also runs on a computing server. It includes a policy execution unit that loads a policy network model trained through reinforcement learning. It receives the results from the performance prediction module and combines them with the target specifications of the current process (such as...). The system calculates the performance deviation, then calls the policy network model, inputs the current state (process parameter diagram and performance prediction diagram), and outputs the optimal compensation action vector (i.e., process formula).
[0072] (4) Process execution module 400, configured to adjust at least one process parameter in subsequent process steps according to the space-adaptive process formula, so as to actively correct the electrical performance deviation in the wafer plane.
[0073] It should be further explained that the process execution module 400 is a combination of hardware and software. Its software part runs on the equipment host and is responsible for translating the abstract compensation instructions (such as "zonal dose adjustment vector") sent by the formula generation module into specific instruction sequences that the downstream process equipment controller can understand (such as the scanning speed control instruction file for a certain type of ion implanter). Its hardware part is the programmable logic controller (PLC) or motion control card of the downstream process equipment itself. It receives and executes these instructions to precisely control mechanical or physical parameters (such as beam switch, heater power, and gas valve opening), thereby realizing spatially differentiated process compensation at the physical level. All modules exchange data and synchronize status through a unified factory automation protocol, forming a real-time, online intelligent control closed loop.
[0074] Understandably, this system visualizes each key step in the aforementioned methods as an independent, functionally defined hardware and software module, clearly defining the interfaces and data flows between modules. This modular design facilitates system development, deployment, and maintenance. It fully utilizes existing metering equipment, network infrastructure, and programmable process equipment in modern semiconductor factories, achieving a qualitative leap in the perception, decision-making, and execution capabilities of the manufacturing process by adding an intelligent computing layer. This system constitutes a complete intelligent manufacturing entity, its innovation lying in the deep integration of advanced AI algorithms with precision semiconductor manufacturing equipment, constructing the industry's first online uniformity control system capable of achieving "spatial adaptive feedforward compensation," possessing significant industrial application value.
[0075] In a preferred embodiment, this application also provides an electronic device, the electronic device comprising: The computer device includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, implement the online control method for uniform electrical performance in the wafer plane. The computer device can be broadly categorized as a server, terminal, or any other electronic device with the necessary computing and / or processing capabilities. In one embodiment, the computer device may include a processor, memory, network interface, communication interface, etc., connected via a system bus. The processor of the computer device can be used to provide the necessary computing, processing, and / or control capabilities. The memory of the computer device may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system, computer programs, etc. The internal memory can provide an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface and communication interface of the computer device can be used to connect and communicate with external devices via a network. When the computer program is executed by the processor, it performs the steps of the method of the present invention.
[0076] This invention can be implemented as a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the steps of the methods of embodiments of the invention to be performed. In one embodiment, the computer program is distributed across multiple network-coupled computer devices or processors, such that the computer program is stored, accessed, and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, may be executed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations may be executed by one or more computer devices or processors, and one or more other method steps / operations may be executed by one or more other computer devices or processors. One or more computer devices or processors may execute a single method step / operation, or execute two or more method steps / operations.
[0077] Those skilled in the art will understand that the method steps of this invention can be performed by a computer program instructing related hardware, such as a computer device or processor, to perform the steps of this invention when executed. Depending on the context, any references herein to memory, storage, databases, or other media may include non-volatile and / or volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, etc. Examples of volatile memory include random access memory (RAM), external cache memory, etc.
[0078] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.
[0079] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A method for online control of in-plane electrical performance uniformity of a wafer based on a machine learning model, characterized in that, include: S100. During wafer fabrication, key process parameters at multiple locations within the wafer surface are obtained; S200. The key process parameters are input into a pre-trained machine learning model to predict the estimated electrical performance at different locations within the wafer plane. The machine learning model is configured to model the spatial correlation between different locations within the wafer plane. S300. Based on the difference between the estimated electrical performance and the target electrical performance, generate a space-adaptive process formula for differentiated process compensation in different regions of the wafer. S400. Based on the space-adaptive process formulation, adjust at least one process parameter in subsequent process steps to actively correct electrical performance deviations within the wafer plane.
2. The method according to claim 1, characterized in that, The machine learning model is a graph neural network, in which different locations on the wafer are modeled as nodes of a graph, and spatial or process relationships between locations are modeled as edges of the graph.
3. The method according to claim 2, characterized in that, The training process of the graph neural network incorporates historical wafer data from different process batches or different product models to enhance the model's generalization ability under different process conditions.
4. The method according to claim 3, characterized in that, The method further includes: training an agent using a reinforcement learning algorithm, wherein the agent dynamically makes decisions and outputs the spatially adaptive process recipe based on the current wafer process parameters and the prediction results of the graph neural network.
5. The method according to claim 4, characterized in that, The reward function of the reinforcement learning algorithm is constructed based on the modified wafer actual electrical performance uniformity index to guide the learning direction of the agent.
6. The method according to any one of claims 1-5, characterized in that, The key process parameters include at least one of the following: film thickness, key dimensions, and doping concentration, measured by an integrated metering unit.
7. The method according to claim 6, characterized in that, The generation of space-adaptive process formulations specifically includes: generating differentiated doping compensation formulations or differentiated stress application formulations for different regions of the wafer.
8. The method according to claim 7, characterized in that, Adjusting at least one process parameter in a subsequent process step includes performing the differentiated process compensation by adjusting at least one of the following methods: adjusting the mask pattern in the photolithography process, adjusting the implantation dose and energy in the ion implantation process, or adjusting the temperature and time in the annealing process.
9. The method according to claim 1, characterized in that, The pre-trained machine learning model is a model built on a meta-learning framework, which can be quickly and adaptively fine-tuned based on a small amount of initial measurement data from the current wafer.
10. A wafer-level in-plane electrical performance uniformity control system based on a machine learning model, characterized in that, The system for implementing the method as described in any one of claims 1-9 comprises: The parameter acquisition module is configured to acquire key process parameters at multiple locations within the wafer surface during wafer fabrication. The performance prediction module has a built-in machine learning model configured to receive the key process parameters and predict the estimated electrical performance at different locations within the wafer surface. The machine learning model is configured to model the spatial correlation between different locations within the wafer surface. The recipe generation module is configured to generate a spatially adaptive process recipe for differentiated process compensation in different regions of the wafer based on the difference between the estimated electrical performance and the target electrical performance. The process execution module is configured to adjust at least one process parameter in subsequent process steps based on the space-adaptive process recipe, so as to actively correct electrical performance deviations within the wafer plane.