A back-powered optoelectronic interconnect chip system and its manufacturing method

CN122094483APending Publication Date: 2026-05-26HUBEI JIUFENGSHAN LAB
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUBEI JIUFENGSHAN LAB
Filing Date
2026-02-11
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Existing technologies struggle to effectively reduce signal transmission latency while ensuring power efficiency and data communication quality, especially in data transmission between XPUs and between XPUs and memory.

Method used

The optoelectronic interconnect chip system adopts back-powered power supply. By introducing a 3D stacked chip structure on the basis of electrical interconnection and back-powered power supply, it utilizes the optical interconnection of laser chip, computing chip, memory chip and optical interconnect module, and provides vertical back-powered power supply through power module. Combined with silicon photonic heterogeneous integrated laser and optical interposer, it realizes optoelectronic signal conversion and efficient power supply.

Benefits of technology

While ensuring power supply efficiency and data communication quality, it significantly reduces signal transmission delay, increases communication bandwidth, reduces power consumption, and reduces electromagnetic interference.

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Abstract

This application discloses a back-powered optoelectronic interconnect chip system and its manufacturing method, applicable to the field of optoelectronic integration technology. The system includes: a laser chip, a computing chip, a memory chip, a 3D stacked chip, an optical interconnect module, and a power module. The optical interconnect module is connected to the front of the laser chip, computing chip, memory chip, and 3D stacked chip, realizing optical interconnection among them. The power module is connected to the back of the laser chip, computing chip, memory chip, and 3D stacked chip, supplying power to them. The 3D stacked chip includes a first chip and a second chip with electrical interconnection. Thus, by introducing a 3D stacked chip structure with electrical interconnection between the first and second chips on top of electrical interconnection and back-powered operation, signal transmission delay is reduced while ensuring power efficiency and data communication quality.
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