Thin-film transistors with high electrical performance and thermal stability and their fabrication methods

Abstract

This invention discloses a thin-film transistor (TFT) with high electrical performance and thermal stability, and its fabrication method. The TFT includes a substrate, a bottom heat dissipation layer, an active layer, and a top heat dissipation layer stacked sequentially. Multiple electrodes are embedded in the top heat dissipation layer, with the top surfaces of the electrodes exposed. A gate dielectric layer is sandwiched between the electrode corresponding to the gate region and the top surface of the active layer, while the electrode corresponding to the non-gate region abuts against the top surface of the active layer. Both the bottom and top heat dissipation layers are made of hexagonal boron nitride (h-BN). The aforementioned TFT uses hexagonal boron nitride (h-BN) as the top heat dissipation layer in both the bottom and passivation layers, thus constructing a dual heat dissipation structure. This achieves high electrical performance and thermal stability of the TFT while maintaining low cost and high compatibility, improving the TFT's high-temperature resistance and stability. By mitigating the device's self-heating effect, the thermal stability of the device's electrical performance is enhanced.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and in particular to a thin-film transistor with high electrical performance and thermal stability, and its fabrication method. Background Technology

[0002] The applications of thin-film transistors (TFTs) have expanded from traditional displays to a wide range of fields, including sensors, automotive electronics, radio frequency front-ends, industrial IoT, smart homes, and intelligent transportation. As devices rapidly evolve towards miniaturization and high power density, the self-heating effect becomes increasingly prominent. The self-heating effect refers to the Joule heating generated when current flows through the active layer and electrodes during device operation. The inability to dissipate this heat in time leads to a cumulative increase in internal temperature, causing abnormal carrier mobility, a surge in leakage current, and other problems. This directly results in distortion of electrical performance, severely affecting the stability and lifespan of the device's electrical performance, and becoming an obstacle to the development of TFTs towards high power and high performance. Therefore, existing TFT technologies suffer from poor electrical performance due to insufficient heat dissipation. Summary of the Invention

[0003] This invention provides a thin-film transistor with high electrical performance and thermal stability, and a method for fabricating the same, aiming to solve the problem of poor electrical performance of thin-film transistors in existing technologies due to insufficient heat dissipation.

[0004] In a first aspect, embodiments of this application provide a thin-film transistor with high electrical performance and thermal stability, wherein the thin-film transistor includes a substrate, a bottom heat dissipation layer, an active layer and a top heat dissipation layer stacked sequentially; Multiple electrodes are embedded in the top heat dissipation layer, with the top surface of the electrodes exposed; A gate dielectric layer is sandwiched between the electrode corresponding to the gate region and the top surface of the active layer, and the electrode corresponding to the non-gate region abuts against the top surface of the active layer; Both the bottom heat dissipation layer and the top heat dissipation layer are made of hexagonal boron nitride.

[0005] Secondly, embodiments of this application also provide a preparation method, wherein the preparation method is used to prepare a thin-film transistor with high electrical performance and thermal stability as described in the first aspect above, the preparation method comprising: After the substrate is cleaned and dried, a hexagonal boron nitride layer is sputtered and deposited as the bottom heat dissipation layer. An amorphous indium oxide thin film is sputtered and deposited on the upper layer of the bottom heat dissipation layer to form an active layer; An alumina gate dielectric layer is grown on the active layer at the position corresponding to the gate region by atomic layer deposition, and then annealed in an oxygen atmosphere at 270~320℃ for 1.2~2 hours. The gate pattern is defined by electron beam lithography, a self-aligned gate stack is constructed on the dielectric layer by dry etching, and molybdenum metal is obtained as the electrode corresponding to the gate region based on the lift-off process. After annealing the device in an oxygen atmosphere at 270~320℃ for 0.3~0.75 hours, the source and drain regions are bombarded with Ar plasma to reduce the contact resistance of the corresponding regions. A hexagonal boron nitride layer is sputtered and deposited around the electrode in the gate region as a top heat dissipation layer; Molybdenum metal is processed in the source and drain regions of the top heat dissipation layer using ultraviolet lithography and lift-off processes, and is used as electrodes corresponding to the source and drain regions, respectively.

[0006] This invention provides a thin-film transistor (TFT) with high electrical performance and thermal stability, and its fabrication method. The TFT includes a substrate, a bottom heat dissipation layer, an active layer, and a top heat dissipation layer stacked sequentially. Multiple electrodes are embedded in the top heat dissipation layer, with the top surfaces of the electrodes exposed. A gate dielectric layer is sandwiched between the electrode corresponding to the gate region and the top surface of the active layer, and the electrode corresponding to the non-gate region abuts against the top surface of the active layer. Both the bottom and top heat dissipation layers are made of hexagonal boron nitride (h-BN). This TFT uses hexagonal boron nitride (h-BN) as the top heat dissipation layer in both the bottom and passivation layers, thus constructing a dual heat dissipation structure. This achieves high electrical performance and thermal stability while maintaining low cost and high compatibility, improving the TFT's high-temperature resistance and stability. By mitigating the device's self-heating effect, the thermal stability of the device's electrical performance is enhanced. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A cross-sectional view of a thin-film transistor provided in an embodiment of the present invention; Figure 2 This is a cross-sectional view of a thin-film transistor in the prior art; Figure 3 A comparative test diagram of the transfer characteristic curves of thin-film transistors provided in embodiments of the present invention; Figure 4 A comparative test diagram of the output characteristic curves of thin-film transistors provided in the embodiments of the present invention; Figure 5This is a simulation test diagram of the internal temperature distribution of a thin-film transistor in the prior art; Figure 6 The simulation test diagram of the internal temperature distribution of the thin-film transistor provided in the embodiment of the present invention; Figure 7 The output characteristic curves of existing thin-film transistors under self-heating are shown in the simulation. Figure 8 The simulation output characteristic curve of the thin-film transistor under self-heating is provided for the embodiments of the present invention; Figure 9 A flowchart illustrating the preparation method provided in an embodiment of the present invention.

[0009] Reference numerals: 1. Substrate; 2. Bottom heat dissipation layer; 3. Active layer; 41. Top heat dissipation layer; 42. Electrode; 5. Gate dielectric layer; 6. Silicon dioxide passivation layer. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0012] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0013] This invention also provides a thin-film transistor with high electrical performance and thermal stability, such as... Figure 1As shown, the thin-film transistor includes a substrate 1, a bottom heat dissipation layer 2, an active layer 3, and a top heat dissipation layer 41 stacked sequentially; multiple electrodes 42 are embedded in the top heat dissipation layer 41, and the top surface of the electrodes 42 is exposed; a gate dielectric layer 5 is sandwiched between the electrode 42 corresponding to the gate region and the top surface of the active layer 3, and the electrode 42 corresponding to the non-gate region abuts against the top surface of the active layer 3; the bottom heat dissipation layer 2 and the top heat dissipation layer 41 are both made of hexagonal boron nitride.

[0014] like Figure 2 As shown, in existing thin-film transistor structures, the active layer 3 is directly disposed on the upper layer of the substrate 1, and the electrode 42 is embedded in the silicon dioxide passivation layer 6, without any thermally conductive material. The passivation layer made of silicon dioxide can only achieve the basic functions of protecting the electrode 42 and isolating impurities, but silicon dioxide has low thermal conductivity (approximately 1.4 W·m). -1 ・K -1 The device cannot solve the problem of temperature accumulation caused by self-heating effect. The internal temperature of the device is prone to rise sharply when it is working, which will lead to distortion of electrical performance. Therefore, its heat dissipation capacity is insufficient, resulting in poor thermal stability of electrical performance.

[0015] This application addresses the shortcomings of existing thin-film transistors by improving their structure. It employs a substrate 1, a bottom heat dissipation layer 2, an active layer 3, and a top heat dissipation layer 41, stacked sequentially. Multiple electrodes 42 are embedded in the top heat dissipation layer 41, with their top surfaces exposed for electrical connection to external devices. The thin-film transistor includes a gate region, a source region, and a drain region, each corresponding to one electrode 42. The electrodes 42 in the non-gate regions abut against the top surface of the active layer 3, while a gate dielectric layer 5 (i.e., a dielectric layer) is sandwiched between the electrode 42 in the gate region and the top surface of the active layer 3. To improve heat dissipation, both the bottom heat dissipation layer 2 and the top heat dissipation layer 41 are made of hexagonal boron nitride (h-BN). Using h-BN as the bottom and top heat dissipation layers creates a dual heat dissipation structure, achieving high electrical performance and thermal stability in the thin-film transistor.

[0016] Specifically, a hexagonal boron nitride layer of a certain thickness is added between the substrate 1 and the active layer 3 as a bottom heat dissipation layer 2. This is not simply a heat dissipation film, but rather a layer that is tightly bonded to the interface between the substrate 1 and the active layer 3. This not only reduces interface defect states to optimize interface quality, but also, due to its own insulation, does not have any additional negative impact on the device, while forming a highly efficient heat conduction channel. At the same time, a hexagonal boron nitride layer of a certain thickness is added at the gap between the electrodes 42 as a top heat dissipation layer 41. The top heat dissipation layer 41 is a top passivation-heat dissipation integrated layer. It is not a traditional independent heat dissipation layer, but completely replaces the conventional silicon dioxide passivation layer 6. In addition to achieving the core passivation functions such as electrode protection and impurity isolation, it also has an additional highly efficient heat dissipation capability.

[0017] In a more specific embodiment, the thickness of the bottom heat dissipation layer 2 and the thickness of the top heat dissipation layer 41 are not less than 30 nm. Specifically, the thickness of the bottom heat dissipation layer 2 is 30~200 nm.

[0018] Specifically, in order to achieve efficient heat dissipation of the bottom heat dissipation layer 2 and the top heat dissipation layer 41, the thickness of both the bottom heat dissipation layer 2 and the top heat dissipation layer 41 can be set to be not less than 30nm; in specific applications, the thickness of the bottom heat dissipation layer 2 can be set to 30~200nm; in a preferred embodiment, the thickness of both the bottom heat dissipation layer 2 and the top heat dissipation layer 41 can be set to 50nm.

[0019] In a more specific embodiment, the gate dielectric layer 5 is made of aluminum oxide. Specifically, the active layer 3 is an amorphous indium oxide thin film. The substrate 1 includes a silicon substrate and a silicon dioxide layer disposed on the silicon substrate, with the silicon dioxide layer disposed on the side facing the bottom heat dissipation layer 2.

[0020] The gate dielectric layer 5 can be prepared using alumina. Alumina has a high dielectric constant and low interface state density, which can effectively reduce leakage current and improve the breakdown voltage and stability of the device. The film is dense and uniform, and has good compatibility with the active layer 3, which is conducive to the fabrication of high-performance thin-film transistors. The active layer 3 is made of amorphous indium oxide film, which has high electron mobility, fast device switching speed and strong driving capability. In addition, the amorphous structure has good uniformity and excellent large-area film formation performance, making it suitable for large-scale device applications such as flat panel displays and sensors. The substrate 1 is composed of a silicon substrate and silicon dioxide layers. The silicon substrate has high mechanical strength and good thermal conductivity. Together with the bottom heat dissipation layer 2, it can quickly dissipate heat and improve the heat dissipation of the device. The silicon dioxide layer, as an insulating layer, has excellent electrical isolation effect, reduces parasitic leakage current and crosstalk, and improves the reliability and withstand voltage of the device.

[0021] In a more specific embodiment, the top surface of the electrode 42 is not higher than the top surface of the top heat dissipation layer 41. The area of ​​the top surface of the electrode 42 is larger than the area of ​​its bottom surface. Furthermore, the electrode 42 is made of molybdenum.

[0022] The top surface of electrode 42 can be configured to be no higher than the top surface of the top heat dissipation layer 41, thereby protecting electrode 42 through the top heat dissipation layer 41. For example, the top surface of electrode 42 can be flush with the top surface of the top heat dissipation layer 41, or the top surface of the top heat dissipation layer 41 can be higher than the top surface of electrode 42. The top surface area of ​​electrode 42 can be larger than the bottom surface area. This configuration can increase the contact area between electrode 42 and external devices, reduce contact resistance, and improve carrier injection efficiency. At the same time, this configuration is beneficial for microfabrication processes such as photolithography, etching, and lift-off, improving pattern morphology and process yield. It can also enhance the bonding and adhesion between electrode 42 and adjacent film layers, improving device reliability. For example, in the embodiments of this application, the cross-sectional structure of electrode 42 is an inverted trapezoid. Furthermore, the motor is made of molybdenum metal. Molybdenum metal electrodes have a high melting point and good thermal stability, and can withstand high-temperature processes without melting, diffusion, or morphological degradation. They also have excellent conductivity and low resistivity, which can reduce device power consumption and signal loss. Moreover, molybdenum metal electrodes have good compatibility with films such as indium oxide, aluminum oxide, and silicon dioxide, and are less prone to interfacial reactions and atomic interdiffusion, thus improving device stability and lifespan.

[0023] This application discloses a preparation method in specific embodiments, wherein the preparation method is used to prepare a thin-film transistor with high electrical performance and thermal stability as described in the above embodiments; please refer to... Figure 9 The preparation method includes steps S1 to S7.

[0024] S1. After the substrate is cleaned and dried, a hexagonal boron nitride layer is sputtered and deposited as the bottom heat dissipation layer.

[0025] A silicon substrate with a SiO2 insulating layer is preferred to ensure mechanical strength and electrical isolation. The substrate cleaning process involves: ultrasonic cleaning with acetone for 5–10 min to remove organic residues; ultrasonic cleaning with isopropanol for 5–10 min to replace the acetone; rinsing with deionized water for 3–5 min; and drying with nitrogen gas and an oven at 120℃ for 10–15 min. Subsequently, radio frequency magnetron sputtering is used with high-purity hexagonal boron nitride (hBN) as the target material in a vacuum environment with a base vacuum pressure ≤5×10⁻⁶. -4 Pa; the working gas is high-purity Ar, with a pressure of 0.3–0.8 Pa; sputtering power is 50–120 W; deposition thickness is 30–200 nm. The hexagonal boron nitride layer serves as the bottom heat dissipation layer, exhibiting high thermal conductivity, good insulation, and chemical stability, enabling rapid dissipation of device operating heat and suppression of self-heating effects.

[0026] S2. An amorphous indium oxide thin film is sputtered and deposited on the upper layer of the bottom heat dissipation layer to form an active layer in a patterned manner.

[0027] Further deposition of amorphous indium oxide (IO) films was performed by sputtering an IO film approximately 4–20 nm thick onto a cleaned silicon substrate. During sputtering, a mixed atmosphere of argon and oxygen was used, with a ratio of 47 sccm of argon and 3 sccm of oxygen, a sputtering pressure of approximately 0.40 Pa, and a sputtering power of 100 W. Subsequently, the active layer was patterned using a photolithography-etching method. The IO film was etched using a wet etching method with a hydrochloric acid solution (HCl:H₂O = 1:50) at an etching rate of approximately 0.5 nm / s. After forming the active islands in the IO film, the IO surface underwent pre-oxidation treatment using an N₂O plasma treatment process. This process was performed via plasma-enhanced chemical vapor deposition (PECVD), with an N₂O flow rate of 400 sccm, a treatment temperature of 150 °C, a treatment power of 50 W, and a treatment time of 120 seconds.

[0028] S3. An aluminum oxide gate dielectric layer is grown on the upper layer of the active layer at the position corresponding to the gate region by atomic layer deposition, and then annealed in an oxygen atmosphere at 270~320℃ for 1.2~2 hours.

[0029] Alumina with a thickness of 3-30 nm is deposited as a gate dielectric layer using ALD (Atomic Layer Deposition), with a preferred embodiment being a 5 nm thick layer. The precursor is TMA (trimethylaluminum), the oxidant is ozone, and the deposition temperature can be set to 150–250 °C. Each ALD cycle includes one TMA pulse, a 30-second nitrogen purging, one ozone pulse, and another 30-second nitrogen purging. Under this process, the alumina growth rate is approximately 1.0 Å / cycle; the deposited alumina gate dielectric layer exhibits excellent characteristics of dense, uniform film and step coverage. Annealing is then performed at 270-320 °C in a flowing high-purity oxygen atmosphere for 1.2-2 hours. In a preferred embodiment, the annealing temperature is 300 °C for 1.5 hours. The purpose of annealing is to repair interface defects, reduce interface state density, reduce leakage current, and improve breakdown field strength.

[0030] S4. Define the gate pattern by electron beam lithography, construct a self-aligned gate stack on the dielectric layer by dry etching, and obtain molybdenum metal as the electrode corresponding to the gate region based on the lift-off process.

[0031] Following annealing, a 15-30 nm layer of molybdenum metal was sputtered as the top electrode. Subsequently, the gate electrode was patterned using photolithography-etching, followed by wet etching of the molybdenum metal and dry etching of the alumina. The resulting molybdenum metal electrode exhibits characteristics of high temperature resistance, low resistivity, non-diffusion, and good adhesion.

[0032] S5. After annealing the device in an oxygen atmosphere at 270~320℃ for 0.3~0.75 hours, bombard the source and drain regions with Ar plasma to reduce the contact resistance of the corresponding regions.

[0033] The device is subjected to secondary annealing in an oxygen atmosphere at a temperature of 270–320°C and a flowing atmosphere of high-purity oxygen for 0.3–0.75 hours; in a preferred embodiment, the annealing temperature can be set to 300°C for 0.5 hours. Subsequently, the indium oxide in the source and drain regions undergoes low-resistivity treatment using conventional Ar plasma processing. The gate electrode is used as a hard mask, and the sample is bombarded with Ar plasma using reactive ion etching. The Ar plasma flow rate is 100 sccm, the processing power is 100 W, and the processing time is 100 seconds.

[0034] S6. A hexagonal boron nitride layer is sputtered and deposited around the electrode in the gate region as a top heat dissipation layer.

[0035] A hexagonal boron nitride layer is sputtered again on the surface of the device as a top heat dissipation layer to enhance heat dissipation. The resulting top heat dissipation layer, combined with the electrodes, forms a passivation layer. The passivation layer protects the device by isolating it from moisture, oxygen, and impurities. Since the surface of the electrodes is exposed, it does not affect the subsequent electrode lead-out. The specific deposition process is the same as in step S1.

[0036] S7. Molybdenum metal is processed in the source and drain regions of the top heat dissipation layer by ultraviolet lithography and lift-off process, and used as electrodes corresponding to the source and drain regions, respectively.

[0037] The source and drain contact electrodes are formed using a negative resist stripping method. First, a photoresist pattern for the source and drain electrodes is formed using photolithography. Then, molybdenum metal of a certain thickness is sputtered. The source and drain contact electrodes are then formed by resist stripping. Finally, cleaning and drying steps are performed. In a specific embodiment, if the passivation layer thickness is set to 50 nm and the electrodes corresponding to the source and drain regions are set to have the same thickness as the passivation layer, then 50 nm of molybdenum metal can be sputtered as the source and drain contact electrodes.

[0038] Based on the aforementioned fabrication process, a two-dimensional model was constructed using TCAD tools. The drift-diffusion transport model and the Poisson equation were used for self-consistent solution. Physical models such as FERMI, SRH, BGN, and QTUNN.EL were introduced, and a Gummel-Newton hybrid iterative algorithm (maxtrap=100, itlimit=50) was employed. Key parameters of the active layer (bandgap 3.8 eV, electron affinity 4.5 eV, etc.) were set. A DOS model consisting of "conduction band tail state + valence band tail state + two types of deep-level defect states" was used to iteratively extract parameters. The transfer and output characteristic curves of the simulation model were made consistent with the electrical test results of the actual device, verifying the model's accuracy.

[0039] The electrical test results of the simulation model and the actual device are as follows: Figure 3 and Figure 4 As shown, Figure 3 The vertical axis represents the drain-source current, and the horizontal axis represents the gate-source voltage. The drain-source voltage is set to 0.1V. Figure 4 The vertical axis represents the drain-source current, and the horizontal axis represents the drain-source voltage. The gate-source voltage gradients are set to 0.5V, 1V, 1.5V, 2V, and 2.5V. As can be seen from the curves in the figure, the transfer characteristic curves of the simulation model are highly consistent with the transfer characteristic curves of the actual device, and the output characteristic curves of the two are also highly consistent. This verifies that the model parameters accurately reflect the physical characteristics of the device and provides a reliable foundation for subsequent thermal stability optimization simulation.

[0040] Based on the verified model above, a double-layer hexagonal boron nitride layer is set in the device structure. Specifically, the thickness of the top heat dissipation layer and the bottom heat dissipation layer based on hexagonal boron nitride material can both be set to 50nm. Furthermore, the temperature distribution and electrical performance stability of the device simulation are compared and analyzed to verify the thermal stability optimization effect.

[0041] The specific simulation test results of temperature distribution are as follows: Figure 5 and Figure 6 As shown, where Figure 5 Based on Figure 2 The simulation test results obtained by performing simulation tests on the device structure shown. Figure 6 Based on Figure 1 The simulation test results obtained by performing simulation tests on the device structure shown (i.e., the embodiment of this application); Figure 5 and Figure 6The device is divided into source, gate, and drain regions, with T representing temperature in Kelvin (K). Comparing the two sets of test results shows that the synergistic effect of the h-BN dual-layer functional structure effectively suppresses internal temperature accumulation: the highest internal temperature of the unoptimized device reaches 502K, while the highest internal temperature of the optimized device with the h-BN layer is only 315K, a significant temperature reduction. This effectively avoids abnormal carrier mobility caused by high temperatures, providing temperature assurance for electrical performance stability. Simultaneously, the dual-functional structure makes the device temperature distribution more uniform, further reducing performance distortion caused by localized high temperatures.

[0042] With gate-source voltages set to 0.5V, 1V, 1.5V, 2V, and 2.5V, electrical performance simulation tests were conducted under these conditions. The output characteristic curves obtained from the simulation tests are shown below. Figure 7 and Figure 8 As shown, where Figure 7 Based on Figure 2 The simulation test results obtained by performing simulation tests on the device structure shown. Figure 8 Based on Figure 1 The simulation test results are obtained by performing simulation tests on the device structure shown (i.e., the embodiment of this application). Under relatively small gate-source voltage conditions (such as gate-source voltages of 0.5V and 1V), the drain-source current of the device is relatively small, which will be represented by overlapping curves in the figure, but this does not affect the analysis of the electrical performance and thermal stability of the device by the test results. By comparing the two sets of test results, it can be seen that the electrical performance, thermal stability and reliability of the technology of this application are significantly improved compared with the prior art. In the figure, the vertical axis represents the drain-source current and the horizontal axis represents the drain-source voltage. The critical distortion point (the point pointed to by the orange arrow) is defined as: the point in the output characteristic curve where the drain-source current rises sharply, called the "self-heating induced electrical performance distortion critical point". Its physical essence is that the self-heating effect causes the internal temperature of the device to accumulate to a critical value, which leads to a surge in carrier mobility, runaway leakage current, and the device deviating from the normal operating threshold, making it unable to maintain stable electrical output characteristics. The comparison of the two technologies shows that the existing technology's device exhibits the distortion critical point when the drain-source voltage rises to 0.93V, while the device in this embodiment only exhibits this phenomenon when the drain-source voltage rises to 3.92V. Calculations show that the critical drain-source voltage value for resisting self-heating-induced distortion is increased by 321.5%. Stability and reliability are related: the timing of the distortion critical point directly reflects the device's electrical performance and thermal stability—the higher the drain-source voltage value corresponding to the critical point, the stronger the device's ability to maintain stable electrical performance under high voltage and high power conditions, thereby extending the device's lifespan and improving long-term operational reliability.

[0043] Based on the test results and analysis of the heat dissipation principle of the device, it can be concluded that the h-BN material has excellent thermal conductivity. The lower h-BN layer ensures the basic electrical performance of the device with its excellent interface quality and insulation, and can quickly conduct the Joule heat generated by the active layer to the substrate and dissipate it. The upper h-BN layer acts as a passivation layer to isolate and protect the electrode from oxidation and the intrusion of external impurities. On the other hand, it directly dissipates the heat from the electrode and active layer surface into the air. The dual-function structure works synergistically to effectively suppress the temperature accumulation caused by self-heating, avoid electrical performance distortion, and improve the thermal stability of the device.

[0044] The thin-film transistor structure in this application has the following advantages: (1) Structural innovation: The lower h-BN layer is tightly bonded to the interface of the substrate and the active layer, providing an atomically smooth surface. Due to its insulation, it will not have any additional negative impact on the device. The upper h-BN layer realizes the three-in-one function of "passivation + heat dissipation + patterning". It is different from the existing h-BN heat dissipation scheme of simply laying film and the traditional SiO2 passivation layer scheme. It breaks through the design limitations of a single heat dissipation layer or a single passivation layer, and solves the problems that traditional devices cannot take passivation and heat dissipation into account and the lack of patterning adaptation of existing h-BN schemes; (2) Excellent thermal stability: The dual-function structure effectively suppresses temperature accumulation and solves the problem of electrical performance distortion caused by the self-heating effect of the device; (3) Low cost advantage: The use of low-cost h-BN material solves the problem of high cost of silicon carbide substrate, piezoelectric layer and other schemes; (4) Strong compatibility: h-BN can be fabricated in a large area and patterned manner through sputtering and chemical vapor deposition processes. It is fully compatible with the existing TFT fabrication process and does not require modification of the production line, thus solving the defect of poor compatibility of some schemes.

[0045] This invention provides a thin-film transistor (TFT) with high electrical performance and thermal stability, and its fabrication method. The TFT includes a substrate, a bottom heat dissipation layer, an active layer, and a top heat dissipation layer stacked sequentially. Multiple electrodes are embedded in the top heat dissipation layer, with the top surfaces of the electrodes exposed. A gate dielectric layer is sandwiched between the electrode corresponding to the gate region and the top surface of the active layer, and the electrode corresponding to the non-gate region abuts against the top surface of the active layer. Both the bottom and top heat dissipation layers are made of hexagonal boron nitride (h-BN). This TFT uses hexagonal boron nitride (h-BN) as the top heat dissipation layer in both the bottom and passivation layers, thus constructing a dual heat dissipation structure. This achieves high electrical performance and thermal stability while maintaining low cost and high compatibility, improving the TFT's high-temperature resistance and stability. By mitigating the device's self-heating effect, the thermal stability of the device's electrical performance is enhanced.

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A thin-film transistor with high electrical performance and thermal stability, characterized in that, The thin-film transistor includes a substrate, a bottom heat dissipation layer, an active layer, and a top heat dissipation layer stacked sequentially. Multiple electrodes are embedded in the top heat dissipation layer, with the top surface of the electrodes exposed; A gate dielectric layer is sandwiched between the electrode corresponding to the gate region and the top surface of the active layer, and the electrode corresponding to the non-gate region abuts against the top surface of the active layer; Both the bottom heat dissipation layer and the top heat dissipation layer are made of hexagonal boron nitride.

2. The thin-film transistor with high electrical performance and thermal stability according to claim 1, characterized in that, The thickness of the bottom heat dissipation layer and the thickness of the top heat dissipation layer are not less than 30 nm.

3. The thin-film transistor with high electrical performance and thermal stability according to claim 2, characterized in that, The thickness of the bottom heat dissipation layer is 30~200nm.

4. The thin-film transistor with high electrical performance and thermal stability according to claim 3, characterized in that, The gate dielectric layer is made of aluminum oxide.

5. The thin-film transistor with high electrical performance and thermal stability according to claim 4, characterized in that, The active layer is an amorphous indium oxide thin film.

6. The thin-film transistor with high electrical performance and thermal stability according to claim 5, characterized in that, The substrate includes a silicon substrate and a silicon dioxide layer disposed on the silicon substrate, wherein the silicon dioxide layer is disposed on the side facing the bottom heat dissipation layer.

7. The thin-film transistor with high electrical performance and thermal stability according to any one of claims 1-6, characterized in that, The top surface of the electrode is not higher than the top surface of the top heat dissipation layer.

8. The thin-film transistor with high electrical performance and thermal stability according to claim 7, characterized in that, The area of ​​the top surface of the electrode is greater than the area of ​​the bottom surface of the electrode.

9. The thin-film transistor with high electrical performance and thermal stability according to claim 8, characterized in that, The electrode is made of molybdenum.

10. A preparation method, characterized in that, The preparation method is used to prepare a thin-film transistor with high electrical performance and thermal stability as described in any one of claims 1-9, and the preparation method includes: After the substrate is cleaned and dried, a hexagonal boron nitride layer is sputtered and deposited as the bottom heat dissipation layer. An amorphous indium oxide thin film is sputtered and deposited on the upper layer of the bottom heat dissipation layer to form an active layer; An alumina gate dielectric layer is grown on the active layer at the position corresponding to the gate region by atomic layer deposition, and then annealed in an oxygen atmosphere at 270~320℃ for 1.2~2 hours. The gate pattern is defined by electron beam lithography, a self-aligned gate stack is constructed on the dielectric layer by dry etching, and molybdenum metal is obtained as the electrode corresponding to the gate region based on the lift-off process. After annealing the device in an oxygen atmosphere at 270~320℃ for 0.3~0.75 hours, the source and drain regions are bombarded with Ar plasma to reduce the contact resistance of the corresponding regions. A hexagonal boron nitride layer is sputtered and deposited around the electrode in the gate region as a top heat dissipation layer; Molybdenum metal is processed in the source and drain regions of the top heat dissipation layer using ultraviolet lithography and lift-off processes, and is used as electrodes corresponding to the source and drain regions, respectively.

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