QFP packaging structure and its molding process

Abstract

This application provides a QFP packaging structure and its molding process. The QFP packaging structure includes a frame, a first semiconductor chip, a second semiconductor chip, and a molding body. The frame has pads in its central region, and at least one slot in the sidewall of the frame. The first surface of the first semiconductor chip is mounted on the first side of the pads, and the I / O pads of the first semiconductor chip are electrically connected to a first pin corner of the frame via first metal leads located at the edge of the sidewall of the frame. The first surface of the second semiconductor chip is mounted on the second side of the pads, and the I / O pads of the second semiconductor chip are electrically connected to the first pin corner of the frame via second metal leads passing through the slot. The molding body at least covers the first semiconductor chip, the first surface and sidewall of the second semiconductor chip, the first metal leads, the second metal leads, and the frame. This solves the problem of reduced packaging performance caused by excessively long interconnect paths in QFP packaging.

Description

Technical Field

[0001] This application relates to integrated circuit packaging technology, and more specifically, to a QFP packaging structure and its molding process. Background Technology

[0002] Traditional QFPs employ internal flip-chip (Die-on-Package) or ball grid array (BGA) interconnects, often resulting in long interconnect paths. With continuously shrinking package sizes and increasing power consumption and heat dissipation requirements, the pad layout of traditional interconnects is constrained. The external pad (E-PAD) is typically located at the bottom of the die, and the die is smaller than the E-PAD. Therefore, a structural solution is needed that can provide short-distance, low-impedance, reliable interconnects within the QFP package while remaining compatible with high-temperature curing molding compounds. Summary of the Invention

[0003] The main objective of this application is to provide a QFP packaging structure and its molding process, so as to at least solve the problem of reduced packaging performance caused by excessively long interconnect paths in the existing QFP packaging.

[0004] To achieve the above objectives, according to one aspect of this application, a QFP package structure is provided, comprising: a frame, wherein a pad is provided in the central region of the frame, and at least one slot is provided in the sidewall of the frame; a first semiconductor chip, wherein a first surface of the first semiconductor chip is mounted on the first side of the pad, and the I / O pad of the first semiconductor chip is electrically connected to a first pin corner of the frame via a first metal lead, the first pin corner being located at the edge of the sidewall of the frame; a second semiconductor chip, wherein a first surface of the second semiconductor chip is mounted on the second side of the pad, and the I / O pad of the second semiconductor chip is electrically connected to the first pin corner of the frame via a second metal lead passing through the slot, the second side of the pad being parallel to and opposite to the first side of the pad; and a molded body, which at least covers the first semiconductor chip, the first surface and sidewall of the second semiconductor chip, the first metal lead, the second metal lead, and the frame.

[0005] Optionally, the pad is surrounded by a silver-plated area, and the first semiconductor chip is electrically connected to the silver-plated area via a third metal lead, and the second semiconductor chip is electrically connected to the silver-plated area via the third metal lead.

[0006] Optionally, the depth of the slot is the same as the thickness of the frame.

[0007] Optionally, the fourth metal lead is corner-connected to the ground attribute pin of the frame, and the fourth metal lead is one or more metal leads, and multiple fourth metal leads are arranged in parallel.

[0008] Optionally, the diameter of the first metal lead and the second metal lead is 0.7 mil or 0.8 mil.

[0009] Optionally, the frame is made of a copper alloy conductive material.

[0010] Optionally, the total height of the molded body is determined based on the height of the first semiconductor chip, the height of the second semiconductor chip, and the wiring configuration of the first metal lead and the second metal lead.

[0011] According to another aspect of this application, a molding process is provided for any of the QFP package structures described above, comprising: mounting a first surface of a first semiconductor chip on a first side of a pad of a frame, and electrically connecting the I / O pad of the first semiconductor chip to a first pin corner of the frame via a first metal lead; mounting a first surface of a second semiconductor chip on a second side of the pad, and electrically connecting the I / O pad of the second semiconductor chip to a first pin corner of the frame via a second metal lead passing through a slot, wherein the slot is disposed on a sidewall of the frame, the first pin corner is located at the edge of the sidewall of the frame, and the second side of the pad is parallel to and opposite to the first side of the pad; and molding the first semiconductor chip, the first surface and sidewall of the second semiconductor chip, the first metal lead, the second metal lead, and the frame using a molding compound.

[0012] Optionally, mounting the first surface of the first semiconductor chip onto the first side of the pad of the frame includes: mounting the first surface of the first semiconductor chip onto the first side of the pad using silver paste; mounting the first surface of the second semiconductor chip onto the second side of the pad includes: mounting the first surface of the second semiconductor chip onto the second side of the pad using thermosetting epoxy adhesive, wherein the curing temperature is 120°C to 150°C.

[0013] Optionally, before using the molding compound to encapsulate the first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead, and the frame, the process further includes: curing a low-shrinkage epoxy resin material to obtain the molding compound, wherein the curing temperature range is 120°C to 150°C.

[0014] According to the technical solution of this application, the QFP package structure includes a frame, a first semiconductor chip, a second semiconductor chip, and a molding body. The frame has a pad in its central region, and at least one slot in its sidewall. The first surface of the first semiconductor chip is mounted on the first side of the pad. The I / O pads of the first semiconductor chip are electrically connected to the first pin corner of the frame via a first metal lead, and the first pin corner is located at the edge of the sidewall of the frame. The first surface of the second semiconductor chip is mounted on the second side of the pad. The I / O pads of the second semiconductor chip are electrically connected to the first pin corner of the frame via a second metal lead passing through the slot. The second side of the pad is parallel to and opposite to the first side of the pad. The molding body at least covers the first semiconductor chip, the first surface and sidewall of the second semiconductor chip, the first metal lead, the second metal lead, and the frame. In this solution, by pre-setting at least one slot in the sidewall of the frame and using the second metal lead passing through the slot to directly form an electrical connection with the I / O pads of the second semiconductor chip and the first pin corner of the frame, fast, low-impedance interconnection between the chip and external circuits is achieved. Meanwhile, the first semiconductor chip is connected to the frame pin corner via a first metal lead, together forming a highly compact package layout. This structure shortens the interconnect path, reduces impedance during signal transmission, and improves package performance, thereby solving the problem of reduced package performance caused by excessively long interconnect paths in existing QFP packages. Attached Figure Description

[0015] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 A schematic diagram of the overall structure of a QFP package structure provided in an embodiment of this application is shown;

[0017] Figure 2 A schematic diagram of the first part of a QFP package structure provided according to an embodiment of this application is shown;

[0018] Figure 3 A second portion of a schematic diagram of a QFP package structure provided according to an embodiment of this application is shown;

[0019] Figure 4 A schematic flow diagram of a molding process according to an embodiment of this application is shown;

[0020] Figure 5 A schematic diagram of a third part of a QFP package structure provided according to an embodiment of this application is shown;

[0021] Figure 6A schematic diagram of the fourth part of a QFP package structure provided according to an embodiment of this application is shown;

[0022] Figure 7 A fifth schematic diagram of a QFP package structure provided according to an embodiment of this application is shown.

[0023] The above figures include the following reference numerals:

[0024] 01. QFP package structure; 10. Frame; 20. First semiconductor chip; 30. Second semiconductor chip; 40. Molded body; 100. Pad; 100-1. First side of pad; 100-2. Second side of pad; 102. Slot; 201. I / O pad of the first semiconductor chip; 301-1. First I / O pad of the second semiconductor chip; 301-2. Second I / O pad of the second semiconductor chip; 302. Second surface; 103. First lead corner; 500-1. First metal lead; 500-4. Second metal lead; 500-2. Third metal lead; 500-3. Fourth metal lead; 500-5. Fifth metal lead; 101. Silver-plated area; 501-1. Silver paste; 501-2. Thermosetting epoxy adhesive; 103-1. Straight lead corner; 103-2. Bend. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] As described in the background section, the interconnection paths of QFP packages in the prior art are relatively long. In order to solve the problem that the excessively long interconnection paths in QFP packages lead to reduced packaging performance, the embodiments of this application provide a QFP packaging structure and its molding process.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] This application provides a QFP packaging structure, such as Figure 1 As shown, the QFP package structure 01 includes a frame 10, a first semiconductor chip 20, a second semiconductor chip 30, and a molded body 40. The frame 10 has a pad 100 in its central region, and at least one slot 102 on its sidewall. The first surface of the first semiconductor chip 20 is mounted on the first surface 100-1 of the pad. The I / O pad 201 of the first semiconductor chip is electrically connected to the first pin corner 103 of the frame 10 via a first metal lead 500-1. The first pin corner 103 is located at the edge of the sidewall of the frame. The first surface of the second semiconductor chip 30 is mounted on the second surface 100-1 of the pad. 0-2, the first I / O pad 301-1 of the second semiconductor chip is electrically connected to the first pin corner 103 of the frame through the slot 102 via the second metal lead 500-4. The second side 100-2 of the pad is parallel to and opposite to the first side 100-1 of the pad. The molded body 40 at least covers the first surface and side surface of the first semiconductor chip 20, the second semiconductor chip 30, the first metal lead 500-1, the second metal lead 500-4, and the frame 10.

[0031] Specifically, the package structure is based on a frame with a central pad (E-PAD) for connecting the chip. The frame's sidewall has at least one slot designed to allow metal leads to pass through in a specific manner, enabling direct electrical connection between the chip and the frame pins. A first semiconductor chip's first surface is mounted on the first side of the pad, meaning the bottom of the chip is directly bonded to the top surface of the pad. The chip's I / O pads are electrically connected to the first pin corners of the frame's sidewall edge via first metal leads, providing the path for communication between the chip within the package and an external circuit board. A second semiconductor chip's first surface is mounted on the opposite second side of the same pad. This chip's I / O pads are electrically connected to the first pin corners via second metal leads passing through the slot in the frame's sidewall. This design allows both chips to connect to the outside via the shortest path, reducing signal transmission impedance and improving heat dissipation efficiency. The outer part of the package structure is formed by a molded body, which at least covers the first semiconductor chip, the first surface and side surfaces of the second semiconductor chip (i.e., the surfaces of the second semiconductor chip 30 excluding the second surface 302), and all metal leads and frames. The molded body plays a role in protecting the chip and leads and providing mechanical support during the packaging process.

[0032] In some embodiments of this application, the second I / O pad 301-2 of the second semiconductor chip is electrically connected to the first pin corner 103 of the frame via a fourth metal lead 500-3 and a fifth metal lead 500-5.

[0033] Overall, this embodiment achieves efficient electrical interconnection between chips and between chips and the external environment by setting slots on the sidewalls of the frame and using metal leads to directly connect the chip to the pin corners through the slots. Simultaneously, the molded body provides reliable packaging and protection. Compared to traditional QFP packaging, this structure offers shorter connection paths, lower impedance, and better heat dissipation performance, making it suitable for packaging electronic components with high power, high speed, and strong heat dissipation requirements. Specifically, by pre-setting at least one slot on the sidewall of the frame and using a second metal lead passing through this slot to directly connect to the I / O pads of the second semiconductor chip and the first pin corner of the frame, fast, low-impedance interconnection between the chip and external circuitry is achieved. Simultaneously, the first semiconductor chip is connected to the frame pin corners through the first metal lead, together forming a highly compact package layout. This structure shortens the interconnect path, reduces impedance during signal transmission, and improves packaging performance, thereby solving the problem of reduced packaging performance caused by excessively long interconnect paths in existing QFP packaging technologies.

[0034] In some embodiments of this application, see Figure 2 and Figure 1The pad 100 is surrounded by a silver-plated area 101. The first semiconductor chip 20 is electrically connected to the silver-plated area 101 via a third metal lead 500-2. The second semiconductor chip 30 is electrically connected to the silver-plated area 101 via the third metal lead 500-2.

[0035] Specifically, a silver-plated area is set around the pads of the QFP package frame. This area is primarily designed to enhance the conductivity and oxidation resistance of the pads. Silver is a metal with excellent electrical conductivity, maintaining stable electrical contact under high temperatures and prolonged use. Therefore, silver plating around the pads improves the electrical performance and reliability of the package. Grounding refers to the connection to the ground in a circuit, i.e., connecting to the zero potential point in the circuit, providing a path for current loops and helping to stabilize the circuit potential. In the package structure, the corresponding I / O pads of the first and second semiconductor chips are connected to the silver-plated area via a third metal lead, forming a grounding electrical connection. This means that the chip's ground portion is directly connected to the silver-plated area of ​​the package frame via a metal lead, ensuring good grounding between the chip and the external circuit board. This is crucial for reducing noise in the circuit and improving signal integrity and stability. The third metal lead is a metal wire used to establish a ground path. In the packaging process, metal leads are typically thin metal wires, such as gold or copper wires, used to establish electrical connections between the chip's I / O pads and the pins of the package frame. In this embodiment, the third metal lead not only connects the grounding portions of the first and second semiconductor chips, but also connects to the silver-plated area around the pads, forming a low-impedance grounding network that ensures effective grounding of the chip within the package.

[0036] By placing silver-plated areas around the pads of the QFP package structure and using third metal leads to form a grounded electrical connection between the first and second semiconductor chips and these silver-plated areas, the electrical stability and heat dissipation performance of the package are greatly enhanced. This design provides a low-impedance electrical path, enabling the chip to be effectively grounded, reducing electromagnetic interference and signal noise, and improving the overall circuit performance. Simultaneously, the silver-plated areas also help improve the thermal conductivity between the chip and the frame, as silver has excellent thermal conductivity, promoting rapid heat dissipation from the chip to the outside of the package, thereby reducing thermal stress during chip operation and extending the lifespan of the package structure.

[0037] In some embodiments of this application, the depth of the slot is the same as the thickness of the frame.

[0038] Specifically, the depth of the slot is the same as the thickness of the frame, which means that in the QFP package structure, the slot pre-set for the metal wires to pass through is perfectly matched with the thickness of the frame, that is, the slot runs through the thickness of the entire sidewall of the frame.

[0039] Ensuring the slot depth matches the frame thickness allows metal leads to pass directly through the slot from the I / O pads of the second semiconductor chip without obstruction, forming a complete electrical connection with the first pin corner of the frame's sidewall edge, thus achieving the shortest interconnect path. The shorter the direct connection path of the metal wires, the lower the impedance during signal transmission, which helps reduce signal delay and attenuation, improving the high-frequency performance of the circuit. Furthermore, reduced impedance also helps reduce electromagnetic interference and crosstalk within the package. The metal frame itself has excellent thermal conductivity; designing the slot to penetrate the frame thickness increases the thermal contact area between the metal leads and the frame, allowing heat generated by the chip to be more effectively conducted to the outside through the metal frame, thereby improving the package's heat dissipation efficiency. The slot depth matching the frame thickness ensures that the molding compound (packaging material) can uniformly fill and cover the frame and metal leads during the molding process, avoiding encapsulation bubbles or cavities caused by insufficient slot depth, thus improving the robustness and reliability of the package structure.

[0040] In some embodiments of this application, see Figure 1 The fourth metal lead 500-3 is connected to the ground attribute pin of the above frame. The fourth metal lead is one or more metal leads, and multiple fourth metal leads are connected in parallel.

[0041] Specifically, in the package structure, the ground attribute pin corner is a specific pin used to ground the chip. These pins are typically connected to the system ground or zero potential point to ensure potential stability during chip operation and reduce electromagnetic interference and signal noise. The fourth metal lead is a metal wire used to connect the ground portions of the first and second semiconductor chips to the ground attribute pin corner. Unlike the first and second metal leads, the fourth metal lead is specifically for grounding connections, ensuring electrical isolation and stability between the chip and the external environment. When multiple fourth metal leads are present, they are designed to be connected in parallel, meaning each lead is independently connected to the ground attribute pin corner. Parallel connections significantly reduce the total impedance of the grounding system because the total impedance in a parallel circuit is lower than the impedance of any single branch. This is particularly important for high-power or high-speed signal applications, as a low-impedance grounding network effectively reduces signal delay and attenuation, improving overall system performance. Connecting multiple metal leads in parallel for grounding also increases the thermal contact area between the chip and the package frame, thereby improving the chip's heat dissipation efficiency. Metal leads not only serve as electrical connections but also act as heat conduction paths, helping to quickly transfer the heat generated by the chip to the package frame, which then dissipates it to the external environment. Parallel lead configurations also provide redundant paths; even if one lead fails due to a fault or high temperature, the remaining leads can maintain electrical connection, thereby improving the reliability and durability of the package.

[0042] This embodiment significantly improves the electrical performance and heat dissipation efficiency of the QFP package structure. Specifically, multiple parallel fourth metal leads reduce the package's grounding impedance, decrease electromagnetic interference, and enhance signal integrity, making it particularly suitable for applications with stringent high-frequency performance requirements. Simultaneously, due to the excellent thermal conductivity of the metal leads, they also act as effective heat conduction paths, significantly improving the chip's heat dissipation capacity, reducing thermal stress, and thus extending the lifespan of the packaged device. The parallel arrangement also increases connection redundancy, improving the reliability of the package structure. Even if individual leads fail, the remaining leads can still maintain normal function, ensuring continuous and stable operation of the package in complex or harsh environments.

[0043] In some embodiments of this application, the wire diameters of the first metal lead and the second metal lead are 0.7 mil or 0.8 mil.

[0044] Specifically, the 0.7mil and 0.8mil wire diameters are extremely fine, approximately 18µm and 20µm respectively. This allows for highly precise interconnections between metal leads, making them suitable for high-density, miniaturized packages, especially in QFPs where complex electrical connections need to be made within a limited space. Fine-diameter metal leads can provide lower signal impedance over short distances, which is beneficial for high-frequency signal transmission, reduces signal delay and attenuation, and improves signal integrity—crucial for ultra-high-speed circuit design. While finer wire diameters generally increase cost, they also offer better electrical and thermal performance. The choice of 0.7mil and 0.8mil wire diameters strikes a balance between cost and performance, ensuring that the package structure meets high-performance requirements while also considering production costs and process feasibility. The use of fine-diameter metal leads reduces the spacing between leads, thereby increasing the interconnect density between the chip and pins within the package, contributing to smaller, more compact packages. 0.7mil or 0.8mil wire diameters are suitable for automated wire bonding processes, ensuring a stable and efficient bonding process on high-precision automated production lines, reducing production defects and improving packaging success rates.

[0045] By limiting the wire diameters of the first and second metal leads to 0.7 mil or 0.8 mil, a significant improvement in electrical performance and thermal efficiency is achieved in the QFP packaging structure. The fine wire diameter not only reduces signal transmission impedance and enhances signal integrity, making it suitable for high-speed circuits, but also effectively disperses current, reduces heat accumulation, and improves chip heat dissipation through parallel connection. Simultaneously, the use of fine wire diameters reflects the trend of packaging technology towards higher density and smaller size. This design achieves optimization of high-performance QFP packaging in terms of interconnect density, signal impedance, cost control, and manufacturing process compatibility.

[0046] In some embodiments of this application, the material of the frame is a copper alloy conductive material.

[0047] Specifically, copper alloys possess excellent electrical and thermal conductivity, enabling the frame to effectively carry current and rapidly conduct heat generated by the chip from the inside to the outside, which is particularly important for packages with high power and high heat dissipation requirements. The use of copper alloys also provides the necessary mechanical strength, ensuring the structural stability and impact resistance of the package in various application environments. Copper alloy frames are highly adaptable to packaging processes, compatible with various packaging technologies, including high-temperature curing, ensuring that the frame does not deform during molding and maintaining the structural integrity of the package.

[0048] In some embodiments of this application, the total height of the molded body is determined based on the height of the first semiconductor chip, the height of the second semiconductor chip, and the wiring configuration of the first metal lead and the second metal lead.

[0049] Specifically, see Figure 3 The total height H of the molded body 40 is determined based on the height H2 of the first semiconductor chip, the height H3 of the second semiconductor chip, and the wiring of the first and second metal leads (actually, the wiring of all metal leads, i.e., the wire bonding height H1).

[0050] The height difference of semiconductor chips directly affects the overall size of the package. The first and second semiconductor chips may have different thicknesses or heights; therefore, the total height of the molded body must account for these differences to ensure that the package completely covers the chip without causing pressure or damage. The routing of metal leads, including their direction, length, and curvature, also significantly impacts the height design of the molded body. Metal leads need to be properly laid out within the molded body to ensure reliable electrical connections and reduce impedance in signal transmission paths. Therefore, the height of the molded body must accommodate the routing requirements of the metal leads, ensuring sufficient space for lead placement within the package while avoiding performance degradation due to excessively long leads.

[0051] In summary, the design of the molded body height in this embodiment is based on precise consideration of the heights of the first and second semiconductor chips and adaptation to the metal lead wiring situation. It aims to achieve the best balance between electrical performance, thermal management, structural stability and cost-effectiveness of the package, ensuring the high efficiency and reliability of the package structure.

[0052] This application also provides a molding process applicable to any of the above-mentioned QFP packaging structures, such as... Figure 4 As shown, the molding process includes the following steps:

[0053] Step S401: The first surface of the first semiconductor chip is mounted on the first side of the pad of the frame, and the I / O pad of the first semiconductor chip is electrically connected to the first pin corner of the frame through the first metal lead.

[0054] Specifically, such as Figure 1 As shown, the first surface of the first semiconductor chip 20 is mounted on the first surface of the pad 100 of the frame 10. Here, the pad is a key part of the frame used to fix the chip and establish electrical connections. Then, the input / output (I / O) pads of the first semiconductor chip 20 are electrically connected to the first pin corner 103 of the frame 10 through the first metal lead 500-1 to realize signal interaction between the chip and external circuits.

[0055] Step S402: The first surface of the second semiconductor chip is mounted on the second surface of the pad, and the I / O pad of the second semiconductor chip is electrically connected to the first pin corner of the frame through the slot via the second metal lead. The slot is located on the side wall of the frame, and the first pin corner is located at the edge of the side wall of the frame. The second surface of the pad is parallel to and opposite to the first surface of the pad.

[0056] Specifically, see Figure 1 The first surface of the second semiconductor chip 30 is mounted on the second surface of the pad 100, which is the opposite side to the first semiconductor chip 20. The I / O pads of the second semiconductor chip are electrically connected to the first pin corner 103 via second metal leads 500-4 passing through slots 102 pre-defined in the sidewall of the frame. This design allows the metal leads to pass directly from the slots along the shortest path to connect the pin corners, thereby greatly reducing the transmission distance of electrical signals, lowering impedance, and also facilitating rapid heat conduction.

[0057] Step S403: The first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead and the frame are encapsulated using a molding compound.

[0058] Specifically, through a full-mold injection molding process, a molded body 40 is used to completely encapsulate the first semiconductor chip 20, the first surface and sides of the second semiconductor chip 30, the first metal lead 500-1, the second metal lead 500-4 (actually all metal leads are included), and the frame. This process uses materials such as low-shrinkage epoxy resin or silicone, which are cured at high temperatures to form a molded body, providing physical protection for the chip and leads, while also serving as a good heat dissipation channel to ensure that the heat generated by the chip during operation can be dissipated in a timely manner, maintaining the chip's operating temperature within an acceptable range.

[0059] In summary, this molding process not only ensures reliable electrical connections between the semiconductor chip and external circuits, but also achieves efficient heat dissipation and high mechanical strength of the package by optimizing the wiring path of the metal leads and using high-quality molding materials. This significantly improves the performance and reliability of the packaged electronic components under high power consumption and high speed conditions, solving the problem of reduced packaging performance caused by excessively long interconnect paths in existing QFP packaging technologies. This process is particularly suitable for the semiconductor industry's needs for high-density packaging, short signal paths, and effective heat dissipation solutions.

[0060] In some embodiments of this application, the first surface of the first semiconductor chip is mounted on the first side of the pads of the frame, including: see [link to previous embodiment]. Figure 5The first surface of the first semiconductor chip 20 is attached to the first surface 100-1 of the pad using silver paste 501-1, and the first surface of the second semiconductor chip is attached to the second surface of the pad, including: attaching the first surface of the second semiconductor chip 30 to the second surface 100-2 of the pad using thermosetting epoxy adhesive 501-2, with a curing temperature of 120°C to 150°C.

[0061] Specifically, the first surface of the first semiconductor chip is mounted to the first side of the pads on the frame using silver paste. Silver paste is widely used in chip mounting due to its excellent electrical and thermal conductivity. It can cure at lower temperatures, reducing thermal damage to the chip while providing good electrical connection and heat conduction path, ensuring the electrical performance and heat dissipation of the chip after packaging. The first surface of the second semiconductor chip is mounted to the second side of the pads using thermosetting epoxy adhesive. Unlike silver paste, epoxy adhesive typically requires higher curing temperatures. In this embodiment, the curing temperature range is 120°C to 150°C. This temperature condition ensures that the epoxy adhesive can fully harden after mounting, forming a strong bond. At the same time, the high insulation and temperature resistance of epoxy adhesive enable it to maintain structural stability and electrical isolation after high-temperature curing, making it less prone to deformation or failure even during subsequent packaging processes. The curing temperature setting (120°C to 150°C) is to balance material properties and process requirements. On the one hand, high-temperature curing helps to improve the curing degree of epoxy adhesive, enhance adhesion and thermal stability; on the other hand, this temperature range is also within the tolerance of many encapsulation materials (such as certain types of epoxy molding compounds) and will not cause damage to the encapsulation structure.

[0062] Through the above steps, it is ensured that the two different chips can be mounted in the package frame in an optimized manner, which not only guarantees the reliability of electrical connection, but also takes into account the heat dissipation requirements of the chips and the mechanical strength of the overall package, providing a solid foundation for high-power, high-speed QFP packaging.

[0063] In some embodiments of this application, before using a molding compound to encapsulate the first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead, and the frame, the process further includes: curing a low-shrinkage epoxy resin material to obtain the molding compound, wherein the temperature range of the curing treatment is 120°C to 150°C.

[0064] Specifically, the curing material is low-shrinkage epoxy resin, which exhibits minimal volume change during curing. This maintains the pre-encapsulation dimensions, preventing package deformation or physical stress on internal chips and leads due to material shrinkage, thus protecting the chips and leads from damage and ensuring post-encapsulation electrical performance and mechanical stability. The curing temperature range is set between 120°C and 150°C. This high-temperature curing condition ensures the epoxy resin fully hardens, forming a highly stable structure. High temperature promotes chemical reactions in the resin, accelerates the curing process, and also helps expel air bubbles, reducing voids in the package and improving its density and reliability. Pre-curing the epoxy resin before molding the first and second semiconductor chips, metal leads, and frame prevents significant curing reactions during subsequent high-temperature molding, reducing package dimensional changes and ensuring structural consistency before and after encapsulation. Furthermore, pre-curing helps assess material performance in advance, ensuring the controllability of the entire packaging process.

[0065] By curing the material within a temperature range of 120°C to 150°C, shrinkage after molding is effectively reduced, and the increased tension of electrical connections and chip displacement within the package are avoided. This significantly improves the overall performance of the packaged QFP component in terms of electrical performance, thermal management, and mechanical strength, and helps to enhance the performance and stability of the package.

[0066] like Figure 6 As shown, the first pin 103 of the frame can be a straight pin angle 103-1. In some embodiments of this application, the first pin angle of the frame can be bent into a bend angle 103-2 through a bend forming process. The bend forming process is a method for manufacturing the shape of the pin end, where mechanical force is used to bend the pin material (usually a copper alloy) at a predetermined angle to form the bend angle 103-2. The bend forming process is typically completed during the package frame manufacturing stage, using molds and stamping equipment to achieve precise control of the bending angle, ensuring that each pin end has a consistent and stable bending shape. Bent pins provide better mechanical stability and thermal management performance. The bending design can increase the contact area between the package and the PCB, improving the reliability of the electrical connection; simultaneously, bent pins can disperse stress, reducing the risk of pin breakage during transportation and use. In high-power packages or packages requiring good heat dissipation, the bend design of the pins can allow heat to be conducted from the chip to the heat dissipation surface more quickly, improving the thermal performance of the package.

[0067] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the molding process of this application will be described in detail below with reference to specific embodiments.

[0068] refer to Figure 1 , Figure 2 , Figure 3 , Figure 5 and Figure 6 The QFP packaging structure provided in this embodiment mainly includes a frame 10, a first semiconductor chip 20, a second semiconductor chip 30, and a molded body 40.

[0069] The frame 10 (made of copper alloy conductive material) has a central pad (E-PAD) 100, which includes a first surface 100-1 and a second surface 100-2. A silver-plated area 101 surrounds the pad (E-PAD), with a width of 150~300um. A slot 102 (width W=0.5–1.2mm) with a depth matching the lead frame thickness ensures complete alignment of the bond wire with the pad. A lead angle (first pin angle 103) is provided (the bend angle 103-2 can be achieved through a bend forming process). Metal Bond-Wire, specifications: Cu / Au wire, wire diameter 0.7mil (≈18µm) or 0.8mil (≈20µm). The first semiconductor chip 20 (DIE-1) is mounted on the first side 100-1 of the pads using silver paste 501-1. The I / O pads 201 of the first semiconductor chip are directly electrically connected to the lead corner (first pin corner 103) via the first metal lead 500-1 (gold or copper wire). The third metal lead 500-2 forms a ground electrical connection with the silver-plated area 101 of the E-PAD. The fourth metal lead 500-3 (multiple leads) is connected to the corresponding ground frame corner. Multiple metal leads are connected in parallel to reduce local impedance. The second semiconductor chip 30 (DIE-2) is mounted on the second side 100-2 of the pads using thermosetting epoxy adhesive 501-2 (curing temperature 120°C–150°C), with the distance between the adhesive layer and the pad ≥150µm. The first I / O pad 301-1 of the second semiconductor chip is electrically connected to the lead corner (first pin corner 103) via the second metal lead 500-4 through the slot 102. The second I / O pad 301-2 of the second semiconductor chip is electrically connected to the silver-plated area 101 of the E-PAD via the fourth metal lead 500-3 and the fifth metal lead 500-5 to form a ground property electrical connection. The molded body 40 (full mold injection molding body) has a total height H. It is made of low-shrinkage epoxy resin and cured at 120°C–150°C to form an epoxy resin molded body, which covers the first semiconductor chip 20, the second semiconductor chip 30, all metal leads, and the frame 10, providing mechanical support and heat dissipation channels.

[0070] Through the above structure, the metal bond-wire (CU / AU 0.7mil or 0.8mil) achieves a direct path from DIE-2 to the PIN corner (pin corner) within the slot, significantly shortening the interconnect path, reducing the impedance to ≤10Ω, effectively improving heat dissipation, and maintaining structural integrity after high-temperature curing. The first semiconductor chip 20 is mounted on the first side 100-1 of the pad using silver paste 501-1. The I / O pad 201 of the first semiconductor chip is electrically connected to the corresponding frame corner (first pin corner 103) via first metal leads 500-1, such as gold or copper wires. The third metal lead 500-2 is linked to the E-PAD, and the fourth metal lead 500-3 (multiple metal leads can be connected) is connected to the corresponding ground frame corner, achieving electrical connection of the E-PAD ground property. The first surface of the second semiconductor chip 30 is attached to the second surface 100-2 of the pad using thermosetting epoxy adhesive. The first I / O pad 301-1 of the second semiconductor chip is electrically connected to the first pin corner 103 of the frame via a second metal lead 500-4 passing through the slot 102. Figure 7 As shown, the thermosetting epoxy adhesive 501-2 needs to maintain a preset distance S with the first I / O pad 301-1 of the second semiconductor chip and the second I / O pad 301-2 of the second semiconductor chip, respectively, wherein the preset distance S is greater than 150um. The first I / O pad 301-1 of the second semiconductor chip is electrically connected to the corresponding frame corner (first pin corner 103) through the slot groove 102 via a second metal lead 500-4 such as gold or copper wire.

[0071] The molded body 40 has a total height determined based on the molding die height H, the height H2 of the first semiconductor chip 20, the height H3 of the second semiconductor chip 30, and the wire bonding details H1. The epoxy resin molding compound, formed through a transfer molding process, encapsulates the first surface and sides of the first semiconductor chip 20 and the second semiconductor chip 30, all metal leads, and the frame 10, providing protection and mechanical support. For applications requiring high heat dissipation, the chip can be made in an exposed form. Full mold injection molding uses low-shrinkage epoxy resin, cured at 120°C–150°C, with a dimensional change of <0.5% after curing. This structure achieves significantly shortened interconnect paths, low impedance, good heat dissipation, and maintains structural integrity even after high-temperature curing. Exposed DIE encapsulation is performed during molding. For applications requiring high heat dissipation, the DIE can be directly exposed to an external heat dissipation surface, reducing thermal resistance by approximately 30%–40%. High-temperature curing: After curing at 120°C–150°C, the slot, metal wire, and molded body all maintain structural integrity, with a cycle life ≥1. Secondary thermal shock.

[0072] The bend 103-2 is formed using a bend forming process.

[0073] This embodiment provides a structure for arranging exposed chips inside a QFP package. By pre-setting slots on the package sidewalls and having metal wires directly pass through the slots to connect to the PINs, a highly reliable packaging solution with the shortest interconnect path, lowest impedance, optimal heat dissipation, and compatibility with low-temperature curing plastic packages is achieved. This structure can be widely used in high-power, ultra-high-speed, and high-heat-dissipation QFP packages, achieving significant improvements in interconnect density, heat dissipation, and reliability compared to traditional QFPs.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0076] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A QFP packaging structure, characterized in that, include: A frame, wherein a pad is provided in the central region of the frame, and at least one slot is provided in the side wall of the frame; A first semiconductor chip, the first surface of the first semiconductor chip is mounted on the first side of the pad, and the I / O pad of the first semiconductor chip is electrically connected to the first pin corner of the frame through a first metal lead, the first pin corner being located at the edge of the sidewall of the frame; The second semiconductor chip has a first surface mounted on the second side of the pad. The I / O pad of the second semiconductor chip is electrically connected to the first pin corner of the frame through the slot via a second metal lead. The second side of the pad is parallel to and opposite to the first side of the pad. The molded body at least covers the first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead, and the frame.

2. The QFP packaging structure according to claim 1, characterized in that, The pads are surrounded by a silver-plated area. The first semiconductor chip is electrically connected to the silver-plated area via a third metal lead, and the second semiconductor chip is electrically connected to the silver-plated area via the third metal lead.

3. The QFP packaging structure according to claim 1, characterized in that, The depth of the slot is the same as the thickness of the frame.

4. The QFP packaging structure according to claim 1, characterized in that, The fourth metal lead is corner-connected to the ground attribute pin of the frame. The fourth metal lead is one or more metal leads, and multiple fourth metal leads are arranged in parallel.

5. The QFP packaging structure according to claim 1, characterized in that, The diameter of the first metal lead and the second metal lead is 0.7 mil or 0.8 mil.

6. The QFP packaging structure according to claim 1, characterized in that, The frame is made of copper alloy conductive material.

7. The QFP packaging structure according to claim 1, characterized in that, The total height of the molded body is determined based on the height of the first semiconductor chip, the height of the second semiconductor chip, and the wiring configuration of the first and second metal leads.

8. A molding process applied to the QFP packaging structure according to any one of claims 1 to 7, characterized in that, include: The first surface of the first semiconductor chip is mounted on the first side of the pad of the frame, and the I / O pad of the first semiconductor chip is electrically connected to the first pin corner of the frame through the first metal lead; The first surface of the second semiconductor chip is mounted on the second surface of the pad, and the I / O pad of the second semiconductor chip is electrically connected to the first pin corner of the frame through the slot via the second metal lead. The slot is located on the side wall of the frame, and the first pin corner is located at the edge of the side wall of the frame. The second surface of the pad is parallel to and opposite to the first surface of the pad. The first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead, and the frame are encapsulated using a molding compound.

9. The molding process according to claim 8, characterized in that, Mounting the first surface of the first semiconductor chip onto the first side of the pads of the frame includes: mounting the first surface of the first semiconductor chip onto the first side of the pads using silver paste. Mounting the first surface of the second semiconductor chip onto the second side of the pad includes: mounting the first surface of the second semiconductor chip onto the second side of the pad using a thermosetting epoxy adhesive, wherein the curing temperature is 120°C to 150°C.

10. The molding process according to claim 8, characterized in that, Before molding the first semiconductor chip, the first surface and side surface of the second semiconductor chip, the first metal lead, the second metal lead, and the frame using a molding compound, the process further includes: The low-shrinkage epoxy resin material is cured to obtain the molded body, and the curing temperature range is 120°C to 150°C.

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