Apparatus for testing plurality of integrated circuits on semiconductor wafer

Abstract

The present invention relates to an apparatus for testing "high power" integrated circuits (1001) on a semiconductor wafer (1000) during performance and fault tests using a tester (3004) not designed to perform tests on the "high power" integrated circuits (1001). The apparatus comprises: a probe (3002a) for establishing a temporary electrical connection with a connector (2000) of the integrated circuits (1001) to be tested; a buffer circuit (4001a) for sharing a power supply resource (SC1) of the tester (3004) with the power supply input (VCC) of the integrated circuits (1001) to be tested; and a group (4002) consisting of a multiplexer circuit (4002a-d), each multiplexer circuit has a first input connected to a shared high voltage resource (HVC1) of the tester (3004), a second input connected to a different data input / output electronic resource (DC1-4) in communication with the tester (3004), and an output in communication with a test input / output (SPT) of an integrated circuit (1001a-d) to be tested.

Description

Technical Field

[0001] This invention relates to an apparatus and method for testing multiple integrated circuits on a semiconductor wafer. Background Technology

[0002] In the microelectronics industry, chips, integrated circuits, and dies are typically manufactured in large quantities in series on a single semiconductor wafer (especially on a silicon wafer). Integrated circuits can include a variety of components such as memory circuits, microprocessors, fuse circuits, communication buses, flip-flops, latch or buffer logic circuits, and other input / output (I / O) interface circuits.

[0003] Before dicing and packaging, each integrated circuit (IC) undergoes performance testing or fault testing to verify that its electrical characteristics meet its design specifications. For example, performance testing involves sending signals in the form of data frames to the IC's inputs and monitoring and analyzing the response signals at the circuit's outputs. If the response signals are inconsistent, the IC is deemed defective and discarded. Static fault testing can also be performed, in which high voltage and / or high current are applied to the IC to screen out those prone to premature failure.

[0004] The common practice is to use automated test equipment (ATE) in the form of a programmable electronic system for performance and fault testing. The primary function of this test equipment is to execute test procedures, such as sending a set of data frames or voltage and / or current values ​​to the inputs of an integrated circuit, and then collecting and analyzing the circuit's response signals. To perform this function, the test equipment has input / output terminals called channels, the number of which typically determines the number of integrated circuits that the test equipment can test simultaneously.

[0005] Automated test equipment typically communicates with integrated circuits under test conditions via an interface card, which itself connects to a probe card. The probe card is configured to establish an electrical connection between the interface card and the IC-specific test pads. The interface card relays and optionally preprocesses the signals between the probe card and the test equipment. When integrated circuits are under conditions being tested by automated test equipment, they are typically referred to as DUTs (Device Under Test). These integrated circuits are usually tested directly in rows on a semiconductor wafer.

[0006] Probe cards typically take the form of electronic cards with multiple pins or studs. The number and size of these pins or studs correspond to the density and size of test pads specific to the integrated circuit, and the arrangement of these pins or studs allows for the redistribution of electrical signals exchanged between the test equipment and the integrated circuit via an interface card. In use, the probe card is usually held stationary while a probe station is used to place the die containing the integrated circuit beneath the probe card, establishing electrical contact between the integrated circuit's pads in a row of circuits and the probe card's pins.

[0007] In the semiconductor industry, and more generally in the microelectronics industry, the cost of test equipment and the time required to perform procedures for testing the performance of integrated circuits are major issues in addressing the increasing and faster demands of circuit production.

[0008] A common trend is to increase the number of integrated circuits (ICs) tested simultaneously, especially when test programs have particularly long cycles. This is true for ICs including non-volatile memory, which requires numerous write and erase operations in their test programs. Today, depending on the available channels on the test equipment and probe cards, dozens or even hundreds of ICs are tested in parallel. In addition to increasing the number of ICs tested simultaneously, it is also common to optimize test programs or modify circuit design to reduce test duration.

[0009] US Patent 4956602 A, issued by AMBER ENGINEERING INC. (USA), dated November 9, 1990, describes a semiconductor wafer whose surface includes multiple integrated circuits and multiple multiplexers, the multiplexers being composed of multiplexed lines located in diced regions of the wafer. The integrated circuits are connected to a small number of test pads via the multiplexers. A larger number of integrated circuits can be tested in parallel using the same number of test pads.

[0010] US Patent 6366112 B1 [Micron Technology Corporation [USA]] 09.10.2001 describes a probe card that includes multiplexer circuitry configured to selectively broadcast and transmit test signals from a test facility to integrated circuits on a semiconductor wafer. The multiplexer circuitry allows channels of the test facility to be distributed across several integrated circuits being tested in parallel. The probe card includes a silicon substrate on which contactors are formed by chemical etching. The contactors are appropriately sized to contact the pads of the integrated circuit under test. Each multiplexer circuit is formed of multiple field-effect transistors that allow the contactors to be selected using control signals. Each multiplexer circuitry reallocates channels from each test station of the test facility to increase the number of integrated circuits that could otherwise be tested at each test station.

[0011] US Patent 6400173 B1 [Hitachi, Ltd. [Japan] 04.06.2002] describes a system that enables a reduction in the time required to test integrated circuits on a semiconductor wafer. The system includes a probe card with multiple pins arranged spatially to connect to pads on an integrated circuit. These pins are connected to multiple test circuits contained within the probe card. These test circuits are configured to exchange electrical signals with the integrated circuit and generate test results according to a given test procedure.

[0012] US 2003 074611 A1 [Tower Semiconductor, Inc. [USA]] 17.04.2003 describes a system that enables an increase in the number of non-volatile memory integrated circuits that can be tested simultaneously in parallel. The system includes a test apparatus, a probe card, and an alignment plate. The probe card includes a substrate with auxiliary circuitry, a first series of pads disposed on one surface of the substrate and adapted for electrical connection to the test apparatus, and a second series of pads disposed on the other surface of the substrate and adapted for electrical connection to pads disposed on a wafer including the integrated circuit under test. Both series of pads are also connected to the auxiliary circuitry via switches configured to optionally bypass the auxiliary circuitry. The auxiliary circuitry includes multiple self-diagnostic circuits that can be associated with the integrated circuit on the wafer in parallel, respectively. This configuration enables a reduction in the time required for read or erase operations in the non-volatile memory of the integrated circuit. The self-diagnostic circuits can also be directly integrated into the dicing lines of the wafer including the integrated circuit under test. They are configured to utilize only a limited number of pads on the integrated circuit and share some pads among several circuits, thereby increasing the number of circuits that can be tested in parallel.

[0013] US Patent 6903565 B2 [Infineon Technologies AG [Germany]] 07.06.2005 describes a system for parallel testing of multiple integrated circuits on a semiconductor wafer. The system includes a probe card and an interface card with pins. The system includes an external power supply unit that enables the supply voltage to be supplied to the multiple integrated circuits. The interface card includes a voltage regulation unit controlled by a reference voltage source and a current limiting unit that enables the measurement of the current consumed by the integrated circuits. The current limiting unit is configured to operate an electrical isolation device when the consumed current exceeds a certain threshold.

[0014] WO 2006 083856 A1 [FORMFACTOR INC. [USA]] 10.08.2006 and WO 2007 146583 A2 [FORMFACTOR INC. [USA]] 21.12.2007 describe a probe card that includes circuitry enabling the sharing of a power supply path for a test apparatus among four integrated circuits. The circuitry associates each integrated circuit with a voltage regulation module that enables isolation of the integrated circuit in the event of a current overload. The probe card may include multiplexer circuitry for redirecting output signals from the integrated circuits to the test apparatus.

[0015] US Patent 8378698 B2 [Samsung Electronics Co., Ltd. [Korea]] 19.02.2013 describes a probe card with pins adapted for electrical contact with pads of multiple integrated circuits on a semiconductor wafer. The probe card includes multiple test circuits, each of which includes multiple signal transmitters corresponding to the integrated circuit under test on the semiconductor wafer. Voltage and control signals from the test equipment are relayed by the signal transmitters and sent to the integrated circuit. These signal transmitters are further configured to relay response signals from the integrated circuit to the test equipment.

[0016] US Patent and Trademark Office No. 2016011232 A1 [Infineon Technologies AG [Germany]] 14.01.2016 describes a system for increasing the number of integrated circuits that can be tested simultaneously in parallel without increasing the number of channels in the test equipment. The system includes a test device, an interface card, and a probe card in the form of a circuit, which is provided with multiple pads suitable for connection to multiple integrated circuits. The circuitry of the probe card is configured to exchange the same instructions with all integrated circuits connected to it and to exchange instructions with the test device via the interface card.

[0017] US Patent and Trademark Office No. 341991 A1 [Winbond Electronics Inc. [Taiwan]] 27.10.2022 describes a system for enabling the simultaneous parallel testing of a number of integrated circuits (ICs) by sharing available channels of a test device. The system includes a test device and a test apparatus consisting of interface circuitry and analysis circuitry. The interface circuitry is simultaneously connected to four ICs under test on a silicon wafer and enables the transmission of signals from the test device to the ICs. The interface circuitry includes a buffer circuitry coupled to the four ICs under test and the design circuitry. The buffer circuitry enables the redistribution of power supply channels for the test device among the four circuits and among control signals and input / output signals. The analysis circuitry uses trigger circuitry to receive the output signals of the four ICs and serialize these output signals before transmitting them to the test device. Summary of the Invention

[0018] Technical issues

[0019] A key trend in the microelectronics industry is the development of low-power integrated circuits (ICs) to reduce their power consumption. Specifically, this trend leads to lower operating voltages and currents for ICs. For example, in the smart card field, current development efforts focus on Class B and Class C ICs conforming to the ISO / IEC 7816-3:2006 standard. This means that Class B ICs have operating voltages and currents of less than 3.3 V and 50 mA, respectively, while Class C ICs have operating voltages and currents of less than 1.98 V and 30 mA, respectively.

[0020] This trend has directly led to a high priority in developing test equipment suitable for this type of integrated circuit, and due to the high cost and technical limitations of installing such test equipment, it is preferably deployed within semiconductor manufacturing plants, particularly in open manufacturing facilities. In other words, "high-power" test equipment for high-operating-voltage electronic circuits (e.g., Class A integrated circuits in the smart card field) is becoming increasingly difficult to obtain in manufacturing plants. In existing manufacturing plants, this test equipment is gradually being replaced by "low-power" test equipment, or it is no longer deployed in new manufacturing plants.

[0021] While low-power electronics are becoming increasingly prevalent, there is still a need to manufacture high-power integrated circuits, such as Class A integrated circuits in the smart card field. However, performing performance and fault testing (especially static fault testing) on ​​this type of integrated circuit requires the use of "high-power" test equipment, which is becoming increasingly scarce. Furthermore, for cost reasons, integrated circuits must be tested on-site (i.e., at the manufacturing plant). Therefore, there is a need to perform these tests on this type of integrated circuit using test equipment that is unsuitable for performance and fault testing of "high-power" circuits, such as Class A integrated circuits, especially in the smart card field.

[0022] Technical solutions

[0023] In a first aspect of the invention, a probe card for testing multiple integrated circuits on a semiconductor wafer is provided, the probe card comprising:

[0024] - Multiple pins, which are adapted to provide temporary electrical connections to pads of multiple integrated circuits under test on a semiconductor wafer;

[0025] - At least one buffer circuit, which is arranged to share the same power supply channel of the test equipment with the power supply input of the group consisting of at least four integrated circuits in the plurality of integrated circuits under test;

[0026] - At least one group consisting of at least four multiplexer circuits, the at least four multiplexer circuits being arranged such that they share the same high-voltage channel of the test device with the first input of each of the four multiplexer circuits, different data input / output electronic channels of the test device being electrically in communication with the second input of each of the four multiplexer circuits, and the output of each of the four multiplexer circuits being electrically in communication with the test input / output of the integrated circuit in the group consisting of the at least four integrated circuits among the plurality of integrated circuits under test.

[0027] In some specific embodiments, the probe card conforming to the present invention may further include one or more of the following features, which may be considered individually or in all possible combinations of technologies:

[0028] - Each multiplexer circuit in the multiplexer circuit group is configured to simultaneously connect the high-voltage channel of the test device to the test input / output of each integrated circuit in the group consisting of at least four integrated circuits, according to a first value of the control signal.

[0029] - Each multiplexer circuit in the multiplexer circuit group is configured to sequentially connect the high-voltage channel of the test device to the test input / output terminal of each integrated circuit in the group consisting of at least four integrated circuits, according to a second value of the control signal.

[0030] - Each multiplexer circuit in the multiplexer circuit group is configured to simultaneously connect the electronic channel of the test device to the test input / output of each integrated circuit in the group consisting of at least four integrated circuits, according to a third value of the control signal.

[0031] - The first value of the control signal corresponds to performing a static fault test on these integrated circuits under test by applying a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

[0032] - The second value of the control signal corresponds to measuring and testing these integrated circuits under test with a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

[0033] - The third value of the control signal corresponds to current measurement of these integrated circuits under test using a voltage less than a threshold, preferably less than a threshold fixed at 4.5 V.

[0034] - These buffer circuits and / or these multiplexer circuit groups are integrated into an interface card that communicates electrically with the probe card.

[0035] - This probe card is further suitable for electrical communication with test equipment for Class B and / or Class C integrated circuits conforming to ISO / IEC 7816-3:2006, as well as multiple Class A integrated circuits to be tested.

[0036] - This probe card is further adapted for electrical communication with test equipment configured to test semiconductor mass storage and / or random access memory architectures.

[0037] In a second aspect of the invention, a system for testing multiple integrated circuits on a semiconductor wafer is provided, the system comprising a testing apparatus and a probe card according to a first aspect of the invention.

[0038] In a third aspect of the invention, alternative or additional methods for testing multiple integrated circuits on a semiconductor wafer are provided, in particular:

[0039] - A method for testing multiple integrated circuits on a semiconductor wafer, the method comprising the following steps:

[0040] - The power supply channel of the test equipment is shared with the power supply input of the group consisting of at least four integrated circuits in the plurality of integrated circuits under test;

[0041] - Connect the same high-voltage channel of the test equipment in parallel with the test input / output terminal of each of the multiple integrated circuits under test in a group consisting of at least four integrated circuits;

[0042] - Apply a voltage greater than a threshold to the test input / output terminal of each of the group consisting of at least four integrated circuits;

[0043] - Verify the operation of each integrated circuit by analyzing the response signals from the corresponding test inputs / outputs of these integrated circuits.

[0044] - A method for testing multiple integrated circuits on a semiconductor wafer, the method comprising the following steps:

[0045] - Connect the high-voltage channel of the test equipment sequentially to the test input / output terminal of each integrated circuit in the group consisting of at least four integrated circuits in the plurality of integrated circuits under test;

[0046] - Apply a voltage greater than a threshold sequentially to the test input / output terminal of each integrated circuit in the group consisting of at least four integrated circuits;

[0047] - The response of each integrated circuit is measured sequentially by analyzing the response signals from the corresponding test inputs / outputs of these integrated circuits.

[0048] - A method for testing multiple integrated circuits on a semiconductor wafer, the method comprising the following steps:

[0049] - Connect the data input / output electronic channels of the test equipment in parallel with the test input / output terminals of each of the multiple integrated circuits under test in a group consisting of at least four integrated circuits;

[0050] - Send data frames in parallel to the test input / output of each of the at least four integrated circuits in the group;

[0051] - Response data frames from each integrated circuit are received in parallel by analyzing the response signals from the corresponding test inputs / outputs of these integrated circuits.

[0052] In a fourth aspect of the invention, a computer program is provided, the computer program including instructions that, when executed by a computer, cause the computer to implement one of the methods according to the third aspect of the invention using the system according to the second aspect. Attached Figure Description

[0053] Figure 1 It is a schematic depiction of a semiconductor wafer on which integrated circuits are formed.

[0054] Figure 2 This is a schematic depiction of a group consisting of four integrated circuits.

[0055] Figure 3 It is a schematic depiction of a system used to test the performance and faults of integrated circuits on semiconductor wafers.

[0056] Figure 4 This is a structural diagram of a probe card according to the first aspect of the present invention.

[0057] Figure 5 This is a functional diagram of the probe card according to the first embodiment.

[0058] Figure 6 This is a functional diagram of the probe card according to the second embodiment.

[0059] Figure 7 This is a functional diagram of the probe card according to the third embodiment. Detailed Implementation

[0060] refer to Figure 1 Integrated circuits 1001 (also known as electronic chips) are typically fabricated in large quantities in series on a single semiconductor wafer 1000. Their arrangement usually follows a Hippodamian plan, in which these circuits are arranged in columns 1002a-n and rows 1003a-n for easy positioning and to enable several of these circuits to be tested in parallel during performance testing and fault testing.

[0061] In the context of this invention, "integrated circuit" means a group of inseparable electronic components that are electrically interconnected and inseparably associated on a semiconductor substrate. An integrated circuit implements logical operations for processing electromagnetic signals (especially electrical signals) through its components. It can be a programmable microcontroller or one or more sub-elements, such as a microprocessor, random access memory, read-only memory, fuse circuit, communication bus, flip-flop, latch or buffer logic circuit, and other input / output (I / O) interface circuits.

[0062] refer to Figure 2Integrated circuit 1001 includes a number of input-output terminals VCC, DQ, and SPT. Some of these input-output terminals, VCC and DQ, can be used during performance test procedures and fault test procedures, and subsequently during the implementation and use of the integrated circuit in an electronic device. The other input-output terminal, SPT, is used only for performance test procedures and fault test procedures. These input-output terminals have different functions. Figure 2 In the example, input / output VCC is the power supply input, input / output DQ is the input / output used to exchange data during the subsequent use of the circuit in the electronic device, and input / output SPT is the input / output of a program specifically used to test the performance and faults of circuit 1001.

[0063] On wafer 1000, the input-output terminals of the circuitry are connected to pads 2000 so that they can be connected to pins of a probe card during performance and failure test procedures. These pads may be dedicated solely to test procedures and not intended for use in the electronic device in which the circuitry will subsequently be implemented. They may be arranged in the die-cutting area so that they can be removed during circuit packaging, or simply left in the electronic device during packaging but not used.

[0064] refer to Figure 3 A system 3000 for testing the performance and faults of an integrated circuit 1001 on a semiconductor wafer 1000 includes a stage or probe station 3001 for the semiconductor wafer, a probe card 3002, an interface card 3003, and an automated test equipment (ATE) 3004. The probe card 3002 is shaped like an electronic card and has multiple pins or studs 3002a. The pins 3002a contact test pads (not depicted) specific to the integrated circuit 1001 and enable the redistribution of electrical signals exchanged between the test equipment 3004 and the integrated circuit 1001 via the interface card 3003. Their number and size correspond to the density and size of the test pads of the integrated circuit 1001.

[0065] During system operation, the probe card 3002 is typically held stationary while a wafer 1000, including an integrated circuit 1001, is placed beneath the probe card via a stage or probe station 3001, so that electrical contact is established between the pads 2000 of the integrated circuit 1001 in a row of circuits and the pins 3002a of the probe card 3002. Each test pad of the integrated circuit 1001 is thus positioned to electrically communicate with a channel 3004a of the test equipment 3004. For example, refer to... Figure 2The input / output terminal VCC can electrically communicate with the power supply channel of the test equipment, and the input / output terminal SPT can electrically communicate with the high-voltage channel or electronic channel of the test equipment. The number of channels of the test equipment usually determines the number of integrated circuits that the test equipment can test simultaneously.

[0066] In the context of this invention, a “channel” of a test device means an input-output terminal of the test device that enables the exchange of a set of data frames with electronic circuits and / or the application of voltage and / or current values ​​to the input terminals of an integrated circuit.

[0067] In the context of this invention, a "power supply channel" of a test device means a channel that can provide sufficient voltage and / or current to power and enable an integrated circuit. An "electronic channel" means a channel that allows the exchange of data frames between the test device and the pads of the integrated circuit. A "high-voltage channel" of a test device means a channel that can provide a voltage higher than that of one of its electronic channels. Notably, this type of channel can provide voltages of tens of volts (e.g., up to 30 volts).

[0068] like Figure 3 As shown, the probe card 3002 includes a set of circuits 3002b, which functions to allocate channels of the test equipment to the pads of the integrated circuit via the interface card.

[0069] In a first aspect of the invention, reference is made to Figure 3 and Figure 4 A probe card 3002 is provided for testing multiple integrated circuits 1001 on a semiconductor wafer 1000, the probe card 3002 comprising:

[0070] - Multiple pins 3002a, which are adapted to provide temporary electrical connections to pads 2000 of multiple integrated circuits 1001 to be tested on semiconductor wafer 1000;

[0071] - At least one buffer circuit 4001a, which is arranged to share the same power supply channel SC1 of the test equipment 3004 with the power supply input VCC of the group consisting of at least four integrated circuits 1001a-d in the plurality of integrated circuits under test 1001;

[0072] - At least one group 4002 consisting of at least four multiplexer circuits 4002a-d, the at least four multiplexer circuits being arranged such that they share the same high-voltage channel HVC1 of the test device 3004 with the first input of each of the four multiplexer circuits 4002a-d, the different data input / output electronic channels DC1-4 of the test device 3004 being electrically in communication with the second input of each of the four multiplexer circuits 4002a-d, and the output of each of the four multiplexer circuits 4002a-d being electrically in communication with the test input / output SPT of the integrated circuit 1001a-d in the group consisting of at least four integrated circuits 1001a-d among the plurality of integrated circuits under test 1001.

[0073] For illustrative purposes, in Figure 4 The diagram depicts two buffer circuits 4001a and 4001b and two multiplexer circuit groups 4002 and 4003. The number of buffer circuits and multiplexer circuit groups depends on the number of high-voltage channels in the test device 3004. For example, for test devices such as the Magnum V EV (comprising 512 electronic channels, 128 high-voltage channels, and 128 power supply channels) sold by Teradyne®, the number of buffer circuits and multiplexer circuit groups can reach 512. The probe card 3002 according to the first aspect of the invention can be implemented with other types of test devices, particularly with test devices comprising 1024 electronic channels, 256 high-voltage channels, and 256 power supply channels. In this case, the number of integrated circuits that can be tested simultaneously using the probe card according to the first aspect of the invention can reach 1024.

[0074] The number of integrated circuits corresponding to each buffer circuit and each multiplexer circuit group is at least four, with each integrated circuit corresponding to one multiplexer circuit. Therefore, in the configuration of the foregoing example, the probe card 3002 according to the first aspect of the invention can simultaneously test 512 integrated circuits by means of a shared power supply channel and high-voltage channel of the test equipment. The number of integrated circuits corresponding to each buffer circuit and each multiplexer circuit group can be more. It can be equal to a power of 2, where N is greater than 2.

[0075] A significant advantage of the probe card according to the first aspect of the invention is that it enables the performance of these tests on this type of integrated circuit using test equipment unsuitable for static testing of integrated circuits, particularly Class A integrated circuits in the field of smart cards. In the aforementioned example, the voltage provided by the electronic channels of the Magnum V EV test equipment is suitable for Class B and Class C integrated circuits. The probe card according to the first aspect of the invention makes it possible to use such test equipment on Class A integrated circuits, particularly for static performance testing or fault testing of non-volatile (e.g., flash) memory elements of integrated circuits.

[0076] The multiplexer circuits 4002a-d and 4003a-d in each group 4002 and 4003 are configured to propagate one of their inputs to their outputs according to the values ​​of control signals CS1 and CS2. This operation can be performed in different ways depending on the nature of the test performed on the integrated circuit.

[0077] According to the first embodiment, refer to Figure 5 Each multiplexer circuit in group 4002, consisting of multiplexer circuits 4002a-d, is configured to simultaneously connect the high-voltage channel HVC1 of test device 3004 to the test input / output terminal SPT of each of the at least four integrated circuits 1001 in the group consisting of multiple integrated circuits 1001a-d, according to a first value of control signal CS1. According to the first value of control signal CS1, the multiplexer circuits 4002a-d in group 4002 simultaneously and therefore in parallel propagate the same high-voltage channel HVC1 to the test input / output terminal SPT of each integrated circuit 1001a-d at their outputs.

[0078] This first embodiment is particularly suitable for performing static fault testing on integrated circuits, especially memory elements of Class A integrated circuits. Therefore, according to a preferred variant, the first value of the control signal CS1 corresponds to performing static fault testing on these integrated circuits under test by applying a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

[0079] According to the second embodiment (which is an alternative or additional solution to the first embodiment), refer to Figure 6Each multiplexer circuit in group 4002, consisting of multiplexer circuits 4002a-d, is configured to sequentially connect the high-voltage channel HVC1 of test device 3004 to the test input / output terminal SPT of each of the at least four integrated circuits 1001 in the group 1001, according to the second value of control signal CS1. According to the second value of control signal CS1, the multiplexer circuits 4002a-d in group 4002, one after another at their outputs, and thus sequentially propagate the same high-voltage channel HVC1 to the test input / output terminal SPT of each integrated circuit 1001a-d. The integrated circuits are tested individually, one after another.

[0080] This second embodiment is particularly suitable for performing static performance testing on integrated circuits based on the measurement and analysis of their response signals. Measuring the response signals may in particular include measuring the voltage at the test input / output terminal SPT of each integrated circuit 1001a-d. Thus, according to a preferred variant particularly suitable for Class A integrated circuits, the second value of the control signal (CS1) corresponds to measuring and testing these integrated circuits under test with a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

[0081] According to the third embodiment (which is an alternative or additional solution to the two other embodiments mentioned above), refer to Figure 7 Each multiplexer circuit in the group 4002, consisting of multiplexer circuits 4002a-d, is configured to simultaneously connect the electronic channel DC1-4 of the test device 3004 to the test input / output terminal SPT of each of the at least four integrated circuits 1001 in the group consisting of at least four integrated circuits 1001a-d, according to the third value of the control signal CS1. According to the third value of the control signal CS1, the multiplexer circuits 4002a-d simultaneously and therefore in parallel propagate the data input / output electronic channel DC1-4 from the test device 3004 to the test input / output terminal SPT of each of the at least four integrated circuits 1001a-d. A single data input / output electronic channel DC1-4 of the test device 3004 is used for each integrated circuit 1001a-d.

[0082] This third embodiment is particularly suitable for performing current measurement tests on integrated circuits, such as exchanging one or more data frames between a test device and the integrated circuit. The one or more data frames may consist of a series of voltage values, the duration and value of which correspond to a time constant and a bit value, respectively. For example, the test device may transmit instructions to the integrated circuit via its electronic channels to perform a series of write and read operations in its memory elements. In a preferred variant, a third value of the control signal CS1 corresponds to current measurement of these integrated circuits under test using a voltage less than a threshold, preferably less than a fixed threshold of 4.5 V.

[0083] In all the above embodiments and variations, buffer circuits 4001a, 4001b and multiplexer circuit groups 4002, 4003 form part of probe card 3002. However, in some systems 3000 used for testing integrated circuit 1001 (e.g., Figure 3 In the system shown, it may typically be necessary to use an interface card 3003 between the test equipment and the probe card 3002. Furthermore, in some alternative embodiments, buffer circuits 4001a, 4001b and / or multiplexer circuit groups 4002, 4003 are integrated into the interface card 3003, which is in electrical communication with the probe card 3002.

[0084] The probe card 3002 according to the first aspect of the invention can operate with any type of suitable test equipment. However, as described above, an advantage of the probe card 3002 according to the first aspect of the invention is that it enables the performance of these tests on this type of integrated circuit using test equipment that is not suitable for performing static testing on Class A integrated circuits 1001 in the field of smart cards. Furthermore, according to some preferred embodiments that can be combined with all the above embodiments, the probe card 3002 according to the first aspect of the invention is further suitable for electrical communication with Class B and / or Class C integrated circuits 1001 conforming to the ISO / IEC 7816-3:2006 standard and a plurality of Class A integrated circuits to be tested by test equipment 3004.

[0085] The probe card 3002, according to any embodiment of the first aspect of the invention, can be advantageously used to test any type of integrated circuit, particularly non-volatile memory elements of integrated circuits. According to some preferred embodiments, the probe card can be further adapted for electrical communication with a test apparatus 3004 configured to test semiconductor mass storage (e.g., flash memory) and / or random access memory architectures.

[0086] In a second aspect of the invention, a system 3000 for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000 is provided. The system includes a probe card 3002 according to a first aspect of the invention and a test apparatus 3004. The test apparatus 3004 may be a test apparatus for Class A integrated circuits 1001 conforming to the ISO / IEC 7816-3:2006 standard, or a test apparatus for Class B and / or Class C integrated circuits.

[0087] In a third aspect of the invention, several alternative or additional methods for testing multiple integrated circuits on a semiconductor wafer are provided.

[0088] According to a first variation, a method for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000 is provided, the method comprising the following steps:

[0089] - The power supply input VCC of the test equipment 3004 is shared with the power supply channel SC1 of the test equipment 3004 with the power supply input VCC of a group consisting of at least four integrated circuits 1001a-d in a plurality of integrated circuits under test 1001;

[0090] - Connect the same high-voltage channel HVC1 of the test equipment 3001 in parallel with the test input / output terminal SPT of each of the multiple integrated circuits under test 1001 in a group consisting of at least four integrated circuits 1001a-d;

[0091] - Apply a voltage greater than a threshold to the test input / output terminal SPT of each of the at least four integrated circuits 1001a-d;

[0092] - The operation of each integrated circuit is verified by analyzing the response signals of the corresponding test input / output terminals (SPTs) of these integrated circuits 1001a-d.

[0093] According to this first variation, the integrated circuits are simultaneously subjected to static fault testing by applying a voltage greater than a threshold through the same high-voltage channel of a shared test device. This method is particularly suitable for performing static fault testing on non-volatile memory elements of Class A integrated circuits. The voltage threshold can advantageously be fixed at 4.5 V.

[0094] According to a second variation, a method for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000 is provided, the method comprising the following steps:

[0095] - Connect the high-voltage channel HVC1 of the test equipment 3004 sequentially to the test input / output terminal SPT of each of the multiple integrated circuits under test 1001 in a group consisting of at least four integrated circuits 1001a-d;

[0096] - A voltage greater than a threshold is sequentially applied to the test input / output terminal SPT of each of the group consisting of at least four integrated circuits 1001a-d;

[0097] - The response of each integrated circuit is measured sequentially by analyzing the response signals of the corresponding test input / output terminals SPT of these integrated circuits 1001a-d.

[0098] According to this second variation, integrated circuits are sequentially subjected to performance testing by applying voltages greater than a threshold through the same high-voltage channel of a shared test device. This method is particularly suitable for static fault testing of non-volatile memory elements of Class A integrated circuits. The voltage threshold can advantageously be fixed at 4.5 V.

[0099] According to a third variation, a method is provided for testing a plurality of integrated circuits 1001a-d on a semiconductor wafer 1000, the method comprising the following steps:

[0100] - Connect the data input / output electronic channel DC1-4 of the test device 3004 in parallel with the test input / output terminal SPT of each of the multiple integrated circuits under test 1001 in a group consisting of at least four integrated circuits 1001a-d;

[0101] - Send data frames in parallel to the test input / output terminal SPT of each of the group consisting of at least four integrated circuits 1001a-d;

[0102] - Response data frames from each integrated circuit are received in parallel by analyzing the response signals of the corresponding test input / output terminals (SPTs) of these integrated circuits 1001a-d.

[0103] According to this third variation, the method simultaneously subjects integrated circuits to current measurement tests by exchanging data frames between the test equipment and the integrated circuits via the electronic channels of the test equipment. For example, the test equipment can transmit instructions to the integrated circuits (especially Class A integrated circuits) via its electronic channels to perform a series of write and read operations in their memory elements.

[0104] The methods according to the foregoing three variations can be implemented alternatively or additionally by any means. Preferably, they are implemented using a system according to the second aspect of the invention. They can be implemented by the test equipment itself or by a data processing device configured to control the test equipment, causing the test equipment to perform the steps of these methods.

[0105] An example of a data processing device is one that can automatically perform a series of arithmetic or logical operations to perform a task or action. This device (also referred to as a computer) may include one or more central processing units (CPUs) and / or one or more graphics processing units (GPUs), as well as at least one control device suitable for performing these operations. It may also include other electronic components, such as input / output interfaces, non-volatile or volatile storage devices, and communication buses for transferring data between internal components of the device or with external components. One of the input / output devices may be a user interface for human-computer interaction, for example, a graphical user interface for displaying human-understandable information. To implement one or more methods according to the third aspect of the invention, the device may include an input / output interface for electronic communication with a test device, and optionally a probe card according to the first aspect of the invention.

[0106] In a fourth aspect of the invention, a computer program is provided, comprising instructions that, when executed by a computer, cause the computer to implement one or more methods according to the third aspect of the invention via a system according to a second aspect of the invention. The program may be stored in the memory of a data processing apparatus as described above and executed by that data processing apparatus. Alternatively, the program may be executed by the test apparatus itself after being loaded into memory.

[0107] Any type of compiled or interpreted programming language can be used to implement the steps of the method according to the third aspect of the invention in a computer program. The computer program can form part of a software solution, namely a set of executable instructions, code, scripts, etc., and / or a database.

[0108] Computer programs can be stored on a recording medium that can be read by a computer or testing equipment. The recording medium is preferably non-volatile memory, such as a hard disk or semiconductor reader. It can be a removable or non-removable storage medium that forms part of a computer. It can also be volatile memory within a removable medium, or form part of a computer used as a server from which executable instructions can be downloaded, and which, when executed by the computer, ensure that the computer performs the method according to the third aspect of the invention.

[0109] References

[0110] Patent documents

[0111] US 4956602 A, [AMBER ENGINEERING INC. [USA]], 11.09.1990.

[0112] US 6366112 B1 [Micron Technology Corporation [USA]] 09.10.2001.

[0113] US 6400173 B1 [Hitachi Manufacturing Co., Ltd. [Japan]] 04.06.2002.

[0114] US 2003 074611 A1 [Tower Semiconductor Inc. [USA]] 17.04.2003.

[0115] US 6903565 B2 [Infineon Technologies AG [Germany]] 07.06.2005.

[0116] WO 2006 083856 A1 [FORMFACTOR INC. [USA]] 10.08.2006.

[0117] WO 2007 146583 A2 [FORMFACTOR INC. [USA]] 21.12.2007.

[0118] US 8378698 B2 [Samsung Electronics Co., Ltd. [South Korea]] 19.02.2013.

[0119] US 2016011232 A1 [Infineon Technologies AG [Germany]] 14.01.2016.

[0120] US 2022 341991 A1 [Winbond Electronics Co., Ltd. [Taiwan, China]] 27.10.2022.

[0121] Non-patent literature

[0122] ISO / IEC 7816-3 - Identification cards — Integrated circuit cards — Part 3: Cards with contacts — Electrical interface and transmission protocols, 2006.

Claims

1. A probe card (3002) for testing multiple integrated circuits (1001) on a semiconductor wafer (1000), the probe card (3002) comprising: - Multiple pins (3002a) adapted to provide temporary electrical connections to pads (2000) of multiple integrated circuits (1001) under test on a semiconductor wafer (1000); - At least one buffer circuit (4001a) is arranged to share the same power supply channel (SC1) of the test equipment (3004) with the power supply input (VCC) of the group consisting of at least four integrated circuits (1001a-d) in the plurality of integrated circuits under test (1001). - At least one group (4002) consisting of at least four multiplexer circuits (4002a-d), the at least four multiplexer circuits being arranged such that they share the same high-voltage channel (HVC1) of the test device (3004) with the first input of each of the four multiplexer circuits (4002a-d), the different data input / output electronic channels (DC1-4) of the test device (3004) being electrically in communication with the second input of each of the four multiplexer circuits (4002a-d), and the output of each of the four multiplexer circuits (4002a-d) being electrically in communication with the test input / output (SPT) of the integrated circuit (1001a-d) in the group consisting of the at least four integrated circuits (1001a-d) of the plurality of integrated circuits to be tested (1001).

2. The probe card (3002) as described in claim 1, wherein, Each multiplexer circuit in the group (4002) consisting of multiplexer circuits (4002a-d) is configured to simultaneously connect the high voltage channel (HVC1) of the test device (3004) to the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d) in the plurality of integrated circuits under test (1001) according to a first value of the control signal (CS1).

3. The probe card as described in any one of claims 1 and 2, wherein, Each multiplexer circuit in the group (4002) consisting of multiplexer circuits (4002a-d) is configured to sequentially connect the high voltage channel (HVC1) of the test device (3004) to the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d) in the plurality of integrated circuits to be tested (1001) according to the second value of the control signal (CS1).

4. The probe card (3002) as described in any one of claims 1 to 3, wherein, Each multiplexer circuit in the group (4002) consisting of multiplexer circuits (4002a-d) is configured to simultaneously connect the electronic channel (DC1-4) of the test device (3004) to the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d) in the plurality of integrated circuits to be tested (1001) according to the third value of the control signal (CS1).

5. The probe card (3002) as described in claim 2, wherein, The first value of the control signal (CS1) corresponds to performing a static fault test on these integrated circuits under test by applying a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

6. The probe card (3002) as described in claim 3, wherein, The second value of the control signal (CS1) corresponds to measuring and testing these integrated circuits under test with a voltage greater than a threshold, preferably greater than a threshold fixed at 4.5 V.

7. The probe card (3002) as described in claim 4, wherein, The third value of the control signal (CS1) corresponds to current measurement of these integrated circuits under test using a voltage less than a threshold, preferably less than a threshold fixed at 4.5 V.

8. The probe card (3002) as described in any one of claims 1 to 7, wherein, These buffer circuits (4001a, 4001b) and / or these multiplexer circuit groups (4002, 4003) are integrated into an interface card (3003) that is in electrical communication with the probe card (3002).

9. The probe card (3002) as described in any one of claims 1 to 8, wherein, The probe card is further adapted for electrical communication with test equipment (3004) for Class B and / or Class C integrated circuits (1001) conforming to ISO / IEC 7816-3:2006 and multiple Class A integrated circuits to be tested.

10. The probe card (3002) as described in any one of claims 1 to 9, wherein, The probe card is further adapted for electrical communication with test equipment (3004) configured to test semiconductor mass storage and / or random access memory architectures.

11. A system (3000) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), the system comprising a test device (3004) and a probe card (3002) as claimed in any one of claims 1 to 10.

12. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), the method comprising the steps of: - The power supply input (VCC) of the test equipment (3004) is shared with the power supply channel (SC1) of the group consisting of at least four integrated circuits (1001a-d) in the plurality of integrated circuits to be tested (1001). - Connect the same high voltage channel (HVC1) of the test device (3004) in parallel with the test input / output (SPT) of each of the group of at least four integrated circuits (1001a-d) in the plurality of integrated circuits to be tested (1001); - Apply a voltage greater than a threshold at the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d); - Verify the operation of each integrated circuit by analyzing the response signals of the corresponding test inputs / outputs (SPTs) of these integrated circuits (1001a-d).

13. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), the method comprising the steps of: - Connect the high voltage channel (HVC1) of the test device (3004) sequentially to the test input / output terminal (SPT) of each of the multiple integrated circuits to be tested (1001) in a group consisting of at least four integrated circuits (1001a-d); - A voltage greater than a threshold is sequentially applied at the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d); - The response of each integrated circuit is measured sequentially by analyzing the response signals of the corresponding test inputs / outputs (SPTs) of these integrated circuits (1001a-d).

14. A method for testing a plurality of integrated circuits (1001a-d) on a semiconductor wafer (1000), the method comprising the steps of: - Connect the data input / output electronic channels (DC1-4) of the test equipment (3004) in parallel with the test input / output terminals (SPT) of each of the multiple integrated circuits under test (1001) in a group consisting of at least four integrated circuits (1001a-d); - Send data frames in parallel to the test input / output (SPT) of each of the group consisting of at least four integrated circuits (1001a-d). - Response data frames from each integrated circuit are received in parallel by analyzing the response signals via the corresponding test inputs / outputs (SPTs) of these integrated circuits (1001a-d).

15. A computer program comprising instructions that, when executed by a computer, cause the computer to use the system of claim 11 to implement the method of any one of claims 12 to 14.

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