Address-based hardware listening logic with configurable listening space settings for hardware assistance

Abstract

Systems and techniques for listening for input / output (I / O) events in a computing system are described. An example technique includes obtaining a configuration including a plurality of listening space profiles, each listening space profile indicating a respective range of memory addresses mapped to a respective completion queue. The technique also includes monitoring input / output (I / O) traffic exchanged on a communication interface between an I / O adapter and a processor in the computing system based on the configuration. The technique further includes performing one or more actions to assist in processing of the I / O traffic based in part on the monitoring.

Description

Background Technology

[0001] This invention relates to computing systems, and more particularly, to a hardware-based controller for listening to input / output (I / O) events in a computing system.

[0002] Much of the work in a computing system involves data input, data output, or a combination of both. In such a system, as an illustrative, non-limiting example, the operating system typically handles I / O management for various I / O devices, such as disks, tapes, printers, network interface cards (or connections), and audio I / O. I / O management can include programmed I / O methods, interrupt-based I / O methods, or direct memory access (DMA) I / O methods.

[0003] In programmed I / O methods, the inputs of each I / O device connected to the computing system are periodically checked (e.g., polled). Once the computing system receives an input signal from the device, it can execute the request until it no longer receives input signals. Interrupt-based I / O methods typically allow the processor (e.g., the central processing unit (CPU)) to continue processing other tasks and be interrupted when an input signal is received from an I / O device. DMA I / O methods typically allow the transfer of blocks of data between memory and I / O devices without involving the processor.

[0004] As modern computing systems evolve to support an ever-increasing number of I / O devices, providing effective I / O management using conventional technologies becomes increasingly difficult. Summary of the Invention

[0005] One embodiment described herein is a computer-implemented method. This computer-implemented method includes obtaining a configuration comprising multiple listener space profiles, each listener space profile indicating a corresponding memory address range mapped to a corresponding completion queue. The computer-implemented method also includes monitoring input / output (I / O) traffic exchanged between communication interfaces between I / O adapters and processors across a computing system based on the configuration. The computer-implemented method further includes performing one or more actions, partially based on the monitoring, to assist in the processing of I / O traffic.

[0006] Another embodiment described herein is a computer-readable storage medium. This computer-readable storage medium has computer-readable program code embodied therein. This computer-readable program code is executable by one or more computer processors to perform operations. The operations include obtaining a configuration comprising a plurality of listener space profiles, each listener space profile indicating a corresponding memory address range mapped to a corresponding completion queue. The operations also include monitoring input / output (I / O) traffic exchanged on a communication interface between an I / O adapter and a processor in a computing system based on the configuration. The operations also include performing one or more actions, partially based on the monitoring, to assist in the processing of I / O traffic.

[0007] Another embodiment described herein is a computing system. The computing system includes one or more memories, input / output (I / O) adapters, and one or more processors coupled to the one or more memories and I / O adapters. The one or more processors are configured individually or collectively to perform operations. The operations include obtaining a configuration comprising multiple listener space profiles, each listener space profile indicating a corresponding memory address range mapped to a corresponding completion queue. The operations also include monitoring input / output (I / O) traffic exchanged across the communication interface between the I / O adapters and processors based on the configuration. The operations also include performing one or more actions, partly based on the monitoring, to assist in the processing of I / O traffic. Attached Figure Description

[0008] Figure 1 This is a block diagram of a computing environment according to one embodiment.

[0009] Figure 2 This is a diagram of an example computing system according to one embodiment.

[0010] Figure 3 This further illustrates an embodiment. Figure 2 A diagram depicting some components of a computing system.

[0011] Figure 4 This is a flowchart of a method for listening to input / output (I / O) events in a computing system.

[0012] Figure 5 This is a flowchart of another method for monitoring input / output (I / O) events in a computing system. Detailed Implementation

[0013] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to techniques found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0014] In the following text, reference is made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements, whether or not associated with different embodiments, is contemplated as implementing and practicing the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a given embodiment achieves a particular advantage does not limit the scope of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, references to “the invention” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0015] Various aspects of the present invention may take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which are generally referred to herein as “circuit,” “module,” or “system.”

[0016] Various aspects of this disclosure are described by way of text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0017] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any set of one or more storage media (also referred to as “media”) collectively included in a set of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions used by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (e.g., punched cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. As used herein, the term computer-readable storage medium should not be construed as storage in the form of transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will understand, data typically moves at certain incidental points in time during the normal operation of the storage device (such as during access, defragmentation, or garbage collection), but this does not render the storage device transient, as the data is not transient at the time of storage.

[0018] The computing environment 100 includes examples of environments for executing at least some computer code relating to the execution of the methods of the present invention, such as block 160, which includes listening logic 165 configured to snoop on I / O events occurring within the computing system. In addition to block 160, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including processing circuitry 120 and a cache 121), a communication infrastructure 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 160, as described above), a peripheral device set 114 (including a user interface (UI) device set 123, a storage device 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, host physical machine set 142, virtual machine set 143, and container set 144.

[0019] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases (such as remote database 130). As is well understood in the field of computer technology, and depending on the technology, the execution of computer-implemented methods may be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 100, the detailed discussion focuses on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 may reside in the cloud, even if it is in... Figure 1 The computer 101 is not shown in the cloud. On the other hand, except to any extent that can be definitively indicated, the computer 101 is not required to be in the cloud.

[0020] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package(s) and is typically used for data or code that should be readily accessible by the threads or cores running on processor set 110. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache used in the processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to work with qubits and perform quantum computing.

[0021] Computer-readable program instructions are typically loaded onto computer 101 to cause the processor set 110 of computer 101 to perform a series of operational steps to implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or descriptive descriptions of the computer-implemented method included in this document (collectively, the “method of the invention”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the method of the invention. In computing environment 100, at least some of the instructions for performing the method of the invention may be stored in persistent memory 113 in block 160.

[0022] Communication structure 111 is a signal transmission path that allows various components of computer 101 to communicate with each other. Typically, this structure consists of switches and conductive paths, such as switches and conductive paths forming buses, bridges, physical input / output ports, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0023] Volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, but this is not necessary unless explicitly stated otherwise. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 101.

[0024] The persistent storage device 113 is any form of non-volatile storage device for a computer, now known or to be developed in the future. The non-volatility of this storage device means that the stored data is maintained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage device 113. The persistent storage device 113 may be a read-only memory (ROM), but typically, at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some common forms of persistent storage include hard disks and solid-state storage devices. The operating system 122 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface type operating systems employing a kernel. The code included in box 160 generally includes at least some of the computer code involved in performing the methods of the present invention.

[0025] Peripheral device set 114 includes a collection of peripheral devices for computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, near field communication (NFC) connectivity, connections via cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., secure digital (SD) cards), connections via local area communication networks, and even connections via wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as displays, speakers, microphones, wearable devices (e.g., goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 124 is an external storage device (such as an external hard drive) or a pluggable storage device (such as an SD card). Storage device 124 may be persistent and / or volatile. In some embodiments, storage device 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments requiring computer 101 to have substantial storage (e.g., where computer 101 locally stores and manages a large database), this storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in IoT applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0026] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or unpacking data for transmission over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0027] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology now known or to be developed in the future for transmitting computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0028] End User Equipment (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and can take any of the forms discussed above in connection with computer 101. EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, assuming computer 101 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 can be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0029] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 can be controlled and used by the same entity operating computer 101. Remote server 104 represents (multiple) machines that collect and store helpful and useful data for use by other computers, such as computer 101. For example, if computer 101 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0030] Public cloud 105 is any computer system available to multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without the need for direct, active management by users. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and / or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers constituting host physical assembly 142, which is a universe of physical computers in and / or available to public cloud 105. Virtual computing environments typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after the VCEs are instantiated. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages the active instantiation of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allow public cloud 105 to communicate via WAN 102.

[0031] Now, we will provide some further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two familiar types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically appear as real computers. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this is a feature known as containerization.

[0032] Private cloud 106 is similar to public cloud 105, except that computing resources are only available for use by a single enterprise. While private cloud 106 is depicted communicating with WAN 102, in other embodiments, private cloud may be completely disconnected from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardization or proprietary technology that enables orchestration, management, and / or data / application portability across the multiple component clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.

[0033] Note that, in order to clearly point out the novel features of the invention, the following discussion omits or only briefly describes the conventional features of data processing systems that are obvious to those skilled in the art. It is assumed that those skilled in the art are familiar with the general architecture of processors, and particularly with processors that operate in an ordered dispatch, unordered execution, or ordered completion manner. It can be noted that numbered elements are numbered according to the accompanying drawings in which the element is introduced, and are referred to by that number in subsequent drawings. Furthermore, as used herein, the hyphenated form of the reference numerals refers to a specific instance of an element, while the non-hyphenated form refers to a set of elements. Thus, for example, device "12-1" refers to an instance of a class of devices that can be collectively referred to as device "12", and any one of them can be collectively referred to as device "12".

[0034] Figure 2 This is a diagram of an example computing system 200 according to one embodiment. The features described with respect to computing system 200 can be used in conjunction with other embodiments described herein. For example, computing system 200 can... Figure 1 The computing environment 100 described herein is implemented within it. For example, computing system 200 can represent... Figure 1 An example implementation of computer 101 is shown. In some embodiments, computing system 200 may be implemented as a mainframe computer. However, other implementations of computing system 200 are also contemplated.

[0035] The computing system 200 includes, but is not limited to, a central processing complex (CPC) 205 communicatively coupled to an I / O subsystem 210, which is communicatively coupled to one or more I / O devices 270 1-K. The CPC 205 includes a central processing unit (CPU) 220 and memory 230, which may include volatile memory, persistent memory, or a combination thereof. The CPU 220 includes a plurality of processor cores 225 1-N having any suitable implementation.

[0036] CPU 220 also includes an I / O processor 235 communicatively coupled to processor core 225 1-N. In some embodiments, CPU 220 also includes a Peripheral Component Interconnect Fast (PCIe) Bridge Unit (PBU) 240 communicatively coupled to I / O processor 235 and I / O subsystem 210. I / O processor 235 includes a listener logic controller 265 configured to monitor traffic exchanged between CPC 205 and I / O subsystem 210, listen for certain I / O events occurring within the traffic, and process the I / O events. Listener logic controller 265 may include hardware, software, or a combination thereof. In some embodiments, listener logic controller 265 is configured to implement listener logic 165, which is described in more detail herein. Note that while various components are described as being included within CPU 220, alternative embodiments may have different arrangements of components within CPC 205. For example, in some embodiments, I / O processor 235 may be implemented separately from the CPU.

[0037] I / O subsystem 210 includes a switch 245, which is communicatively coupled to PBU 240 via communication link 215 and communicatively coupled to I / O adapter 255 of I / O subsystem 210 via communication link 250. Communication links 215 and 250 are implemented using one or more conductors of any suitable form (e.g., conductive traces or wires). In a non-limiting example, communication links 215 and 250 each include an 8-channel PCIe connection, with each channel including two corresponding conductors. However, note that other configurations of communication links 215 and 250 are also contemplated, which may include the use of different protocols. I / O adapter 255 connects computing system 200 to one or more I / O devices 270. As an illustrative, non-limiting example, examples of I / O devices 270 may include network interface cards (NICs) (also called network interface cards), storage devices, and printers. In some embodiments, one or more of the I / O adapters 255 may use any suitable technology such as Ethernet to connect the computing system to an external network (not shown) (e.g., a storage area network (SAN) with one or more storage devices).

[0038] Computing system 200 (more specifically, I / O processor 235) defines multiple channels 280 (or communication paths) between CPC 205 and I / O devices 270. Each channel 280 is assigned a different channel path identifier (CHPID), which may represent a physical channel port location (PCHID), a logical channel subsystem, or a combination thereof. In some embodiments, the channels 280 established by I / O processor 235 are virtualized, allowing any instance of an operating system executing on one of the processor cores 225 1-N to access any channel.

[0039] The architecture of computing system 200, and more specifically, the use of I / O processor 235 within CPC 205, offers numerous benefits. Generally, computing system 200 provides more efficient operation reflecting updates to the architecture of CPC 205. For example, providing I / O processor 235 within CPC 205 shortens the path length from processor core 225 I-N to I / O functions, thereby supporting greater throughput and responsiveness. I / O processor 235 can be reconfigured and is therefore adaptable to new types of communication links used by I / O subsystem 210. Furthermore, the use of I / O processor 235 allows for the integration of new types of I / O adapters 255 into computing system 200 without the need to develop custom interface hardware in I / O subsystem 210 (e.g., using a single ASIC and I / O card). In this way, the overall cost and / or power consumption of computing system 200 can be reduced.

[0040] Figure 3 Further illustration is shown according to one embodiment Figure 2 The figure depicts certain components of the computing system 200. As shown, the I / O processor 235 of the computing system 200 includes, but is not limited to, one or more processing elements 310 and a listener logic controller 265. One or more processing elements 310 typically provide connectivity to channel 280 and implement protocols on channel 280. Processing element 310. Processing element 310 can have any suitable implementation. In a non-limiting example, processing element 310 implements a RISC-V instruction set architecture, which allows processing element 310 to be dynamically updated to support new features and / or functions, and to provide functionality beyond that discussed above.

[0041] The listening logic controller 265 includes, but is not limited to, listening logic 165 and one or more completion queues 320. Each completion queue 320 typically stores events indicating the completion of a data transfer operation. For example, a completion queue 320 may include one or more completion queue entries 330, wherein each completion queue entry 330 includes information about the completed work request (e.g., status, size, etc.).

[0042] Typically, a completion event is generated when a send or receive adapter operation completes. In a conventional system, the network adapter places this event in completion queue entry 330 on completion queue 320, and the network device driver (e.g., operating system 122) must typically monitor and process completion queue entries to handle the completion event. However, in some instances, monitoring and processing completion queue entries can lead to cache thrashing because the network device driver must interact with the network adapter to determine when to write to the completion queue entry and read memory areas written by the network adapter to process the completion queue entry.

[0043] To address this issue, in some embodiments, the listening logic controller 265 includes listening logic 165, which is configured to listen for certain I / O events occurring in the computing system. Specifically, listening logic 165 can detect in hardware when a network adapter (e.g., I / O adapter 255) writes an entry to completion queue 320. Upon detecting that an entry has been written to completion queue 320, listening logic 165 can send an indication to the network device driver (e.g., operating system 122) that a new completion queue entry has been written. In some embodiments, the network device driver can receive the indication before the I / O adapter completes the completion queue entry.

[0044] like Figure 3 As shown, in some embodiments, the snoop logic 165 is configured with one or more snoop space profiles 340. Each snoop space profile 340 is associated with a defined memory region (or memory address range) that maps to a corresponding completion queue 320. For example, each snoop space profile 340 may include multiple bits defining a corresponding memory range for a completion event. In one exemplary embodiment, each snoop space profile 340 includes a 15-bit space offset and a 17-bit size. In some aspects, a first set of snoop space profiles 340 may be used to send adapter operations (e.g., data transfer from I / O device 270), and a second set of snoop space profiles 340 may be used to receive adapter operations (e.g., data transfer to I / O device 270).

[0045] Once the listening logic 165 is configured with the listening space profile 340, it can monitor each write from the I / O adapter 255 to the memory region indicated by the listening space profile 340. As part of the monitoring, the listening logic 165 can compare the incoming memory address with each listening space profile 340 to determine whether the address is within the memory range defined by the listening space profile 340. If the address does not fall within the memory range, the listening logic 165 can refrain the execution of auxiliary functions (e.g., write completion queue entries can be performed without assistance).

[0046] On the other hand, if the address does fall within the memory range, the listening logic 165 can determine the type of auxiliary function associated with the memory range. As an illustrative, non-limiting example, such an auxiliary function type could include sending a notification including information about a completion queue entry, triggering a counter, invoking a timer, and using an arrival algorithm. In some embodiments, the listening logic 165 can determine the type of auxiliary function based on a completion queue entry. For example, a completion queue entry could include elements indicating the type of auxiliary function.

[0047] When determining the type of auxiliary function, the listening logic 165 can trigger firmware (e.g., I / O processor 235) in the computing system to execute the auxiliary function. In this way, the listening logic 165 can improve the performance of the computing system by enabling firmware to avoid polling memory locations associated with completion queue entries and by enabling I / O adapter 255 to avoid write interrupts.

[0048] Figure 4 This is a flowchart of a method 400 for listening to I / O events in a computing system. Method 400 may be executed by a listening logic controller (e.g., listening logic controller 265).

[0049] Method 400 enters at block 402, where the listening logic controller obtains a configuration of a set of listening space profiles (e.g., listening space profile 340). Each listening space profile indicates a corresponding memory range mapped to a corresponding completion queue. At block 404, the listening logic controller monitors traffic exchanged on a communication interface (e.g., communication interface 215) between an I / O adapter (e.g., I / O adapter 255) and a processor (e.g., CPU 220).

[0050] Figure 5 This is a flowchart of a method 500 for listening to I / O events in a computing system. Method 500 may be executed by a listening logic controller (e.g., listening logic controller 265). In some embodiments, method 500 may be used to implement... Figure 4 The method described in box 404 is 400.

[0051] For each incoming write address, the listener logic controller may perform the operation in box 504. At box 504, the listener logic controller determines whether the write address maps to one of a plurality of listener space profiles (e.g., listener space profile 340). If not, method 500 continues to evaluate the next incoming write address (e.g., at box 504). Alternatively, if the write address maps to a particular listener space profile, then method 500 proceeds to box 506.

[0052] At box 506, the listening logic controller sends an indication that a completion queue entry associated with the listening space profile has been written. At box 508, the listening logic controller determines the type of accessibility function based on the completion queue entry. At box 510, the listening logic controller sends a trigger (e.g., to firmware) to initiate the accessibility function.

[0053] As used herein, “processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or more operations, or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, the execution of one or more operations may be divided among different processors, although a single processor may perform multiple operations, and multiple processors may collectively perform a single operation. Similarly, “memory,” “at least one memory,” or “one or more memory” generally refers to a single memory configured to store data and / or instructions, or multiple memories configured to collectively store data and / or instructions.

[0054] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A computer-implemented method, comprising: Obtain a configuration including multiple listener space profiles, each listener space profile indicating the corresponding memory address range mapped to the corresponding completion queue; Based on the configuration, monitor the input / output (I / O) traffic exchanged between the communication interfaces between I / O adapters and processors across the computing system; and One or more actions may be performed, in part, based on the monitoring, to assist in the processing of the I / O traffic.

2. The computer-implemented method according to claim 1, wherein, Monitoring the I / O service includes determining whether the incoming address of the I / O service is within the corresponding memory address range associated with a listener space profile in the listener space profile.

3. The computer-implemented method according to claim 2, wherein, The determination is that the incoming address is within the corresponding memory address range associated with a listener space profile in the listener space profile.

4. The computer-implemented method according to claim 3, wherein, Performing the one or more actions includes sending an indication that a completion queue entry associated with the memory address range has been written.

5. The computer-implemented method according to claim 3, further comprising: The one or more actions are determined based on the completion queue entries associated with the memory address range within which the incoming address is located.

6. The computer-implemented method according to claim 5, wherein, The one or more actions include triggering a count, invoking a timer, or initiating an arrival algorithm.

7. The computer-implemented method according to claim 2, wherein, The determination is that the incoming address is outside the corresponding memory address range of each of the listening space profiles.

8. The computer-implemented method according to claim 7, wherein, Performing the one or more actions includes: in response to the determination, writing a completion queue entry to the incoming address.

9. A computer-readable storage medium having computer-readable program code embodied therein, the computer-readable program code being executable by one or more computer processors to perform operations including: Obtain a configuration including multiple listener space profiles, each listener space profile indicating the corresponding memory address range mapped to the corresponding completion queue; Based on the configuration, monitor the input / output (I / O) traffic exchanged between the communication interfaces between I / O adapters and processors across the computing system; and One or more actions may be performed, in part, based on the monitoring, to assist in the processing of the I / O traffic.

10. The computer-readable storage medium according to claim 9, wherein, Monitoring the I / O service includes determining whether the incoming address of the I / O service is within the corresponding memory address range associated with a listener space profile in the listener space profile.

11. The computer-readable storage medium according to claim 10, wherein, The determination is that the incoming address is within the corresponding memory address range associated with a listener space profile in the listener space profile.

12. The computer-readable storage medium according to claim 11, wherein, Performing the one or more actions includes sending an indication that a completion queue entry associated with the memory address range has been written.

13. The computer-readable storage medium of claim 11, further comprising: The one or more actions are determined based on the completion queue entries associated with the memory address range within which the incoming address is located.

14. The computer-readable storage medium according to claim 13, wherein, The one or more actions include triggering a count, invoking a timer, or initiating an arrival algorithm.

15. The computer-readable storage medium according to claim 10, wherein, The determination is that the incoming address is outside the corresponding memory address range of each of the listening space profiles.

16. The computer-readable storage medium according to claim 15, wherein, Performing the one or more actions includes: in response to the determination, writing a completion queue entry to the incoming address.

17. A computing system, comprising: One or more memory units; Input / output (I / O) adapters; One or more processors coupled to one or more memories and the I / O adapter, the one or more processors being individually or collectively configured to perform operations including: Obtain a configuration including multiple listener space profiles, each listener space profile indicating the corresponding memory address range mapped to the corresponding completion queue; Based on the configuration, monitor input / output (I / O) traffic exchanged across the communication interface between the I / O adapter and the processor; and One or more actions may be performed, in part, based on the monitoring, to assist in the processing of the I / O traffic.

18. The computing system according to claim 17, wherein, Monitoring the I / O service includes determining whether the incoming address of the I / O service is within the corresponding memory address range associated with a listener space profile in the listener space profile.

19. The computing system according to claim 18, wherein, The determination is that the incoming address is within the corresponding memory address range associated with a listener space profile in the listener space profile.

20. The computing system according to claim 19, wherein, Performing the one or more actions includes sending an indication that a completion queue entry associated with the memory address range has been written.

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