Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which the amount of lithium (Li) present in an external electrode is set to an appropriate amount, and deterioration in moisture resistance can be suppressed. A multilayer ceramic capacitor according to the present invention is provided with: a multilayer body including a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, the first surface and the second surface are opposite to each other in the stacking direction, the third surface and the fourth surface are opposite to each other in a first direction orthogonal to the stacking direction, and the fifth surface and the sixth surface are opposite to each other in a second direction orthogonal to the stacking direction and the first direction. A first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate. The laminated body includes an inner layer portion and two outer layer portions disposed so as to sandwich the inner layer portion in the lamination direction, and the inner layer portion includes: a first internal electrode having one end exposed on the third surface; a second internal electrode, one end of which is exposed on the fourth surface; and an inner dielectric layer in which the first internal electrode and the second internal electrode are disposed, the inner dielectric layer containing at least Ca, Sr, or Zr as the main component and Li. In at least one of a region of the first external electrode within 15 [mu] m in the first direction from an interface between the laminate and the first external electrode, and a region of the second external electrode within 15 [mu] m in the first direction from an interface between the laminate and the second external electrode, a region of the first external electrode within 15 [mu] m in the first direction. The content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] Among multilayer ceramic capacitors used in electronic devices, multilayer ceramic capacitors with high dielectric constant systems are known, as well as multilayer ceramic capacitors for temperature compensation where the change in electrostatic capacitance is linear with respect to temperature change, as described in Patent Document 1.

[0003] For example, the multilayer ceramic capacitor described in Patent Document 2 uses copper or a copper-containing alloy as the internal electrode and calcium zirconate as the main component in the dielectric layer. However, if copper is used as the internal electrode, its low melting point sometimes causes problems such as over-sintering of the internal electrode during the dielectric sintering process, a decrease in the effective area of ​​the internal electrode, and a reduction in electrostatic capacitance. In Patent Document 2, in order to lower the dielectric sintering temperature to be as close as possible to the temperature of copper, a sintering aid that forms a liquid phase during the sintering of lithium, silicon, etc., is used as a sintering aid.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-24542

[0007] Patent Document 2: Japanese Patent Application Publication No. 2009-7209

[0008] Patent Document 3: Japanese Patent Application Publication No. 2019-62177 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] However, as also described in Patent Document 3, lithium is volatile and has already evaporated during the process of sintering the dielectric.

[0011] Furthermore, and not limited to this, when copper is used in the external electrode, lithium in the dielectric may sometimes volatilize and disperse into the external electrode during the sintering process. If lithium disperses into the external electrode, it acts as a sintering aid, which may cause the external electrode to become over-densified, resulting in blister formation, etc. In addition, the moisture resistance of multilayer ceramic capacitors may sometimes deteriorate.

[0012] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that suppresses the deterioration of moisture resistance by setting an appropriate amount of lithium (Li) present in the external electrode.

[0013] Technical solutions for solving the problem

[0014] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in a first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode disposed on the third surface of the multilayer body; and a second external electrode disposed on the fourth surface of the multilayer body. The multilayer body includes an inner layer portion and two outer layers portion disposed to sandwich the inner layer portion in the stacking direction. The inner layer portion has: a first internal electrode, one end of which is on the third surface. The first internal electrode is exposed on the upper surface; the second internal electrode is exposed at one end on the fourth surface; and the inner dielectric layer is disposed with the first internal electrode and the second internal electrode. The inner dielectric layer contains at least Ca, Sr or Zr as the main components and Li. In at least one of the regions of the first external electrode within 15 μm square in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 15 μm square in the first direction from the interface between the laminate and the second external electrode, the content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

[0015] According to the multilayer ceramic capacitor of the present invention, the inner dielectric layer contains at least Ca, Sr or Zr as the main components and Li. In a region within 15 μm square in a first direction from the interface between the multilayer and the first outer electrode, the content of Li in the first outer electrode is less than the content of Li in the inner dielectric layer, thereby suppressing the decrease in moisture resistance to the multilayer.

[0016] Invention Effects

[0017] According to the present invention, it is possible to provide a multilayer ceramic capacitor that suppresses the deterioration of moisture resistance by setting an appropriate amount of lithium (Li) present in the external electrode.

[0018] The above-mentioned objects, other objects, features, and advantages of the present invention will become more apparent from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0020] Figure 2 yes Figure 1 A sectional view at line II-II.

[0021] Figure 3 yes Figure 1A cross-sectional view at line III-III.

[0022] Figure 4 yes Figure 1 A cross-sectional view at line IV-IV.

[0023] Figure 5 Is Figure 3 The sectional view shown is a sectional view of a modified example of the first embodiment.

[0024] Figure 6 This is a perspective view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention.

[0025] Figure 7 yes Figure 6 A cross-sectional view at line VII-VII.

[0026] Figure 8 yes Figure 6 A cross-sectional view at line VIII-VIII.

[0027] Figure 9 yes Figure 6 A cross-sectional view at line IX-IX.

[0028] Figure 10 Is Figure 7 The cross-sectional view shown is a modified example of the second embodiment.

[0029] Figure 11 This is a perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention.

[0030] Figure 12 yes Figure 11 A cross-sectional view at line XII-XII.

[0031] Figure 13 yes Figure 11 A cross-sectional view at line XIII-XIII.

[0032] Figure 14 yes Figure 11 A cross-sectional view at line XIV-XIV. Detailed Implementation

[0033] 1. Multilayer ceramic capacitor

[0034] A. First Implementation

[0035] The first embodiment of the present invention relates to a multilayer ceramic capacitor.

[0036] Figure 1This is a perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 yes Figure 1 A sectional view at line II-II. Figure 3 yes Figure 1 A cross-sectional view at line III-III. Figure 4 yes Figure 1 A cross-sectional view at line IV-IV.

[0037] like Figures 1 to 3 As shown, the multilayer ceramic capacitor 10 includes a cuboid multilayer 12 and external electrodes 30 disposed at both ends of the multilayer 12.

[0038] (Layered structure)

[0039] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 20 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first surface 12a and a second surface 12b opposite each other in the stacking direction x, a third surface 12c and a fourth surface 12d opposite each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposite each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0040] Furthermore, it is preferable that the first surface 12a and the second surface 12b, or one of them, are flat. If they are flat, the stress experienced by the nozzle picking up the multilayer ceramic capacitor 10 can be dispersed on the flat surface. As a result, the strength of the multilayer ceramic capacitor can be improved during installation.

[0041] In addition, the surface of the laminate 12 can also be roughened.

[0042] The laminate 12 may also have rounded corners at the corners and edges.

[0043] Furthermore, the portion where two of the following surfaces intersect (12a, 12b, 12c, 12d, 12e, and 12f) are called an edge portion, and the portion where three of the following surfaces intersect is called a corner portion. The edge portions and corner portions are preferably rounded and have a radius (R). By giving the edge portions and corner portions a radius (R), cracking can be prevented. When the edge portions and corner portions have a radius (R), the main surfaces of the surfaces other than the edge portions and corner portions can also be flat.

[0044] like Figure 2 as well as Figure 3As shown, the laminate 12 has an inner layer 16 in the lamination direction x that connects the first surface 12a and the second surface 12b to each other, in which dielectric layers 14 and internal electrodes 20 are alternately stacked; a first surface outer layer 18a formed by a plurality of dielectric layers 14 located between the first surface 12a and the internal electrode 20 located on the side closest to the first surface 12a; and a second surface outer layer 18b formed by a plurality of dielectric layers 14 located between the second surface 12b and the internal electrode 20 located on the side closest to the second surface 12b.

[0045] (Inner layer)

[0046] The inner layer 16 is composed of a plurality of inner dielectric layers 14a among a plurality of dielectric layers 14. That is, the inner layer 16 is configured such that a plurality of internal electrodes 20 are opposed to each other with respect to the inner dielectric layers 14a.

[0047] The inner dielectric layer 14a contains at least Ca, Sr, or Zr as the main components, and Li. For example, it may contain CaZrO3 or SrZrO3 as dielectric components, and Li as a sintering aid. In addition, it may also contain Mn, Na, Ti, etc.

[0048] The main components of the inner dielectric layer 14a can be observed as follows.

[0049] That is, the cross-section of the multilayer ceramic capacitor 10 is exposed when it is ground in the second direction z up to half of the W dimension in the second direction z. Then, the exposed cross-section is observed using TOF.SIM (manufactured by ION-TOF Corporation) under conditions of 30 μm square.

[0050] like Figure 2 as well as Figure 3 As shown, the internal electrode 20 has a first internal electrode 20a and a second internal electrode 20b. The first internal electrode 20a and the second internal electrode 20b are alternately stacked with an inner dielectric layer 14a in between.

[0051] The first internal electrode 20a is disposed on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode 20a has a first opposing electrode portion 22a opposite to the second internal electrode 20b, and a first lead-out electrode portion 24a located at one end of the first internal electrode 20a and extending from the first opposing electrode portion 22a to the third surface 12c of the laminate 12. The end of the first lead-out electrode portion 24a is led out to the surface of the third surface 12c and exposed from the laminate 12. That is, the end of the first lead-out electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. Specifically, the end of the first internal electrode 20a is slightly recessed from the fourth surface 12d.

[0052] The shape of the first opposing electrode portion 22a of the first internal electrode 20a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in a certain direction.

[0053] The shape of the first lead-out electrode portion 24a of the first internal electrode 20a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in a certain direction.

[0054] The width of the first opposing electrode portion 22a of the first internal electrode 20a and the width of the first lead-out electrode portion 24a of the first internal electrode 20a can be formed with the same width, or one of them can be formed with a narrower width.

[0055] The second internal electrode 20b is disposed on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode 20b has a second opposing electrode portion 22b opposite to the first internal electrode 20a, and a second lead-out electrode portion 24b located at one end of the second internal electrode 20b and extending from the second opposing electrode portion 22b to the fourth surface 12d of the laminate 12. The end of the second lead-out electrode portion 24b is led out to the surface of the fourth surface 12d and exposed from the laminate 12. That is, the end of the first lead-out electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the third surface 12c, the fifth surface 12e, and the sixth surface 12f. Specifically, the end of the second internal electrode 20b is slightly recessed from the third surface 12c.

[0056] The shape of the second opposing electrode portion 22b of the second internal electrode 20b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in a certain direction.

[0057] The shape of the second lead-out electrode portion 24b of the second internal electrode 20b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in a certain direction.

[0058] The width of the second opposing electrode portion 22b of the second internal electrode 20b and the width of the second lead-out electrode portion 24b of the second internal electrode 20b can be formed with the same width, or one of them can be formed with a narrower width.

[0059] The laminate 12 includes a side portion 26a formed between one end of the laminate 12 in the second direction z of the first opposing electrode portion 22a and the second opposing electrode portion 22b and the fifth surface 12e, and a side portion 26b formed between the other end of the laminate 12 in the second direction z of the first opposing electrode portion 22a and the second opposing electrode portion 22b and the sixth surface 12f. Furthermore, the laminate 12 includes an end portion 27a formed between the end of the first inner electrode 20a opposite to the first lead-out electrode portion 24a and the fourth surface 12d, and an end portion 27b formed between the end of the second inner electrode 20b opposite to the second lead-out electrode portion 24b and the third surface 12c.

[0060] The internal electrode 20 is preferably made of Cu as the main component. This reduces the resistance of the internal electrode 20 and allows it to be formed using inexpensive materials.

[0061] The main components of the internal electrode 20 can be observed as follows.

[0062] That is, the cross-section of the multilayer ceramic capacitor 10 is exposed when it is ground in the second direction z up to half of the W dimension in the second direction z. Then, the exposed cross-section is observed using TOF.SIM (manufactured by ION-TOF Corporation) under conditions of 30 μm square.

[0063] The thickness of the internal electrode 20 is preferably 0.8 μm or more and 3.5 μm or less. In addition, the total number of the first internal electrode 20a and the second internal electrode 20b is preferably 2 or more and 30 or less.

[0064] (First side outer layer, second side outer layer)

[0065] The first surface outer layer 18a is located on the first surface 12a side of the laminate 12, and is an assembly of multiple dielectric layers 14, i.e. multiple outer dielectric layers 14b, located between the first surface 12a and the inner electrode 20 closest to the first surface 12a.

[0066] The second-side outer layer 18b is located on the second surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14, i.e. multiple outer dielectric layers 14b, located between the second surface 12b and the inner electrode 20 closest to the second surface 12b.

[0067] The area sandwiched between the first outer layer 18a and the second outer layer 18b is the inner layer 16.

[0068] The first-side outer layer 18a and the second-side outer layer 18b are each formed of an insulating material. When the first-side outer layer 18a and the second-side outer layer 18b are formed of the same type of dielectric material as the inner dielectric layer 14, each outer layer 18a, 18b can be composed of multiple outer dielectric layers 14b or a single outer dielectric layer 14b. Alternatively, the outer dielectric layer 14b and the inner dielectric layer 14a can be formed with different compositions. For example, the material of the inner dielectric layer 14a can be a material with a higher dielectric constant than that of the outer dielectric layer 14b, while the material of the outer dielectric layer 14b can be a material with good moisture resistance, weather resistance, or strength resistance.

[0069] The dimensions of the laminate 12 are not particularly limited.

[0070] (External electrode)

[0071] like Figures 1 to 3 As shown, external electrodes 30 are disposed on the third surface 12c side and the fourth surface 12d side of the laminate 12.

[0072] The external electrode 30 includes a base electrode layer 32 comprising a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0073] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0074] The first external electrode 30a is connected to the first internal electrode 20a and is disposed at least on the surface of the third surface 12c. Furthermore, the first external electrode 30a extends from the third surface 12c of the laminate 12 and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 20a.

[0075] The second external electrode 30b is connected to the second internal electrode 20b and is disposed at least on the surface of the fourth surface 12d. Furthermore, the second external electrode 30b extends from the fourth surface 12d of the laminate 12 and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode 20b.

[0076] Within the laminate 12, the first opposing electrode portion 22a of the first internal electrode 20a and the second opposing electrode portion 22b of the second internal electrode 20b are opposed to each other across the dielectric layer 14, thereby forming an electrostatic capacitance. Therefore, an electrostatic capacitance can be obtained between the first external electrode 30a connected to the first internal electrode 20a and the second external electrode 30b connected to the second internal electrode 20b, exhibiting the characteristics of a capacitor.

[0077] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0078] The first base electrode layer 32a is connected to the first internal electrode 20a and disposed on the surface of the third surface 12c. Furthermore, the first base electrode layer 32a extends from the third surface 12c and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 20a.

[0079] The second base electrode layer 32b is connected to the second internal electrode 20b and disposed on the surface of the fourth surface 12d. Furthermore, the second base electrode layer 32b extends from the fourth surface 12d and is also disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode 20b.

[0080] The substrate electrode layer 32 uses Cu as its main component. In addition to Cu, the substrate electrode layer 32 also contains glass. By using Cu, which has a low resistivity, as the main component, the substrate electrode layer 32 can reduce the ESR of the multilayer ceramic capacitor 10. Furthermore, by including glass, the sinterability of the substrate electrode layer 32 can be improved.

[0081] The D50 of the Cu particles constituting the substrate electrode layer 32 is preferably 0.3 μm or more and 0.6 μm or less. Furthermore, the content of the glass component in the substrate electrode layer 32 is preferably 21 vol% or more and 25 vol% or less. This suppresses the diffusion of Li into the substrate electrode layer 32 during the subsequent formation process, and suppresses the Li content in the substrate electrode layer 32.

[0082] The thickness of the first direction y, which connects the third surface 12c and the fourth surface 12d, at the center of the stacking direction x of the first base electrode layer 32a located on the third surface 12c, is preferably 19 μm or more and 24 μm or less.

[0083] The thickness of the first direction y, which connects the third surface 12c and the fourth surface 12d, at the center of the stacking direction x of the second base electrode layer 32b located on the fourth surface 12d, is preferably 19 μm or more and 24 μm or less.

[0084] In a cross-section of the multilayer ceramic capacitor 10 ground in the second direction z up to half the W dimension in the second direction z, using a TOF-SIM (manufactured by ION-TOF), the base electrode layer 32 located at the center of the stacking direction x is observed with a 30 μm square image centered on the interface between the stack 12 and the base electrode layer 32. In a region within a 15 μm square from the interface between the stack 12 and the base electrode layer 32, the Li content in the base electrode layer 32 is less than the Li content in the inner dielectric layer 14a. Alternatively, the Li content in the base electrode layer 32 may decrease as it moves away from the interface between the stack 12 and the base electrode layer 32 in the first direction y. This reduces the Li content in the base electrode layer 32, thus suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 10. More preferably, in a region within 5 μm square from the interface between the laminate 12 and the base electrode layer 32, the Li content in the base electrode layer 32 is preferably less than the Li content in the inner dielectric layer 14a. Even more preferably, Li is absent in the base electrode layer 32. This further suppresses the decrease in moisture resistance of the laminated ceramic capacitor 10.

[0085] Specifically, in at least one of the regions of the first base electrode layer 32a within a 15 μm square in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, and the region of the second base electrode layer 32b within a 15 μm square in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, the content of Li in the first base electrode layer 32a and / or the second base electrode layer 32b is less than the content of Li in the inner dielectric layer 14a.

[0086] Furthermore, preferably, in at least one of the regions of the first base electrode layer 32a within 5 μm square in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, and in the region of the second base electrode layer 32b within 5 μm square in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, the content of Li in the first base electrode layer 32a and / or the second base electrode layer 32b is less than the content of Li in the inner dielectric layer 14a.

[0087] Furthermore, as the interface between the laminate 12 and the first base electrode layer 32a moves away from the first direction y, the content of Li in the first base electrode layer 32a decreases, and as the interface between the laminate 12 and the second base electrode layer 32b moves away from the first direction y, the content of Li in the second base electrode layer 32b also decreases.

[0088] As described above, the Li content in the substrate electrode layer 32 and the Li content in the inner dielectric layer 14a can be determined by TOF-SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The determination conditions based on this TOF-SIMS are as follows.

[0089] • Device Name: TOF.SIMS (Made by ION-TOF Company)

[0090] Primary ion: Bi +

[0091] Accelerating voltage: 25kV

[0092] Secondary ion polarity: Positive

[0093] • Number of scans: 32

[0094] • Pixel count: 256 pixels × 256 pixels

[0095] • Measurement area: 30μm × 30μm square

[0096] Furthermore, the Li content is derived by counting the number of pixels with a Li intensity of 1.0 or higher in a 256-pixel × 256-pixel array.

[0097] Furthermore, in a cross-section of the multilayer ceramic capacitor 10 ground in the second direction z up to half the W dimension in the second direction z, using TOF-SIMS (manufactured by ION-TOF), when observing the base electrode layer 32 located at the center of the stacking direction x with a 30 μm square image and taking the interface between the multilayer and the base electrode layer 32 as the center of the image, there is no Li in the region of the base electrode layer 32 located further away from the multilayer 12 in the first direction y than 15 μm from the interface between the multilayer and the base electrode layer 32. That is, the distance from the interface between the multilayer and the base electrode layer 32 to Li is 15 μm or less. Preferably, with respect to Li, the distance from the interface between the multilayer and the base electrode layer 32 to Li is preferably 5 μm or less. More preferably, Li is not contained in the base electrode layer 32. Therefore, reducing the amount of Li scattering from the dielectric layer 14 reduces the Li content within the base electrode layer 32, thus suppressing the decrease in the moisture resistance of the multilayer ceramic capacitor 10.

[0098] Specifically, Li is not present in at least one of the regions of the first base electrode layer 32a that are more than 15 μm away from the first base electrode layer 32a in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, and the regions of the second base electrode layer 32b that are more than 15 μm away from the second base electrode layer 32b in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b.

[0099] Furthermore, preferably, in at least one of the regions of the first base electrode layer 32a that is more than 5 μm away from the first base electrode layer 12 in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, and in the region of the second base electrode layer 32b that is more than 5 μm away from the first base electrode layer 12 in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, Li is not present.

[0100] As described above, the presence or absence of Li in the substrate electrode layer 32 can be confirmed by TOF-SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The determination conditions based on this TOF-SIMS are as follows.

[0101] • Device Name: TOF.SIMS (Made by ION-TOF Company)

[0102] Primary ion: Bi +

[0103] Accelerating voltage: 25kV

[0104] Secondary ion polarity: Positive

[0105] • Number of scans: 32

[0106] • Pixel count: 256 pixels × 256 pixels

[0107] • Measurement area: 30μm × 30μm square

[0108] Furthermore, the presence or absence of Li is confirmed by the presence of pixels with an intensity of Li greater than 1.0 within a 256-pixel × 256-pixel area.

[0109] Next, refer to Figure 2 as well as Figure 3 The plating layers 34 disposed on the substrate electrode layer 32, namely the first plating layer 34a and the second plating layer 34b, will be described.

[0110] The first plating layer 34a and the second plating layer 34b may, for example, include at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0111] The first plating layer 34a is configured to completely cover the first substrate electrode layer 32a.

[0112] The second plating layer 34b is configured to completely cover the second substrate electrode layer 32b.

[0113] The first plating layer 34a and the second plating layer 34b may also be formed from multiple layers. In this case, the plating layer 34 is preferably a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the substrate electrode layer 32 based on Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer based on Sn plating.

[0114] That is, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a.

[0115] Furthermore, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0116] The lower plating layer 36 based on Ni plating is used to prevent the base electrode layer 32 from being eroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 38 based on Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, so that it can be easily mounted.

[0117] The thickness of each of the lower plating layer 36 and the upper plating layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0118] The dimension of the first direction y of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension L. The dimension of the stacking direction x of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension T. The dimension of the second direction z of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, is set as dimension W.

[0119] Regarding the dimensions of the multilayer ceramic capacitor 10, the L dimension in the first direction y is 0.25 mm or more and 2.0 mm or less, the W dimension in the second direction z is 0.125 mm or more and 1.25 mm or less, and the T dimension in the stacking direction x is 0.125 mm or more and 1.25 mm or less. Furthermore, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0120] exist Figure 1 In the multilayer ceramic capacitor 10 shown, in a region within 15 μm square from the interface between the multilayer 12 and the base electrode layer 32, the content of Li in the base electrode layer 32 is less than the content of Li in the inner dielectric layer 14a, thus suppressing the decrease in moisture resistance.

[0121] In addition, Figure 1 In the multilayer ceramic capacitor 10 shown, if the content of Li in the base electrode layer 32 is less than the content of Li in the inner dielectric layer 14a in a region within 5 μm square from the interface between the multilayer 12 and the base electrode layer 32, the decrease in moisture resistance can be further suppressed.

[0122] In addition, Figure 1 In the multilayer ceramic capacitor 10 shown, there is no region in the first direction y that is further away from the multilayer 12 than 15 μm from the interface between the multilayer 12 and the base electrode layer 32. Therefore, the decrease in moisture resistance can be suppressed.

[0123] Furthermore, in Figure 1 In the multilayer ceramic capacitor 10 shown, if the distance from the interface between the multilayer body 12 and the base electrode layer 32 to Li is less than 5 μm, the decrease in moisture resistance can be further suppressed.

[0124] (A variation of the first embodiment)

[0125] Next, an example of a modified example of the first embodiment of the present invention, involving a multilayer ceramic capacitor 10A, will be described. Figure 5This is a schematic cross-sectional view illustrating an example of a multilayer ceramic capacitor according to a variation of the first embodiment of the present invention. Regarding... Figures 1 to 4 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0126] The modified example of the first embodiment involves a multilayer ceramic capacitor 10A comprising a cuboid multilayer 12A and external electrodes 30 disposed at both ends of the multilayer 12A.

[0127] The laminate 12A has a plurality of stacked dielectric layers 14. Furthermore, the laminate 12A has a first surface 12a and a second surface 12b opposite each other in the stacking direction x, a third surface 12c and a fourth surface 12d opposite each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposite each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0128] like Figure 5 As shown, the laminate 12A has a pair of first internal electrodes 20A and a pair of second internal electrodes 20B as internal electrodes 20.

[0129] A pair of first internal electrodes 20A consists of two first internal electrodes 20a that are consecutively adjacent in the stacking direction x. The pair of first internal electrodes 20A are electrically connected to the first external electrode 30a.

[0130] A pair of second internal electrodes 20B consists of two second internal electrodes 20b that are continuously adjacent in the stacking direction x. The pair of second internal electrodes 20B is electrically connected to the second external electrode 30b.

[0131] Therefore, even if the thickness of a single internal electrode is small, the overall conductivity can be ensured by multiple internal electrodes.

[0132] according to Figure 5 The modified example of the first embodiment shown relates to a multilayer ceramic capacitor 10A, which performs in conjunction with... Figure 1 The same effect is achieved with the stacked ceramic capacitor 10.

[0133] B. Second Implementation Method

[0134] Next, an example of the multilayer ceramic capacitor 110 according to the second embodiment of the present invention will be described. Figure 6 This is a perspective view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Figure 7 yes Figure 6 A cross-sectional view at line VII-VII. Figure 8 yes Figure 6 A cross-sectional view at line VIII-VIII. Figure 9 yes Figure 6 A cross-sectional view at line IX-IX.

[0135] The second embodiment of the present invention relates to a multilayer ceramic capacitor 110, which includes a multilayer body 112 having the same structure as the multilayer ceramic capacitor 10 of the first embodiment, and an external electrode 30. However, the size relationship between the L dimension and the W dimension is reversed in the multilayer ceramic capacitor 110 compared to the multilayer ceramic capacitor 10 of the first embodiment, with the W dimension being larger than the L dimension.

[0136] The second embodiment of the multilayer ceramic capacitor 110 includes a cuboid multilayer 112 and external electrodes 30 disposed at both ends of the multilayer 112.

[0137] The laminate 112 has a plurality of stacked dielectric layers 14. Furthermore, the laminate 112 has a first surface 112a and a second surface 112b opposite each other in the stacking direction x, a third surface 112c and a fourth surface 112d opposite each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 112e and a sixth surface 112f opposite each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0138] Compared to the multilayer ceramic capacitor 10 of the first embodiment, the size relationship between the L dimension and the W dimension of the multilayer ceramic capacitor 110 is reversed, with the W dimension being larger than the L dimension.

[0139] according to Figure 6 The laminated ceramic capacitor 110 according to the second embodiment shown plays a role in... Figure 1 The same effect is achieved with the stacked ceramic capacitor 10.

[0140] (A variation of the second embodiment)

[0141] Next, an example of a modified embodiment of the second embodiment of the invention, involving a multilayer ceramic capacitor 110A, will be described. Figure 10 This is a schematic cross-sectional view illustrating an example of a multilayer ceramic capacitor according to a variation of the second embodiment of the present invention. Regarding... Figures 6 to 8 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0142] like Figure 10 As shown, in the modified example of the second embodiment, the laminate 112A of the laminated ceramic capacitor 110A has a pair of first internal electrodes 20A and a pair of second internal electrodes 20B as internal electrodes 20.

[0143] A pair of first internal electrodes 20A consists of two first internal electrodes 20a that are consecutively adjacent in the stacking direction x. The pair of first internal electrodes 20A are electrically connected to the first external electrode 30a.

[0144] A pair of second internal electrodes 20B consists of two second internal electrodes 20b that are continuously adjacent in the stacking direction x. The pair of second internal electrodes 20B is electrically connected to the second external electrode 30b.

[0145] Therefore, even if the thickness of a single internal electrode is small, the overall conductivity can be ensured by multiple internal electrodes.

[0146] according to Figure 10 The modified example of the second embodiment shown relates to a multilayer ceramic capacitor 110A, which performs in conjunction with... Figure 1 The same effect is achieved with the stacked ceramic capacitor 10.

[0147] C. Third Implementation

[0148] Next, an example of the multilayer ceramic capacitor 210 according to the third embodiment of the present invention will be described. Figure 11 This is a perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 12 yes Figure 11 A cross-sectional view at line XII-XII. Figure 13 yes Figure 11 A cross-sectional view at line XIII-XIII. Figure 14 yes Figure 11 A cross-sectional view at line XIV-XIV.

[0149] The third embodiment of the multilayer ceramic capacitor 210 includes a cuboid multilayer 212 and external electrodes 30 disposed at both ends of the multilayer 212.

[0150] The laminate 212 has a plurality of stacked dielectric layers 14. Furthermore, the laminate 212 has a first surface 212a and a second surface 212b opposite each other in the stacking direction x, a third surface 212c and a fourth surface 212d opposite each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 212e and a sixth surface 212f opposite each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0151] In the laminate 212, as Figure 13 as well as Figure 14 As shown, in its inner layer 216, the first internal electrode 20a and the second internal electrode 20b are disposed on the same dielectric layer 14 at a given interval.

[0152] according to Figure 10 The multilayer ceramic capacitor 210 shown in the third embodiment plays a role in... Figure 1 The same effect is achieved with the stacked ceramic capacitor 10.

[0153] 2. Manufacturing method of multilayer ceramic capacitors

[0154] Next, as an example, the manufacturing method of the multilayer ceramic capacitor according to the first embodiment will be described.

[0155] (The process of preparing raw ceramic slabs)

[0156] First, prepare the ceramic green sheet for the dielectric layer and the conductive paste for the internal electrodes. The ceramic green sheet and the conductive paste for the internal electrodes contain an adhesive and a solvent. The adhesive and solvent can be known adhesives and solvents.

[0157] At this point, the ceramic green sheet used in the inner dielectric layer region is formed, for example, from a dielectric paste containing Li in CaZrO3. More specifically, this dielectric paste contains at least Ca, Sr, or Zr as the main components, and Li. For example, it contains CaZrO3 and SrZrO3 as dielectric components, and Li as a sintering aid. In addition, Mn, Na, Ti, etc., may also be included.

[0158] In addition, when CaZrO3 is the main component, the amount of Li relative to CaZrO3 in the dielectric paste used to form the inner dielectric layer region can be set to 0.06 wt% or more and 0.16 wt%.

[0159] Then, conductive paste for the internal electrodes is printed on a ceramic green sheet for the dielectric layer in a given pattern, for example by screen printing, gravure printing, or the like. Thus, a ceramic green sheet with a pattern of the first internal electrode and a ceramic green sheet with a pattern of the second internal electrode are prepared.

[0160] (The process of obtaining the laminated wafer)

[0161] Next, by stacking a given number of unprinted inner electrode patterns on an outer ceramic sheet, a portion forming the second-side outer layer is created. Then, by sequentially stacking a ceramic sheet with a first inner electrode pattern and a ceramic sheet with a second inner electrode pattern on the portion forming the second-side outer layer, the structure of the present invention is achieved, thereby forming the inner layer. A given number of unprinted inner electrode patterns on an outer ceramic sheet are then stacked on this inner layer, thereby forming the first-side outer layer. Thus, a laminated sheet is produced.

[0162] (The process of obtaining the stacked blocks)

[0163] Next, laminated sheets are pressed in the lamination direction using methods such as isostatic pressing to produce laminated blocks.

[0164] (The process of obtaining stacked chips)

[0165] Then, the stacked blocks are cut to the given size, and small stacked pieces are cut out to become the stacked parts.

[0166] (The process of obtaining small sintered pieces)

[0167] Next, the stacked small pieces are fired to produce fired small pieces. Specifically, after heating to 200°C or higher and 300°C or lower, the pieces are fired in a non-oxidizing atmosphere at a heating rate of 3.33°C / min or higher and 200°C / min or lower, and at a maximum firing temperature of 900°C or higher and 1040°C or lower to form fired small pieces.

[0168] Next, prepare a conductive paste for the base electrode layer, which contains both metallic and glass components.

[0169] (The process of forming the external electrode)

[0170] A conductive paste, prepared to serve as a base electrode layer, is applied to each of the third and fourth surfaces of the sintered small sheet to form the base electrode layer. The application of the conductive paste to the surfaces corresponding to the third and fourth surfaces of the sintered small sheet is performed, for example, by an impregnation method. For instance, in the conductive paste forming the base electrode layer, Cu is used as the main metallic component, and a glass component can be included in an amount of 21 vol% or more and 25 vol% or less. In this case, the Cu particles can be spherical in shape, and the D50 can be 0.3 μm or more and 0.6 μm or less.

[0171] Next, the sintered body sheet coated with conductive paste is fired to form a sintered body sheet with a base electrode layer. At this time, it is preferable to adjust the firing conditions so that an appropriate amount of Li is contained in the base electrode layer after firing the conductive paste. If firing is performed under conditions where Li is not contained in the base electrode layer, excessive densification of the base electrode layer can be suppressed, thus reducing the porosity within the base electrode layer and improving the moisture resistance of the multilayer ceramic capacitor. Furthermore, by suppressing the Li that diffuses into the base electrode layer to less than 15 μm from the interface between the multilayer (sintered body sheet) and the base electrode layer, excessive densification can be suppressed. Lowering the firing temperature or shortening the firing time can reduce the distance and amount of Li that diffuses into the base electrode layer, but correspondingly, the densification of the base electrode layer becomes insufficient. Therefore, appropriate firing conditions are set so that Li becomes a component of the multilayer ceramic capacitor of the present invention. For example, firing can be carried out under the following conditions: in a reducing atmosphere, at a temperature of 600°C or higher and 750°C or lower, and for a duration of 0.3 hours or higher and 0.5 hours or lower.

[0172] Next, as needed, plating is performed on the surface of the substrate electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the substrate electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the substrate electrode layer. As a plating process, electrolytic plating is preferred. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a roller plating method.

[0173] As described above, the multilayer ceramic capacitor 10 of this embodiment is manufactured.

[0174] 3. Experimental Example

[0175] Next, in order to confirm the effect of the multilayer ceramic capacitor of the present invention, a multilayer ceramic capacitor with a changed C-axis orientation was manufactured according to the above manufacturing method as an experimental sample, and an experiment based on electrostriction test was conducted to confirm whether cracks were generated.

[0176] (1) Specifications of the multilayer ceramic capacitor made as an experimental example

[0177] Using the manufacturing method described in the above embodiments, multilayer ceramic capacitors were produced as samples numbered 1 to 10.

[0178] • Dimensions of the multilayer ceramic capacitor (design value): L×W×T=400μm×200μm×200μm

[0179] Ceramic material: CaZrO3

[0180] • Material of internal electrodes: Cu

[0181] • The base electrode layer of the external electrode: a combination of conductive metal (Cu) and glass.

[0182] • The thickness of the base electrode layer, which is half the W dimension in the second direction z of the multilayer ceramic capacitor and at the center in the stacking direction x, is 20 μm.

[0183] · Coating layer

[0184] Two layers are formed: a Ni plating layer and a Sn plating layer.

[0185] Ni plating thickness: approximately 3μm

[0186] Sn plating thickness: approximately 5μm

[0187] (2) Method for adjusting the scattering distance of Li from the interface between the laminate and the external electrode

[0188] The distance at which Li scatters from the interface between the laminate and the external electrode is adjusted by adjusting the firing time and firing temperature of the sintered body piece coated with conductive paste in the manufacturing method described in the above embodiments. Table 1 shows the distance at which Li scatters from the interface between the laminate and the external electrode for each sample number. Furthermore, sample number 1 shows whether Li scatters at the interface between the substrate electrode layer and the plating layer, while sample number 10 shows that Li did not scatter to the substrate electrode layer (external electrode).

[0189] (3) Method of moisture resistance test

[0190] First, the multilayer ceramic capacitors involved in each sample were mounted onto a wiring substrate using solder, and their insulation resistance was measured. Then, the multilayer ceramic capacitors mounted on the wiring substrate were placed in a high-temperature, high-humidity bath and maintained at 85°C and 85% RH for 2000 hours with a DC current of 200V applied to the external electrodes of each sample, thus performing a humidity resistance test. Next, the insulation resistance of the multilayer ceramic capacitors involved in each sample was measured after the humidity resistance test. A decrease of more than one digit in the insulation resistance after the humidity resistance test compared to the insulation resistance before the humidity resistance test was classified as NG (Not Good). The number of samples was set to 100.

[0191] (4) Method for determining the distance of Li dispersion

[0192] The distance at which Li scatters from the interface between the laminate and the external electrode is defined by measuring the distance of the substrate electrode layer 32 located at the center of the lamination direction x in a cross-section of the laminated ceramic capacitor involved in each sample, ground to half the W dimension in the second direction z, using TOF-SIM (manufactured by ION-TOF), under conditions of 30 μm square, with the interface between the laminate 12 and the substrate electrode layer 32 as the center of the observed image. The determination of the presence of Li is made as follows.

[0193] That is, the presence or absence of Li in the substrate electrode layer is confirmed by TOF-SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The determination conditions based on this TOF-SIMS are as follows.

[0194] • Device Name: TOF.SIMS (Made by ION-TOF Company)

[0195] Primary ion: Bi +

[0196] Accelerating voltage: 25kV

[0197] Secondary ion polarity: Positive

[0198] • Number of scans: 32

[0199] • Pixel count: 256 pixels × 256 pixels

[0200] • Measurement area: 30μm × 30μm square

[0201] Furthermore, the presence or absence of Li was confirmed by the presence of pixels with an intensity of Li greater than 1.0 within a 256-pixel × 256-pixel area. Additionally, in each of specimens numbered 1 and 2, observations were performed by offsetting the centers of the observed images.

[0202] (5) Results

[0203] Table 1 shows the distance Li scatters from the interface between the laminate and the external electrode in the multilayer ceramic capacitors based on specimen numbers 1 to 10, and the results of the moisture resistance test for that distance.

[0204] [Table 1]

[0205]

[0206] According to Table 1, it was confirmed that as the distance from sample number 1 to sample number 10 decreased, the distance of Li scattering from the interface between the laminate and the external electrode decreased, and as this distance decreased, the number of samples that became NG based on the results of the moisture resistance test decreased.

[0207] Based on the above results, it was confirmed that in this invention, the greater the distance that Li disperses from the interface between the laminate and the external electrode, the greater the decrease in moisture resistance. Therefore, it is suggested that by appropriately configuring lithium (Li) in the external electrode of the laminated ceramic capacitor, the degradation of moisture resistance can be suppressed.

[0208] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0209] That is, various changes can be made to the above-described embodiments regarding mechanism, shape, material, quantity, position or configuration without departing from the technical concept and purpose of the present invention, and these changes are included in the present invention.

[0210] <1>

[0211] A multilayer ceramic capacitor, comprising:

[0212] A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to the stacking direction and the first direction.

[0213] A first external electrode is disposed on the third surface of the laminate; and

[0214] The second external electrode is disposed on the fourth surface of the laminate.

[0215] The laminate includes an inner layer and two outer layers configured to sandwich the inner layer in the lamination direction.

[0216] The inner layer has:

[0217] The first internal electrode has one end exposed on the third surface;

[0218] The second internal electrode has one end exposed on the fourth surface; and

[0219] An inner dielectric layer is provided with the first internal electrode and the second internal electrode.

[0220] The inner dielectric layer contains at least Ca, Sr or Zr as the main component, and Li.

[0221] In at least one of the regions of the first external electrode within 15 μm square in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 15 μm square in the first direction from the interface between the laminate and the second external electrode, the content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

[0222] <2> According to the multilayer ceramic capacitor described in <1>, wherein,

[0223] In at least one of the regions of the first external electrode within 5 μm square in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 5 μm square in the first direction from the interface between the laminate and the second external electrode, the content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

[0224] <3>

[0225] A multilayer ceramic capacitor, comprising:

[0226] A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to the stacking direction and the first direction.

[0227] A first external electrode is disposed on the third surface of the laminate; and

[0228] The second external electrode is disposed on the fourth surface of the laminate.

[0229] The laminate includes an inner layer and two outer layers configured to sandwich the inner layer in the lamination direction.

[0230] The inner layer has:

[0231] The first internal electrode has one end exposed on the third surface;

[0232] The second internal electrode has one end exposed on the fourth surface; and

[0233] An inner dielectric layer is provided with the first internal electrode and the second internal electrode.

[0234] The inner dielectric layer contains at least Ca, Sr or Zr as the main component, and Li.

[0235] Li is absent in at least one of the regions of the first external electrode located more than 15 μm away from the first external electrode in the first direction from the interface between the laminate and the first external electrode, and the regions of the second external electrode located more than 15 μm away from the second external electrode in the first direction from the interface between the laminate and the second external electrode.

[0236] <4> According to the multilayer ceramic capacitor described in <3>, among which,

[0237] Li is absent in at least one of the regions of the first external electrode located more than 5 μm away from the first external electrode in the first direction from the interface between the laminate and the first external electrode, and the regions of the second external electrode located more than 5 μm away from the second external electrode in the first direction from the interface between the laminate and the second external electrode.

[0238] <5> According to any one of <1> to <4>, the multilayer ceramic capacitor, wherein,

[0239] The internal electrode is Cu.

[0240] <6> According to any one of <1> to <5>, the multilayer ceramic capacitor, wherein,

[0241] As the interface between the laminate and the first external electrode moves away from the first direction, the Li content in the first external electrode decreases, and / or,

[0242] As the interface between the laminate and the second external electrode moves away from the first direction, the amount of Li in the second external electrode decreases.

[0243] <7> According to any one of <1> to <6>, the multilayer ceramic capacitor, wherein,

[0244] At least one of the first external electrode and the second external electrode comprises Cu particles and glass components as main components.

[0245] The D50 of the Cu particles is greater than 0.3 μm and less than 0.6 μm.

[0246] The glass component content is 21 vol% or more and 25 vol% or less.

[0247] <8> According to any one of <4> to <7>, the multilayer ceramic capacitor, wherein,

[0248] At least one of the first external electrode and the second external electrode does not contain Li.

[0249] Explanation of reference numerals in the attached figures

[0250] 10, 10A, 110, 110A, 210 laminated ceramic capacitors

[0251] 12, 12A, 112, 112A, 212 laminates

[0252] Page 1 of 12a, 112a, and 212a

[0253] Page 2 of 12b, 112b, and 212b

[0254] 12c, 112c, 212c, Page 3

[0255] 12d, 112d, 212d, Page 4

[0256] Page 5 of 12e, 112e, and 212e

[0257] Page 6, 12f, 112f, 212f

[0258] 14 Dielectric layer

[0259] 14a Inner Dielectric Layer

[0260] 14b Outer Dielectric Layer

[0261] 16 Inner layer

[0262] 18a First surface outer layer

[0263] 18b Second side outer layer

[0264] 20 Internal Electrodes

[0265] 20a First internal electrode

[0266] 20b Second internal electrode

[0267] 20A Pair of first internal electrodes

[0268] 20B A pair of second internal electrodes

[0269] 22 Opposite electrode section

[0270] 22a First Opposite Electrode Section

[0271] 22b Second Opposite Electrode Section

[0272] 24a First lead electrode section

[0273] 24b Second lead-out electrode section

[0274] 26a, 26b Side

[0275] Ends of 27a and 27b

[0276] 30 External Electrode

[0277] 30a First external electrode

[0278] 30b Second external electrode

[0279] 32. Substrate electrode layer

[0280] 32a First base electrode layer

[0281] 32b Second base electrode layer

[0282] 34 Coating Layer

[0283] 34a First plating layer

[0284] 34b Second plating layer

[0285] 36 Lower plating layer

[0286] 36a First lower plating layer

[0287] 36b Second lower plating layer

[0288] 38. Top Coating

[0289] 38a First upper plating layer

[0290] 38b Second upper plating layer

[0291] x Stacking direction

[0292] y 1st direction

[0293] z Second direction.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to the stacking direction and the first direction. A first external electrode is disposed on the third surface of the laminate; and The second external electrode is disposed on the fourth surface of the laminate. The laminate includes an inner layer and two outer layers configured to sandwich the inner layer in the lamination direction. The inner layer has: The first internal electrode has one end exposed on the third surface; The second internal electrode has one end exposed on the fourth surface; and An inner dielectric layer is provided with the first internal electrode and the second internal electrode. The inner dielectric layer contains at least Ca, Sr or Zr as the main component, and Li. In at least one of the regions of the first external electrode within 15 μm square in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 15 μm square in the first direction from the interface between the laminate and the second external electrode, the content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein, In at least one of the regions of the first external electrode within 5 μm square in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 5 μm square in the first direction from the interface between the laminate and the second external electrode, the content of Li in the first external electrode and / or the second external electrode is less than the content of Li in the inner dielectric layer.

3. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to the stacking direction and the first direction. A first external electrode is disposed on the third surface of the laminate; and The second external electrode is disposed on the fourth surface of the laminate. The laminate includes an inner layer and two outer layers configured to sandwich the inner layer in the lamination direction. The inner layer has: The first internal electrode has one end exposed on the third surface; The second internal electrode has one end exposed on the fourth surface; and An inner dielectric layer is provided with the first internal electrode and the second internal electrode. The inner dielectric layer contains at least Ca, Sr or Zr as the main component, and Li. Li is absent in at least one of the regions of the first external electrode located more than 15 μm away from the first external electrode in the first direction from the interface between the laminate and the first external electrode, and the regions of the second external electrode located more than 15 μm away from the second external electrode in the first direction from the interface between the laminate and the second external electrode.

4. The multilayer ceramic capacitor according to claim 3, wherein, Li is absent in at least one of the regions of the first external electrode located more than 5 μm away from the first external electrode in the first direction from the interface between the laminate and the first external electrode, and the regions of the second external electrode located more than 5 μm away from the second external electrode in the first direction from the interface between the laminate and the second external electrode.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The internal electrode is Cu.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, As the interface between the laminate and the first external electrode moves away in the first direction, the Li content in the first external electrode decreases, and / or, As the interface between the laminate and the second external electrode moves away from the first direction, the amount of Li in the second external electrode decreases.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein, At least one of the first external electrode and the second external electrode comprises Cu particles as the main component and glass components. The D50 of the Cu particles is greater than 0.3 μm and less than 0.6 μm. The glass component content is 21 vol% or more and 25 vol% or less.

8. The multilayer ceramic capacitor according to any one of claims 4 to 7, wherein, At least one of the first external electrode and the second external electrode does not contain Li.

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