Bridge tunnel line shape and rigidity detection method and system based on optical fiber sensing technology

Abstract

The application discloses a bridge tunnel line shape and rigidity detection method and system based on an optical fiber sensing technology, relates to the technical field of bridge displacement monitoring, and comprises a fiber grating strain sensor, a fiber grating displacement sensor, a rigidity detection module, an acceleration sensor, an analog-digital conversion module, an amplification circuit module, a filter circuit module, a data processing module, a data transmission module, an interface module, a memory module, a display module, an alarm module, a clock module and a power module. The application realizes the functions of real-time monitoring of physical parameters such as bridge stress, bridge main bridge tower displacement, bridge vibration quantity, bridge vertical distance change quantity and displacement, data analysis and processing, bridge health state evaluation, bridge structure health early warning and the like by monitoring various parameters of the bridge in real time through a wireless sensor network, and effectively avoids various accidents.

Description

Technical Field

[0001] This invention relates to the field of bridge displacement monitoring technology, and in particular to a method and system for detecting the alignment and stiffness of bridges and tunnels based on fiber optic sensing technology. Background Technology

[0002] With the deepening of modern theoretical research and the maturation and improvement of bridge construction technology, bridges built with various new materials and processes are emerging in an endless stream. However, over time, any highway bridge will eventually become an old bridge; structures that have been used for a long time will inevitably suffer various kinds of damage due to various reasons, exhibiting different degrees of defects and illnesses, requiring repair, reinforcement, and renovation. Before repair and reinforcement, reasonable testing and evaluation are necessary to determine the actual working condition and load-bearing capacity of the bridge, analyze the causes of defects and damage, and propose effective repair and reinforcement measures. Highway bridge projects are costly and play a vital role in highway transportation. Therefore, various measures are always taken during the bridge construction process to ensure project quality.

[0003] Monitoring the health status of bridges is of great significance for their safe operation. Unlike traditional detection techniques, health monitoring of bridges with special structures not only requires rapid and high-capacity information acquisition and communication capabilities in testing, but also strives for real-time monitoring of the overall structural behavior and intelligent assessment of the structural condition.

[0004] During use, bridges are subject to various factors, resulting in varying degrees of damage and deterioration in different structural components. Timely monitoring and repair of this damage are crucial; otherwise, traffic safety will be compromised, bridge lifespan shortened, and catastrophic accidents caused by sudden bridge failure and collapse may occur. Therefore, higher demands are placed on sensing and safety monitoring technologies in this field. Currently, mechanical sensing technologies widely used in bridge monitoring are simple and practical, but they are not easy to automate data acquisition and cannot meet the needs of real-time disaster and accident monitoring. Electrical sensing technologies widely used in engineering are mainly resistive, piezoelectric, and vibrating wire types. However, because electrical sensors are active devices, their long-term stability is poor, they are susceptible to electromagnetic interference, have complex networking requirements, and short signal transmission distances. These drawbacks not only affect the accuracy and stability of monitoring results but also require additional signal transmission equipment, increasing system complexity. Existing automatic detection technologies, such as wireless sensors and sensor networks, GPS, DC resistivity methods, and microseismic monitoring, are widely used in practical safety monitoring. However, these technologies also have some drawbacks, such as susceptibility to environmental noise interference.

[0005] Compared with traditional mechanical and electrical sensing and monitoring technologies, fiber optic sensing technology has the advantages of being resistant to electromagnetic interference, having strong waterproof performance, small size, light weight, easy to embed in materials or structures for non-destructive testing, wide dynamic range, high sensitivity, long transmission distance of sensing information, flexible and simple packaging process, and the ability to achieve large-scale networking through composite technology.

[0006] With economic development and continuous advancements in science and technology, bridge construction both domestically and internationally is trending towards larger scale and greater prevalence. However, due to current knowledge levels and limitations in understanding structural complexity, bridges face numerous unpredictable and uncertain safety risks, including those arising from physical and chemical corrosion, sudden earthquakes, vehicle-ship collisions, and exceeding their service life. Factors. Therefore, during the operation of bridge structures, in order to ensure the safety performance and structural durability of long-span bridges, it is necessary to conduct health monitoring of the bridge structure and understand its working condition. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a method and system for detecting the alignment and stiffness of bridges and tunnels based on fiber optic sensing technology, thereby monitoring the health of bridge structures, understanding the working condition of bridge structures, and ensuring the safe use of bridges.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology includes a fiber optic strain sensor, a fiber optic displacement sensor, a stiffness detection module, an acceleration sensor, an analog-to-digital conversion module, an amplifier circuit module, a filter circuit module, a data processing module, a data transmission module, an interface module, a memory module, a display module, an alarm module, a clock module, and a power supply module. The fiber optic strain sensor, fiber optic displacement sensor, stiffness detection module, and acceleration sensor are connected to the data processing module in sequence via an analog-to-digital conversion module, an amplification circuit module, and a filtering circuit module. The data transmission module, interface module, data transmission module, memory module, display module, alarm module, clock module, and power supply module are connected to the data processing module. Among them, the fiber optic strain sensor is used to measure bridge stress. Fiber grating displacement sensor used to monitor the displacement of the main bridge tower. Accelerometers are used to measure the amount of vibration in bridges. Fiber optic grating displacement sensor is used to monitor the displacement of the main bridge tower. The stiffness testing module is used to measure the change in the vertical distance of the bridge. The analog-to-digital converter module is used to convert the acquired data into electrical signals; The amplifier circuit module is used to amplify the acquired parameters. The filtering circuit module is used to filter the amplified parameters. The data processing module is used to process the detection data parameters; The data transmission module is used to transmit the collected bridge data parameters; The interface module is used for data transmission; A memory module for storing bridge parameters; The display module is used to display the collected bridge parameters in real time. Alarm module, used for issuing alarms; The clock module is used to record time; The power module is used to provide the required electrical energy.

[0009] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the data processing module includes a channel switching unit, an AD acquisition control unit, a data processing unit, a clock and reset unit, a W5500 control unit, and an STM32 control unit; the data processing unit is connected to the channel management and switching module through the channel switching unit; the data processing unit is connected to the ADC signal acquisition module through the AD acquisition control unit; the data processing unit is connected to the power supply and clock module through the clock and reset unit; the data processing unit is connected to the Ethernet TCP / IP communication module through the W5500 control unit; and the data processing unit is connected to the STM32 control module through the STM32 control unit.

[0010] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the filtering circuit module includes chip IC1, capacitors C8, C15, C16, C18, C20, resistors R8, R12, C22, C24, R13, R14, and R15; one end of capacitor C15 is connected to the signal input terminal, the other end of capacitor C15, one end of capacitor C8, one end of capacitor C16, and one end of resistor R12 are connected, the other end of capacitor C16, one end of resistor R8, and pin 2 of chip IC1 are connected, and the other end of capacitor C8, the other end of resistor R8, and pin 1 of chip IC1 are connected to serve as the output terminal of the second-order low-pass filter circuit; pin 11 of chip IC1 is grounded, the other end of resistor R12 is connected to pin 3 of chip IC1 and then grounded, and pin 4 of chip IC1, capacitor C8, C15, C16, C18, C20, and R10 are connected to pin 3 of chip IC1 and then grounded. One end of capacitor C18 and one end of capacitor C20 are connected to a 5V power supply. The other end of capacitor C18 and the negative terminal of capacitor C20 are connected to ground. The model of the chip IC1 shown is LM324. Capacitors C8, C15, C16, and C18 are ceramic capacitors, and capacitor C20 is an electrolytic capacitor. One end of resistor R14 is connected to the output of the second-order low-pass filter circuit. The other end of resistor R14, one end of resistor R13, one end of capacitor C13, and one end of capacitor C24 are connected. The other end of resistor R15, one end of capacitor C22, and pin 6 of chip IC1 are connected. The other end of resistor R13, the other end of capacitor C22, and pin 7 of chip IC1 are connected to serve as the output of the second-order high-pass filter circuit. The other end of capacitor C24 is connected to pin 5 of chip IC1 and then grounded. The model of the chip IC1 shown is LM324, and capacitors C22 and C24 are ceramic capacitors.

[0011] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the data transmission module includes an antenna ANT1, capacitor C11, capacitor C12, and capacitor C13. Capacitors C14, C15, and C16; resistors R21 and R22; inductors L11 and L12; chips U1, U2, and U3; antenna ANT1 is connected to one end of inductor L11 and one end of capacitor C16, with the other end of inductor L11 grounded. The other end of capacitor C16 is connected to one end of inductor L12 and pin 2 of chip U1, with the other end of inductor L12 grounded. Pins 3 and 4 of chip U1 are connected to one end of capacitor C14, one end of capacitor C15, and VDD, with the other ends of capacitors C14 and C15 grounded. Pin 1 of chip U1 is connected to one end of capacitor C13, VDD, pin 30, and pin 29, with the other end of capacitor C13 grounded. Pin 31 of chip U1 is connected to resistor R... One end of resistor R21 is grounded, and the other end of resistor R21 is grounded. Pin 28 of chip U1 is connected to one end of capacitor C11 and pin 1 of chip U2. Pin 2 of chip U2 is grounded, and the other end of capacitor C11 is grounded. Pin 4 of chip U2 is grounded. Pin 3 of chip U2 is connected to one end of capacitor C12 and pin 27 of chip U1. The other end of capacitor C12 is grounded. Pin 18 of chip U1 is connected to pin 7 of chip U3. Pin 19 of chip U1 is connected to pin 3 of chip U3. Pin 20 of chip U1 is connected to pin 1 of chip U3. Pin 21 of chip U1 is connected to pin 6 of chip U3 through resistor R22. Pin 22 of chip U1 is connected to pin 2 of chip U3. Pin 23 of chip U1 is connected to pin 5 of chip U3. Pin 17 of chip U1 is connected to pin 11 of chip U1 and the VDD terminal.

[0012] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the amplification circuit module includes an LNA low-noise amplifier, a power divider, a first filter, a second filter, a first amplifier, a second amplifier, a combiner, a third amplifier, and a third filter. The output terminal of the LNA is connected to the input terminal of the power divider, and the output terminal of the power divider is connected to the input terminals of the first and second filters, respectively. The output terminals of the first and second filters are connected to the input terminal of the combiner via the first and second amplifiers, respectively. The output terminal of the combiner is connected to the input terminal of the third filter via the third amplifier.

[0013] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the interface circuit module includes the DALI_RX terminal of the MCU, the DALI_TX terminal of the MCU, the VCC voltage terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first diode, a second diode, a third diode, a first Zener diode, a first transistor, a second transistor, a third transistor, an LM317 chip, a voltage regulator chip, a first capacitor, a second capacitor, and a third capacitor; wherein, the VCC voltage terminal is connected to one end of the first capacitor, the Vin terminal of the voltage regulator chip, and the cathode of the first diode respectively; the anode of the first diode is connected to the V0 terminal of the voltage regulator chip, the anode of the first diode, the cathode of the second diode, and the DA+ terminal respectively; the other end of the first resistor is connected to one end of the second resistor, the ADJ terminal of the voltage regulator chip, the anode of the second diode, and one end of the second capacitor respectively. The other end of the second resistor is connected to the other end of the second capacitor, the other end of the first capacitor, and the DA- terminal, and grounded. The DA+ terminal is connected to the gate of the third transistor, one end of the seventh resistor, and the cathode of the Zener diode. The anode of the Zener diode is connected to one end of the fifth resistor and one end of the sixth resistor. The other end of the fifth resistor is connected to the cathode of the third diode, one end of the fourth resistor, and the 5V voltage terminal through the first transistor. The anode of the third diode is connected to the DALI_RX terminal of the MCU and one end of the third resistor. The other end of the third resistor is connected to the 3.3V voltage terminal. The gate of the third transistor is connected to one end of the tenth resistor and the collector of the second transistor through the eleventh resistor. The other end of the tenth resistor is connected to the 5V voltage terminal. The base of the second transistor is connected to one end of the eighth resistor and the DALI_TX terminal of the MCU through the ninth resistor. The other end of the eighth resistor is connected to the 3.3V voltage terminal. The other ends of the fourth, sixth, and seventh resistors, the emitter of the second transistor, and the DA- terminal are interconnected and grounded.

[0014] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the clock module includes a clock chip DS3231, a capacitor C4, resistors R25, R26, R27, and R28. The VCC terminal is connected to one end of resistor R25 and one end of resistor R26, respectively. The other end of resistor R25 is connected to the SDA terminal of the clock chip DS3231, and the other end of resistor R26 is connected to the SCL terminal of the clock chip DS3231. The VDD terminal is connected to one end of resistor R27, one end of resistor R28, one end of capacitor C4, and port 2 of the clock chip DS3231, respectively. The other end of resistor R27 is connected to port 1 of the clock chip DS3231, and the other end of resistor R28 is connected to port 3 of the clock chip DS3231. The other end of capacitor C4 is grounded.

[0015] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the fiber optic displacement sensor array adopts the SR-RP-S1 type fiber optic displacement sensor, the fiber optic strain sensor array adopts the GSYC-T1 type fiber optic strain sensor, and the acceleration sensor adopts the ServoK-Beam8330A type servo acceleration sensor.

[0016] As a further preferred embodiment of the bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology of the present invention, the power supply module includes a mains power module, a PV photovoltaic module, a power conversion circuit, a battery, a boost module, and a voltage regulator module. The output terminal of the mains power module is connected to the input terminal of the microprocessor module. The output terminal of the PV photovoltaic module is connected to the input terminal of the battery through the power conversion circuit. The input and output terminals of the battery are connected to the input terminal of the microprocessor module through the boost module and the voltage regulator module in sequence. The power conversion circuit includes a DC 12V voltage input terminal, a first diode, a first capacitor, a second capacitor, an LM2576S-5.0 power chip, a second diode, a first inductor, a third capacitor, a 5V voltage output terminal, a 5V voltage input terminal, a fourth capacitor, a TPS7A7001 power chip, a first resistor, a second resistor, a fifth capacitor, and a 3.3V voltage output terminal. The DC12V voltage input terminal is connected to the negative terminal of the first diode, one end of the first capacitor, one end of the second capacitor, and the VIN terminal of the LM2576S-5.0 power chip. The other end of the first diode is connected to the other end of the first capacitor, the other end of the second capacitor, the EN# terminal of the LM2576S-5.0 power chip, the GND terminal of the LM2576S-5.0 power chip, the positive terminal of the second diode, and one end of the third capacitor and grounded. The negative terminal of the second diode is connected to the VOUT terminal of the LM2576S-5.0 power chip and one end of the first inductor. The other end of the first inductor is connected to the other end of the third capacitor, the FB terminal of the LM2576S-5.0 power chip, and the 5V output terminal. The 5V input terminal is connected to one end of the fourth capacitor, the EN terminal of the TPS7A7001 power chip, and the IN terminal of the TPS7A7001 power chip. The other end of the fourth capacitor is grounded. The GND terminal of the TPS7A7001 power chip is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor and the FB terminal of the TPS7A7001 power chip. The other end of the second resistor is connected to one end of the fifth capacitor, the OUT terminal of the TPS7A7001 power chip, and the 3.3V output terminal. The other end of the fifth capacitor is grounded.

[0017] A detection method for a bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology, characterized by the following steps; Step 1, using fiber optic strain sensor, fiber optic displacement sensor, stiffness detection module, and acceleration sensor. The device collects real-time data on bridge stress, bridge main tower displacement, bridge vibration, bridge main tower displacement, and changes in the bridge's vertical distance. Step 2: The collected data is converted into electrical signals by the analog-to-digital converter module, the collected parameters are amplified by the amplifier module, and then the amplified parameters are filtered by the filter module before being uploaded to the data processing module. Step 3: Compare the detected bridge parameters with the preset parameters. If the parameters exceed the preset safety range, an alarm will be triggered. The alarm module issues an alarm, which then notifies supervisory personnel to carry out maintenance, completing functions such as real-time monitoring, data analysis and processing, bridge health status assessment, and bridge structural health early warning.

[0018] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects: 1. This invention relates to a bridge and tunnel alignment and stiffness detection method and system based on fiber optic sensing technology. It uses a wireless sensor network to monitor various bridge parameters in real time, enabling real-time monitoring, data analysis and processing, bridge health status assessment, and early warning of bridge structural health, including physical parameters such as bridge stress, main tower displacement, bridge vibration, changes in vertical distance, and displacement. This effectively prevents various accidents; it also allows for real-time understanding of the bridge structure's safe service status and the implementation of effective preventative maintenance, repair, and reinforcement, ensuring that bridge inspection and maintenance strategies are targeted, timely, and efficient. This provides a scientific basis for decision-making regarding maintenance needs and measures, thereby ensuring the safety of bridge use and reducing bridge maintenance costs. 2. The data processing module of this invention is based on an FPGA and TOE architecture to realize a multi-channel acquisition and switching system for TCP / IP protocol data transmission. This system involves modules for parallel data acquisition, multi-channel switching, and TCP / IP protocol communication. It enables remote or local accurate control and real-time display via a host computer (PC) or keyboard and an LCD, meeting the requirements for multi-channel switching, parallel acquisition of analog signals, and reliable transmission. To ensure the reliability of long-distance control and data transmission in data acquisition applications, and to meet the requirements for switching multiple signal interfaces and parallel data acquisition, the system uses a Xilinx Spartan-6 series FPGA as the main control chip, capable of switching 8 groups × 13 channels and synchronous acquisition and real-time transmission of 16 analog signals. It employs an FPGA+TOE architecture to implement TCP / IP protocol communication and is equipped with a monitoring host computer. Testing shows that the system can stably perform multi-channel switching and high-speed acquisition and real-time transmission over a long period, and is convenient to use and highly reliable. Attached Figure Description

[0019] Figure 1 This is a structural principle diagram of the bridge and tunnel alignment and stiffness detection method and system based on fiber optic sensing technology of the present invention; Figure 2 This is a schematic diagram of the data processing module of the present invention; Figure 3 This is a circuit diagram of the filter circuit module of the present invention; Figure 4 This is a circuit diagram of the data transmission module of the present invention; Figure 5 This is a circuit diagram of the amplifier circuit module of the present invention; Figure 6 This is a circuit diagram of the interface circuit module of the present invention; Figure 7 This is a circuit diagram of the clock module of the present invention; Figure 8 This is a schematic diagram of the power module structure of the present invention; Figure 9 This is a circuit diagram of the power supply conversion circuit of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology, such as Figure 1As shown, it includes a fiber optic strain sensor, a fiber optic displacement sensor, a stiffness detection module, an acceleration sensor, an analog-to-digital conversion module, an amplifier circuit module, a filter circuit module, a data processing module, a data transmission module, an interface module, a memory module, a display module, an alarm module, a clock module, and a power supply module. The fiber optic strain sensor, fiber optic displacement sensor, stiffness detection module, and acceleration sensor are connected to the data processing module in sequence via an analog-to-digital conversion module, an amplification circuit module, and a filtering circuit module. The data transmission module, interface module, data transmission module, memory module, display module, alarm module, clock module, and power supply module are connected to the data processing module. Among them, the fiber optic strain sensor is used to measure bridge stress. Fiber grating displacement sensor used to monitor the displacement of the main bridge tower. Accelerometers are used to measure the amount of vibration in bridges. Fiber optic grating displacement sensor is used to monitor the displacement of the main bridge tower. The stiffness testing module is used to measure the change in the vertical distance of the bridge. The analog-to-digital converter module is used to convert the acquired data into electrical signals; The amplifier circuit module is used to amplify the acquired parameters. The filtering circuit module is used to filter the amplified parameters. The data processing module is used to process the detection data parameters; The data transmission module is used to transmit the collected bridge data parameters; The interface module is used for data transmission; A memory module for storing bridge parameters; The display module is used to display the collected bridge parameters in real time. Alarm module, used for issuing alarms; The clock module is used to record time; The power module is used to provide the required electrical energy.

[0022] This invention relates to a method and system for detecting the alignment and stiffness of bridges and tunnels based on fiber optic sensing technology. It uses a wireless sensor network to monitor various parameters of the bridge in real time, enabling real-time monitoring, data analysis and processing, bridge health status assessment, and early warning of bridge structural health, including changes in bridge stress, main tower displacement, vibration, vertical distance, and other physical parameters. This effectively prevents various accidents. Furthermore, it allows for real-time understanding of the bridge structure's safe service status and enables effective preventative maintenance, repair, and reinforcement, ensuring that bridge inspection and maintenance strategies are targeted, timely, and efficient. This provides a scientific basis for decision-making regarding maintenance needs and measures, thereby ensuring the safety of bridge use and reducing bridge maintenance costs.

[0023] like Figure 2 As shown, the data processing module includes a channel switching unit, an AD acquisition control unit, a data processing unit, a clock and reset unit, a W5500 control unit, and an STM32 control unit. The data processing unit is connected to the channel management and switching module through the channel switching unit; the data processing unit is connected to the ADC signal acquisition module through the AD acquisition control unit; the data processing unit is connected to the power supply and clock module through the clock and reset unit; the data processing unit is connected to the Ethernet TCP / IP communication module through the W5500 control unit; and the data processing unit is connected to the STM32 control module through the STM32 control unit.

[0024] This invention's data processing module, based on an FPGA and TOE architecture, implements a multi-channel acquisition and switching system for TCP / IP protocol data transmission. The system involves modules for parallel data acquisition, multi-channel switching, and TCP / IP protocol communication. It enables remote or local accurate control and real-time display via a host computer (PC) or keyboard and an LCD, meeting the requirements for multi-channel switching, parallel analog signal acquisition, and reliable transmission. To ensure the reliability of long-distance control and data transmission in data acquisition applications, and to meet the requirements for switching multiple signal interfaces and parallel data acquisition, the system uses a Xilinx Spartan-6 series FPGA as the main control chip, capable of switching 8 groups × 13 channels and synchronous acquisition and real-time transmission of 16 analog signals. It employs an FPGA+TOE architecture for TCP / IP protocol communication and is equipped with a monitoring host computer. Testing shows that the system can stably perform multi-channel switching and high-speed acquisition and real-time transmission over a long period, demonstrating ease of use and high reliability.

[0025] FPGA logic control module The FPGA logic control module utilizes the AC6150 core board, developed based on the Xilinx Spartan-6 series XC6SLX150-2FG484C, which features high speed, high bandwidth, and high capacity. This core board measures 60 mm × 60 mm, incorporates FPGA power-on configuration functionality, expands to 168 user I / O interfaces, and possesses abundant internal logic resources. Its through-hole design provides engineers with a simplified FPGA solution, significantly reducing design complexity and time.

[0026] The FPGA is the core control unit of the lower-level machine. The logic design is implemented using the hardware description language (Verilog HDL) and the integrated development kit ISE14.7. The top-level design of the FPGA logic control module includes sub-modules such as clock management and system reset, W5500 control, data processing, channel switching, AD acquisition control, and STM32 control. The top-level module is responsible for the connection and logic synthesis of each sub-module.

[0027] Ethernet TCP / IP communication module The Ethernet TCP / IP communication module mainly uses the WIZnet W5500, a multi-functional all-hardware Ethernet interface chip. It integrates a 10 / 100 M Ethernet controller, embeds TOE technology, and supports protocols such as TCP, UDP, and IPv4. There is no need to consider the internal layer relationships of the protocols, and it does not involve the operating system. As long as it is configured correctly, network connection can be achieved. The interface circuit is simple and the programming is flexible and convenient.

[0028] Channel Management and Switching Module The channel management and switching module consists of a channel selection chip (ADG1408YRUZ), a level conversion chip (LSF0108DCUR), a control switching chip (ADG819BRM), and a relay (G3FD-X03SN) to enable the selection, driving, and control of different peripheral interface pins. The channel selection chip enables one-to-eight-channel selection; the control switching chip and relay control whether external input channels are connected; the FPGA pin output level is 3.3V, which is difficult to directly drive peripheral devices, so the level conversion chip converts the output to 5V to improve the driving capability.

[0029] When the data parsing module receives the channel switching command, the FPGA controls the peripheral chips through the channel switching submodule, and manages and switches multiple different channels.

[0030] 2.4 ADC Signal Acquisition Module: The ADC signal acquisition module consists of voltage acquisition and signal conditioning submodules. The voltage acquisition submodule uses the high-precision analog-to-digital converter chip AD7609BSTZ from Analog Devices (ADI). It is an 18-bit, 8-channel, true differential, synchronous sampling analog-to-digital data acquisition system (DAS) with a maximum throughput of 200 kS / s. This system uses two AD7609 chips to acquire the voltage and current of the eight measured channels respectively, with an analog signal input range of ±5 V. At the acquisition front end, the signal conditioning submodule is connected, using a current-to-voltage converter chip (MAX4080SASA+) to convert the measured current signal into an analog voltage signal. This voltage signal is then divided by a voltage signal conditioning chip (AD8276ARZ) and appropriate high-precision resistors, ensuring that the measured analog signal input to the AD chip is within the range of -5 V to +5 V.

[0031] After the FPGA completes the channel management and switching, it initiates AD acquisition of the 8 channels connected to the test through the AD acquisition control submodule. The sampling frequency is 10 kHz, with 16 channels acquired in parallel, and the sampling speed reaches 2.88 Mb / s (16×18 bit×10kHz / s). The AD acquisition control submodule operates in a serial mode. After each acquisition, the data is handed over to the data processing submodule for framing, and then transmitted to the host PC via the W5500 using the TCP / IP protocol.

[0032] like Figure 3As shown, the filter circuit module includes chip IC1, capacitors C8, C15, C16, C18, and C20, resistors R8, R12, C22, C24, R13, R14, and R15. One end of capacitor C15 is connected to the signal input terminal. The other end of capacitor C15, one end of capacitor C8, one end of capacitor C16, and one end of resistor R12 are connected together. The other end of capacitor C16, one end of resistor R8, and pin 2 of chip IC1 are connected together. The other end of capacitor C8, the other end of resistor R8, and pin 1 of chip IC1 are connected together to serve as the output terminal of the second-order low-pass filter circuit. Pin 11 of chip IC1 is grounded. The other end of resistor R12 is connected to pin 3 of chip IC1 and then grounded. Pin 4 of chip IC1, one end of capacitor C18, and one end of capacitor C20 are connected together. Connect to a 5V power supply. The other end of capacitor C18 and the negative terminal of capacitor C20 are connected to ground. The IC1 chip shown is model LM324. Capacitors C8, C15, C16, and C18 are ceramic capacitors, and capacitor C20 is an electrolytic capacitor. One end of resistor R14 is connected to the output of the second-order low-pass filter circuit. The other end of resistor R14, one end of resistor R13, one end of capacitor C13, and one end of capacitor C24 are connected. The other end of resistor R15, one end of capacitor C22, and pin 6 of IC1 chip are connected. The other end of resistor R13, the other end of capacitor C22, and pin 7 of IC1 chip are connected to serve as the output of the second-order high-pass filter circuit. The other end of capacitor C24 is connected to pin 5 of IC1 chip and then grounded. The IC1 chip shown is model LM324, and capacitors C22 and C24 are ceramic capacitors.

[0033] To reduce noise interference, this invention designs a bandpass filter using a Butterworth filter with a smooth frequency response curve across the passband. This invention utilizes an LM324 to design a second-order low-pass filter and a second-order high-pass filter, thus forming a bandpass filter. The filtered signal is then provided to the microcontroller for direct sampling and analysis.

[0034] This invention utilizes the LM324, a common operational amplifier with a wide range of applications. It can operate in 3-32V power supply circuits, has low bias current, and can be internally compensated. Therefore, it is used in many circuits. The power rating of the components needs to be determined by consulting the datasheet to prevent damage caused by exceeding the output power. Generally, the maximum power required by the filter is affected by the power of the desired signal and the amount of unwanted noise. Since noise can be affected by various interferences, unwanted high-power signals may appear, so a component with slightly higher power should be selected to construct the filter. Regarding signal attenuation caused by the filter, useful signals within the passband often experience very little attenuation, ranging from 0.5 dB to 2.5 dB, mainly affected by the type of filter. However, unwanted signals outside the passband are significantly affected, effectively reducing interference outside the frequency band. During the design process, it is necessary to ensure that the signal attenuation within the passband is as small as possible, the attenuation outside the passband is as high as possible, and the passband flatness is guaranteed.

[0035] This invention designs a second-order Butterworth filter based on the LM324 operational amplifier. This type of filter has a flat passband, and its frequency response gradually changes outside the passband. By combining a high-pass filter and a low-pass filter, a band-pass filter is constructed, which reduces noise interference to the difference frequency signal.

[0036] like Figure 4As shown, the data transmission module includes an antenna ANT1, capacitors C11, C12, C13, C14, C15, and C16, resistors R21 and R22, inductors L11 and L12, and chips U1, U2, and U3. Antenna ANT1 is connected to one end of inductor L11 and one end of capacitor C16, with the other end of inductor L11 grounded. The other end of capacitor C16 is connected to one end of inductor L12 and pin 2 of chip U1, with the other end of inductor L12 grounded. Pins 3 and 4 of chip U1 are connected to one end of capacitor C14, one end of capacitor C15, and the VDD terminal, with the other ends of capacitors C14 and C15 grounded. Pin 1 of chip U1 is connected to one end of capacitor C13, the VDD terminal, pin 30 of chip U1, and pin 29 of chip U1, with the other end of capacitor C13 grounded. Pin 31 of chip U1 is connected to resistor R21. One end of resistor R21 is grounded, and the other end of resistor R21 is grounded. Pin 28 of chip U1 is connected to one end of capacitor C11 and pin 1 of chip U2. Pin 2 of chip U2 is grounded, and the other end of capacitor C11 is grounded. Pin 4 of chip U2 is grounded. Pin 3 of chip U2 is connected to one end of capacitor C12 and pin 27 of chip U1. The other end of capacitor C12 is grounded. Pin 18 of chip U1 is connected to pin 7 of chip U3. Pin 19 of chip U1 is connected to pin 3 of chip U3. Pin 20 of chip U1 is connected to pin 1 of chip U3. Pin 21 of chip U1 is connected to pin 6 of chip U3 through resistor R22. Pin 22 of chip U1 is connected to pin 2 of chip U3. Pin 23 of chip U1 is connected to pin 5 of chip U3. Pin 17 of chip U1 is connected to pin 11 of chip U1 and the VDD terminal.

[0037] It uses the ESP8266 as the main control chip. When used as a communication module, it connects the terminal device to the Internet for data transmission via serial-to-Wi-Fi conversion. The communication method adopts a basic network topology. The ESP8266 is a serial-to-wireless module chip with built-in firmware, which is simple for users to operate and does not require programming timing signals.

[0038] like Figure 5 As shown, the amplifier circuit module includes an LNA (low-noise amplifier), a power divider, a first filter, a second filter, a first amplifier, a second amplifier, a synthesizer, a third amplifier, and a third filter. The output of the LNA is connected to the input of the power divider, and the output of the power divider is connected to the inputs of the first and second filters. The outputs of the first and second filters are connected to the input of the synthesizer via the first and second amplifiers, respectively. The output of the synthesizer is connected to the input of the third filter via the third amplifier.

[0039] like Figure 6As shown, the interface circuit module includes the DALI_RX terminal of the MCU, the DALI_TX terminal of the MCU, the VCC voltage terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first diode, a second diode, a third diode, a first Zener diode, a first transistor, a second transistor, a third transistor, an LM317 chip, a voltage regulator chip, a first capacitor, a second capacitor, and a third capacitor. The VCC voltage terminal is connected to one end of the first capacitor, the Vin terminal of the voltage regulator chip, and the cathode of the first diode. The anode of the first diode is connected to the V0 terminal of the voltage regulator chip, the anode of the first diode, the cathode of the second diode, and the DA+ terminal. The other end of the first resistor is connected to one end of the second resistor, the ADJ terminal of the voltage regulator chip, the anode of the second diode, and one end of the second capacitor. The other end of the second resistor is connected to the second... The other end of the capacitor, the other end of the first capacitor, and the DA- terminal are grounded; the DA+ terminal is connected to the gate of the third transistor, one end of the seventh resistor, and the cathode of the Zener diode. The anode of the Zener diode is connected to one end of the fifth resistor and one end of the sixth resistor. The other end of the fifth resistor is connected to the cathode of the third diode, one end of the fourth resistor, and the 5V voltage terminal through the first transistor. The anode of the third diode is connected to the DALI_RX terminal of the MCU and one end of the third resistor. The other end of the third resistor is connected to the 3.3V voltage terminal. The gate of the third transistor is connected to one end of the tenth resistor and the collector of the second transistor through the eleventh resistor. The other end of the tenth resistor is connected to the 5V voltage terminal. The base of the second transistor is connected to one end of the eighth resistor and the DALI_TX terminal of the MCU through the ninth resistor. The other end of the eighth resistor is connected to the 3.3V voltage terminal. The other ends of the fourth, sixth, and seventh resistors, the emitter of the second transistor, and the DA- terminal are interconnected and grounded.

[0040] The interface circuit module of this invention uses the LM317 voltage regulator chip to provide the operating voltage for the MCU and the output stable voltage for the bus interface. In device transmission, it effectively improves the interface's anti-disturbance capability, can adapt to the level signal range specified by the DALI 2.0 standard, and improves the reliability of the system.

[0041] like Figure 7As shown, the clock module includes a clock chip DS3231, a capacitor C4, resistors R25, R26, R27, and R28. The VCC terminal is connected to one end of resistor R25 and one end of resistor R26. The other end of resistor R25 is connected to the SDA terminal of the clock chip DS3231, and the other end of resistor R26 is connected to the SCL terminal of the clock chip DS3231. The VDD terminal is connected to one end of resistor R27, one end of resistor R28, one end of capacitor C4, and port 2 of the clock chip DS3231. The other end of resistor R27 is connected to port 1 of the clock chip DS3231, and the other end of resistor R28 is connected to port 3 of the clock chip DS3231. The other end of capacitor C4 is grounded.

[0042] The clock circuit is designed and implemented using the low-cost, high-precision real-time clock chip DS3231. The DS3231's register addresses are 00h to 12h. It obtains clock and Hitachi information by reading appropriate register bytes and obtains clock and calendar information by writing appropriate register bytes. It also sets or initializes clock and calendar data by writing appropriate register bytes.

[0043] The fiber Bragg grating displacement sensor array uses an SR-RP-S1 type fiber Bragg grating displacement sensor, the fiber Bragg grating strain sensor array uses a GSYC-T1 type fiber Bragg grating strain sensor, and the acceleration sensor uses a ServoK-Beam8330A type servo acceleration sensor.

[0044] like Figure 8 As shown, the power module includes an AC power module, a PV photovoltaic module, a power conversion circuit, a battery, a boost module, and a voltage regulator module. The output of the AC power module is connected to the input of the microprocessor module. The output of the PV photovoltaic module is connected to the input of the battery through the power conversion circuit. The input and output of the battery are connected to the input of the microprocessor module through the boost module and the voltage regulator module in sequence.

[0045] like Figure 9 As shown, the power conversion circuit includes a DC 12V voltage input terminal, a first diode, a first capacitor, a second capacitor, an LM2576S-5.0 power chip, a second diode, a first inductor, a third capacitor, a 5V voltage output terminal, a 5V voltage input terminal, a fourth capacitor, a TPS7A7001 power chip, a first resistor, a second resistor, a fifth capacitor, and a 3.3V voltage output terminal. The DC12V voltage input terminal is connected to the negative terminal of the first diode, one end of the first capacitor, one end of the second capacitor, and the VIN terminal of the LM2576S-5.0 power chip. The other end of the first diode is connected to the other end of the first capacitor, the other end of the second capacitor, the EN# terminal of the LM2576S-5.0 power chip, the GND terminal of the LM2576S-5.0 power chip, the positive terminal of the second diode, and one end of the third capacitor and grounded. The negative terminal of the second diode is connected to the VOUT terminal of the LM2576S-5.0 power chip and one end of the first inductor. The other end of the first inductor is connected to the other end of the third capacitor, the FB terminal of the LM2576S-5.0 power chip, and the 5V output terminal. The 5V input terminal is connected to one end of the fourth capacitor, the EN terminal of the TPS7A7001 power chip, and the IN terminal of the TPS7A7001 power chip. The other end of the fourth capacitor is grounded. The GND terminal of the TPS7A7001 power chip is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor and the FB terminal of the TPS7A7001 power chip. The other end of the second resistor is connected to one end of the fifth capacitor, the OUT terminal of the TPS7A7001 power chip, and the 3.3V output terminal. The other end of the fifth capacitor is grounded.

[0046] It adopts a dual power supply mode of solar power and mains power, which effectively avoids unexpected situations such as power outages caused by severe weather.

[0047] A detection method for a bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology, characterized by the following steps; Step 1, using fiber optic strain sensor, fiber optic displacement sensor, stiffness detection module, and acceleration sensor. The device collects real-time data on bridge stress, bridge main tower displacement, bridge vibration, bridge main tower displacement, and changes in the bridge's vertical distance. Step 2: The collected data is converted into electrical signals by the analog-to-digital converter module, the collected parameters are amplified by the amplifier module, and then the amplified parameters are filtered by the filter module before being uploaded to the data processing module. Step 3: Compare the detected bridge parameters with the preset parameters. If the parameters exceed the preset safety range, an alarm will be triggered. The alarm module issues an alarm, which then notifies supervisory personnel to carry out maintenance, completing functions such as real-time monitoring, data analysis and processing, bridge health status assessment, and bridge structural health early warning.

[0048] Finally, the following points should be noted: First, in the description of this application, it should be noted that, unless otherwise specified and limited, the terms "installation", "connection", and "linkage" should be interpreted broadly, and can be mechanical or electrical connections, or internal connections between two components, or direct connections. "Up", "down", "left", "right", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may change. Secondly: The accompanying drawings of the embodiments disclosed in this invention only involve the structures involved in the embodiments disclosed in this invention. Other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of this invention can be combined with each other. In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology, characterized in that: It includes a fiber Bragg grating strain sensor, a fiber Bragg grating displacement sensor, a stiffness detection module, an acceleration sensor, an analog-to-digital conversion module, an amplifier circuit module, a filter circuit module, a data processing module, a data transmission module, an interface module, a memory module, a display module, an alarm module, a clock module, and a power supply module; The fiber optic strain sensor, fiber optic displacement sensor, stiffness detection module, and acceleration sensor are connected to the data processing module in sequence via an analog-to-digital conversion module, an amplification circuit module, and a filtering circuit module. The data transmission module, interface module, data transmission module, memory module, display module, alarm module, clock module, and power supply module are connected to the data processing module. Among them, the fiber optic strain sensor is used to measure bridge stress. Fiber grating displacement sensor used to monitor the displacement of the main bridge tower. Accelerometers are used to measure the amount of vibration in bridges. Fiber optic grating displacement sensor is used to monitor the displacement of the main bridge tower. The stiffness testing module is used to measure the change in the vertical distance of the bridge. The analog-to-digital converter module is used to convert the acquired data into electrical signals; The amplifier circuit module is used to amplify the acquired parameters. The filtering circuit module is used to filter the amplified parameters. The data processing module is used to process the detection data parameters; The data transmission module is used to transmit the collected bridge data parameters; The interface module is used for data transmission; A memory module for storing bridge parameters; The display module is used to display the collected bridge parameters in real time. Alarm module, used for issuing alarms; The clock module is used to record time; The power module is used to provide the required electrical energy.

2. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The data processing module includes a channel switching unit, an AD acquisition control unit, a data processing unit, a clock and reset unit, a W5500 control unit, and an STM32 control unit. The data processing unit is connected to the channel management and switching module through the channel switching unit; the data processing unit is connected to the ADC signal acquisition module through the AD acquisition control unit; the data processing unit is connected to the power supply and clock module through the clock and reset unit; the data processing unit is connected to the Ethernet TCP / IP communication module through the W5500 control unit; and the data processing unit is connected to the STM32 control module through the STM32 control unit.

3. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The filtering circuit module includes chip IC1, capacitors C8, C15, C16, C18, C20, resistors R8, R12, C22, C24, R13, R14, and R15. One end of capacitor C15 is connected to the signal input terminal. The other end of capacitor C15, one end of capacitor C8, one end of capacitor C16, and one end of resistor R12 are connected together. The other end of capacitor C16, one end of resistor R8, and pin 2 of chip IC1 are connected together. The other end of capacitor C8, the other end of resistor R8, and pin 1 of chip IC1 are connected together to serve as the output terminal of the second-order low-pass filter circuit. Pin 11 of chip IC1 is grounded. The other end of resistor R12 is connected to pin 3 of chip IC1 and then grounded. Pin 4 of chip IC1, one end of capacitor C18, and one end of capacitor C20 are connected together. Connect to a 5V power supply. The other end of capacitor C18 and the negative terminal of capacitor C20 are connected to ground. The IC1 chip shown is model LM324. Capacitors C8, C15, C16, and C18 are ceramic capacitors, and capacitor C20 is an electrolytic capacitor. One end of resistor R14 is connected to the output of the second-order low-pass filter circuit. The other end of resistor R14, one end of resistor R13, one end of capacitor C13, and one end of capacitor C24 are connected. The other end of resistor R15, one end of capacitor C22, and pin 6 of IC1 chip are connected. The other end of resistor R13, the other end of capacitor C22, and pin 7 of IC1 chip are connected to serve as the output of the second-order high-pass filter circuit. The other end of capacitor C24 is connected to pin 5 of IC1 chip and then grounded. The IC1 chip shown is model LM324, and capacitors C22 and C24 are ceramic capacitors.

4. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The data transmission module includes an antenna ANT1, capacitors C11, C12, C13, C14, C15, and C16, resistors R21 and R22, inductors L11 and L12, and chips U1, U2, and U3. Antenna ANT1 is connected to one end of inductor L11 and one end of capacitor C16, with the other end of inductor L11 grounded. The other end of capacitor C16 is connected to one end of inductor L12 and pin 2 of chip U1, with the other end of inductor L12 grounded. Pins 3 and 4 of chip U1 are connected to one end of capacitor C14, one end of capacitor C15, and the VDD terminal, with the other ends of capacitors C14 and C15 grounded. Pin 1 of chip U1 is connected to one end of capacitor C13, the VDD terminal, pin 30 of chip U1, and pin 29 of chip U1, with the other end of capacitor C13... The circuit is grounded. Pin 31 of chip U1 is connected to one end of resistor R21, and the other end of resistor R21 is grounded. Pin 28 of chip U1 is connected to one end of capacitor C11 and pin 1 of chip U2. Pin 2 of chip U2 is grounded, and the other end of capacitor C11 is grounded. Pin 4 of chip U2 is grounded. Pin 3 of chip U2 is connected to one end of capacitor C12 and pin 27 of chip U1, and the other end of capacitor C12 is grounded. Pin 18 of chip U1 is connected to pin 7 of chip U3. Pin 19 of chip U1 is connected to pin 3 of chip U3. Pin 20 of chip U1 is connected to pin 1 of chip U3. Pin 21 of chip U1 is connected to pin 6 of chip U3 through resistor R22. Pin 22 of chip U1 is connected to pin 2 of chip U3. Pin 23 of chip U1 is connected to pin 5 of chip U3. Pin 17 of chip U1 is connected to pin 11 of chip U1 and the VDD terminal.

5. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The amplifier circuit module includes an LNA (low noise amplifier), a power divider, a first filter, a second filter, a first amplifier, a second amplifier, a synthesizer, a third amplifier, and a third filter. The output of the LNA is connected to the input of the power divider, and the output of the power divider is connected to the inputs of the first and second filters. The outputs of the first and second filters are connected to the input of the synthesizer via the first and second amplifiers, respectively. The output of the synthesizer is connected to the input of the third filter via the third amplifier.

6. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The interface circuit module includes the MCU's DALI_RX terminal, the MCU's DALI_TX terminal, a VCC voltage terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first diode, a second diode, a third diode, a first Zener diode, a first transistor, a second transistor, a third transistor, an LM317 chip, a voltage regulator chip, a first capacitor, a second capacitor, and a third capacitor. The VCC voltage terminal is connected to one end of the first capacitor, the Vin terminal of the voltage regulator chip, and the cathode of the first diode. The anode of the first diode is connected to the V0 terminal of the voltage regulator chip, the anode of the first diode, the cathode of the second diode, and the DA+ terminal. The other end of the first resistor is connected to one end of the second resistor, the ADJ terminal of the voltage regulator chip, the anode of the second diode, and one end of the second capacitor. The other end of the second resistor is connected to the second capacitor. The other end, the other end of the first capacitor, the DA- terminal and ground are connected; the DA+ terminal is connected to the gate of the third transistor, one end of the seventh resistor, and the cathode of the Zener diode. The anode of the Zener diode is connected to one end of the fifth resistor and one end of the sixth resistor. The other end of the fifth resistor is connected to the cathode of the third diode, one end of the fourth resistor and the 5V voltage terminal through the first transistor. The anode of the third diode is connected to the DALI_RX terminal of the MCU and one end of the third resistor. The other end of the third resistor is connected to the 3.3V voltage terminal. The gate of the third transistor is connected to one end of the tenth resistor and the collector of the second transistor through the eleventh resistor. The other end of the tenth resistor is connected to the 5V voltage terminal. The base of the second transistor is connected to one end of the eighth resistor and the DALI_TX terminal of the MCU through the ninth resistor. The other end of the eighth resistor is connected to the 3.3V voltage terminal. The other ends of the fourth resistor, the sixth resistor, and the seventh resistor are connected to the emitter of the second transistor and the DA- terminal and grounded.

7. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that: The clock module includes a clock chip DS3231, a capacitor C4, resistors R25, R26, R27, and R28. The VCC terminal is connected to one end of resistor R25 and one end of resistor R26. The other end of resistor R25 is connected to the SDA terminal of the clock chip DS3231. The other end of resistor R26 is connected to the SCL terminal of the clock chip DS3231. The VDD terminal is connected to one end of resistor R27, one end of resistor R28, one end of capacitor C4, and port 2 of the clock chip DS3231. The other end of resistor R27 is connected to port 1 of the clock chip DS3231. The other end of resistor R28 is connected to port 3 of the clock chip DS3231. The other end of capacitor C4 is grounded.

8. The method and system for detecting bridge and tunnel alignment and stiffness based on fiber optic sensing technology according to claim 1, characterized in that, The fiber Bragg grating displacement sensor array uses an SR-RP-S1 type fiber Bragg grating displacement sensor, the fiber Bragg grating strain sensor array uses a GSYC-T1 type fiber Bragg grating strain sensor, and the acceleration sensor uses a ServoK-Beam8330A type servo acceleration sensor.

9. The bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology according to claim 1, characterized in that, The power module includes an AC power module, a PV photovoltaic module, a power conversion circuit, a battery, a boost module, and a voltage regulator module. The output of the AC power module is connected to the input of the microprocessor module. The output of the PV photovoltaic module is connected to the input of the battery through the power conversion circuit. The input and output of the battery are connected to the input of the microprocessor module through the boost module and the voltage regulator module in sequence. The power conversion circuit includes a DC 12V voltage input terminal, a first diode, a first capacitor, a second capacitor, an LM2576S-5.0 power chip, a second diode, a first inductor, a third capacitor, a 5V voltage output terminal, a 5V voltage input terminal, a fourth capacitor, a TPS7A7001 power chip, a first resistor, a second resistor, a fifth capacitor, and a 3.3V voltage output terminal. The DC12V voltage input terminal is connected to the negative terminal of the first diode, one end of the first capacitor, one end of the second capacitor, and the VIN terminal of the LM2576S-5.0 power chip. The other end of the first diode is connected to the other end of the first capacitor, the other end of the second capacitor, the EN# terminal of the LM2576S-5.0 power chip, the GND terminal of the LM2576S-5.0 power chip, the positive terminal of the second diode, and one end of the third capacitor and grounded. The negative terminal of the second diode is connected to the VOUT terminal of the LM2576S-5.0 power chip and one end of the first inductor. The other end of the first inductor is connected to the other end of the third capacitor, the FB terminal of the LM2576S-5.0 power chip, and the 5V output terminal. The 5V input terminal is connected to one end of the fourth capacitor, the EN terminal of the TPS7A7001 power chip, and the IN terminal of the TPS7A7001 power chip. The other end of the fourth capacitor is grounded. The GND terminal of the TPS7A7001 power chip is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor and the FB terminal of the TPS7A7001 power chip. The other end of the second resistor is connected to one end of the fifth capacitor, the OUT terminal of the TPS7A7001 power chip, and the 3.3V output terminal. The other end of the fifth capacitor is grounded.

10. A detection method for a bridge and tunnel alignment and stiffness detection system based on fiber optic sensing technology as described in any one of claims 1 to 9, characterized in that: Specifically, it includes the following steps; Step 1: Real-time data acquisition of bridge stress, bridge main tower displacement, bridge vibration, and changes in bridge vertical distance are obtained using fiber optic strain sensors, fiber optic displacement sensors, stiffness detection modules, and acceleration sensors. Step 2: The collected data is converted into electrical signals by the analog-to-digital converter module, the collected parameters are amplified by the amplifier module, and then the amplified parameters are filtered by the filter module before being uploaded to the data processing module. Step 3: Compare the detected bridge parameters with the preset parameters. If the parameters exceed the preset safety range, an alarm will be issued through the alarm module, thereby notifying the supervisory personnel to carry out maintenance.

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