A multi-parameter detection method and system for a SiC-based MOS structure transistor

Abstract

The present application relates to the technical field of multi-parameter detection, and a SiC-based MOS structure transistor multi-parameter detection method and system, comprising: obtaining static evaluation parameters, obtaining normal single-cycle current waveband, drain-source voltage waveform diagram, drain current waveform diagram and cycle gate-source voltage sequence, obtaining dynamic evaluation parameters, inputting the static evaluation parameters and the dynamic evaluation parameters into a pre-constructed deep learning model to obtain a comprehensive performance score, if the comprehensive performance score is greater than a preset comprehensive performance score threshold, regarding the SiC MOS structure transistor to be detected as a qualified SiC MOS structure transistor, otherwise, regarding the SiC MOS structure transistor to be detected as a defective SiC MOS structure transistor, and completing SiC-based MOS structure transistor multi-parameter detection based on the qualified SiC MOS structure transistor or the defective SiC MOS structure transistor. The present application can improve the reliability of SiC MOS devices and optimize the application performance thereof.

Description

Technical Field

[0001] This invention relates to the field of multi-parameter detection technology, and in particular to a method and system for multi-parameter detection of SiC-based MOS structure transistors. Background Technology

[0002] SiC refers to silicon carbide, a wide bandgap compound semiconductor material with high critical breakdown electric field, high thermal conductivity, and high saturation drift velocity. It is used to manufacture power devices that can withstand high voltage, high temperature, and high frequency. A MOS structure transistor is a field-effect transistor with a metal-oxide-semiconductor structure as its core, including at least three terminals: gate, drain, and source. The drain-source current is controlled by the gate electric field.

[0003] Traditional detection and characterization methods have significant limitations. Firstly, they typically focus on measuring a single parameter. Secondly, most characterization techniques (such as deep-level transient spectroscopy and traditional CV testing) require offline testing on specific equipment, failing to reflect the dynamic behavior of the device in actual operating circuits and hindering state monitoring during operation. Therefore, improving the reliability of SiC MOS devices and optimizing their application performance are urgent technical challenges. Summary of the Invention

[0004] This invention provides a multi-parameter detection method for SiC-based MOS structure transistors and a computer-readable storage medium. Its main purpose is to improve the intelligence level of high-temperature testing of titanium rods and reduce the excessive consumption of time and human resources.

[0005] To achieve the above objectives, this invention provides a multi-parameter detection method for SiC-based MOS structure transistors, comprising:

[0006] The SiC MOS structure transistor under test and the detection unit were identified. The SiC MOS structure transistor under test includes: gate, drain and source.

[0007] The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0008] Based on the static evaluation parameters obtained from the connected gate, connected drain, and connected source, the voltage of the connected drain and connected gate is switched to obtain the switched drain and switched gate.

[0009] Based on the switched drain, switched gate, and connected source, obtain the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0010] Dynamic evaluation parameters are obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0011] Receive multi-parameter detection instructions, and input static evaluation parameters and dynamic evaluation parameters into the pre-built deep learning model according to the multi-parameter detection instructions to obtain a comprehensive performance score;

[0012] If the overall performance score is greater than the preset overall performance score threshold, the SiC MOS structure transistor under test will be regarded as a qualified SiC MOS structure transistor.

[0013] Otherwise, the SiC MOS structure transistor under test will be considered a defective SiC MOS structure transistor;

[0014] Multi-parameter detection of SiC-based MOS structure transistors was performed using qualified or defective SiC MOS structure transistors.

[0015] Optionally, obtaining static evaluation parameters based on the connected gate, connected drain, and connected source includes:

[0016] The first DC bias voltage and the triangular wave scanning voltage are obtained from the detection unit. The connected drain and the connected gate are synchronously tested using the first DC bias voltage, the preset sampling rate and the triangular wave scanning voltage to obtain the drain current response value sequence and the gate voltage value sequence. The drain voltage response value sequence includes multiple drain voltage response values ​​and the gate voltage value sequence includes multiple gate voltage values. The drain voltage response value and the gate voltage value correspond one-to-one.

[0017] The static parameters are calculated based on the drain current response sequence and the gate voltage sequence. The static parameters include: threshold voltage, hysteresis window, subthreshold swing and channel on-resistance.

[0018] The first DC bias voltage, triangular wave scanning voltage, and static parameters are stored to obtain static evaluation parameters.

[0019] Optionally, the step of calculating the static parameters based on the drain current response sequence and the gate voltage sequence includes:

[0020] A forward differential operation is performed on the gate voltage value sequence to obtain a gate voltage difference sequence. Gate voltage differences are extracted sequentially from the gate voltage difference sequence, and the extracted gate voltage differences are removed from the gate voltage difference sequence to obtain an updated gate voltage difference sequence.

[0021] Compare the extracted gate voltage difference with a preset positive threshold;

[0022] If the extracted gate voltage difference is greater than the positive threshold, then return to the step of extracting gate voltage differences sequentially from the gate voltage difference sequence until the extracted gate voltage difference is not greater than the positive threshold. Then, the gate voltage difference that is not greater than the positive threshold is used as the reverse scan difference, and the adjacent gate voltage difference is obtained from the updated gate voltage difference sequence based on the reverse scan difference.

[0023] The inflection point time is determined based on the difference between adjacent gate voltages. The gate voltage value sequence is then divided based on the inflection point time to obtain the forward scan voltage value sequence and the reverse scan voltage value sequence.

[0024] A transfer characteristic curve is constructed based on the forward scanning voltage value sequence. The transfer characteristic curve is numerically differentiated to obtain the transconductance sequence. The transconductance with the largest value in the transconductance sequence is taken as the forward scanning threshold voltage.

[0025] The reverse scanning threshold voltage is obtained based on the reverse scanning voltage value sequence. The hysteresis window is calculated based on the forward scanning threshold voltage and the reverse scanning threshold voltage. The hysteresis window is the absolute difference between the forward scanning threshold voltage and the reverse scanning threshold voltage.

[0026] A subthreshold sequence is selected from the transfer characteristic curve, and a linear fit is performed on the subthreshold sequence to obtain a fitted line. The subthreshold swing is calculated based on the fitted line, and the channel on-resistance is calculated based on the forward scan voltage value sequence and the drain current response value sequence.

[0027] The static parameters were determined based on the threshold voltage, hysteresis window, subthreshold swing, and channel on-resistance.

[0028] Optionally, the step of calculating the channel on-resistance based on the forward scan voltage value sequence and the drain current response value sequence includes:

[0029] The scanning endpoint voltage is identified from the forward scanning voltage value sequence, and the voltage stability lower limit is calculated based on the preset voltage relative error threshold and the scanning endpoint voltage.

[0030] The preceding scan voltage value is obtained from the forward scan voltage value sequence based on the scan endpoint voltage;

[0031] If the preceding scan voltage value is greater than or equal to the lower voltage stability limit, then the preceding scan voltage index is determined based on the preceding scan voltage value, the target drain current index is determined from the drain current response value sequence based on the preceding scan voltage index, the drain current response value corresponding to the target drain current index is taken as the final current, the preceding scan voltage value is taken as the scan endpoint voltage, and the step of obtaining the preceding scan voltage value from the forward scan voltage value sequence based on the scan endpoint voltage is returned until the preceding scan voltage value is less than the lower voltage stability limit;

[0032] Summarize the final currents to obtain the final current set, and calculate the maximum conducting current based on the final current set, where the maximum conducting current is the average value of the final current set;

[0033] The channel on-resistance is calculated based on the maximum on-current and the first DC bias voltage, where the channel on-resistance is the value obtained by dividing the first DC bias voltage by the maximum on-current.

[0034] Optionally, the step of obtaining the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence based on the switched drain, switched gate, and connected source includes:

[0035] Using a preset dynamic sampling rate, signals from the switched drain, switched gate, and connected source are synchronously acquired to obtain the gate-source voltage sequence, gate current sequence, drain-source voltage sequence, and drain current sequence.

[0036] Construct gate current waveforms, drain-source voltage waveforms, and drain current waveforms based on the gate current sequence, drain-source voltage sequence, and drain current sequence;

[0037] The single-cycle current band set is identified from the gate current waveform diagram, and the single-cycle current band set is sorted according to the time sequence to obtain the single-cycle current band sequence.

[0038] The target single-cycle current band is identified from the single-cycle current band sequence, and the target gate current sequence is identified based on the target single-cycle current band.

[0039] Based on the target gate current sequence, a periodic gate-source voltage sequence is identified from the gate-source voltage sequence. A discrete integration operation is then performed on the target gate current sequence to obtain the gate charge sequence.

[0040] The normal gate charge set is identified based on the gate charge sequence, and the target single-cycle current band corresponding to the normal gate charge set is taken as the normal single-cycle current band.

[0041] Optionally, the step of identifying the normal gate charge set based on the gate charge sequence includes:

[0042] Gate charges are extracted sequentially from the gate charge sequence, and adjacent gate charges are identified from the gate charge sequence based on the extracted gate charges, wherein adjacent gate charges are adjacent and lag behind the extracted gate charges;

[0043] If the extracted gate charge is less than the adjacent gate charge, the gate charge sequence is regarded as an abnormal gate charge sequence and is removed from the single-cycle current band sequence to obtain an updated cycle current band sequence. The updated cycle current band sequence is regarded as a single-cycle current band sequence, and the step of identifying the target single-cycle current band from the single-cycle current band sequence is returned until the extracted gate charge is not less than the adjacent gate charge.

[0044] If the extracted gate charge is not less than the adjacent gate charge, then the extracted gate charge is taken as the normal gate charge.

[0045] The normal gate charge is summed to obtain the normal gate charge set.

[0046] Optionally, the step of obtaining dynamic evaluation parameters based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence includes:

[0047] Based on the normal single-cycle current waveform, the drain-source voltage waveform and drain current waveform can be identified.

[0048] The normal gate charge set is arranged in ascending order to obtain the normal gate charge sequence;

[0049] The periodic gate-source voltage sequence is combined with the normal gate charge sequence to obtain a combined data pair set, wherein the combined data pair set includes multiple combined data pairs, and each combined data pair includes a periodic gate-source voltage and a normal gate charge.

[0050] Gate charge curves are constructed based on the combined data set, where the horizontal axis of the gate charge curve represents the normal gate charge, and the vertical axis of the gate charge curve represents the periodic gate-source voltage.

[0051] Gate charge parameters are obtained based on the gate charge curve, and switching speed parameters and switching energy loss parameters are obtained based on the drain-source voltage band and drain current band.

[0052] By integrating gate charge parameters, switching speed parameters, and switching energy loss parameters, dynamic evaluation parameters are obtained.

[0053] Optionally, obtaining the gate charge parameters based on the gate charge curve includes:

[0054] The Miller plateau curve segment is identified based on the gate charge curve. The gate-source voltage set of the plateau period is determined based on the Miller plateau curve segment. The Miller plateau voltage of the gate-source voltage set of the plateau period is calculated, where the Miller plateau voltage is the average value of the gate-source voltage set of the plateau period.

[0055] The periodic gate-source voltage is extracted sequentially from the gate charge curve, and the extracted periodic gate-source voltage is compared with the preset peak gate voltage.

[0056] If the extracted periodic gate-source voltage is not equal to the peak gate voltage, then return to the step of sequentially extracting the periodic gate-source voltage from the gate charge curve until the extracted periodic gate-source voltage is equal to the peak gate voltage.

[0057] If the extracted periodic gate-source voltage is equal to the peak gate voltage, then the normal gate charge corresponding to the extracted periodic gate-source voltage is taken as the total gate charge.

[0058] The gate charge parameters were determined based on the Miller plateau voltage and total gate charge.

[0059] Optionally, the step of obtaining switching speed parameters and switching energy loss parameters based on the drain-source voltage band and drain current band includes:

[0060] The falling drain voltage sequence and the rising drain voltage sequence were identified from the drain-source voltage band.

[0061] Linear fitting is performed on the falling drain voltage sequence to obtain the turn-on voltage drop rate, and linear fitting is performed on the rising drain voltage sequence to obtain the turn-on voltage rise rate.

[0062] The turn-on current decrease rate and turn-on current rise rate are obtained based on the drain current band, and the turn-on process integral interval and turn-off process integral interval are determined based on the normal single-cycle current band and drain-source voltage band.

[0063] The normal current sequence and voltage sequence of the turn-on process are determined based on the integral interval of the turn-on process, and the instantaneous power curve of the turn-on process is constructed based on the normal current sequence and voltage sequence of the turn-on process.

[0064] Numerical integration is performed on the instantaneous power curve during turn-on to obtain the energy loss value during a single turn-on, and the energy loss during a single turn-off is obtained based on the integration interval of the turn-off process.

[0065] The switching speed parameters are determined based on the turn-on voltage drop rate, turn-on voltage rise rate, turn-on current drop rate, and turn-on current rise rate.

[0066] The switching energy loss parameters are determined based on the energy loss value of a single turn-on and a single turn-off.

[0067] To achieve the above objectives, the present invention also provides a multi-parameter detection system for SiC-based MOS structure transistors, comprising:

[0068] The transistor test preparation module is used to identify the SiC MOS structure transistor under test and the detection unit. The SiC MOS structure transistor under test includes a gate, a drain, and a source. The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0069] The static parameter acquisition module is used to acquire static evaluation parameters based on the connected gate, connected drain and connected source, and to switch the voltage of the connected drain and connected gate to obtain the switched drain and switched gate.

[0070] The dynamic parameter acquisition module is used to acquire normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence based on the switched drain, switched gate and connected source, and to acquire dynamic evaluation parameters based on normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence.

[0071] The intelligent judgment module receives multi-parameter detection instructions and inputs static and dynamic evaluation parameters into a pre-built deep learning model according to the instructions to obtain a comprehensive performance score. If the comprehensive performance score is greater than a preset comprehensive performance score threshold, the SiC MOS structure transistor under test is considered a qualified SiC MOS structure transistor; otherwise, it is considered a defective SiC MOS structure transistor. The multi-parameter detection of SiC-based MOS structure transistors is completed based on qualified or defective SiC MOS structure transistors.

[0072] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0073] Memory, storing at least one instruction;

[0074] The processor executes the instructions stored in the memory to implement the above-described multi-parameter detection method for SiC-based MOS structure transistors.

[0075] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the above-described SiC-based MOS structure transistor multi-parameter detection method.

[0076] To address the problems described in the background art, this invention identifies the SiC MOS structure transistor under test and the detection unit. The SiC MOS structure transistor under test includes a gate, a drain, and a source. This invention accurately determines the SiC structure under test. The MOS structure transistor and its corresponding detection unit ensure that subsequent detection processes target the correct object, avoiding detection errors or confusion, and ensuring the accuracy and specificity of the detection. Connecting the gate, drain, and source to the detection unit yields a connected gate, connected drain, and connected source. This invention establishes an electrical connection between the transistor under test and the detection unit, enabling signal interaction between the detection unit and the transistor. This provides a physical channel for acquiring various transistor parameters. Only with correct connection can the detection unit accurately acquire and measure relevant electrical signals of the transistor, thus ensuring the reliability of subsequent parameter acquisition. Static evaluation parameters are obtained based on the connected gate, connected drain, and connected source. Voltage switching is performed on the connected drain and connected gate to obtain a switched drain and switched gate. This invention simulates the transistor's behavior under different operating states, allowing the transistor to enter a dynamic operating mode, creating conditions for subsequent dynamic parameter acquisition. Different voltage states can excite different electrical responses in the transistor, thus more comprehensively detecting its performance. Normal single-cycle current bands, drain-source voltage waveforms, and drain current are obtained based on the switched drain, switched gate, and connected source. The waveform diagrams and periodic gate-source voltage sequences of this invention reflect the performance of transistors during dynamic operation. By acquiring dynamic evaluation parameters, a deeper understanding of the transistor's performance during dynamic operation can be achieved, providing a more accurate basis for evaluating the transistor's practical application capabilities. Based on normal single-cycle current bands, drain-source voltage waveforms, drain current waveforms, and periodic gate-source voltage sequences, dynamic evaluation parameters are obtained. These parameters comprehensively reflect the transistor's performance and characteristics during actual operation. Compared to static evaluation parameters, dynamic evaluation parameters consider the transistor's dynamic response during switching. The invention receives multi-parameter detection commands and inputs both static and dynamic evaluation parameters into a pre-built deep learning model to obtain a comprehensive performance score. This invention utilizes a deep learning model for comprehensive analysis, enabling a more comprehensive and objective evaluation of transistor performance. The deep learning model can process large amounts of complex data and uncover potential relationships between parameters, thus providing a comprehensive performance score. This avoids the limitations of single-parameter evaluation and more accurately reflects the overall performance of the transistor. If the comprehensive performance score exceeds a preset comprehensive performance score threshold, the SiC under test is... As a qualified SiC MOS structure transistor, this invention provides a clear standard for judging whether a transistor is qualified by setting a comprehensive performance scoring threshold. This quantitative judgment method is simple and intuitive, and can quickly and accurately screen out qualified and defective transistors.This invention facilitates the classification and subsequent processing of transistors, improving the efficiency and accuracy of production quality control. Otherwise, the SiC MOS structure transistor under test is treated as a defective SiC MOS structure transistor, and multi-parameter testing of SiC-based MOS structure transistors is performed based on either qualified or defective SiC MOS structure transistors. Therefore, this invention can improve the reliability of SiC MOS devices and optimize their application performance. Attached Figure Description

[0077] Figure 1 This is a flowchart illustrating a multi-parameter detection method for SiC-based MOS structure transistors according to an embodiment of the present invention.

[0078] Figure 2 A functional block diagram of a SiC-based MOS transistor multi-parameter detection system provided in an embodiment of the present invention;

[0079] Figure 3 This is a schematic diagram of an electronic device that implements the multi-parameter detection method for SiC-based MOS structure transistors, according to an embodiment of the present invention.

[0080] Explanation of reference numerals in the attached figures:

[0081] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0082] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0083] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0084] This application provides a method for multi-parameter detection of SiC-based MOS transistors. The executing entity of this SiC-based MOS transistor multi-parameter detection method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the SiC-based MOS transistor multi-parameter detection method can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0085] Reference Figure 1 The diagram shown is a flowchart illustrating a multi-parameter detection method for a SiC-based MOS transistor according to an embodiment of the present invention. In this embodiment, the SiC-based MOS transistor multi-parameter detection method includes:

[0086] S1. Identify the SiC MOS structure transistor under test and the detection unit. The SiC MOS structure transistor under test includes: gate, drain and source.

[0087] It should be explained that the SiC MOS structure transistor under test refers to a testable discrete device or chip-level unit using silicon carbide (SiC) as the semiconductor material and possessing a metal-oxide-semiconductor (MOS) structure. It includes at least three external terminals: gate, drain, and source, and is used to withstand static and dynamic electrical stress tests. The detection unit refers to a test hardware device that integrates a controllable voltage source, a current sampling module, a timing control module, and a signal processing module. Its output port can form conductive connections with the gate, drain, and source of the SiC MOS structure transistor under test to provide bias voltage, scan waveforms, and sample voltage-current response data.

[0088] S2. Connect the gate, drain, and source to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0089] It should be explained that connecting the gate, drain, and source to the detection unit means connecting the gate, drain, and source to the precision voltage source and high-speed data acquisition unit of the detection unit, respectively. This ensures good electromagnetic shielding in the testing environment to reduce noise interference. A connected gate refers to a gate that has already been connected, the purpose of which is to apply and control the gate voltage. A connected drain refers to a drain that has already been connected, the purpose of which is to apply the drain voltage and acquire the drain current. A connected source refers to a source that has already been connected, the purpose of which is to provide a stable reference potential.

[0090] S3. Based on the connected gate, connected drain and connected source, obtain static evaluation parameters, and perform voltage switching on the connected drain and connected gate to obtain the switched drain and switched gate.

[0091] Specifically, obtaining static evaluation parameters based on the connected gate, connected drain, and connected source includes:

[0092] The first DC bias voltage and the triangular wave scanning voltage are obtained from the detection unit. The connected drain and the connected gate are synchronously tested using the first DC bias voltage, the preset sampling rate and the triangular wave scanning voltage to obtain the drain current response value sequence and the gate voltage value sequence. The drain voltage response value sequence includes multiple drain voltage response values ​​and the gate voltage value sequence includes multiple gate voltage values. The drain voltage response value and the gate voltage value correspond one-to-one.

[0093] The static parameters are calculated based on the drain current response sequence and the gate voltage sequence. The static parameters include: threshold voltage, hysteresis window, subthreshold swing and channel on-resistance.

[0094] The first DC bias voltage, triangular wave scanning voltage, and static parameters are stored to obtain static evaluation parameters.

[0095] It should be explained that the first DC bias voltage refers to a constant DC voltage signal provided by the detection unit and applied to the drain or gate of the device under test. This voltage is designed to keep the device operating in the linear region and avoid interference from high electric field effects. For example, the first DC bias voltage is 50mV. The triangular wave scan voltage refers to a periodically linearly varying voltage signal generated by the detection unit. Its waveform is triangular and is used to apply a continuously varying voltage to the gate or drain to scan the electrical response of the device at different operating points. For example, the triangular wave scan voltage is -5V. The sampling rate refers to the number of times the detection unit samples the voltage or current signal per unit time, used to determine the time resolution and accuracy of data acquisition. Synchronous detection means that during the test, the detection unit simultaneously applies the triangular wave scan voltage to the connected gate and the first DC bias voltage to the connected drain, and simultaneously acquires the response data of the gate voltage and drain current to ensure that the correspondence between the two in time is consistent. The drain current response sequence refers to multiple drain current values ​​continuously acquired by the detection unit at a sampling rate during synchronous testing. This sequence reflects the change in drain current of the device under different gate voltages. The gate voltage sequence refers to multiple gate voltage values ​​synchronously acquired by the detection unit at a sampling rate during synchronous testing. This sequence corresponds one-to-one with the drain current response sequence in time and is used to establish the relationship between gate voltage and drain current. Static evaluation parameters include, but are not limited to, threshold voltage, hysteresis window, subthreshold swing, and channel on-resistance.

[0096] Specifically, the calculation of static parameters based on the drain current response sequence and the gate voltage sequence includes:

[0097] A forward differential operation is performed on the gate voltage value sequence to obtain a gate voltage difference sequence. Gate voltage differences are extracted sequentially from the gate voltage difference sequence, and the extracted gate voltage differences are removed from the gate voltage difference sequence to obtain an updated gate voltage difference sequence.

[0098] Compare the extracted gate voltage difference with a preset positive threshold;

[0099] If the extracted gate voltage difference is greater than the positive threshold, then return to the step of extracting gate voltage differences sequentially from the gate voltage difference sequence until the extracted gate voltage difference is not greater than the positive threshold. Then, the gate voltage difference that is not greater than the positive threshold is used as the reverse scan difference, and the adjacent gate voltage difference is obtained from the updated gate voltage difference sequence based on the reverse scan difference.

[0100] The inflection point time is determined based on the difference between adjacent gate voltages. The gate voltage value sequence is then divided based on the inflection point time to obtain the forward scan voltage value sequence and the reverse scan voltage value sequence.

[0101] A transfer characteristic curve is constructed based on the forward scanning voltage value sequence. The transfer characteristic curve is numerically differentiated to obtain the transconductance sequence. The transconductance with the largest value in the transconductance sequence is taken as the forward scanning threshold voltage.

[0102] The reverse scanning threshold voltage is obtained based on the reverse scanning voltage value sequence. The hysteresis window is calculated based on the forward scanning threshold voltage and the reverse scanning threshold voltage. The hysteresis window is the absolute difference between the forward scanning threshold voltage and the reverse scanning threshold voltage.

[0103] A subthreshold sequence is selected from the transfer characteristic curve, and a linear fit is performed on the subthreshold sequence to obtain a fitted line. The subthreshold swing is calculated based on the fitted line, and the channel on-resistance is calculated based on the forward scan voltage value sequence and the drain current response value sequence.

[0104] The static parameters were determined based on the threshold voltage, hysteresis window, subthreshold swing, and channel on-resistance.

[0105] It should be explained that the forward differential operation steps are existing technology and will not be described in detail here. The gate voltage differential sequence refers to the ordered sequence of all gate voltage differentials directly output by the forward differential operation, used to characterize the instantaneous change in gate voltage. The updated gate voltage differential sequence refers to the sequence formed by the remaining gate voltage differentials after iterative removal of those already extracted. The positive threshold is a pre-set value used to compare with the extracted gate voltage differentials to confirm that the device is in the forward scan phase. The inflection point time refers to the sampling time corresponding to the reverse scan differential, used as the time boundary to divide the forward and reverse scan data. The forward scan voltage value sequence refers to all gate voltage value sequences before the inflection point time (including adjacent gate voltage differentials). The reverse scan voltage value sequence refers to all gate voltage value sequences after the inflection point time (including adjacent gate voltage differentials). The steps for constructing the transfer characteristic curve based on the forward scanning voltage value sequence are as follows: Obtain the index value set of the forward scanning voltage value sequence; determine the forward drain current value sequence from the drain current response value sequence based on the index value set; and construct the transfer characteristic curve based on the forward scanning voltage value sequence and the forward drain current value sequence. The horizontal axis of the transfer characteristic curve represents the forward scanning voltage value, and the vertical axis represents the forward drain current value. The index value set refers to the set of index values ​​corresponding to each forward scanning voltage value in the forward scanning voltage value sequence. The forward drain current value sequence refers to the sequence of drain current response values ​​in the drain current response value sequence that corresponds to each index value in the index value set. Adjacent gate voltage differentials refer to the updated gate voltage differential sequence that is adjacent to and precedes the reverse scanning differential sequence. For example, if the updated gate voltage differential sequence is {F, G, H, I, J}, where H is the reverse scanning differential, then G is the adjacent gate voltage differential. If the extracted gate voltage difference is greater than a positive threshold, it clearly indicates that the SiC MOS structure transistor under test is in the forward gate voltage scan phase. At this time, the gate oxide interface traps are in a continuously filling state and a stable conductive channel has not yet been established on the semiconductor surface. Based on this criterion, the cyclic monitoring mechanism accurately captures the state transition critical point from forward scan to reverse scan by tracking the gate voltage change trend in real time. The continuous filling state of the gate oxide interface traps means that during the process of gate voltage increase, the injected electrons are continuously and one by one filling the defects at the gate oxide interface (bond breakage, atomic dislocation, and impurities caused by atomic-level imperfections at the SiC and SiO2 interface), rather than all of them being used to establish a conductive channel.

[0106] Understandably, the transconductance sequence refers to the sequence of all transconductances generated by numerical differentiation, reflecting the relationship between the device's transconductance and the gate voltage. The forward scan threshold voltage refers to the maximum transconductance in the transconductance sequence. The method for obtaining the reverse scan threshold voltage based on the reverse scan voltage value sequence is the same as the method for obtaining the forward scan threshold voltage based on the forward scan voltage value sequence, and will not be repeated here. The step of selecting the subthreshold sequence from the transfer characteristic curve is as follows: the drain current is transferred from... A grew to All forward scan voltage values ​​within the gate voltage interval corresponding to A are considered as the subthreshold sequence. Linear fitting of the subthreshold sequence refers to using the least squares method to linearly fit the subthreshold sequence. The fitted line is the straight line obtained through linear fitting. The subthreshold swing refers to the slope of the fitted line.

[0107] Specifically, the calculation of the channel on-resistance based on the forward scan voltage value sequence and the drain current response value sequence includes:

[0108] The scanning endpoint voltage is identified from the forward scanning voltage value sequence, and the voltage stability lower limit is calculated based on the preset voltage relative error threshold and the scanning endpoint voltage.

[0109] The preceding scan voltage value is obtained from the forward scan voltage value sequence based on the scan endpoint voltage;

[0110] If the preceding scan voltage value is greater than or equal to the lower voltage stability limit, then the preceding scan voltage index is determined based on the preceding scan voltage value, the target drain current index is determined from the drain current response value sequence based on the preceding scan voltage index, the drain current response value corresponding to the target drain current index is taken as the final current, the preceding scan voltage value is taken as the scan endpoint voltage, and the step of obtaining the preceding scan voltage value from the forward scan voltage value sequence based on the scan endpoint voltage is returned until the preceding scan voltage value is less than the lower voltage stability limit;

[0111] Summarize the final currents to obtain the final current set, and calculate the maximum conducting current based on the final current set, where the maximum conducting current is the average value of the final current set;

[0112] The channel on-resistance is calculated based on the maximum on-current and the first DC bias voltage, where the channel on-resistance is the value obtained by dividing the first DC bias voltage by the maximum on-current.

[0113] It should be explained that the scan endpoint voltage refers to the gate voltage value located at the very end of the time axis in the forward scan voltage value sequence, used to characterize the highest gate potential reached during this scan process. The voltage relative error threshold is a preset value used to multiply by the scan endpoint voltage to define the allowable deviation range required to determine voltage stability. The calculation formula for the lower limit of voltage stability in the step of calculating the lower limit of voltage stability based on the preset voltage relative error threshold and the scan endpoint voltage is as follows:

[0114] ;

[0115] in, Indicates the lower limit of voltage stability. Indicates the voltage at the end of the scan. This represents the voltage relative error threshold. The preceding scan voltage index refers to the array index corresponding to the preceding scan voltage value in the forward scan voltage value sequence, used to locate the drain current acquired synchronously with that voltage value. The target drain current index refers to the array index with the same value as the preceding scan voltage index, used to extract the current value at the same sampling time from the drain current response value sequence. The final current refers to the drain current response value corresponding to the target drain current index. The final current set refers to the set composed of all final currents. The preceding scan voltage value refers to the forward scan voltage value adjacent to the scan endpoint voltage and located one position before the scan endpoint voltage in the forward scan voltage value sequence. For example, if the forward scan voltage value sequence is {A, B, C, D, E}, where E is the scan endpoint voltage, then D is the preceding scan voltage value. If the preceding scan voltage value is greater than or equal to the lower voltage stability limit, it indicates that the MOS device channel at the current data point has been fully formed and the conduction state is approaching saturation, indicating a stable operating stage. At this time, the measured drain current response value truly reflects the device's conduction capability under the maximum gate electric field drive.

[0116] S4. Based on the switched drain and switched gate, obtain the normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence.

[0117] In detail, the acquisition of normal single-cycle current bands, drain-source voltage waveforms, drain current waveforms, and periodic gate-source voltage sequences based on the switched drain, switched gate, and connected source includes:

[0118] Using a preset dynamic sampling rate, signals from the switched drain, switched gate, and connected source are synchronously acquired to obtain the gate-source voltage sequence, gate current sequence, drain-source voltage sequence, and drain current sequence.

[0119] Construct gate current waveforms, drain-source voltage waveforms, and drain current waveforms based on the gate current sequence, drain-source voltage sequence, and drain current sequence;

[0120] The single-cycle current band set is identified from the gate current waveform diagram, and the single-cycle current band set is sorted according to the time sequence to obtain the single-cycle current band sequence.

[0121] The target single-cycle current band is identified from the single-cycle current band sequence, and the target gate current sequence is identified based on the target single-cycle current band.

[0122] Based on the target gate current sequence, a periodic gate-source voltage sequence is identified from the gate-source voltage sequence. A discrete integration operation is then performed on the target gate current sequence to obtain the gate charge sequence.

[0123] The normal gate charge set is identified based on the gate charge sequence, and the target single-cycle current band corresponding to the normal gate charge set is taken as the normal single-cycle current band.

[0124] It should be explained that the step of switching the voltage of the connected drain and the connected gate to obtain the switched drain and the switched gate is as follows: the voltage of the connected drain is switched using a preset third DC bias voltage to obtain the switched drain, and the voltage of the connected gate is switched using a preset fourth voltage signal to obtain the switched gate. The third DC bias voltage refers to a preset bias voltage. For example, the third DC bias voltage is 400V. The fourth voltage signal refers to a preset series of high-frequency square wave pulses. For example, the valley voltage of the high-frequency square wave pulses is -5V, the peak voltage is 15V, the frequency is 100kHz, and the duty cycle is 50%. N pulses are applied continuously, where N is an integer greater than 1000, preferably 10,000 to 100,000 times, to apply sufficient switching electrical stress. The dynamic sampling rate refers to a preset sampling frequency to ensure complete capture of high-speed transient processes. For example, the dynamic sampling rate is 100MS / s. The gate-source voltage sequence refers to the sequence of voltage values ​​between the gate and source obtained from dynamic sampling rate, arranged in chronological order. The gate current sequence refers to the sequence of current values ​​flowing into the gate terminal obtained from dynamic sampling rate, arranged in chronological order. The drain-source voltage sequence refers to the sequence of voltage values ​​between the drain and source obtained from dynamic sampling rate, arranged in chronological order. The drain current sequence refers to the sequence of current values ​​flowing into the drain terminal obtained from dynamic sampling rate, arranged in chronological order. The gate current waveform, drain-source voltage waveform, and drain current waveform are respectively time-domain waveforms plotted from the gate current sequence, the drain-source voltage sequence, and the drain current sequence.

[0125] Importantly, the step of identifying the single-cycle current band set from the gate current waveform diagram is as follows: The gate current waveform diagram is raised from a low level (e.g., -5V) to a high level (e.g., +15V) until it drops back to a low level. The corresponding band in the gate current waveform diagram is taken as a single-cycle current band. This step is repeated to summarize the single-cycle current bands, resulting in a single-cycle current band set. A single-cycle current band set refers to a collection composed of single-cycle current bands. A single-cycle current band sequence refers to an ordered sequence formed by sorting the single-cycle current band set in chronological order. A target single-cycle current band refers to a single periodic current segment selected from the single-cycle current band sequence for current analysis. It should be noted that this invention extracts the current from the single-cycle current band sequence in chronological order. A target gate current sequence refers to the gate current subsequence extracted from the target single-cycle current band, used for charge calculation. A periodic gate-source voltage sequence refers to the gate-source voltage subsequence that is time-synchronized with the target gate current sequence, used to ensure that voltage and current are time-aligned. The discrete integration operation refers to the numerical integration of the target gate current sequence over time steps. The gate charge sequence is an ordered sequence of charge values ​​generated by the discrete integration operation arranged in chronological order, used to characterize the amount of accumulated charge at the gate. Gate charge refers to a single charge value within the gate charge sequence.

[0126] Specifically, the identification of the normal gate charge set based on the gate charge sequence includes:

[0127] Gate charges are extracted sequentially from the gate charge sequence, and adjacent gate charges are identified from the gate charge sequence based on the extracted gate charges, wherein adjacent gate charges are adjacent and lag behind the extracted gate charges;

[0128] If the extracted gate charge is less than the adjacent gate charge, the gate charge sequence is regarded as an abnormal gate charge sequence and is removed from the single-cycle current band sequence to obtain an updated cycle current band sequence. The updated cycle current band sequence is regarded as a single-cycle current band sequence, and the step of identifying the target single-cycle current band from the single-cycle current band sequence is returned until the extracted gate charge is not less than the adjacent gate charge.

[0129] If the extracted gate charge is not less than the adjacent gate charge, then the extracted gate charge is taken as the normal gate charge.

[0130] The normal gate charge is summed to obtain the normal gate charge set.

[0131] It should be explained that the abnormal gate charge sequence refers to the gate charge smaller than the adjacent gate charge. The updated periodic current band sequence refers to the set of remaining periodic current bands formed after removing the single-cycle current bands corresponding to the abnormal gate charge sequence from the current single-cycle current band sequence, which is used as the input for the next round of iterative screening. The normal gate charge refers to the gate charge extracted that is not smaller than the adjacent gate charge. The normal gate charge set refers to the set composed of all normal gate charges. If the extracted gate charge is smaller than the adjacent gate charge, it indicates that the gate charge sequence has a non-monotonic increase anomaly. This anomaly originates from data asynchrony or signal acquisition distortion in the gate current integration process, leading to a logical error in the charge accumulation process. Conversely, if the extracted gate charge value is not smaller than the adjacent gate charge value, it indicates that the charge accumulation process conforms to the monotonically increasing characteristics of physical laws, and this data point truly reflects the continuous accumulation state of the gate charge.

[0132] S5. Dynamic evaluation parameters are obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0133] In detail, the acquisition of dynamic evaluation parameters based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence includes:

[0134] Based on the normal single-cycle current waveform, the drain-source voltage waveform and drain current waveform can be identified.

[0135] The normal gate charge set is arranged in ascending order to obtain the normal gate charge sequence;

[0136] The periodic gate-source voltage sequence is combined with the normal gate charge sequence to obtain a combined data pair set, wherein the combined data pair set includes multiple combined data pairs, and each combined data pair includes a periodic gate-source voltage and a normal gate charge.

[0137] Gate charge curves are constructed based on the combined data set, where the horizontal axis of the gate charge curve represents the normal gate charge, and the vertical axis of the gate charge curve represents the periodic gate-source voltage.

[0138] Gate charge parameters are obtained based on the gate charge curve, and switching speed parameters and switching energy loss parameters are obtained based on the drain-source voltage band and drain current band.

[0139] By integrating gate charge parameters, switching speed parameters, and switching energy loss parameters, dynamic evaluation parameters are obtained.

[0140] It should be explained that the drain-source voltage band refers to the synchronous voltage subsequence extracted from the drain-source voltage waveform within the time window corresponding to the normal single-cycle current band, used to characterize the transient changes of the drain-source voltage within that cycle. The drain current band refers to the synchronous current subsequence extracted from the drain current waveform within the time window corresponding to the same normal single-cycle current band, used to characterize the transient changes of the drain current within that cycle. The normal gate charge sequence refers to the ordered set of normal gate charges obtained by arranging the normal gate charge set in ascending order of charge value, to ensure that the horizontal axis monotonically increases when constructing subsequent curves. Combining the periodic gate-source voltage sequence with the normal gate charge sequence means pairing the periodic gate-source voltage sequence with the normal gate charge sequence one-to-one according to the same time index. The gate charge curve refers to the curve plotted with the combined data set as the data source, with normal gate charge as the horizontal axis and periodic gate-source voltage as the vertical axis, used to extract gate charge parameters. Integration refers to the operation of putting the gate charge parameters, switching speed parameters, and switching energy loss parameters into the same set.

[0141] Specifically, obtaining the gate charge parameters based on the gate charge curve includes:

[0142] The Miller plateau curve segment is identified based on the gate charge curve. The gate-source voltage set of the plateau period is determined based on the Miller plateau curve segment. The Miller plateau voltage of the gate-source voltage set of the plateau period is calculated, where the Miller plateau voltage is the average value of the gate-source voltage set of the plateau period.

[0143] The periodic gate-source voltage is extracted sequentially from the gate charge curve, and the extracted periodic gate-source voltage is compared with the preset peak gate voltage.

[0144] If the extracted periodic gate-source voltage is not equal to the peak gate voltage, then return to the step of sequentially extracting the periodic gate-source voltage from the gate charge curve until the extracted periodic gate-source voltage is equal to the peak gate voltage.

[0145] If the extracted periodic gate-source voltage is equal to the peak gate voltage, then the normal gate charge corresponding to the extracted periodic gate-source voltage is taken as the total gate charge.

[0146] The gate charge parameters were determined based on the Miller plateau voltage and total gate charge.

[0147] It should be explained that the step of identifying the Miller plateau curve segment based on the gate charge curve is as follows: extracting a continuous data point set from the gate charge curve in sequence, wherein the continuous data point set includes: the previous data point, the current data point, and the subsequent data point;

[0148] The slope of the current data point is calculated based on the continuous data point set, and the adjacent continuous data point set and the end continuous data point set are obtained on the gate charge curve using a preset moving interval.

[0149] Treat adjacent consecutive data point sets as consecutive data point sets, and return to the step of calculating the slope of the current data point based on the consecutive data point set until the consecutive data point set equals the end consecutive data point set.

[0150] Summarize the slopes of the current data points to obtain the current data point slope set. Extract the current data point slopes from the current data point slope set in turn, calculate the absolute value of the current data point slope, and if the extracted absolute value of the slope is less than the preset positive slope threshold, then the extracted current data point slope is taken as a flat point.

[0151] The flat points are summarized to obtain a flat point set. A candidate segment set is obtained based on this flat point set, and the Miller plateau curve segment is confirmed based on the candidate segment set. The preceding data point refers to a data point on the gate charge curve that is located before and immediately adjacent to the current data point along the horizontal axis (normal gate charge). The current data point refers to the gate charge curve data point that is in the middle of the continuous data point set and is used to calculate the local slope. The following data point refers to a data point on the gate charge curve that is located after and immediately adjacent to the current data point along the horizontal axis, forming a three-point sliding window together with the preceding and current data points. Calculating the slope of the current data point based on the continuous data point set refers to calculating the slope of the current data point using the central difference method based on the continuous data point set. The moving interval refers to a pre-set fixed step size. For example, the moving interval is one data point. The adjacent continuous data point set refers to the new three-point combination obtained after the sliding window moves forward one step according to the moving interval. The terminal continuous data point set refers to the three-point combination formed when the following data point of the sliding window reaches the last data point of the gate charge curve, used as a criterion for traversal termination. The current data point slope set refers to the set of slopes of all current data points. The absolute value of the slope refers to the absolute value of the slope of the current data point. The positive slope threshold is a pre-set constant used to mathematically quantify and define approximately horizontal segments in the gate charge curve. For example, the positive slope threshold is 0.05. If the extracted absolute slope value is less than the preset positive slope threshold, it indicates that the injected gate charge is mainly used to charge and discharge the gate-drain capacitance to complete the extraction of the drain voltage, while the gate voltage itself remains in a dynamically stable plateau period. Therefore, this data point can be marked as a flat point characterizing the Miller plateau. The flat point set refers to the set of all flat points. Obtaining the candidate segment set based on the flat point set refers to combining consecutive flat points in the flat point set to obtain candidate segments, and summarizing the candidate segments to obtain the candidate segment set.

[0152] Importantly, the step of identifying the Miller plateau curve segment based on the candidate segment set is as follows: obtaining the maximum gate charge and the initial gate charge according to the gate charge curve, calculating the total charge span based on the maximum gate charge and the initial gate charge, and calculating the start charge threshold and the end charge threshold based on the total charge span.

[0153] Candidate segments are extracted sequentially from the candidate segment set. The starting charge of the candidate segment is determined based on the extracted candidate segment. If the starting charge of the candidate segment is greater than the back-end charge threshold or less than the start charge threshold, the extracted candidate segment is removed to obtain an updated candidate segment set. The updated candidate segment set is used as the candidate segment set, and the process of extracting candidate segments sequentially from the candidate segment set is repeated until all candidate segments are extracted.

[0154] Otherwise, the extracted candidate segments will be used as the remaining candidate segments;

[0155] The remaining candidate segments are summarized to obtain a set of remaining candidate segments. The average gate-source voltage of each remaining candidate segment in the set of remaining candidate segments is calculated to obtain a set of average gate-source voltages. Based on the set of average gate-source voltages, the Miller plateau curve segment is identified. Maximum gate charge refers to the maximum value of the horizontal axis coordinate in the gate charge curve, corresponding to the amount of charge accumulated required to drive the device to a fully on state. Initial gate charge refers to the minimum value of the horizontal axis coordinate in the gate charge curve, corresponding to the initial accumulated charge in the off state of the device. Total charge span refers to the difference calculated from the maximum gate charge and the initial gate charge. The starting charge threshold is the product of the total charge span and a preset starting charge coefficient. The ending charge threshold is the product of the total charge span and a preset ending charge coefficient. Both the starting charge coefficient and the ending charge coefficient are preset coefficients. For example, the starting charge coefficient is 0.2, and the ending charge coefficient is 0.8. The initial charge of the candidate segment refers to the normal gate charge value corresponding to the first data point in the horizontal direction of the extracted candidate segment. The updated candidate segment set refers to the new set of candidate segments remaining after removing candidate segments whose starting charge is greater than the back-end charge threshold or whose starting charge is less than the beginning charge threshold. The remaining candidate segments refer to all candidate segments except those whose starting charge is greater than the back-end charge threshold or whose starting charge is less than the beginning charge threshold. The remaining candidate segment set is the set composed of all remaining candidate segments. The average gate-source voltage refers to the average value of the periodic gate-source voltages of all data points within a single remaining candidate segment. The average gate-source voltage set is the set of all average gate-source voltages. The Miller plateau curve segment identified based on the average gate-source voltage set refers to the remaining candidate segments after removing the remaining candidate segments corresponding to the average gate-source voltages that are less than a preset low-voltage threshold (e.g., 2V).

[0156] It should also be explained that the plateau periodic gate-source voltage set refers to the set of periodic gate-source voltages corresponding to all data points within the identified Miller plateau curve segment. The peak gate voltage is a pre-set value representing the maximum gate-source voltage that the device drive circuit can provide, used as a reference to determine whether the curve has reached its peak. The total gate charge is the normal gate charge corresponding to a periodic gate-source voltage equal to the peak gate voltage. The gate charge parameter is a parameter composed of the Miller plateau voltage and the total gate charge. The initial charge threshold is used to exclude flat sections located in the early stages of the charging process. These sections correspond to the initial linear charging phase of the gate oxide capacitance, where the voltage has not yet reached the level required to form a conductive channel and induce the Miller effect. The back-end charge threshold is used to exclude flat sections located at the end of the charging process. These sections correspond to the final charging stage after the gate voltage reaches the Miller plateau and before the device is fully turned on. Physically, this represents the final recovery of the gate voltage to the peak gate voltage, rather than a voltage stagnation phenomenon dominated by Miller capacitance. Therefore, if the starting charge of a candidate section is greater than the back-end charge threshold or less than the starting charge threshold, the extracted candidate section is discarded. The initial linear charging stage of the gate oxide capacitor refers to the initial stage of the gate charge curve, where the gate voltage rises from an initial negative voltage but has not yet reached the threshold voltage. During this stage, the injected gate charge primarily acts to establish the surface electric field of the MOS structure. This stage corresponds to the initial linear charging stage of the gate oxide capacitor.

[0157] Specifically, the acquisition of switching speed parameters and switching energy loss parameters based on the drain-source voltage band and drain current band includes:

[0158] The falling drain voltage sequence and the rising drain voltage sequence were identified from the drain-source voltage band.

[0159] Linear fitting is performed on the falling drain voltage sequence to obtain the turn-on voltage drop rate, and linear fitting is performed on the rising drain voltage sequence to obtain the turn-on voltage rise rate.

[0160] The turn-on current decrease rate and turn-on current rise rate are obtained based on the drain current band, and the turn-on process integral interval and turn-off process integral interval are determined based on the normal single-cycle current band and drain-source voltage band.

[0161] The normal current sequence and voltage sequence of the turn-on process are determined based on the integral interval of the turn-on process, and the instantaneous power curve of the turn-on process is constructed based on the normal current sequence and voltage sequence of the turn-on process.

[0162] Numerical integration is performed on the instantaneous power curve during turn-on to obtain the energy loss value during a single turn-on, and the energy loss during a single turn-off is obtained based on the integration interval of the turn-off process.

[0163] The switching speed parameters are determined based on the turn-on voltage drop rate, turn-on voltage rise rate, turn-on current drop rate, and turn-on current rise rate.

[0164] The switching energy loss parameters are determined based on the energy loss value of a single turn-on and a single turn-off.

[0165] It should be explained that identifying the time intervals for the decreasing and increasing drain voltages from the drain-source voltage band refers to extracting corresponding bands from the drain-source voltage band based on pre-defined standard decreasing and increasing voltage intervals to obtain the decreasing and increasing drain voltage sequences. The linear fitting of both the decreasing and increasing drain voltage time sequences is performed using the least squares method. The turn-on voltage drop rate is the absolute value of the slope of the straight line obtained by fitting the decreasing drain voltage sequence. The turn-on voltage rise rate is the slope of the straight line obtained by fitting the increasing drain voltage time sequence. The method for obtaining the turn-on current drop rate and rise rate based on the drain current band is the same as the method for obtaining the turn-on voltage drop rate and rise rate based on the drain-source voltage band, and will not be repeated here. The turn-on process integration interval refers to the time interval jointly determined by the normal single-cycle current band and the drain-source voltage band, starting from the point where the drain-source voltage begins to decrease and ending when the drain current reaches its plateau value. The turn-off process integration interval refers to the time interval jointly determined by the normal single-cycle current band and the drain-source voltage band, starting from the point where the drain current begins to decrease and ending when the drain-source voltage rises back to the bus voltage. The turn-on process normal current sequence refers to the current subsequence extracted from the drain current sequence within the turn-on process integration interval, synchronized with the normal single-cycle current band, and used for power calculation. The turn-on process voltage sequence refers to the voltage subsequence extracted from the drain-source voltage sequence within the turn-on process integration interval, synchronized with the normal single-cycle current band, and used for power calculation. The turn-on instantaneous power curve is the curve plotted by multiplying the turn-on process normal current sequence and the turn-on process voltage sequence point by point, used for energy integration. The single turn-on energy loss value refers to the result of numerically integrating the turn-on instantaneous power curve within the turn-on process integration interval. The method for obtaining the single turn-off energy loss based on the turn-off process integration interval is the same as the method for obtaining the single turn-on energy loss value based on the turn-on process integration interval, and will not be repeated here. The energy loss during a single turn-off refers to the result of numerical integration of the instantaneous power curve constructed within the integral interval of the turn-off process, which characterizes the energy loss during a single turn-off process.

[0166] S6. Receive multi-parameter detection instructions, and input static evaluation parameters and dynamic evaluation parameters into the pre-built deep learning model according to the multi-parameter detection instructions to obtain a comprehensive performance score.

[0167] It should be explained that the comprehensive performance score refers to the value output by the deep learning model. A higher value indicates a higher overall consistency between the static and dynamic performance of the SiC MOS transistor under test. The multi-parameter detection command refers to a trigger signal issued by the test control software, used to initiate a complete test process involving the simultaneous acquisition, processing, and subsequent deep learning judgment of the static and dynamic evaluation parameters of the SiC MOS transistor under test. The deep learning model refers to a neural network model that uses static and dynamic evaluation parameters as input features and the comprehensive performance score as the output target. Its weights and biases have been optimized in the early training phase using a sample library of qualified and defective transistors to achieve end-to-end mapping of transistor quality. The deep learning model of this invention employs, but is not limited to, mature network structures such as multilayer perceptrons (MLP) or convolutional neural networks (CNN). Its weights and biases have been optimized in the early training phase using a large-scale sample library containing both qualified and defective SiC MOS transistors. During the training phase, the deep learning model takes the static and dynamic evaluation parameters corresponding to samples with known labels (qualified / defective) as input and their corresponding comprehensive performance scores (which can be calibrated by an expert system or converted from known performance levels) as the output target. The model continuously optimizes the weights and biases within the deep learning model through the backpropagation algorithm until the comprehensive performance score output by the deep learning model can accurately reflect the true quality level of the transistor.

[0168] For example, a deep learning model is a three-layer fully connected neural network, which includes an input layer (the number of neurons is equal to the total dimension of the input parameters), two hidden layers (the number of neurons is 128 and 64 respectively, and the activation function is ReLU), and an output layer (the number of neurons is 1, the activation function is Sigmoid or Linear, and the output value ranges from 0 to 100).

[0169] S7. If the overall performance score is greater than the preset overall performance score threshold, then the SiC MOS structure transistor under test is regarded as a qualified SiC MOS structure transistor.

[0170] It should be explained that the comprehensive performance score threshold is a pre-set threshold used to determine whether the SiC MOS structure transistor under test is defective. A qualified SiC MOS structure transistor is a device under test whose comprehensive performance score is greater than the comprehensive performance score threshold, and is classified as a usable product whose electrical parameters meet the design specifications and reliability requirements.

[0171] S8. Otherwise, the SiC MOS structure transistor under test will be regarded as a defective SiC MOS structure transistor.

[0172] It should be explained that defective SiC MOS structure transistors refer to devices under test whose overall performance score is not greater than the overall performance score threshold. They are classified as products with static or dynamic electrical deviations, which do not meet the factory standards and are either failed or potentially failed.

[0173] S9. Perform multi-parameter detection of SiC-based MOS structure transistors based on qualified or defective SiC MOS structure transistors.

[0174] Importantly, this invention completes the entire multi-parameter testing process, providing strong support for the production, screening, and application of transistors. Qualified transistors can be put into practical applications, ensuring product performance and reliability. Defective transistors can be further analyzed and processed, such as repaired or scrapped, thereby optimizing the production process, reducing production costs, and improving the overall quality of the product.

[0175] To address the problems described in the background art, this invention identifies the SiC MOS structure transistor under test and the detection unit. The SiC MOS structure transistor under test includes a gate, a drain, and a source. This invention accurately determines the SiC structure under test. The MOS structure transistor and its corresponding detection unit ensure that subsequent detection processes target the correct object, avoiding detection errors or confusion, and ensuring the accuracy and specificity of the detection. Connecting the gate, drain, and source to the detection unit yields a connected gate, connected drain, and connected source. This invention establishes an electrical connection between the transistor under test and the detection unit, enabling signal interaction between the detection unit and the transistor. This provides a physical channel for acquiring various transistor parameters. Only with correct connection can the detection unit accurately acquire and measure relevant electrical signals of the transistor, thus ensuring the reliability of subsequent parameter acquisition. Static evaluation parameters are obtained based on the connected gate, connected drain, and connected source. Voltage switching is performed on the connected drain and connected gate to obtain a switched drain and switched gate. This invention simulates the transistor's behavior under different operating states, allowing the transistor to enter a dynamic operating mode, creating conditions for subsequent dynamic parameter acquisition. Different voltage states can excite different electrical responses in the transistor, thus more comprehensively detecting its performance. Normal single-cycle current bands, drain-source voltage waveforms, and drain current are obtained based on the switched drain, switched gate, and connected source. The waveform diagrams and periodic gate-source voltage sequences of this invention reflect the performance of transistors during dynamic operation. By acquiring dynamic evaluation parameters, a deeper understanding of the transistor's performance during dynamic operation can be achieved, providing a more accurate basis for evaluating the transistor's practical application capabilities. Based on normal single-cycle current bands, drain-source voltage waveforms, drain current waveforms, and periodic gate-source voltage sequences, dynamic evaluation parameters are obtained. These parameters comprehensively reflect the transistor's performance and characteristics during actual operation. Compared to static evaluation parameters, dynamic evaluation parameters consider the transistor's dynamic response during switching. The invention receives multi-parameter detection commands and inputs both static and dynamic evaluation parameters into a pre-built deep learning model to obtain a comprehensive performance score. This invention utilizes a deep learning model for comprehensive analysis, enabling a more comprehensive and objective evaluation of transistor performance. The deep learning model can process large amounts of complex data and uncover potential relationships between parameters, thus providing a comprehensive performance score. This avoids the limitations of single-parameter evaluation and more accurately reflects the overall performance of the transistor. If the comprehensive performance score exceeds a preset comprehensive performance score threshold, the SiC under test is... As a qualified SiC MOS structure transistor, this invention provides a clear standard for judging whether a transistor is qualified by setting a comprehensive performance scoring threshold. This quantitative judgment method is simple and intuitive, and can quickly and accurately screen out qualified and defective transistors.This invention facilitates the classification and subsequent processing of transistors, improving the efficiency and accuracy of production quality control. Otherwise, the SiC MOS structure transistor under test is treated as a defective SiC MOS structure transistor, and multi-parameter testing of SiC-based MOS structure transistors is performed based on either qualified or defective SiC MOS structure transistors. Therefore, this invention can improve the reliability of SiC MOS devices and optimize their application performance.

[0176] like Figure 2 The diagram shown is a functional block diagram of a SiC-based MOS structure transistor multi-parameter detection system provided in an embodiment of the present invention.

[0177] The SiC-based MOS transistor multi-parameter detection system 100 described in this invention can be installed in an electronic device. Depending on the functions implemented, the SiC-based MOS transistor multi-parameter detection system 100 may include a transistor test preparation module 101, a static parameter acquisition module 102, a dynamic parameter acquisition module 103, and an intelligent judgment module 104. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0178] The transistor test preparation module 101 is used to identify the SiC MOS structure transistor under test and the detection unit. The SiC MOS structure transistor under test includes a gate, a drain, and a source. The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0179] The static parameter acquisition module 102 is used to acquire static evaluation parameters based on the connected gate, connected drain and connected source, and to switch the voltage of the connected drain and connected gate to obtain the switched drain and switched gate.

[0180] The dynamic parameter acquisition module 103 is used to acquire normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence based on the switched drain, switched gate and connected source, and to acquire dynamic evaluation parameters based on normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence.

[0181] The intelligent judgment module 104 is used to receive multi-parameter detection instructions, input static evaluation parameters and dynamic evaluation parameters into a pre-built deep learning model according to the multi-parameter detection instructions, and obtain a comprehensive performance score. If the comprehensive performance score is greater than a preset comprehensive performance score threshold, the SiC MOS structure transistor under test is regarded as a qualified SiC MOS structure transistor; otherwise, the SiC MOS structure transistor under test is regarded as a defective SiC MOS structure transistor. The multi-parameter detection of SiC-based MOS structure transistors is completed based on qualified or defective SiC MOS structure transistors.

[0182] In detail, the modules in the SiC-based MOS structure transistor multi-parameter detection system 100 described in this embodiment of the invention employ the same methods as described above. Figure 1 The method used is the same as the multi-parameter detection method for SiC-based MOS structure transistors described above, and it can produce the same technical effect, so it will not be repeated here.

[0183] like Figure 3 The diagram shown is a schematic representation of an electronic device that implements a multi-parameter detection method for SiC-based MOS structure transistors, according to an embodiment of the present invention.

[0184] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a SiC-based MOS structure transistor multi-parameter detection method program.

[0185] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as the portable hard drive of the electronic device 1. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of a multi-parameter detection method program for SiC-based MOS structure transistors, but also to temporarily store data that has been output or will be output.

[0186] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., a SiC-based MOS structure transistor multi-parameter detection method program) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0187] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0188] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0189] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0190] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0191] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0192] The SiC-based MOS structure transistor multi-parameter detection method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0193] The SiC MOS structure transistor under test and the detection unit were identified. The SiC MOS structure transistor under test includes: gate, drain and source.

[0194] The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0195] Based on the static evaluation parameters obtained from the connected gate, connected drain, and connected source, the voltage of the connected drain and connected gate is switched to obtain the switched drain and switched gate.

[0196] Based on the switched drain, switched gate, and connected source, obtain the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0197] Dynamic evaluation parameters are obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0198] Receive multi-parameter detection instructions, and input static evaluation parameters and dynamic evaluation parameters into the pre-built deep learning model according to the multi-parameter detection instructions to obtain a comprehensive performance score;

[0199] If the overall performance score is greater than the preset overall performance score threshold, the SiC MOS structure transistor under test will be regarded as a qualified SiC MOS structure transistor.

[0200] Otherwise, the SiC MOS structure transistor under test will be considered a defective SiC MOS structure transistor;

[0201] Multi-parameter detection of SiC-based MOS structure transistors was performed using qualified or defective SiC MOS structure transistors.

[0202] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0203] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0204] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0205] The SiC MOS structure transistor under test and the detection unit were identified. The SiC MOS structure transistor under test includes: gate, drain and source.

[0206] The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source.

[0207] Based on the static evaluation parameters obtained from the connected gate, connected drain, and connected source, the voltage of the connected drain and connected gate is switched to obtain the switched drain and switched gate.

[0208] Based on the switched drain, switched gate, and connected source, obtain the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0209] Dynamic evaluation parameters are obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence.

[0210] Receive multi-parameter detection instructions, and input static evaluation parameters and dynamic evaluation parameters into the pre-built deep learning model according to the multi-parameter detection instructions to obtain a comprehensive performance score;

[0211] If the overall performance score is greater than the preset overall performance score threshold, the SiC MOS structure transistor under test will be regarded as a qualified SiC MOS structure transistor.

[0212] Otherwise, the SiC MOS structure transistor under test will be considered a defective SiC MOS structure transistor;

[0213] Multi-parameter detection of SiC-based MOS structure transistors was performed using qualified or defective SiC MOS structure transistors.

[0214] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0215] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0216] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0217] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0218] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for multi-parameter detection of SiC-based MOS structure transistors, characterized in that, The method includes: The SiC MOS structure transistor under test and the detection unit were identified. The SiC MOS structure transistor under test includes: gate, drain and source. The gate, drain, and source are connected to the detection unit to obtain a connected gate, a connected drain, and a connected source. Based on the static evaluation parameters obtained from the connected gate, connected drain, and connected source, the voltage of the connected drain and connected gate is switched to obtain the switched drain and switched gate. Based on the switched drain, switched gate, and connected source, obtain the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence. Dynamic evaluation parameters are obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence. Receive multi-parameter detection instructions, and input static evaluation parameters and dynamic evaluation parameters into the pre-built deep learning model according to the multi-parameter detection instructions to obtain a comprehensive performance score; If the overall performance score is greater than the preset overall performance score threshold, the SiC MOS structure transistor under test will be regarded as a qualified SiC MOS structure transistor. Otherwise, the SiC MOS structure transistor under test will be considered a defective SiC MOS structure transistor; Multi-parameter detection of SiC-based MOS structure transistors was performed using qualified or defective SiC MOS structure transistors.

2. The multi-parameter detection method for SiC-based MOS structure transistors as described in claim 1, characterized in that, The method of obtaining static evaluation parameters based on the connected gate, connected drain, and connected source includes: The first DC bias voltage and the triangular wave scanning voltage are obtained from the detection unit. The connected drain and the connected gate are synchronously tested using the first DC bias voltage, the preset sampling rate and the triangular wave scanning voltage to obtain the drain current response value sequence and the gate voltage value sequence. The drain voltage response value sequence includes multiple drain voltage response values ​​and the gate voltage value sequence includes multiple gate voltage values. The drain voltage response value and the gate voltage value correspond one-to-one. The static parameters are calculated based on the drain current response sequence and the gate voltage sequence. The static parameters include: threshold voltage, hysteresis window, subthreshold swing and channel on-resistance. The first DC bias voltage, triangular wave scanning voltage, and static parameters are stored to obtain static evaluation parameters.

3. The multi-parameter detection method for SiC-based MOS structure transistors as described in claim 2, characterized in that, The static parameters calculated based on the drain current response sequence and the gate voltage sequence include: A forward differential operation is performed on the gate voltage value sequence to obtain a gate voltage difference sequence. Gate voltage differences are extracted sequentially from the gate voltage difference sequence, and the extracted gate voltage differences are removed from the gate voltage difference sequence to obtain an updated gate voltage difference sequence. Compare the extracted gate voltage difference with a preset positive threshold; If the extracted gate voltage difference is greater than the positive threshold, then return to the step of extracting gate voltage differences sequentially from the gate voltage difference sequence until the extracted gate voltage difference is not greater than the positive threshold. Then, the gate voltage difference that is not greater than the positive threshold is used as the reverse scan difference, and the adjacent gate voltage difference is obtained from the updated gate voltage difference sequence based on the reverse scan difference. The inflection point time is determined based on the difference between adjacent gate voltages. The gate voltage value sequence is then divided based on the inflection point time to obtain the forward scan voltage value sequence and the reverse scan voltage value sequence. A transfer characteristic curve is constructed based on the forward scanning voltage value sequence. The transfer characteristic curve is numerically differentiated to obtain the transconductance sequence. The transconductance with the largest value in the transconductance sequence is taken as the forward scanning threshold voltage. The reverse scanning threshold voltage is obtained based on the reverse scanning voltage value sequence. The hysteresis window is calculated based on the forward scanning threshold voltage and the reverse scanning threshold voltage. The hysteresis window is the absolute difference between the forward scanning threshold voltage and the reverse scanning threshold voltage. A subthreshold sequence is selected from the transfer characteristic curve, and a linear fit is performed on the subthreshold sequence to obtain a fitted line. The subthreshold swing is calculated based on the fitted line, and the channel on-resistance is calculated based on the forward scan voltage value sequence and the drain current response value sequence. The static parameters were determined based on the threshold voltage, hysteresis window, subthreshold swing, and channel on-resistance.

4. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 3, characterized in that, The calculation of channel on-resistance based on the forward scan voltage value sequence and the drain current response value sequence includes: The scanning endpoint voltage is identified from the forward scanning voltage value sequence, and the voltage stability lower limit is calculated based on the preset voltage relative error threshold and the scanning endpoint voltage. The preceding scan voltage value is obtained from the forward scan voltage value sequence based on the scan endpoint voltage; If the preceding scan voltage value is greater than or equal to the lower voltage stability limit, then the preceding scan voltage index is determined based on the preceding scan voltage value, the target drain current index is determined from the drain current response value sequence based on the preceding scan voltage index, the drain current response value corresponding to the target drain current index is taken as the final current, the preceding scan voltage value is taken as the scan endpoint voltage, and the step of obtaining the preceding scan voltage value from the forward scan voltage value sequence based on the scan endpoint voltage is returned until the preceding scan voltage value is less than the lower voltage stability limit; Summarize the final currents to obtain the final current set, and calculate the maximum conducting current based on the final current set, where the maximum conducting current is the average value of the final current set; The channel on-resistance is calculated based on the maximum on-current and the first DC bias voltage, where the channel on-resistance is the value obtained by dividing the first DC bias voltage by the maximum on-current.

5. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 4, characterized in that, The method of obtaining normal single-cycle current bands, drain-source voltage waveforms, drain current waveforms, and periodic gate-source voltage sequences based on switched drains, switched gates, and connected sources includes: Using a preset dynamic sampling rate, signals from the switched drain, switched gate, and connected source are synchronously acquired to obtain the gate-source voltage sequence, gate current sequence, drain-source voltage sequence, and drain current sequence. Construct gate current waveforms, drain-source voltage waveforms, and drain current waveforms based on the gate current sequence, drain-source voltage sequence, and drain current sequence; The single-cycle current band set is identified from the gate current waveform diagram, and the single-cycle current band set is sorted according to the time sequence to obtain the single-cycle current band sequence. The target single-cycle current band is identified from the single-cycle current band sequence, and the target gate current sequence is identified based on the target single-cycle current band. Based on the target gate current sequence, a periodic gate-source voltage sequence is identified from the gate-source voltage sequence. A discrete integration operation is then performed on the target gate current sequence to obtain the gate charge sequence. The normal gate charge set is identified based on the gate charge sequence, and the target single-cycle current band corresponding to the normal gate charge set is taken as the normal single-cycle current band.

6. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 5, characterized in that, The process of identifying the normal gate charge set based on the gate charge sequence includes: Gate charges are extracted sequentially from the gate charge sequence, and adjacent gate charges are identified from the gate charge sequence based on the extracted gate charges, wherein adjacent gate charges are adjacent and lag behind the extracted gate charges; If the extracted gate charge is less than the adjacent gate charge, the gate charge sequence is regarded as an abnormal gate charge sequence and is removed from the single-cycle current band sequence to obtain an updated cycle current band sequence. The updated cycle current band sequence is regarded as a single-cycle current band sequence, and the step of identifying the target single-cycle current band from the single-cycle current band sequence is returned until the extracted gate charge is not less than the adjacent gate charge. If the extracted gate charge is not less than the adjacent gate charge, then the extracted gate charge is taken as the normal gate charge. The normal gate charge is summed to obtain the normal gate charge set.

7. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 6, characterized in that, The dynamic evaluation parameters obtained based on the normal single-cycle current band, drain-source voltage waveform, drain current waveform, and periodic gate-source voltage sequence include: Based on the normal single-cycle current waveform, the drain-source voltage waveform and drain current waveform can be identified. The normal gate charge set is arranged in ascending order to obtain the normal gate charge sequence; The periodic gate-source voltage sequence is combined with the normal gate charge sequence to obtain a combined data pair set, wherein the combined data pair set includes multiple combined data pairs, and each combined data pair includes a periodic gate-source voltage and a normal gate charge. Gate charge curves are constructed based on the combined data set, where the horizontal axis of the gate charge curve represents the normal gate charge, and the vertical axis of the gate charge curve represents the periodic gate-source voltage. Gate charge parameters are obtained based on the gate charge curve, and switching speed parameters and switching energy loss parameters are obtained based on the drain-source voltage band and drain current band. By integrating gate charge parameters, switching speed parameters, and switching energy loss parameters, dynamic evaluation parameters are obtained.

8. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 7, characterized in that, The method of obtaining gate charge parameters based on the gate charge curve includes: The Miller plateau curve segment is identified based on the gate charge curve. The gate-source voltage set of the plateau period is determined based on the Miller plateau curve segment. The Miller plateau voltage of the gate-source voltage set of the plateau period is calculated, where the Miller plateau voltage is the average value of the gate-source voltage set of the plateau period. The periodic gate-source voltage is extracted sequentially from the gate charge curve, and the extracted periodic gate-source voltage is compared with the preset peak gate voltage. If the extracted periodic gate-source voltage is not equal to the peak gate voltage, then return to the step of sequentially extracting the periodic gate-source voltage from the gate charge curve until the extracted periodic gate-source voltage is equal to the peak gate voltage. If the extracted periodic gate-source voltage is equal to the peak gate voltage, then the normal gate charge corresponding to the extracted periodic gate-source voltage is taken as the total gate charge. The gate charge parameters were determined based on the Miller plateau voltage and total gate charge.

9. The method for multi-parameter detection of SiC-based MOS structure transistors as described in claim 8, characterized in that, The acquisition of switching speed parameters and switching energy loss parameters based on drain-source voltage band and drain current band includes: The falling drain voltage sequence and the rising drain voltage sequence were identified from the drain-source voltage band. Linear fitting is performed on the falling drain voltage sequence to obtain the turn-on voltage drop rate, and linear fitting is performed on the rising drain voltage sequence to obtain the turn-on voltage rise rate. The turn-on current decrease rate and turn-on current rise rate are obtained based on the drain current band, and the turn-on process integral interval and turn-off process integral interval are determined based on the normal single-cycle current band and drain-source voltage band. The normal current sequence and voltage sequence of the turn-on process are determined based on the integral interval of the turn-on process, and the instantaneous power curve of the turn-on process is constructed based on the normal current sequence and voltage sequence of the turn-on process. Numerical integration is performed on the instantaneous power curve during turn-on to obtain the energy loss value during a single turn-on, and the energy loss during a single turn-off is obtained based on the integration interval of the turn-off process. The switching speed parameters are determined based on the turn-on voltage drop rate, turn-on voltage rise rate, turn-on current drop rate, and turn-on current rise rate. The switching energy loss parameters are determined based on the energy loss value of a single turn-on and a single turn-off.

10. A multi-parameter detection system for SiC-based MOS structure transistors, characterized in that, The system includes: The transistor test preparation module is used to identify the SiC MOS structure transistor under test and the detection unit. The SiCMOS structure transistor under test includes a gate, a drain, and a source. The gate, drain, and source are connected to the detection unit to obtain the connected gate, connected drain, and connected source. The static parameter acquisition module is used to acquire static evaluation parameters based on the connected gate, connected drain and connected source, and to switch the voltage of the connected drain and connected gate to obtain the switched drain and switched gate. The dynamic parameter acquisition module is used to acquire normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence based on the switched drain, switched gate and connected source, and to acquire dynamic evaluation parameters based on normal single-cycle current band, drain-source voltage waveform, drain current waveform and periodic gate-source voltage sequence. The intelligent judgment module receives multi-parameter detection instructions and inputs static and dynamic evaluation parameters into a pre-built deep learning model according to the instructions to obtain a comprehensive performance score. If the comprehensive performance score is greater than a preset comprehensive performance score threshold, the SiC MOS structure transistor under test is considered a qualified SiC MOS structure transistor; otherwise, it is considered a defective SiC MOS structure transistor. The multi-parameter detection of SiC-based MOS structure transistors is completed based on qualified or defective SiC MOS structure transistors.

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