Ramp voltage generation circuit and electronic device

Abstract

The application provides a slope voltage generating circuit and an electronic device. The slope voltage generating circuit has a low-pass filter circuit, an alternating current component extracting circuit, a voltage-to-current circuit and a slope voltage output circuit which are coupled in sequence. The slope voltage generating circuit can sequentially perform low-pass filtering, alternating current component extraction, voltage change conversion into current change and finally output the current change as a required slope voltage on an input voltage. The circuit design is simple. The electronic device has the slope voltage generating circuit of the application, and the performance is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a ramp voltage generating circuit and electronic device. Background Technology

[0002] Ramp voltage signals can be used in circuits requiring linear voltage changes, typically as reference signals, slope compensation signals, and control signals. They can be used in display devices or signal conversion applications (such as analog-to-digital converters and power converters). For example, in the controller (which can be a module or a chip) of a power converter with an Adaptive Constant On-Time (ACOT) architecture, a ramp voltage generation circuit can be introduced to address the system stability issues caused by the low equivalent series resistance (ESR) of the output capacitors surrounding the controller (typically around 2 mohms), while also meeting the requirements of external applications.

[0003] Therefore, how to design a ramp voltage generation circuit has always been a hot topic for those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a ramp voltage generating circuit and electronic device that can not only generate the required ramp voltage, but also has a simple circuit structure.

[0005] To achieve the above objectives, the present invention provides a ramp voltage generating circuit, comprising:

[0006] A low-pass filter circuit is coupled to the input terminal of the ramp voltage generating circuit and is used to perform low-pass filtering on the voltage received at the input terminal of the ramp voltage generating circuit and output a filtered signal.

[0007] An AC component extraction circuit, coupled to the low-pass filter circuit, is used to extract the AC component from the filtered signal to generate an analog ramp voltage signal source.

[0008] A voltage-to-current circuit is coupled to the AC component extraction circuit and is used to convert the voltage change of the simulated ramp voltage signal source into a current change.

[0009] The ramp voltage output circuit has its input terminal coupled to the voltage-to-current circuit and is used to output the current change as a ramp voltage.

[0010] Optionally, the low-pass filter circuit includes at least one of an active low-pass filter, a passive RC low-pass filter, and a passive RL low-pass filter.

[0011] Optionally, the passive RC low-pass filter includes a first resistor and a first capacitor, one end of the first resistor is coupled to the input terminal of the low-pass filter circuit, and the other end of the first resistor is coupled to one end of the first capacitor and the output terminal of the low-pass filter circuit.

[0012] Optionally, the low-pass filter circuit further includes a second resistor, which is connected in parallel with the first capacitor.

[0013] Optionally, the AC component extraction circuit includes:

[0014] The first DC blocking and AC passing circuit is coupled to the output of the low-pass filter circuit and is used to extract the AC component in the filtered signal.

[0015] The second DC blocking and AC passing circuit is coupled to the output of the low-pass filter circuit and is used to extract the AC component in the filtered signal.

[0016] An AC component control circuit is coupled to the output terminals of the first DC blocking and AC passing circuit and the second DC blocking and AC passing circuit, and is used to generate the simulated ramp voltage signal source based on the AC components output by the first DC blocking and AC passing circuit and the second DC blocking and AC passing circuit, and to control the voltage amplitude of the simulated ramp voltage signal source when the filtered signal changes.

[0017] Optionally, the AC component control circuit includes a first transistor group having a PMOS transistor and an NMOS transistor connected in series, wherein the gate of the PMOS transistor is coupled to the output terminal of the first DC blocking AC circuit, and the gate of the NMOS transistor is coupled to the output terminal of the second DC blocking AC circuit, and the output of the series node of the PMOS transistor and the NMOS transistor generates the simulated ramp voltage signal source.

[0018] Optionally, the AC component extraction circuit further includes:

[0019] The first bias circuit has its output terminal coupled to the gate of the PMOS transistor and is used to apply a first DC bias voltage to the PMOS transistor.

[0020] The second bias circuit has its output terminal coupled to the gate of the NMOS transistor and is used to apply a second DC bias voltage to the NMOS transistor.

[0021] The first transistor group is turned on under the bias of the first DC bias voltage and the second bias voltage, and the simulated ramp voltage signal source makes the voltage-to-current circuit work.

[0022] Optionally, the ramp voltage generating circuit further includes at least one of the following (1) to (5):

[0023] (1) The first DC blocking and AC passing circuit includes a first DC blocking capacitor, one end of which is coupled to the output terminal of the low-pass filter circuit, and the other end is coupled to the gate of the PMOS transistor and the output terminal of the first bias circuit.

[0024] (2) The second DC blocking and AC passing circuit includes a second DC blocking capacitor. One end of the second DC blocking capacitor is coupled to the output terminal of the low-pass filter circuit, and the other end is coupled to the gate of the NMOS transistor and the output terminal of the second bias circuit.

[0025] (3) The first bias circuit includes a first bias resistor, one end of which is coupled to the first DC bias voltage and the other end is coupled to the gate of the PMOS transistor, for reducing the first DC bias voltage and then supplying it to the PMOS transistor.

[0026] (4) The second bias circuit includes a second bias resistor, one end of which is coupled to the second DC bias voltage and the other end is coupled to the gate of the NMOS transistor, for reducing the second DC bias voltage and then supplying it to the NMOS transistor;

[0027] (5) When the filtered signal rises, the AC component control circuit reduces the voltage of the simulated ramp voltage signal source, and when the filtered signal falls, the AC component control circuit raises the voltage of the simulated ramp voltage signal source.

[0028] Optionally, the voltage-to-current circuit includes a second transistor group, which includes a plurality of MOS transistors, and the plurality of MOS transistors in the second transistor group constitute a current mirror structure. The current mirror structure converts the voltage of the simulated ramp voltage signal source into current and outputs the current mirror.

[0029] Optionally, the ramp voltage output circuit includes a constant current source and a charging / discharging capacitor. One end of the constant current source is coupled to the output terminal of the voltage-to-current circuit and one end of the charging / discharging capacitor to form the output terminal of the ramp voltage output circuit. The ratio between the current provided by the constant current source and the current output by the voltage-to-current circuit is used to control the magnitude of the charging / discharging current when the charging / discharging capacitor is charging and discharging.

[0030] Based on the same inventive concept, the present invention also provides an electronic device comprising a ramp voltage generating circuit as described in the present invention.

[0031] Optionally, the electronic device may be an analog-to-digital converter, a control chip, a power converter, or a display device.

[0032] Optionally, the electronic device is a power converter with an adaptive on-time control architecture, or a control chip for a power converter with an adaptive on-time control architecture. The electronic device further includes an upper power switch, a lower power switch, an inductor, at least one output capacitor, a logic control circuit, an on-time control circuit, and a comparator. The connection node of the upper and lower power switches is coupled to one end of the inductor. The other end of the inductor is coupled to one end of each output capacitor and the input terminal of the ramp voltage generation circuit. The other end of each output capacitor is grounded. The output terminal of the ramp voltage generation circuit is coupled to one input terminal of the comparator. The output terminals of the on-time control circuit and the comparator are both coupled to the logic control circuit. The output terminal of the logic control circuit is coupled to the control terminals of the upper and lower power switches, so as to drive the upper and lower power switches to alternately conduct according to the on-time signal provided by the on-time control circuit and the signal provided by the comparator.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. The ramp voltage generating circuit of the present invention has a low-pass filter circuit, an AC component extraction circuit, a voltage-to-current conversion circuit and a ramp voltage output circuit coupled in sequence. It can perform low-pass filtering, AC component extraction, voltage change conversion into current change and finally output the current change as ramp voltage. The circuit design is simple.

[0035] 2. The ramp voltage generation circuit of the present invention can be applied to corresponding electronic devices to meet application requirements and improve the performance of electronic devices. For example, when the ramp voltage generation circuit is applied to a power converter or control chip with an adaptive constant on-time control architecture, it can solve the system stability problem caused by the low equivalent series resistance of the output capacitor of the control chip, and at the same time meet the application requirements of the control chip. Attached Figure Description

[0036] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0037] Figure 1 This is a schematic diagram of the architecture of a ramp voltage generation circuit according to an embodiment of the present invention.

[0038] Figure 2 This is a schematic diagram of the AC component extraction circuit in a ramp voltage generation circuit according to an embodiment of the present invention.

[0039] Figure 3This is a schematic diagram of an example structure of a ramp voltage generation circuit according to an embodiment of the present invention.

[0040] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of an example architecture of an electronic device according to an embodiment of the present invention.

[0042] Figure 6 This is a schematic diagram of another example architecture of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] Please refer to Figure 1 An embodiment of the present invention provides a ramp voltage generating circuit 10, which includes a low-pass filter circuit 101, an AC component extraction circuit 102, a voltage-to-current conversion circuit 103 and a ramp voltage output circuit 104 coupled in sequence.

[0045] The input terminal of the low-pass filter circuit 101 is coupled to the input terminal of the ramp voltage generating circuit 10 to receive the voltage VOUT input to the ramp voltage generating circuit 10. The low-pass filter circuit 101 is used to perform low-pass filtering on the voltage VOUT received at the input terminal of the ramp voltage generating circuit 10 and output the filtered signal VLPF_OUT.

[0046] The input terminal of the AC component extraction circuit 102 is coupled to the output terminal of the low-pass filter circuit 101. The AC component extraction circuit 102 is used to extract the AC component in the filtered signal VLPF_OUT output by the low-pass filter circuit 101 to generate an analog ramp voltage signal source Vo.

[0047] The input terminal of the voltage-to-current circuit 103 is coupled to the output terminal of the AC component extraction circuit 102. The voltage-to-current circuit 103 is used to convert the voltage change of the analog ramp voltage signal source Vo generated by the AC component extraction circuit 102 into the current change.

[0048] The input terminal of the ramp voltage output circuit 104 is coupled to the output terminal of the voltage-to-current circuit 103, and the output terminal of the ramp voltage output circuit 104 is coupled to the output terminal of the ramp voltage generating circuit 10, and is used to output the current change generated by the voltage-to-current circuit 103 as the ramp voltage VRAMP.

[0049] It should be understood that the low-pass filter circuit 101, AC component extraction circuit 102, voltage-to-current circuit 103 and ramp voltage output circuit 104 in this embodiment can adopt any suitable circuit design, as long as they can achieve the above functions.

[0050] For example, the low-pass filter circuit 101 can be an active low-pass filter (e.g., including active devices such as operational amplifiers), or a passive RC low-pass filter or a passive RL low-pass filter. It can be a first-order filter formed by a single filter or a multi-order filter formed by cascading multiple filters. Therefore, the low-pass filter circuit 101 can include at least one of an active low-pass filter, a passive RC low-pass filter, or a passive RL low-pass filter.

[0051] As an example, please refer to Figure 3 The low-pass filter circuit 101 is a first-order passive RC low-pass filter, which includes a first resistor RLF and a first capacitor CLF. One end of the first resistor RLF is coupled to the input terminal of the low-pass filter circuit 101 to receive the voltage VOUT. The other end of the first resistor RLF is coupled to one end of the first capacitor CLF and the output terminal of the low-pass filter circuit 101. The other end of the first capacitor CLF is grounded. When the ramp generation circuit 10 is working normally, VOUT is first low-pass filtered by RLF and CLF to remove high-frequency noise interference and form a filtered signal (or "filtered voltage") VLPF_OUT.

[0052] Optionally, the low-pass filter circuit 101 in this example also includes a second resistor R2, which is connected in parallel with the first capacitor CLF. That is, one end of the second resistor R2 is coupled to one end of the first capacitor CLF and the other end of the first resistor RLF, and the other end of the second resistor R2 is grounded. The second resistor R2 and the first resistor RLF form a voltage divider circuit to control the magnitude of the filtered signal VLPF_OUT.

[0053] In one example, please refer to Figure 2 The AC component extraction circuit 102 includes a first DC blocking AC circuit 1021, a second DC blocking AC circuit 1022, and an AC component control circuit 1023.

[0054] The first DC blocking AC passing circuit 1021 is coupled to the output of the low-pass filter circuit 101 to receive the filtered signal VLPF_OUT output by the low-pass filter circuit 101. The first DC blocking AC passing circuit 1021 is used to extract the AC component in the filtered signal VLPF_OUT. The first DC blocking AC passing circuit 1021 can adopt any suitable circuit design, for example, it includes a first DC blocking capacitor CHP1. The first terminal of the first DC blocking capacitor CHP1 is coupled to the filtered signal VLPF_OUT, and the second terminal of the first DC blocking capacitor CHP1 is coupled to the AC component control circuit 1023. The first DC blocking capacitor CHP1 can isolate the DC component in the filtered signal VLPF_OUT, so that the DC component in the filtered signal VLPF_OUT cannot pass through, but the AC component in the filtered signal VLPF_OUT is allowed to pass through.

[0055] The second DC-blocking AC-passing circuit 1022 is coupled to the output of the low-pass filter circuit 101 to receive the filtered signal VLPF_OUT output by the low-pass filter circuit 101. The second DC-blocking AC-passing circuit 1022 is used to extract the AC component in the filtered signal VLPF_OUT. The second DC-blocking AC-passing circuit 1022 can adopt any suitable circuit design, for example, it includes a second DC-blocking capacitor CHP2. The first end of the second DC-blocking capacitor CHP2 is coupled to the filtered signal VLPF_OUT, and the second end of the second DC-blocking capacitor CHP2 is coupled to the AC component control circuit 1023. The second DC-blocking capacitor CHP2 can isolate the DC component in the filtered signal VLPF_OUT, so that the DC component in the filtered signal VLPF_OUT cannot pass through, but the AC component in the filtered signal VLPF_OUT is allowed to pass through.

[0056] An AC component control circuit 1023 is coupled to the output terminal of the first DC blocking and AC passing circuit 1021 (i.e., the second terminal of the first DC blocking capacitor CHP1) and the output terminal of the second DC blocking and AC passing circuit 1022 (i.e., the second terminal of the second DC blocking capacitor CHP2). This AC component control circuit 1023 generates a simulated ramp voltage signal source Vo based on the AC components output from the first and second DC blocking and AC passing circuits 1021 and 1022, and controls the voltage amplitude of the simulated ramp voltage signal source Vo as the filtered signal VLPF_OUT changes. Specifically, when VLPF_OUT increases, the AC component control circuit 1023 slightly decreases the Vo voltage; when VLPF_OUT decreases, the AC component control circuit 1023 slightly increases the Vo voltage.

[0057] The AC component control circuit 1023 can employ any suitable circuit design. For example, the AC component control circuit 1023 includes a first transistor group having a PMOS transistor MP1 and an NMOS transistor MN1 connected in series. The source of PMOS transistor MP1 is coupled to the power supply voltage VDD, the drain of PMOS transistor MP1 is coupled to the drain of NMOS transistor MN1, the gate of PMOS transistor MP1 is coupled to the output of a first DC-blocking AC circuit 1021, the source of NMOS transistor MN1 is grounded, and the gate of NMOS transistor MN1 is coupled to the output of a second DC-blocking AC circuit 1022. The output of the series node of PMOS transistor MP1 and NMOS transistor MN1 generates an analog ramp voltage signal source Vo. It should be understood that both PMOS transistor MP1 and NMOS transistor MN1 can be a single MOS transistor, or at least one of PMOS transistor MP1 and NMOS transistor MN1 can be formed by multiple MOS transistors connected in series.

[0058] Optionally, the AC component extraction circuit 102 in this example further includes a first bias circuit 1024 and a second bias circuit 1025. The output of the first bias circuit 1024 is coupled to the gate of the PMOS transistor MP1 and is used to apply a first DC bias voltage VBP1 to the PMOS transistor MP1; the output of the second bias circuit 1025 is coupled to the gate of the NMOS transistor MN1 and is used to apply a second DC bias voltage VBN1 to the NMOS transistor MN1. Thus, the first transistor group (i.e., MP1 and MN1) is turned on under the bias of the first DC bias voltage VBP1 and the second bias voltage VBN1, and the simulated ramp voltage signal source Vo causes the voltage-to-current circuit 103 to operate. It should be understood that the first bias circuit 1024 and the second bias circuit 1025 can each adopt any suitable circuit design. For example, the first bias circuit 1024 includes a first bias resistor RH1, one end of which is coupled to a first DC bias voltage VBP1, and the other end of which is coupled to the gate of a PMOS transistor MP1. The first bias resistor RH1 is used to reduce the voltage of the first DC bias voltage VBP1 and then supply it to the PMOS transistor MP1 to meet the bias requirements of the PMOS transistor MP1. The second bias circuit 1025 includes a second bias resistor RH2, one end of which is coupled to a second DC bias voltage VBN1, and the other end of which is coupled to the gate of an NMOS transistor MN1. The second bias resistor RH2 is used to reduce the voltage of the second DC bias voltage VBN1 and then supply it to the NMOS transistor MN1 to meet the bias requirements of the NMOS transistor MN1. In this example, setting a reasonable first DC bias voltage VBP1 and second DC bias voltage VBN1 can ensure that the corresponding switches or MOS transistors in the voltage-to-current circuit (e.g., Figure 3 MN2 in the middle is turned on.

[0059] Please continue to refer to this. Figure 3 In one example, the voltage-to-current circuit 103 includes a second transistor group comprising multiple MOS transistors connected in a manner that enables these MOS transistors to form a current mirror structure (the mirror ratio can be 1:1 or other). This current mirror structure converts the voltage of the simulated ramp voltage signal source Vo into a current and outputs the current mirrored.

[0060] For example, the second transistor group includes NMOS transistors MN2 and MN3, and PMOS transistors MP2 and MP3. The gate of NMOS transistor MN2 is coupled to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN3 to receive an analog ramp voltage signal source Vo. The sources of NMOS transistors MN2 and MN3 are grounded. The drain of NMOS transistor MN3 is coupled to the drain, gate, and gate of PMOS transistor MP2 and MP3. The sources of PMOS transistors MP2 and MP3 are coupled to the power supply voltage VDD. The drain of PMOS transistor MP3 is the output terminal of the voltage-to-current circuit 103. MN2 and MN3 form the first current mirror structure, converting the voltage change of Vo into a current change. MP3 and MP2 form the second current mirror structure, mirroring (the mirror ratio can be 1:1 or other values) the current of MN3 (i.e., the current that changes with the voltage change of Vo), thus converting the voltage change of Vo into the current change of MP3.

[0061] Please refer to Figure 3 In one example, the ramp voltage output circuit 104 includes a constant current source I0 and a charging / discharging capacitor CRAMP. One end of the constant current source I0 is coupled to the output terminal of the voltage-to-current circuit 103 (i.e., the drain of the PMOS transistor MP3) and one end of the charging / discharging capacitor CRAMP, forming the output terminal of the ramp voltage output circuit 104. The ratio between the current provided by the constant current source I0 and the current output by the voltage-to-current circuit 103 can control the magnitude of the charging / discharging current of the charging / discharging capacitor CRAMP, thereby generating the desired ramp voltage VRAMP across the charging / discharging capacitor CRAMP.

[0062] Please refer to Figure 4 This embodiment also provides an electronic device having a ramp voltage generating circuit 10 as described in this embodiment.

[0063] Optionally, the electronic device can be any suitable electronic device such as an analog-to-digital converter, a control chip, a power converter, or a display device, and can be used as a reference signal, slope compensation signal, control signal, etc., thereby meeting the application requirements of these electronic devices and improving their performance.

[0064] The following example demonstrates the application of this ramp voltage generation circuit 10 in a power converter with an adaptive constant on-time control (ACOT) architecture, or in the control chip of a power converter with an ACOT architecture. Figure 5 The application effects of the ramp voltage generating circuit 10 of the present invention are explained in detail.

[0065] In one example, please refer to Figure 5 The ACOT architecture power converter includes a control chip 1, an inductor L, and an output capacitor COUT. The control chip 1 internally includes a ramp voltage generation circuit 10, a conduction time control circuit 12, a comparator 11, a logic control circuit 13, an upper power switch HS, and a lower power switch LS. The connection node of the upper power switch HS and the lower power switch LS is coupled to one end of the inductor L. The other end of the inductor L is coupled to one end of the output capacitor COUT and the input terminal of the ramp voltage generation circuit 10. The output terminal of the ramp voltage generation circuit 10 is coupled to one input terminal of the comparator 11. The output terminals of the conduction time control circuit 12 and the comparator 11 are both coupled to the logic control circuit 13. The output terminal of the logic control circuit 13 is coupled to the control terminals of the upper power switch HS and the lower power switch LS, so as to drive the upper power switch HS and the lower power switch LS to conduct alternately according to the conduction time signal provided by the conduction time control circuit 12 and the signal provided by the comparator 11 (e.g., a PWM signal).

[0066] When the ACOT architecture power converter DC-DC circuit is operating normally, the current in inductor L rises at a fixed slope when the upper power switch HS is on and the lower power switch LS is off. When the upper power switch HS is off and the lower power switch LS is on, the current in inductor L falls at a fixed slope. The connection node between inductor L and output capacitor COUT is coupled to the corresponding load (not shown) and provides the output voltage VOUT to the load. The average value of the current amplitude change of inductor L is the load current (not shown). The time period during which HS and LS switch once is one cycle, and the proportion of the conduction time of HS in this cycle is the duty cycle of the circuit.

[0067] Furthermore, the VOUT voltage waveform is actually a voltage signal similar to the ramp voltage VRAMP waveform. However, due to the presence of the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor COUT, as well as the generation of LC oscillations, some high-frequency oscillation components are superimposed on the VOUT waveform. In this embodiment, the ramp voltage generation circuit 10 is coupled to the VOUT and performs a series of processes such as low-pass filtering and AC component extraction on the VOUT to generate a ramp voltage VRAMP. The ramp voltage VRAMP can reflect the changes in the VOUT, and the control chip 1 can adjust the output of the comparator 11 based on the changes in the ramp voltage VRAMP. This allows the logic control circuit 13 to control the conduction time of HS and maintain a constant period based on the changes in the output of the comparator 11 and the conduction time signal output by the conduction time control circuit 12, thereby achieving duty cycle adjustment and thus adjusting the output voltage VOUT.

[0068] Therefore, the solution in this example can address the system stability issues caused by the low equivalent series resistance of the output capacitor surrounding the control chip 1, while also meeting the application requirements of the control chip's peripheral components. Thus, the system can maintain stability even without an output capacitor COUT with a large equivalent series resistance (ESR).

[0069] Therefore, in this example, the output capacitor COUT can be a multilayer ceramic capacitor (also known as a "surface mount device") with a large capacitance value and a small equivalent series resistance (ESR) (e.g., 2 molΩ). However, the technical solution of this invention is not limited to this. For other examples of this invention, please refer to... Figure 6 The ACOT architecture power converter includes a control chip 1, an inductor L, and multiple output capacitors (e.g., two output capacitors C1 and C2). One end of each output capacitor is coupled to the other end of the inductor L, and the other ends of each output capacitor are grounded, thus connecting the output capacitors in parallel. While the capacitance values ​​of these output capacitors are relatively small, their parallel connection effectively forms a power converter such as... Figure 5 The large output capacitor COUT shown is designed to meet the application requirements of this ACOT architecture power converter.

[0070] In summary, the ramp voltage generating circuit of the present invention, through its internally coupled low-pass filter circuit, AC component extraction circuit, voltage-to-current conversion circuit, and ramp voltage output circuit, can sequentially perform low-pass filtering, AC component extraction, voltage change conversion into current change, and finally output the current change as ramp voltage. The circuit design is simple and can be used for control chips, display devices, or signal conversion (such as analog-to-digital converters, power converters, etc.).

[0071] The electronic device of the present invention has improved performance due to the use of the ramp voltage generating circuit of the present invention.

[0072] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A ramp voltage generating circuit, characterized in that, include: A low-pass filter circuit is coupled to the input terminal of the ramp voltage generating circuit and is used to perform low-pass filtering on the voltage received at the input terminal of the ramp voltage generating circuit and output a filtered signal. An AC component extraction circuit, coupled to the low-pass filter circuit, is used to extract the AC component from the filtered signal to generate an analog ramp voltage signal source. A voltage-to-current circuit is coupled to the AC component extraction circuit and is used to convert the voltage change of the simulated ramp voltage signal source into a current change. The ramp voltage output circuit has its input terminal coupled to the voltage-to-current circuit and is used to output the current change as a ramp voltage.

2. The ramp voltage generating circuit as described in claim 1, characterized in that, The low-pass filter circuit includes at least one of an active low-pass filter, a passive RC low-pass filter, and a passive RL low-pass filter.

3. The ramp voltage generating circuit as described in claim 2, characterized in that, The passive RC low-pass filter includes a first resistor and a first capacitor. One end of the first resistor is coupled to the input terminal of the low-pass filter circuit, and the other end of the first resistor is coupled to one end of the first capacitor and the output terminal of the low-pass filter circuit.

4. The ramp voltage generating circuit as described in claim 3, characterized in that, The low-pass filter circuit also includes a second resistor, which is connected in parallel with the first capacitor.

5. The ramp voltage generating circuit as described in claim 1, characterized in that, The AC component extraction circuit includes: The first DC blocking and AC passing circuit is coupled to the output of the low-pass filter circuit and is used to extract the AC component in the filtered signal. The second DC blocking and AC passing circuit is coupled to the output of the low-pass filter circuit and is used to extract the AC component in the filtered signal. An AC component control circuit is coupled to the output terminals of the first DC blocking and AC passing circuit and the second DC blocking and AC passing circuit, and is used to generate the simulated ramp voltage signal source according to the AC components output by the first DC blocking and AC passing circuit and the second DC blocking and AC passing circuit, and to control the voltage amplitude of the simulated ramp voltage signal source when the filtered signal changes.

6. The ramp voltage generating circuit as described in claim 5, characterized in that, The AC component control circuit includes a first transistor group having a PMOS transistor and an NMOS transistor connected in series. The gate of the PMOS transistor is coupled to the output of the first DC blocking AC circuit, and the gate of the NMOS transistor is coupled to the output of the second DC blocking AC circuit. The output of the series node of the PMOS transistor and the NMOS transistor generates the simulated ramp voltage signal source.

7. The ramp voltage generating circuit as described in claim 6, characterized in that, The AC component extraction circuit further includes: The first bias circuit has its output terminal coupled to the gate of the PMOS transistor and is used to apply a first DC bias voltage to the PMOS transistor. The second bias circuit has its output terminal coupled to the gate of the NMOS transistor and is used to apply a second DC bias voltage to the NMOS transistor. The first transistor group is turned on under the bias of the first DC bias voltage and the second bias voltage, and the simulated ramp voltage signal source makes the voltage-to-current circuit work.

8. The ramp voltage generating circuit as described in claim 7, characterized in that, It also includes at least one of the following (1) to (5): (1) The first DC blocking and AC passing circuit includes a first DC blocking capacitor, one end of which is coupled to the output terminal of the low-pass filter circuit, and the other end is coupled to the gate of the PMOS transistor and the output terminal of the first bias circuit. (2) The second DC blocking and AC passing circuit includes a second DC blocking capacitor. One end of the second DC blocking capacitor is coupled to the output terminal of the low-pass filter circuit, and the other end is coupled to the gate of the NMOS transistor and the output terminal of the second bias circuit. (3) The first bias circuit includes a first bias resistor, one end of which is coupled to the first DC bias voltage and the other end is coupled to the gate of the PMOS transistor, for reducing the first DC bias voltage and then supplying it to the PMOS transistor. (4) The second bias circuit includes a second bias resistor, one end of which is coupled to the second DC bias voltage and the other end is coupled to the gate of the NMOS transistor, for reducing the second DC bias voltage and then supplying it to the NMOS transistor; (5) When the filtered signal rises, the AC component control circuit reduces the voltage of the simulated ramp voltage signal source, and when the filtered signal falls, the AC component control circuit raises the voltage of the simulated ramp voltage signal source.

9. The ramp voltage generating circuit as described in claim 1, characterized in that, The voltage-to-current circuit includes a second transistor group, which includes multiple MOS transistors. The multiple MOS transistors in the second transistor group form a current mirror structure. The current mirror structure converts the voltage of the simulated ramp voltage signal source into current and outputs the current mirror.

10. The ramp voltage generating circuit as described in any one of claims 1-9, characterized in that, The ramp voltage output circuit includes a constant current source and a charging / discharging capacitor. One end of the constant current source is coupled to the output terminal of the voltage-to-current circuit and one end of the charging / discharging capacitor to form the output terminal of the ramp voltage output circuit. The ratio between the current provided by the constant current source and the current output by the voltage-to-current circuit is used to control the magnitude of the charging / discharging current when the charging / discharging capacitor is charging and discharging.

11. An electronic device, characterized in that, Includes the ramp voltage generating circuit as described in any one of claims 1-9.

12. The electronic device as claimed in claim 11, characterized in that, The electronic device is an analog-to-digital converter, a control chip, a power converter, or a display device.

13. The electronic device as claimed in claim 11 or 12, characterized in that, The electronic device is a power converter with an adaptive on-time control architecture, or a control chip for a power converter with an adaptive on-time control architecture. The electronic device also includes an upper power switch, a lower power switch, an inductor, at least one output capacitor, a logic control circuit, an on-time control circuit, and a comparator. The connection node of the upper and lower power switches is coupled to one end of the inductor. The other end of the inductor is coupled to one end of each output capacitor and the input terminal of the ramp voltage generation circuit. The other end of each output capacitor is grounded. The output terminal of the ramp voltage generation circuit is coupled to one input terminal of the comparator. The output terminals of the on-time control circuit and the comparator are both coupled to the logic control circuit. The output terminal of the logic control circuit is coupled to the control terminals of the upper and lower power switches, driving the upper and lower power switches to alternately conduct according to the on-time signal provided by the on-time control circuit and the signal provided by the comparator.

Images