A large-current DDR power supply stabilizer circuit

Abstract

The embodiment of the application provides a large-current DDR power supply stabilizer circuit, which comprises: a dual-power supply structure, the dual-power supply structure comprising a power supply and a control power supply; a dual-loop stabilizer, the dual-loop stabilizer comprising a pull-up current loop and a pull-down current loop, and the dual-loop stabilizer being connected with the dual-power supply structure; the pull-up current loop comprising a first operational amplifier and a pull-up power tube, and the pull-down current loop comprising a second operational amplifier and a pull-down power tube. The application provides a complete power supply solution with high stability, fast transient response, ultra-low power consumption and compatibility with a wide range of DDR standards, effectively meeting the stringent requirements of advanced application scenarios such as artificial intelligence servers and high-performance computing.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to a high-current DDR power supply regulator circuit. Background Technology

[0002] With the rapid development of memory technology, the operating voltage of DDR memory continues to decrease to achieve higher integration and energy efficiency. This trend places extremely stringent requirements on power supply systems: voltage regulators must provide stable high current at ultra-low output voltages and have the ability to respond quickly to load transients. However, traditional linear voltage regulator architectures have fundamental limitations. They typically use PMOS power transistors, resulting in large chip areas, high manufacturing costs, and the ability to provide only unidirectional pull-up current, which cannot meet the sink current requirements necessary for bidirectional data read and write operations in DDR memory. Furthermore, the voltage regulation performance and transient response of traditional architectures deteriorate significantly when the output voltage approaches the extremely low levels required by nanometer-level process nodes, becoming a key technical bottleneck restricting the performance improvement of advanced computing devices.

[0003] like Figure 1 As shown, the traditional LDO structure has the following three main technical limitations, which prevent it from meeting the power supply requirements of modern DDR:

[0004] 1. Unidirectional load carrying: Traditional LDOs typically use PMOS as power transistors, which can only provide pull-up current, meaning they can only output current to the load. However, DDR memory has bidirectional data read / write characteristics, requiring the regulator to have both pull-up and sink current capabilities. Traditional structures cannot actively absorb current and cannot meet the sink current requirements of DDR.

[0005] 2. High current load is not only large in area but also expensive: If traditional structures are to achieve high current load, due to the low hole mobility of PMOS, a very large aspect ratio needs to be designed, resulting in a huge chip area.

[0006] 3. Difficulty in achieving ultra-low output voltage: Traditional architectures struggle to guarantee high-performance voltage regulation and transient response when the output voltage is extremely low. Summary of the Invention

[0007] The high-current DDR power supply regulator circuit provided in this application provides a complete power supply solution with high stability, fast transient response, ultra-low power consumption and compatibility with a wide range of DDR standards, effectively meeting the stringent requirements of advanced application scenarios such as artificial intelligence servers and high-performance computing.

[0008] In a first aspect, embodiments of this application provide a high-current DDR power supply regulator circuit, including:

[0009] The dual power supply structure includes a power supply and a control power supply. The power supply VLDOIN is used to power the power output stage, and the control power supply VIN is used to power the analog circuit.

[0010] A dual-loop voltage regulator includes a pull-up current loop and a pull-down current loop to achieve pull-up and pull-down current. The dual-loop voltage regulator is connected to a dual-power supply structure.

[0011] The pull-up current loop includes a first operational amplifier and a pull-up power transistor M0, and the pull-down current loop includes a second operational amplifier and a pull-down power transistor M1;

[0012] The non-inverting input of the first operational amplifier U1 is connected to the reference voltage VREF terminal and the control power supply VIN terminal. The inverting input of the first operational amplifier is grounded. The output of the first operational amplifier U1 is connected to the gate of the pull-up power transistor M0 to provide a gate drive signal for the pull-up power transistor M0.

[0013] The non-inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier, the inverting input of the second operational amplifier U2 is connected to the output voltage VO, and the output of the second operational amplifier U2 is connected to the gate of the pull-down power transistor M1 to control the conduction level of the pull-down power transistor M1.

[0014] The gate of the pull-up power transistor M0 is connected to the output terminal of the first operational amplifier U1, the source of the pull-up power transistor is connected to the output voltage VO terminal, and the drain of the pull-up power transistor is connected to the power supply VLDOIN terminal.

[0015] The gate of the pull-down power transistor M1 is connected to the output terminal of the second operational amplifier U2, the drain of the pull-down power transistor is connected to the output voltage VO terminal, and the source of the pull-down power transistor is grounded.

[0016] In one optional implementation, the voltage range of the power supply VLDOIN is 1.2V to 2.5V, and the voltage range of the control power supply VIN is 2.5V to 3.3V.

[0017] In one alternative implementation, both the pull-up power transistor M0 and the pull-down power transistor M1 are NMOS power transistors.

[0018] In one alternative implementation, the first operational amplifier U1 and the second operational amplifier U2 are implemented through an error amplifier circuit, and the error amplifier adopts a three-stage amplifier structure.

[0019] In one alternative implementation, the first stage of the error amplifier uses a PMOS input transistor, the second stage is a folded cascode structure, and the third stage is a source negative feedback amplifier.

[0020] In one alternative implementation, it further includes:

[0021] Bandgap reference circuit and buffer circuit;

[0022] The output of the bandgap reference circuit is connected to the reference voltage VREF terminal to provide a low-temperature drift reference voltage;

[0023] The input of the buffer circuit is coupled to the output of the bandgap reference circuit, and the output of the buffer circuit is connected to the reference input of the error amplifier. The buffer circuit is connected to the bandgap reference circuit and the error amplifier circuit to enhance the reference voltage driving capability.

[0024] In one alternative implementation, it further includes:

[0025] The GM amplifier has two input terminals connected to the sampling signal of the output voltage VO and the reference voltage REFOUT, respectively. The output terminal of the GM amplifier is connected to the gate drive circuit of the pull-up power transistor M0 and the pull-down power transistor M1 to enhance the transient response when the load changes.

[0026] In one alternative implementation, the GM amplifier employs a two-stage amplifier structure, with the first stage being a resistive load of the PMOS input transistor and the second stage employing current cancellation technology.

[0027] In one alternative implementation, a 0.35μm BCD process is used, with an output load capacitance of 20μF and a phase margin greater than 56°.

[0028] In one optional implementation, the no-load static current is 440μA~700μA, the output voltage fluctuation is 50mV when the load current jumps from 0A to 3A, and the settling time is less than 5μs.

[0029] The technical solution provided in this application has the following beneficial effects:

[0030] This invention constructs independent pull-up and pull-down current loops, enabling the voltage regulator to simultaneously provide pull-up and pull-down currents. The two loops can monitor the output voltage in real time and compare it with a reference voltage, independently driving the push-pull output stage. This fundamentally solves the problem of bidirectional current flow in DDR memory due to its bidirectional data read / write characteristics, ensuring power supply stability during high-speed data read / write processes. The push-pull output stage uses low-threshold NMOS transistors, leveraging the inherent characteristics of high electron mobility and low on-resistance of NMOS devices. This structure allows it to provide a large drive current even at extremely low output voltages, successfully breaking through the minimum voltage limitation of traditional PMOS architectures. This not only significantly reduces chip area but also provides a reliable technological reserve for future DDR memory with continuously decreasing operating voltages. A GM amplifier is introduced as an auxiliary control path, detecting... When a load undergoes a sharp change, the device is rapidly activated and instantly adjusts the gate voltage of the power transistor via a high-gain path. This innovatively solves the core problem of large output voltage fluctuations during high-current transitions, ensuring rapid voltage recovery and stability in high-speed data exchange scenarios. By separating the power supply from the control power supply, which supplies power to the power output stage and the precision analog circuit respectively, each power domain only carries the necessary voltage and current, avoiding unnecessary power loss and significantly reducing the static power consumption of the chip in no-load conditions. This makes the invention particularly suitable for power-sensitive mobile devices and IoT applications. Through the synergistic effect of the above technologies, a complete power supply solution with high stability, fast transient response, ultra-low power consumption, and compatibility with a wide range of DDR standards is formed, effectively meeting the stringent requirements of advanced application scenarios such as artificial intelligence servers and high-performance computing. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a conventional voltage regulator architecture circuit provided in an embodiment of this application;

[0032] Figure 2 This is a simplified schematic diagram of a high-current DDR power supply regulator circuit provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of the complete structure of a high-current DDR power supply regulator circuit provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the principle structure of a bandgap reference circuit provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the principle structure of a buffer circuit provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of an error amplifier circuit structure provided in an embodiment of this application;

[0037] Figure 7 This is a simplified diagram of amplifier stability analysis provided in an embodiment of this application;

[0038] Figure 8 This is a simulation diagram of the output voltage of a voltage regulator provided in an embodiment of this application;

[0039] Figure 9 This is a static power consumption simulation diagram provided in an embodiment of this application;

[0040] Figure 10 This is a stability simulation diagram provided in an embodiment of this application; Figure 10 (a) shows the current jacking gain and phase margin; Figure 10 (b) represents the sink current gain and phase margin;

[0041] Figure 11 This is a transient response simulation diagram provided in an embodiment of this application; Figure 11 (a) is the transient response diagram of the traction current; Figure 11 (b) is the transient response diagram of the sink current. Detailed Implementation

[0042] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] As described in the background section, with the rapid development of semiconductor technology, 5nm process has achieved mass production, driving the evolution of memory technology from DRAM and SDRAM to DDR SDRAM. The continuous increase in clock frequency and data transfer rate has led to a continuous decrease in power supply voltage, while the storage capacity of memory has increased significantly. This places stringent requirements on DDR power supply chips for miniaturization, low power supply voltage, high current and low power consumption. As a memory cell with double the read and write speed, DDR's power supply regulator must have bidirectional load capacity to achieve efficient data processing. However, most existing regulators are only unidirectional and have insufficient load capacity, which cannot meet the needs of high-speed data exchange. Therefore, designing a linear regulator that combines pull-in and sink current capacity, fast transient response and low power consumption has become an inevitable choice for DDR applications. This invention aims to solve these technical bottlenecks and provide an efficient power supply solution for artificial intelligence servers, high-performance computing and mobile devices.

[0044] This application provides a high-current DDR power supply regulator circuit. Figure 2 This is a simplified schematic diagram of a high-current DDR power supply regulator circuit provided in an embodiment of this application. Figure 3 This is a schematic diagram of the complete structure of a high-current DDR power supply regulator circuit provided in an embodiment of this application, as shown below. Figure 2 and Figure 3 As shown, the circuit includes:

[0045] The dual power supply structure includes a power supply and a control power supply; the main purpose of this separate design is to reduce static power consumption and improve energy efficiency by providing optimized voltage domains for different circuit modules.

[0046] Specifically, the power supply VLDOIN directly supplies power to the power output stage, with a voltage range of 1.2V to 2.5V. It only needs to meet the power supply requirements of the DDR load. The lower input voltage can reduce the voltage drop on the power transistor, thereby significantly reducing dynamic power consumption and heat generation.

[0047] The control power supply VIN supplies power to analog circuits (such as error amplifiers, bandgap reference circuits, etc.), and its voltage range is 2.5V~3.3V. The higher voltage ensures that the NMOS power transistors have sufficient gate drive voltage (especially for pull-up power transistors M0, the gate voltage must be higher than the output voltage + threshold voltage), thus guaranteeing circuit performance.

[0048] By separating the power and control power domains, the extra power consumption caused by the high voltage difference in the traditional single power supply architecture can be avoided. This is the key means of reducing static power consumption (i.e., the no-load static current reaches 440μA~700μA) in this invention. This design avoids the need for the entire power stage to withstand unnecessary high voltage drop in order to meet the high voltage difference simulation circuit in the traditional single power supply architecture, thereby optimizing energy efficiency at the system level.

[0049] A dual-loop voltage regulator includes a pull-up current loop and a pull-down current loop, and is connected to a dual-power supply structure.

[0050] The pull-up current loop provides the source current, supplying power to the output when the load requires current, while the pull-down current loop draws current from the output when the load needs to release current. The dual loops adjust based on the real-time comparison of the output voltage and the reference voltage. These two loops operate independently, ensuring voltage stability during high-speed DDR read / write operations.

[0051] The pull-up current loop includes a first operational amplifier and a pull-up power transistor M0, and the pull-down current loop includes a second operational amplifier and a pull-down power transistor M1;

[0052] The non-inverting input of the first operational amplifier U1 is connected to the reference voltage VREF and the control power supply VIN. VREF provides a stable voltage comparison reference for the amplifier, while VIN serves as the control power supply to power the amplifier itself. The inverting input of the first operational amplifier is grounded. U1 operates as a comparator or high-gain amplifier, comparing and amplifying the reference voltage VREF at its non-inverting input with the ground potential. The output of the first operational amplifier U1 is directly connected to the gate of the pull-up power transistor M0, providing a gate drive signal for M0.

[0053] The non-inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier. The activation and control reference of the pull-down loop is directly related to the state of the pull-up loop, realizing the coordinated control of the two loops. The inverting input of the second operational amplifier U2 is connected to the output voltage VO terminal to monitor the actual value of the output voltage in real time. The output of the second operational amplifier U2 is directly connected to the gate of the pull-down power transistor M1 to control its conduction level.

[0054] The gate of the pull-up power transistor M0 is connected to the output terminal of the first operational amplifier U1, the source of the pull-up power transistor is connected to the output voltage VO terminal, directly providing current to the load, and the drain of the pull-up power transistor is connected to the power supply VLDOIN terminal, serving as the input source of power current.

[0055] The gate of the pull-down power transistor M1 is connected to the output terminal of the second operational amplifier, the drain of the pull-down power transistor is connected to the output voltage VO terminal, and the current returned by the load is absorbed from here. The source of the pull-down power transistor is grounded.

[0056] Both pull-up power transistor M0 and pull-down power transistor M1 are NMOS power transistors. This choice is based on the inherent advantages of NMOS transistors compared to PMOS transistors.

[0057] In semiconductors, electron mobility is much higher than hole mobility. This means that for the same silicon area, NMOS transistors can provide much greater transconductance and lower on-resistance than PMOS transistors. Traditional PMOS designs require very large aspect ratios to achieve high current loads, resulting in a huge chip footprint. In contrast, the NMOS transistors used in this application can reduce the area by approximately 60% while maintaining the same load capacity. Traditional PMOS power transistors have a specific turn-on condition (the gate voltage must be lower than the source voltage by a threshold value |V)... THN |), at the output voltage V OUT At very low voltages, it is difficult to generate a sufficiently low gate drive voltage to ensure its operation in the linear region (i.e., as a controllable resistor). The turn-on condition for an NMOS power transistor (M0) is that the gate voltage is higher than the source voltage by a threshold voltage V. THN Since the output voltage (i.e., the source voltage of M0) of this invention can be as low as 0.6V, it is only necessary to provide its gate with a voltage higher than (V).OUT + V THN A sufficient drive voltage (provided by a higher control power supply VIN domain) is required to fully turn on M0, thereby stabilizing and maintaining a low output voltage. The higher transconductance of the NMOS transistor means a larger drain current change for the same gate voltage variation. This characteristic allows the power stage to respond faster to the error amplifier output signal, which is beneficial for quickly adjusting the output current to stabilize the voltage during drastic load current changes (such as from 0A to 3A), thus improving transient performance.

[0058] Figure 6 This is a schematic diagram of an error amplifier circuit structure provided in an embodiment of this application. See also... Figure 6 Furthermore, the first operational amplifier U1 and the second operational amplifier U2 are implemented through an error amplifier circuit, which adopts a three-stage amplifier structure. The first stage of the error amplifier uses a PMOS input transistor, the second stage is a folded cascode structure, and the third stage is a source negative feedback amplifier.

[0059] The first stage of the error amplifier uses PMOS transistors as the differential input pair. The advantage of the PMOS input stage is that its input common-mode range can approach or even include ground potential (GND). This is crucial for the low output voltage applications of this invention, as it allows the error amplifier to operate normally even when the input voltage (i.e., the feedback output voltage VO) is extremely low. Its operating principle is to convert the voltage difference between VO and VREF into a differential current. This ensures that the error amplifier input stage remains in the linear operating region even at output voltages as low as 0.6V, enabling accurate acquisition of the error voltage and laying the foundation for high-precision voltage regulation.

[0060] The second stage employs a folded cascode amplifier. This structure "folds" the differential output current generated by the PMOS input pair in the first stage onto a cascode load composed of NMOS transistors via a current mirror. Due to its high output impedance, the cascode structure provides extremely high voltage gain in the first stage of amplification. This extremely high voltage gain means that even small output voltage errors can generate sufficiently large control voltage changes, thereby greatly improving the regulator's line regulation (its ability to suppress input voltage changes) and load regulation (its ability to suppress load current changes), ensuring the accuracy of the output voltage.

[0061] The third stage employs an amplifier structure with source degeneration. By connecting a resistor in series with the source of the transistor (or utilizing the transistor's own impedance to achieve negative feedback), its transconductance (gm) can be stabilized, extending the amplifier's linear input range and reducing output impedance. The lower output impedance allows for rapid charging and discharging of the large gate capacitances of the power transistors (M0 and M1), crucial for achieving fast transient response. The negative feedback further stabilizes the gain, reduces nonlinear distortion, and ensures the accuracy of the control signal throughout the operating range.

[0062] Furthermore, the circuit also includes a bandgap reference circuit and a buffer circuit. Figure 4 This is a schematic diagram of the principle structure of a bandgap reference circuit provided in an embodiment of this application. See also... Figure 4 The core function of the bandgap reference circuit is to generate a highly stable reference voltage VREF that hardly changes with temperature (low temperature drift), providing an accurate voltage reference for the entire voltage regulation system. This is the basis for the error amplifier to compare and adjust.

[0063] In this embodiment, a low-temperature-drift reference voltage is first generated using a Kujik bandgap reference structure. The operational amplifier clamping mechanism ensures that the voltages at nodes A and B are equal. By adjusting the values ​​of resistors R1 and R3, a reference voltage VREF with a low temperature coefficient is obtained. Its output voltage expression is VREF = VBE2 + (R3 / R1)(VT × ln8); where VBE2 is the base-emitter voltage of the bipolar transistor, with a negative temperature coefficient; VT is the thermal voltage (VT = kT / q), with a positive temperature coefficient; and R3 / R1 is the resistance ratio. Through proper design, the positive and negative temperature coefficients compensate for each other, achieving a reference voltage with near-zero temperature drift. This structure ensures the stability of VREF over a wide temperature range, directly improving the output accuracy of the voltage regulator. Based on this reference voltage, a traditional simplified LDO structure is used to generate bias voltages VBIAS1-VBIAS4 and a PTAT current I = VREF / (R4+R5). A current mirror is used to provide a stable bias for subsequent circuits.

[0064] The output of the bandgap reference circuit is directly connected to the reference voltage VREF, providing a reference for the non-inverting input of the error amplifier. Through a low-temperature drift design, the bandgap reference circuit solves the output voltage drift problem caused by temperature fluctuations in traditional reference sources, making it particularly suitable for applications with extremely high voltage accuracy requirements, such as DDR memory.

[0065] Figure 5 This is a schematic diagram of the principle structure of a buffer circuit provided in an embodiment of this application. See also... Figure 5The buffer circuit is connected between the bandgap reference circuit and the error amplifier. Its main function is to enhance the driving capability of VREF, prevent the reference voltage from attenuating or distorting due to the input impedance load effect of the subsequent circuit (such as the error amplifier), and ensure the complete transmission of the reference signal.

[0066] The buffer circuit employs a folded cascode PMOS input transistor structure with 64 input transistors to enhance sensitivity. A Class AB control structure increases the slew rate. N-type transconductance loops (N13 / N12 / N16 / N17) and P-type transconductance loops (P17 / P18 / P19 / P20) ensure that the two sets of VGS are equal, guaranteeing the accuracy of the current mirror. N16 and P19 form a Class AB control circuit as a floating voltage source, ensuring that the gate voltages of output transistors P20 and N17 remain relatively constant, providing a ±10mA load capacity to drive the subsequent error amplifier. This design gives the buffer high input impedance and low output impedance, enabling it to drive the large capacitive load of the subsequent error amplifier without introducing significant errors.

[0067] The input of the buffer circuit is coupled to the output of the bandgap reference circuit, and its output is connected to the reference input of the error amplifier, forming a buffer isolation layer for the reference voltage. Through its high slew rate and strong drive capability, the buffer ensures rapid stabilization of the reference voltage during load transients, reducing system response delay and indirectly improving the transient performance of the voltage regulator.

[0068] A bandgap reference circuit generates a precise reference voltage VREF, which is then enhanced by a buffer circuit to output REFOUT. An error amplifier uses REFOUT as a reference, compares it with the output voltage VO, and adjusts the power transistor accordingly. This cascaded design avoids the stability issues caused by the bandgap reference directly driving a high-capacitive load, supporting the realization of low-dropout, high-precision voltage regulation.

[0069] Furthermore, the circuit also includes a GM amplifier, see reference [link to reference]. Figure 3 and Figure 6 GM amplifiers in Figure 3 Marked as "GM" in Figure 6 The GM amplifier, labeled "auxiliary operational amplifier," has two input terminals connected to the sampling signal of the output voltage VO and the reference voltage REFOUT, respectively. The output terminal of the GM amplifier is connected to the gate drive circuit of the pull-up power transistor M0 and the pull-down power transistor M1. The GM amplifier is used to quickly turn on when the load changes and adjust the gate voltage of the power transistors to stabilize the output. The GM amplifier (transconductance amplifier) ​​is not the main error amplifier, but an auxiliary path designed specifically to handle fast transient events.

[0070] In DDR memory operation, the load current undergoes a rapid and dramatic change within a very short time (e.g., from zero amperes to several amperes). At this time, although the main error amplifier loop (e.g., ...) Figure 6 The transistor (as shown) is responsible for steady-state accuracy, but its bandwidth and slew rate are limited, making it unable to achieve instantaneous and rapid drive of the power transistor's gate independently. This results in significant overshoot or undershoot in the output voltage, as well as a long recovery time, which may lead to data read / write errors. Therefore, this embodiment introduces a GM amplifier to solve this high-speed transient response problem.

[0071] As a high-bandwidth, high-slew-rate auxiliary amplifier, the core function of the GM amplifier is to detect the instantaneous voltage difference between the output voltage (VO) and the reference voltage (REFOUT) at the moment of load change, and respond quickly by injecting a large current to regulate the gate voltage of the power transistors (M0 and M1).

[0072] In steady state or with slow changes, the GM amplifier may be in a shut-off or low-power state to save quiescent current. Once a rapid and large voltage difference is detected between VO and REFOUT (a sign of load switching), the GM amplifier is quickly activated (turned on) and enters the operating state.

[0073] Once activated, the GM amplifier, through its high-gain transconductance stage, instantly converts the detected voltage error into a large drive current, which acts directly on the gate node of the power transistor. This powerful current greatly accelerates the charging and discharging process of the power transistor's gate capacitance, thereby rapidly changing its conduction state and quickly supplying or absorbing a large amount of current to the load to offset the effects of load fluctuations.

[0074] Continue to refer to Figure 6 The GM amplifier (auxiliary operational amplifier loop) adopts a two-stage amplifier structure. The first stage is a resistive load of the PMOS input transistor, and the second stage uses current cancellation technology to greatly improve the gain. By reasonably designing the R16 resistor to control the voltage difference between VO and REFOUT, it can quickly start to work when the load changes significantly.

[0075] By introducing a GM amplifier, when the load current jumps from 0A to 3A, the output voltage fluctuation is controlled within approximately 50V, and the settling time is shortened to below 5μs. This demonstrates that the GM amplifier effectively solves the transient response problem during high current jumps, ensuring the extreme stability of the DDR memory power supply voltage during high-speed read and write operations and preventing data errors.

[0076] Furthermore, Figure 7 This is a simplified diagram of amplifier stability analysis provided in an embodiment of this application, for reference. Figure 7In terms of stability design, Miller compensation is applied to the three-stage amplifier, where CL is the compensation capacitor, RESR1 is the equivalent resistance of the output capacitor, RL1 is the load resistance, RS is the equivalent resistance of the current source of the second-stage amplifier, and C0 is the gate capacitance of the power transistor. Small-signal analysis yields three poles and two zeros, ensuring that the phase margin is above 56° when the output load capacitance is 20μF. 20μF is a common external filter capacitor configuration value for DDR memory modules. In this embodiment, 20μF was selected as the standard load condition in simulation verification, proving that the circuit not only works under this capacitor but also remains stable. 56° is the simulated phase margin result under this capacitor load. Generally, a phase margin greater than 45° is considered stable for analog circuits. The results of this embodiment (>56°) demonstrate that the circuit has excellent robustness and does not oscillate, reflecting the high stability of this design.

[0077] In some embodiments, the layout design uses interdigitated metal traces to ensure uniform current distribution, employs a core-matched symmetrical design for the amplifier input transistors, and the power transistor layout meets the 3A current load requirement.

[0078] Furthermore, this embodiment is implemented using a 0.35μm BCD process.

[0079] Figure 8 This is a simulation diagram of the output voltage of a voltage regulator provided in an embodiment of this application. See also... Figure 8 The figure shows the DC output voltage characteristics of the regulator under typical operating conditions. The horizontal axis represents temperature, and the vertical axis represents the output voltage VO. Simulation results demonstrate that under different input voltages (VLDOIN = 1.2V~2.5V) and process angles (TT / FF / SS), the output voltage VO can be stabilized near the target value (e.g., 1.2V) with minimal fluctuation. This verifies the effectiveness of the high-precision VREF provided by the bandgap reference circuit, the high gain of the error amplifier, and the overall negative feedback loop, indicating that the circuit can achieve accurate voltage regulation under various operating conditions, meeting the basic requirements of DDR memory for power supply voltage stability.

[0080] Figure 9 This is a static power consumption simulation diagram provided in an embodiment of this application. See also... Figure 9The graph shows the total quiescent current IQ of the circuit under no-load (IOUT=0A) conditions. The horizontal axis represents temperature, and the vertical axis represents quiescent current. Simulation waveforms show that under different VIN voltages (2.5V~3.3V) and temperature conditions, the quiescent current IQ stabilizes within the range of 440μA to 700μA. This figure verifies the effectiveness of the dual-supply architecture in reducing quiescent power consumption: the control circuitry (amplifiers, bandgap references, etc.) is powered by a higher VIN to ensure performance, while the power stage is powered by a lower VLDOIN to reduce unnecessary voltage drop losses, thus achieving an overall quiescent current significantly lower than that of traditional architectures. This is crucial for battery-powered mobile devices.

[0081] Figure 10 This is a stability simulation diagram provided in an embodiment of this application; Figure 10 (a) shows the current jacking gain and phase margin; Figure 10 (b) The sink current gain and phase margin are used to analyze loop stability. The horizontal axis represents frequency (Hz, logarithmic scale), and the vertical axes represent gain (dB) and phase (degrees), respectively. The figure contains two curves: the gain curve (amplitude response) and the phase curve. The gain curve shows that the loop gain decreases as the frequency increases, and the frequency value at unity-gain bandwidth (UGBW) reflects the loop velocity. The key conclusion comes from the phase curve: at the frequency point where the gain drops to 0 dB (i.e., the UGBW point), the phase value at this point is read, and the difference between this and -180° is the phase margin (PM). Simulation results clearly show that with an output load capacitance of 20μF, the phase margin is greater than 56°. This proves that through the stability design such as the three-stage Miller compensation in this embodiment, the circuit has sufficient stability margin, will not oscillate, ensures a smooth response during dynamic processes such as load transients, and verifies its robustness.

[0082] Figure 11 This is a transient response simulation diagram provided in an embodiment of this application; Figure 11 (a) is the transient response diagram of the traction current; Figure 11 (b) is the transient response diagram of the sink current; as shown Figure 11 As shown in (a), the load current IOUT jumps from 0A to 3A and then back to 0A, simulating DDR memory suddenly entering a high-speed read operation from an idle state. At the instant of the sudden increase in load current, VO experiences a downsurge due to the increased load; at the instant of the sudden decrease in load current, VO experiences an upsurge due to excess energy. Waveform data shows that the downsurge voltage is approximately 25.69mV with a settling time of approximately 3.08μs; the upsurge voltage is approximately 24.37mV with a settling time of approximately 4.65μs. This demonstrates that the pull-up current loop (M0) can respond quickly, providing the required current to the load, suppressing voltage fluctuations to a very small range, and recovering rapidly. Figure 11 As shown in (b), its waveform is similar to Figure 11 (a) Similarly, but with the load current jump direction reversed, simulating the rapid disappearance of current at the end of a DDR write operation. Waveform data shows that the overshoot voltage is approximately 15.73mV with a settling time of approximately 1.48μs; the undershoot voltage is approximately 27.37mV with a settling time of approximately 5.61μs. This demonstrates that the pull-down current loop (M1) can effectively absorb the energy from the load backflow and prevent voltage spikes.

[0083] Figure 11 The two figures together verify the dual-loop regulator's ability to achieve true bidirectional current operation and demonstrate the effectiveness of the GM amplifier introduction—it acts quickly during drastic load changes (0A-3A / 1μs), controlling the output voltage fluctuation to within about 50mV and shortening the settling time to about 5μs, fully meeting the stringent requirements of DDR memory for high-speed transient response of the power supply.

[0084] The working principle of this invention is based on an innovative dual-loop control mechanism: When the system is working, the bandgap reference circuit first generates a stable low-temperature drift reference voltage VREF, which is then enhanced and driven by a buffer to serve as the reference voltage for the error amplifier. The dual-loop regulator precisely adjusts the voltage by comparing the difference between the output voltage VO and the reference voltage REFOUT in real time—the upper loop operates during current pulling; when the load increases and causes VO to drop, the voltage difference generated by the first-stage resistive load of the main operational amplifier increases, which is amplified by the folded cascode amplifier to raise the voltage of OUT1. The pull-down current is reduced through the current mirror structure, allowing the VO potential to rise again; the lower loop operates symmetrically during current sinking. When the load experiences a sharp change, the GM auxiliary amplifier is quickly activated. It adopts a two-stage high-gain structure and is triggered by detecting the voltage difference between VO and REFOUT. The change in the OUT2 voltage drives a high-current path, instantly adjusting the gate voltage of the power transistor to stabilize the output. The entire system ensures stability through three-level Miller compensation. The power stage uses a low-threshold NMOS push-pull output to achieve output voltage regulation as low as 0.6V under a dual power domain architecture, while maintaining an ultra-low static power consumption of 440-700μA.

[0085] This invention offers significant advantages in terms of safety, ease of operation, and adaptability to small spaces, while also saving manpower and resources.

[0086] The components in the accompanying drawings of this invention are for illustrative purposes only and are not intended to represent specific dimensions. The specific dimensions are determined based on actual production requirements, and the materials of each component can be replaced as needed.

[0087] All electrical components in this invention are commercially available conventional devices known to those skilled in the art. Models can be selected or customized according to actual needs. The setting method, installation method and electrical connection method can be easily understood by those skilled in the art by following the instructions for use, and will not be described in detail here.

[0088] The above embodiments are merely illustrative examples and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A high-current DDR power supply regulator circuit, characterized in that, include: A dual power supply structure is provided, comprising a power supply VLDOIN and a control power supply VIN. The power supply VLDOIN is used to supply power to the power output stage, and the control power supply VIN is used to supply power to the analog circuit. A dual-loop voltage regulator, comprising a pull-up current loop and a pull-down current loop, for realizing pull-down current, wherein the dual-loop voltage regulator is connected to the dual power supply structure; The pull-up current loop includes a first operational amplifier and a pull-up power transistor M0, and the pull-down current loop includes a second operational amplifier and a pull-down power transistor M1; The non-inverting input of the first operational amplifier U1 is connected to the reference voltage VREF and the control power supply VIN. The inverting input of the first operational amplifier is grounded. The output of the first operational amplifier U1 is connected to the gate of the pull-up power transistor M0 to provide a gate drive signal for the pull-up power transistor M0. The non-inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier, the inverting input of the second operational amplifier U2 is connected to the output voltage VO, and the output of the second operational amplifier U2 is connected to the gate of the pull-down power transistor M1 to control the conduction degree of the pull-down power transistor M1. The gate of the pull-up power transistor M0 is connected to the output terminal of the first operational amplifier U1, the source of the pull-up power transistor is connected to the output voltage VO terminal, and the drain of the pull-up power transistor is connected to the power supply VLDOIN terminal. The gate of the pull-down power transistor M1 is connected to the output terminal of the second operational amplifier U2, the drain of the pull-down power transistor is connected to the output voltage VO terminal, and the source of the pull-down power transistor is grounded.

2. The circuit according to claim 1, characterized in that, The voltage range of the power supply VLDOIN is 1.2V~2.5V, and the voltage range of the control power supply VIN is 2.5V~3.3V.

3. The circuit according to claim 1, characterized in that, Both the pull-up power transistor M0 and the pull-down power transistor M1 are NMOS power transistors.

4. The circuit according to claim 1, characterized in that, The first operational amplifier U1 and the second operational amplifier U2 are implemented through an error amplifier circuit, and the error amplifier adopts a three-stage amplifier structure.

5. The circuit according to claim 4, characterized in that, The error amplifier uses a PMOS input transistor in the first stage, a folded cascode structure in the second stage, and a source negative feedback amplifier in the third stage.

6. The circuit according to claim 4, characterized in that, Also includes: Bandgap reference circuit and buffer circuit; The output of the bandgap reference circuit is connected to the reference voltage VREF terminal to provide a low-temperature drift reference voltage. The input terminal of the buffer circuit is coupled to the output terminal of the bandgap reference circuit, and the output terminal of the buffer circuit is connected to the reference input terminal of the error amplifier. The buffer circuit is connected to the bandgap reference circuit and the error amplifier circuit to enhance the reference voltage driving capability.

7. The circuit according to claim 1, characterized in that, Also includes: The GM amplifier has two input terminals connected to the sampling signal of the output voltage VO and the reference voltage REFOUT, respectively. The output terminal of the GM amplifier is connected to the gate drive circuit of the pull-up power transistor M0 and the pull-down power transistor M1, which is used to enhance the transient response when the load changes.

8. The circuit according to claim 7, characterized in that, The GM amplifier adopts a two-stage amplifier structure. The first stage is a resistive load of the PMOS input transistor, and the second stage uses current cancellation technology.

9. The circuit according to claim 1, characterized in that, It is implemented using a 0.35μm BCD process, with an output load capacitance of 20μF and a phase margin greater than 56°.

10. The circuit according to claim 1, characterized in that, The no-load static current is 440μA~700μA, and the output voltage fluctuation is 50mV when the load current jumps from 0A to 3A, with a settling time of less than 5μs.

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