A low voltage bandgap reference circuit with high power supply rejection ratio

Abstract

The application relates to a low-voltage bandgap reference circuit with high power supply rejection ratio, comprising: a start-up circuit for making the circuit operating point out of degeneration region when the power supply is powered on, and automatically shutting down after the reference voltage is established; a high power supply rejection ratio improving circuit comprising a negative feedback loop for suppressing the fluctuation of the node voltage with the power supply voltage by adjusting the current flowing to the internal power supply node, so as to generate a stable internal power supply voltage on the internal power supply node; and a reference core circuit containing an operational amplifier, the power supply end of the operational amplifier being connected to the internal power supply node to be powered by the internal power supply voltage, the reference core circuit being used for generating a reference voltage based on the internal power supply voltage after the start-up circuit completes starting. By introducing a pre-modulation circuit outside the traditional bandgap core structure, the power supply disturbance is pre-fed and compensated, so that the power supply noise is suppressed before entering the bandgap core, thereby significantly improving the overall power supply rejection ratio.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a low-voltage bandgap reference circuit with high power supply rejection ratio. Background Technology

[0002] Bandgap reference circuits are used to generate reference voltages that are independent of both the supply voltage and temperature. Their basic principle is based on the base-emitter junction voltage Vo of a bipolar transistor. BE The negative temperature coefficient and the difference ΔV between the base-emitter junction voltage of the bipolar transistor at different current densities. BE By linearly combining the positive temperature coefficients of various components, first-order temperature compensation is achieved, thereby generating a stable reference voltage. This is the core reference module in analog integrated circuits. As the reference voltage for each comparator, the output accuracy and stability of the reference voltage play a crucial role in the accuracy of the chip's voltage output.

[0003] Traditional bandgap reference circuits, such as Figure 1 As shown, the circuit consists of operational amplifier A1, PMOS transistors MP1, MP2, and MP3, resistors R1 and R2, and PNP bipolar transistors Q1, Q2, and Q3. The size of Q2 is typically N times that of Q1; for layout matching, N is usually an integer such as 8, 24, or 48. MP1 and MP2 are generally the same size, forming a current mirror structure to control the drain current I flowing through MP1 and MP2. D1 and I D2 Same. I D1 and I D2 The current flows entirely into Q1 and Q2 respectively, therefore the current flowing through Q1 and Q2 is the same. The dual-loop feedback loop formed by the operational amplifier controls the voltages at points V1 and V2 to be the same, so the voltage drop across resistor R1 is equal to the junction voltage V0 of transistors Q1 and Q2. BE The difference, according to the junction voltage formula V BE =V T ln(I C / I S The voltage drop across R1 can be obtained as V. T Therefore, the current flowing through R1 is V. T lnN / R1. The current in R1 is copied to R2 through a current mirror, thereby generating a reference voltage V. REF =V BE3 +(R2 / R1) V T lnN. To ensure that the positive and negative temperature coefficients of the reference voltage are equal, the generated reference voltage is typically 1.25V.

[0004] With the miniaturization of integrated circuit technology, chip operating voltages are decreasing, making it difficult to implement traditional bandgap reference structures under low power supply voltage conditions. Therefore, low-voltage bandgap reference structures are needed to achieve low reference voltages. However, under low-voltage process conditions, traditional bandgap reference circuits face the problem of decreased power supply rejection ratio (PSRR), especially when the power supply voltage changes rapidly or ripple interference is present. The reference voltage is easily affected, thus reducing the overall system performance. In applications such as industrial encoders, the system typically operates over a wide input voltage range, accompanied by voltage fluctuations and high-frequency noise from industrial buses, which places higher demands on the PSRR of the bandgap reference. Current technologies often improve PSRR by increasing operational amplifier gain or adding filter capacitors, but these methods suffer from increased power consumption, increased area, or difficulty in applying them to low-voltage conditions. Furthermore, increasing operational amplifier gain can worsen the PSRR at high frequencies, often requiring an increase in operational amplifier bandwidth to enhance PSRR at high frequencies, which inevitably increases circuit power consumption significantly.

[0005] Therefore, it is necessary to propose a bandgap reference circuit structure that can effectively improve the power supply rejection ratio across the entire frequency band under low voltage conditions without significantly increasing power consumption and area. Summary of the Invention

[0006] The purpose of this invention is to provide a low-voltage bandgap reference circuit with a high power supply rejection ratio, so as to solve the shortcomings of existing low-voltage bandgap reference circuits in terms of power supply rejection capability.

[0007] To achieve the above objectives, the present invention provides a low-voltage bandgap reference circuit with high power supply rejection ratio, comprising:

[0008] The startup circuit is used to move the circuit's operating point out of the degenerate region when the power supply is turned on, and to automatically shut down after the reference voltage is established.

[0009] A high power supply rejection ratio (PSRR) improvement circuit has its input connected to a power supply voltage and its output connected to an internal power supply node. The high PSRR improvement circuit includes a negative feedback loop, which is used to suppress the fluctuation of the node voltage with the power supply voltage by adjusting the current flowing to the internal power supply node, thereby generating a stable internal power supply voltage at the internal power supply node.

[0010] The reference core circuit includes an operational amplifier whose power supply terminal is connected to the internal power node to be powered by the internal power supply voltage. The reference core circuit is used to generate a reference voltage based on the internal power supply voltage after the startup circuit has completed startup.

[0011] Optionally, the startup circuit consists of transistors MS1~MS5, MP1, MP2, and MR1~MR3; wherein MS1, MS3, MP1, MP2, MR1, MR2, and MR3 are PMOS transistors, and MS2, MS4, and MS5 are NMOS transistors.

[0012] The gate of MS1 is connected to the switch control signal ENB, the source is connected to the power supply voltage VDD, and the drain is connected to the source of MR1. The gates of MR1~MR3, the drain of MR3, the source of MS2, the source of MS4, and the gate of MS5 are connected together. The drain of MR1 is connected to the source of MR2, and the drain of MR2 is connected to the source of MR3. The gate of MS2 is connected to the reference voltage, and the source is grounded to GND. The gate of MS3 is connected to the switch control signal EN, the source is connected to the power supply voltage VDD, the drain is connected to the lower plate of capacitor C1 and the output terminal of the operational amplifier, and the upper plate of capacitor C1 is connected to the power supply voltage VDD. The gate of MS4 is connected to the switch control signal ENB, and the source is grounded to GND. The drain of MS5 is connected to the gate and drain of MP1 and the gate of MP2, and the source of MS5 is grounded to GND. The sources of MP1 and MP2 are both connected to the power supply voltage VDD, and the drain of MP2 is connected to the reference core circuit.

[0013] Optionally, the reference core circuit includes PMOS transistors MP3~MP5, resistors R1~R4, bipolar transistors Q1 and Q2, and the operational amplifier; wherein,

[0014] The sources of MP3, MP4, and MP5 are all connected to the internal power supply node, and their gates are interconnected and connected to the output of the operational amplifier. The drain of MP3 is connected to the drain of MP2, one end of R2, the emitter of Q1, and the inverting input of the operational amplifier. The drain of MP4 is connected to one end of R1, one end of resistor R3, and the non-inverting input of the operational amplifier. The drain of MP5 is connected to one end of R4 and serves as the reference voltage output. The other end of R1 is connected to the emitter of Q2. The other ends of R2, R3, and R4, as well as the bases and collectors of Q1 and Q2, are all grounded to GND.

[0015] Optionally, MP3, MP4, and MP5 can be the same size.

[0016] Optionally, the emitter junction area of ​​Q2 is 8 times that of Q1.

[0017] Optionally, at least one of R2, R3, and R4 is an adjustable resistor with an adjustable resistance value.

[0018] Optionally, the operational amplifier includes PMOS transistors MP12~MP16, NMOS transistors MN6~MN8, resistor R5, and capacitor C2; wherein,

[0019] The sources of MP12, MP13, and MP14 are interconnected and connected to the internal power supply node; the gate and drain of MP12 are interconnected and connected together with the gates of MP13 and MP14 to the bias current input terminal IB2 of operational amplifier A1; the gates of MP15 and MP16 serve as the inverting input terminal and the non-inverting input terminal of operational amplifier A1, respectively, and the sources of MP15 and MP16 are connected to the drain of MP14; the gates of MN6 and MN7 are interconnected and connected to the drain of MN6 and the drain of MP15; the drain of MN7 is connected to one end of R5 and the gate of MN8; the drain of MN8 is connected to the drain of MP14, one end of C2, and serves as the output terminal of operational amplifier A1; the other end of R5 is connected to the other end of C2.

[0020] Optionally, the high power supply rejection ratio improvement circuit includes PMOS transistors MP6~MP11 and NMOS transistors MN1~MN5; wherein,

[0021] The sources of MP10 and MP11 are connected to the power supply voltage VDD. The drain of MP10 is connected to the sources of MP6, MP7, and MP9, the drain of MN5, and the internal power supply node. The gate of MP10 is connected to the gate and drain of MP11 and the drain of MN2. The gates of MN1 to MN4 are interconnected with the drain of MN1 and connected to the bias current input terminal IB1. The sources of MN1 to MN4 are all grounded to GND. The drain of MN3 is connected to the gate of MN5 and the drain of MP9. The drain of MN4 is connected to the drain and gate of MP6. The gate of MP6 is connected to the gate of MP7. The drain of MP7 is connected to the source of MP8 and the gate of MP9.

[0022] Optionally, the negative feedback loop consists of MP9 and MN5; wherein,

[0023] The source of MP9 is connected to the internal power node, the gate of MP9 is connected to a bias voltage, and the drain of MP9 is connected to the gate of MN5; the drain of MN5 is connected to the internal power node, and its source is grounded.

[0024] Optionally, the high power supply rejection ratio (PSRR) enhancement circuit is configured to increase the PSRR of the internal power node voltage by (1+T) compared to the PSRR of the power supply voltage. loop ) times, of which T loop is the loop gain of the negative feedback loop.

[0025] The low-voltage bandgap reference circuit with high power supply rejection ratio provided by this invention has at least one of the following beneficial effects:

[0026] (1) By introducing a pre-modulation circuit outside the traditional bandgap core structure, the power supply disturbance is fed forward to compensate, so that the power supply noise is suppressed before entering the bandgap core, thereby significantly improving the overall power supply rejection ratio.

[0027] (2) A stable internal power supply is generated by the "high power supply rejection ratio improvement circuit" to power the reference core circuit. This makes the operating voltage of the reference core circuit no longer directly limited by the potentially low external power supply voltage, but generated by the internal circuit, thereby "achieving a stable output of low reference voltage" to meet the low voltage requirements of advanced processes;

[0028] (3) Compared with the method of simply increasing the gain of the operational amplifier, the present invention has lower requirements for the performance of the operational amplifier, which is conducive to low voltage design and does not require large-area off-chip capacitors or high power consumption structures. It is suitable for integrated circuit implementation, and at the same time, it can ensure that the power supply rejection ratio does not degrade at high frequencies, and achieve power supply interference resistance at high frequencies. Attached Figure Description

[0029] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0030] Figure 1 This is a circuit schematic of a traditional bandgap reference circuit.

[0031] Figure 2 This is a circuit schematic diagram of a low-voltage bandgap reference circuit with high power supply rejection ratio provided in an embodiment of the present invention;

[0032] Figure 3 The circuit schematic diagram of an operational amplifier provided in an embodiment of the present invention;

[0033] Figure 4 The figure shows the simulation results of the power supply rejection ratio of the bandgap reference provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0036] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0037] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] Please refer to Figure 2 This invention provides a low-voltage bandgap reference circuit with high power supply rejection ratio, comprising:

[0039] The startup circuit is used to move the circuit's operating point out of the degenerate region when the power supply is turned on, and to automatically shut down after the reference voltage is established.

[0040] The high power supply rejection ratio (PSRR) improvement circuit has its input connected to the power supply voltage and its output connected to an internal power supply node V7. The high power supply rejection ratio improvement circuit includes a negative feedback loop, which is used to suppress the fluctuation of the node voltage with the power supply voltage by adjusting the current flowing to the internal power supply node V7, thereby generating a stable internal power supply voltage at the internal power supply node V7.

[0041] The reference core circuit includes an operational amplifier A1, the power supply terminal of which is connected to an internal power supply node V7 to be powered by the internal power supply voltage. The reference core circuit is used to generate a reference voltage based on the internal power supply voltage after the startup circuit has completed startup.

[0042] Traditional methods rely on increasing the gain of the core operational amplifier A1 to improve the power supply rejection ratio (PSRR), but this sacrifices high-frequency performance. This invention employs a "pre-modulation" approach, introducing a pre-modulation circuit outside the traditional bandgap core structure to feedforward compensate for power supply disturbances. This suppresses power supply noise before it enters the bandgap core, significantly improving the overall PSRR. Compared to simply increasing the gain of operational amplifier A1, this invention places lower demands on A1 performance, facilitating low-voltage design and eliminating the need for large-area off-chip capacitors or high-power structures, making it suitable for integrated circuit implementation. Simultaneously, it ensures that the PSRR does not degrade at high frequencies, achieving high-frequency immunity to power supply interference.

[0043] Specifically, such as Figure 1 As shown, the startup circuit consists of transistors MS1~MS5, MP1, MP2, and MR1~MR3; among them, MS1, MS3, MP1, MP2, MR1, MR2, and MR3 are PMOS transistors, and MS2, MS4, and MS5 are NMOS transistors.

[0044] The gate of MS1 is connected to the switch control signal ENB, the source is connected to the power supply voltage VDD, and the drain is connected to the source of MR1. The gates of MR1~MR3, the drain of MR3, the source of MS2, the source of MS4, and the gate of MS5 are connected together. The drain of MR1 is connected to the source of MR2, and the drain of MR2 is connected to the source of MR3. The gate of MS2 is connected to the reference voltage, and the source is grounded to GND. The gate of MS3 is connected to the switch control signal EN, the source is connected to the power supply voltage VDD, the drain is connected to the lower plate of capacitor C1 and the output terminal of operational amplifier A1, and the upper plate of capacitor C1 is connected to the power supply voltage VDD. The gate of MS4 is connected to the switch control signal ENB, and the source is grounded to GND. The drain of MS5 is connected to the gate and drain of MP1 and the gate of MP2, and the source of MS5 is grounded to GND. The sources of MP1 and MP2 are both connected to the power supply voltage VDD, and the drain of MP2 is connected to the reference core circuit.

[0045] This startup circuit ensures that the entire system can correctly start from a degenerate operating state with zero current and enter the normal operating point upon power-up. After startup, the circuit automatically shuts down to save power.

[0046] The startup process of this startup circuit is as follows: When EN is high and ENB is low, the circuit starts to start, capacitor C1 begins to charge, the voltage at point V2 is pulled down, and MP3~MP5 begin to conduct, injecting current into the circuit below. The loop formed by operational amplifier A1 gradually establishes a stable operating point, and the voltages at points V3 and V4 are kept consistent through negative feedback. Initial state V REF With the voltage at 0V and MS2 off, the deep linear region self-biasing structure composed of MR1~MR3 pulls the voltage at point V1 up to VDD, subsequently turning on MS5, MP1, and MP2. Injecting current into the circuit below via MP2 allows the operating point to move out of the degenerate region, enabling normal circuit operation. When the reference voltage VREF reaches a stable state, MS2 turns on, pulling the gate voltage of MS5 down to GND, turning off MS5 and thus shutting down the startup circuit, reducing static power consumption.

[0047] The reference core circuit includes PMOS transistors MP3~MP5, resistors R1~R4, bipolar transistors Q1 and Q2, and operational amplifier A1; among which,

[0048] The sources of MP3, MP4, and MP5 are all connected to the internal power supply node V7, and their gates are interconnected and connected to the output of operational amplifier A1. The drain of MP3 is connected to the drain of MP2, one end of R2, the emitter of Q1, and the inverting input of operational amplifier A1. The drain of MP4 is connected to one end of R1, one end of resistor R3, and the non-inverting input of operational amplifier A1. The drain of MP5 is connected to one end of R4 and serves as the reference voltage output. The other end of R1 is connected to the emitter of Q2. The other ends of R2, R3, and R4, as well as the bases and collectors of Q1 and Q2, are all grounded to GND.

[0049] The core circuit for generating the reference voltage consists of transistors MP3~MP5, resistors R1~R4, transistors Q1~Q2, and operational amplifier A1. Q1 and Q2 are PNP bipolar transistors, and for layout matching, they are connected in parallel in a 1:8 ratio. After the circuit starts, V3 and V4 have the same potential, and the base-emitter junction voltage V of Q1 and Q2... BE Satisfy the following relation

[0050] (1)

[0051] (2)

[0052] in, This is the saturation current of the transistor. Thermoelectric voltage, and These are the currents flowing through Q1 and Q2, respectively. M13~M15 are designed with identical dimensions, so their drain currents... , , equal.

[0053] (3)

[0054] Simultaneously, the resistances of R2 and R3 are set to be the same. Since V3 and V4 are at the same potential due to the operational amplifier, the current flowing through resistors R2 and R3 is also equal. According to Kirchhoff's current law, we can obtain... and They are also equal. Combining equations (1) and (2), we can obtain the ΔV of the two transistors. BE for

[0055] (4)

[0056] ΔV BE This is also the voltage drop across resistor R1, from which the current across R1 can be calculated.

[0057] (5)

[0058] The current flowing through R3 can be calculated using Ohm's law.

[0059] (6)

[0060] These two currents, biased by a current mirror, ultimately flow through resistors R4~R7, generating different reference voltages, in V... REF For example, this voltage can be expressed as

[0061] (7)

[0062] Preferably, at least one of R2, R3, and R4 is an adjustable resistor with an adjustable resistance value. In this embodiment, R2 to R4 are adjustable resistors and are configured by digital circuitry to calibrate voltage deviations at different process corners.

[0063] Preferably, MP3, MP4, and MP5 players are of the same size to ensure the accuracy of the current mirror.

[0064] Preferably, the emitter junction area of ​​Q2 is N times the emitter junction area of ​​Q1 (e.g., N=8). By setting different area ratios, specific ΔV can be generated. BE It is understood that N can also be other integers greater than 1, such as 24, 48, etc., and this invention does not limit this.

[0065] In this embodiment, as Figure 3As shown, operational amplifier A1 includes PMOS transistors MP12~MP16, NMOS transistors MN6~MN8, resistor R5, and capacitor C2; wherein,

[0066] The sources of MP12, MP13, and MP14 are interconnected and connected to the internal power supply node V7; the gate and drain of MP12 are interconnected and, together with the gates of MP13 and MP14, are connected to the bias current input terminal I of operational amplifier A1. B2 The gates of MP15 and MP16 serve as the inverting and non-inverting inputs of operational amplifier A1, respectively. The sources of MP15 and MP16 are both connected to the drain of MP14. The gates of MN6 and MN7 are interconnected and connected to the drain of MN6 and the drain of MP15. The drain of MN7 is connected to one end of R5 and the gate of MN8. The drain of MN8 is connected to the drain of MP14, one end of C2, and serves as the output of operational amplifier A1. The other end of R5 is connected to the other end of C2.

[0067] In this embodiment, operational amplifier A1 employs a two-stage architecture, which improves loop gain. Resistor R5 and capacitor C2 are connected in series between the outputs of the first stage and the outputs of the second stage for frequency compensation, ensuring loop stability.

[0068] The power supply rejection ratio expression for a low-voltage bandgap reference circuit is:

[0069] (8)

[0070] in: and These are the equivalent small-signal resistances of bipolar transistors Q1 and Q2, respectively. Let A be the gain from the power supply voltage to the output of operational amplifier A1. , , The transconductances of MP3, MP4, and MP5 are respectively. As can be seen from equation (8), increasing the gain of operational amplifier A1 can increase the PSRR of the bandgap reference and increase the power consumption of the circuit. Furthermore, increasing the gain of operational amplifier A1 will lower the dominant pole of the amplifier, thereby deteriorating the high-frequency PSRR performance of the bandgap reference.

[0071] To ensure the PSRR of the bandgap reference at high frequencies without increasing power consumption, this invention adds a high power supply rejection ratio (PSRR) enhancement circuit to the low-voltage bandgap reference. This high PSRR enhancement circuit includes PMOS transistors MP6~MP11 and NMOS transistors MN1~MN5; wherein...

[0072] The sources of MP10 and MP11 are connected to the power supply voltage VDD. The drain of MP10 is connected to the sources of MP6, MP7, and MP9, the drain of MN5, and the internal power supply node V7. The gate of MP10 is connected to the gate and drain of MP11, and the drain of MN2. The gates of MN1 to MN4 are interconnected with the drain of MN1 and connected to the bias current input terminal I. B1 The sources of MN1 to MN4 are all grounded to GND; the drain of MN3 is connected to the gate of MN5 and the drain of MP9; the drain of MN4 is connected to the drain and gate of MP6; the gate of MP6 is connected to the gate of MP7; and the drain of MP7 is connected to the source of MP8 and the gate of MP9.

[0073] The negative feedback loop consists of MP9 and MN5; among them,

[0074] The source of MP9 is connected to the internal power supply node V7, the gate of MP9 is connected to a bias voltage, and the drain of MP9 is connected to the gate of MN5; the drain of MN5 is connected to the internal power supply node V7, and its source is grounded.

[0075] In this embodiment, VDD is the power supply voltage, MN1~MN4, MP6~MP7, and MP10~MP11 provide bias current for their respective branches, and MP9, MN5, and the internal power node V7 constitute a negative feedback loop. The working principle of the negative feedback loop is as follows: when the power supply voltage VDD increases, causing the internal power node V7 to increase, MP9 can be considered a common-gate amplifier, causing the gate voltage of MN5 to increase. Therefore, the drain voltage of MN5 decreases accordingly, i.e., the rise of the internal power node V7 is suppressed. The internal power node V7 is also the power supply voltage of the reference core circuit. Therefore, through this negative feedback loop, the impact of power supply voltage fluctuations on the actual core circuit can be reduced, thereby improving the PSRR of the bandgap reference circuit. The PSRR after adding this circuit increases by (1+T) compared to before. loop ) times, of which T loop This represents the gain of the negative feedback loop.

[0076] This design embodiment is based on Huahong Grace's 110nm process library. Figure 4 The power supply rejection ratio (PSRR) simulation results of the low-voltage bandgap reference circuit designed in this embodiment are presented. The simulation was conducted under relatively stringent conditions: the temperature range was -40℃ to 150℃, covering five process corners: tt, ff, ss, fs, and sf, while the power supply voltage varied from 4.5V to 5.5V, and the simulation frequency range was 0.1Hz to 1GHz, used to comprehensively evaluate the circuit's power supply rejection capability under different operating environments and across the entire frequency band.

[0077] Simulation results show that in the low-frequency range (0.1Hz~1kHz), the PSRR is mainly determined by the high gain of the operational amplifier and the negative feedback loop. High suppression capability is observed at all process corners, indicating that the circuit has a good suppression effect on slowly changing power supply disturbances. In the mid-frequency range (1kHz~100kHz), the PSRR begins to gradually decrease, but remains at a high level overall. At the typical frequency of 10kHz, under the combined conditions of a temperature range of -40℃ to 150℃, a power supply voltage of 4.5V to 5.5V, and different process corners, the simulated PSRR ranges from 59.57dB to 80.21dB, demonstrating the circuit's strong anti-interference capability in the mid-frequency range. In the high-frequency range (>100kHz), the PSRR of traditional bandgap references typically deteriorates significantly due to the bandwidth limitation of the operational amplifier. However, this invention, by introducing a pre-modulation circuit to form feedforward compensation and local negative feedback, results in a smoother PSRR decay at high frequencies without significant collapse, significantly outperforming traditional structures.

[0078] In summary, this invention provides a low-voltage bandgap reference circuit with high power supply rejection ratio (PSRR). By employing a "pre-modulation" approach, a pre-modulation circuit is introduced outside the traditional bandgap core structure to feedforward compensation for power supply disturbances. This suppresses power supply noise before it enters the bandgap core, significantly improving the overall PSRR. Compared to simply increasing the gain of operational amplifier A1, this invention places lower performance requirements on operational amplifier A1, facilitating low-voltage design and eliminating the need for large-area off-chip capacitors or high-power structures. It is suitable for integrated circuit implementation and ensures that the PSRR does not degrade at high frequencies, achieving high-frequency immunity to power supply interference.

[0079] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A low-voltage bandgap reference circuit with high power supply rejection ratio, characterized in that, include: The startup circuit is used to move the circuit's operating point out of the degenerate region when the power supply is turned on, and to automatically shut down after the reference voltage is established. A high power supply rejection ratio (PSRR) improvement circuit has its input connected to a power supply voltage and its output connected to an internal power supply node. The high PSRR improvement circuit includes a negative feedback loop, which is used to suppress the fluctuation of the node voltage with the power supply voltage by adjusting the current flowing to the internal power supply node, thereby generating a stable internal power supply voltage at the internal power supply node. The reference core circuit includes an operational amplifier whose power supply terminal is connected to the internal power node to be powered by the internal power supply voltage. The reference core circuit is used to generate a reference voltage based on the internal power supply voltage after the startup circuit has completed startup.

2. The low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 1, characterized in that, The startup circuit consists of transistors MS1~MS5, MP1, MP2, and MR1~MR3; wherein MS1, MS3, MP1, MP2, MR1, MR2, and MR3 are PMOS transistors, and MS2, MS4, and MS5 are NMOS transistors. The gate of MS1 is connected to the switch control signal ENB, the source is connected to the power supply voltage VDD, and the drain is connected to the source of MR1. The gates of MR1~MR3, the drain of MR3, the source of MS2, the source of MS4, and the gate of MS5 are connected together. The drain of MR1 is connected to the source of MR2, and the drain of MR2 is connected to the source of MR3. The gate of MS2 is connected to the reference voltage, and the source is grounded to GND. The gate of MS3 is connected to the switch control signal EN, the source is connected to the power supply voltage VDD, the drain is connected to the lower plate of capacitor C1 and the output terminal of the operational amplifier, and the upper plate of capacitor C1 is connected to the power supply voltage VDD. The gate of MS4 is connected to the switch control signal ENB, and the source is grounded to GND. The drain of MS5 is connected to the gate and drain of MP1 and the gate of MP2, and the source of MS5 is grounded to GND. The sources of MP1 and MP2 are both connected to the power supply voltage VDD, and the drain of MP2 is connected to the reference core circuit.

3. The low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 2, characterized in that, The reference core circuit includes PMOS transistors MP3~MP5, resistors R1~R4, bipolar transistors Q1 and Q2, and the operational amplifier; wherein... The sources of MP3, MP4, and MP5 are all connected to the internal power supply node, and their gates are interconnected and connected to the output of the operational amplifier. The drain of MP3 is connected to the drain of MP2, one end of R2, the emitter of Q1, and the inverting input of the operational amplifier. The drain of MP4 is connected to one end of R1, one end of resistor R3, and the non-inverting input of the operational amplifier. The drain of MP5 is connected to one end of R4 and serves as the reference voltage output. The other end of R1 is connected to the emitter of Q2. The other ends of R2, R3, and R4, as well as the bases and collectors of Q1 and Q2, are all grounded to GND.

4. The low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 3, characterized in that, MP3, MP4, and MP5 players have the same dimensions.

5. A low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 3, characterized in that, The emitter junction area of ​​Q2 is 8 times that of Q1.

6. The low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 3, characterized in that, At least one of R2, R3, and R4 is an adjustable resistor with an adjustable value.

7. A low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 3, characterized in that, The operational amplifier includes PMOS transistors MP12~MP16, NMOS transistors MN6~MN8, resistor R5, and capacitor C2; wherein... The sources of MP12, MP13, and MP14 are interconnected and connected to the internal power supply node; the gate and drain of MP12 are interconnected and, together with the gates of MP13 and MP14, are connected to the bias current input terminal I of operational amplifier A1. B2 The gates of MP15 and MP16 serve as the inverting and non-inverting inputs of operational amplifier A1, respectively. The sources of MP15 and MP16 are both connected to the drain of MP14. The gates of MN6 and MN7 are interconnected and connected to the drain of MN6 and the drain of MP15. The drain of MN7 is connected to one end of R5 and the gate of MN8. The drain of MN8 is connected to the drain of MP14, one end of C2, and serves as the output of operational amplifier A1. The other end of R5 is connected to the other end of C2.

8. A low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 1, characterized in that, The high power supply rejection ratio improvement circuit includes PMOS transistors MP6~MP11 and NMOS transistors MN1~MN5; wherein... The sources of MP10 and MP11 are connected to the power supply voltage VDD. The drain of MP10 is connected to the sources of MP6, MP7, and MP9, the drain of MN5, and the internal power supply node. The gate of MP10 is connected to the gate and drain of MP11 and the drain of MN2. The gates of MN1 to MN4 are interconnected with the drain of MN1 and connected to the bias current input terminal I. B1 The sources of MN1 to MN4 are all grounded to GND; the drain of MN3 is connected to the gate of MN5 and the drain of MP9; the drain of MN4 is connected to the drain and gate of MP6; the gate of MP6 is connected to the gate of MP7; and the drain of MP7 is connected to the source of MP8 and the gate of MP9.

9. A low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 8, characterized in that, The negative feedback loop consists of MP9 and MN5; wherein... The source of MP9 is connected to the internal power node, the gate of MP9 is connected to a bias voltage, and the drain of MP9 is connected to the gate of MN5; the drain of MN5 is connected to the internal power node, and its source is grounded.

10. A low-voltage bandgap reference circuit with high power supply rejection ratio according to claim 1, characterized in that, The high power supply rejection ratio (PSRR) enhancement circuit is configured to increase the PSRR of the internal power node voltage by (1+T) compared to the PSRR of the power supply voltage. loop ) times, of which T loop is the loop gain of the negative feedback loop.

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