Timing control circuit and method

Abstract

The application discloses a timing control circuit and method, relates to the field of electronic system power management, and aims to solve the problems of high cost of an existing integrated chip scheme and timing contradiction of a traditional RC circuit. The circuit comprises a timing control signal module and three types of control branches, namely, a first control branch, a second control branch and a special control branch, and capacitors are connected to a preset voltage V. A unidirectional control charging and discharging circuit is controlled by a Schottky diode, the charging timing is determined by the resistance value of a branch charging resistor and the capacitance value, the power-off timing is determined by the discharging resistor and the capacitance value, the core voltage is powered on first, the IO voltage is powered on later, the IO voltage is powered off first, and the core voltage is powered off later. The method comprises the steps of capacitor resistor configuration, power-on and power-off triggering, charging and discharging control and completion determination, can be expanded to more than two paths, and is low in cost and high in timing precision.

Description

Technical Field

[0001] This application relates to the field of power management in electronic systems, and more particularly to a timing control circuit and method. Background Technology

[0002] Multi-power supply power-on / off timing control technology is a core branch of electronic system power management, and its development is highly tied to the increasing integration and complexity of equipment. Early electronic systems had limited functionality, using a single power supply and relying on RC charging / discharging circuits and logic gate combinations to achieve fixed timing control. This was low-cost but lacked flexibility and scalability. As equipment evolved towards multi-module, multi-voltage domain architectures, multi-power supplies became standard. Dedicated power supply timing controllers and microcontroller-based programmable control solutions emerged, enabling pre-configured timing and overcoming the rigid limitations of hardware circuits. However, these solutions still suffer from issues such as reliance on hardware programming for timing adjustments, insufficient real-time adaptability, and high costs.

[0003] In the existing technology, patent CN119916711A uses the SN74 series integrated chip to realize the power-on control of 6 channels, which has the disadvantages of high cost and poor scalability, and cannot use a single chip to adapt to the needs of more than 6 channels. The discrete circuit solution controls the voltage enable pin through RC, but because the RC charging and discharging time constant is fixed, it is difficult to meet the timing requirements of the core voltage being powered on first and the IO voltage being powered off first at the same time.

[0004] In summary, existing technologies generally suffer from drawbacks such as high cost, poor flexibility, and incomplete timing adaptation. Summary of the Invention

[0005] In view of this, this application proposes a timing control circuit for controlling the power-on and power-off sequence of different pins of a controlled device. The timing control circuit includes a preset number of control branches, including a first control branch and / or a second control branch and / or a special control branch. The first control branch includes resistor R1, resistor R2, diode D, and capacitor C; the first end of resistor R1 is connected to the output terminal of the timing control signal module, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device, the second end of capacitor C is connected to a preset voltage V, the cathode of diode D is connected to the first end of resistor R1, and the anode of diode D is connected to the second end of resistor R1. The second control branch includes resistor R3, resistor R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device. The second end of capacitor C is connected to a preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output of the timing control signal module. The second end of the resistor RS is connected to the first end of the capacitor C and the power pins of the controlled device. The second end of the capacitor C is connected to a preset voltage V. The resistance values ​​of resistors R1 and R2 in the first control branch, resistors R3 and R4 in the second control branch, and resistor RS in the special control branch are set according to the power-on sequence of the power-on and power-off pins of the controlled device.

[0006] Preferably, the circuit includes a first control branch and a special control branch; When the pins connected to the first control branch are required to be powered on after the pins connected to the special control branch, and the pins connected to the first control branch are powered on before the pins connected to the special control branch, the sum of resistors R1 and R2 is set to be greater than resistor RS.

[0007] Preferably, the circuit includes a first control branch, a special control branch, and a second control branch; The first control branch includes resistor R1, resistor R2, diode D, and capacitor C; the first end of resistor R1 is connected to the output of the timing control signal module, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device, the second end of capacitor C is connected to a preset voltage V, the cathode of diode D is connected to the first end of resistor R1, and the anode of diode D is connected to the second end of resistor R1. The second control branch includes resistor R3, resistor R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the power-on / off pins of the controlled device. The second end of capacitor C is connected to a preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output of the timing control signal module. The second end of the resistor RS is connected to the first end of the capacitor C and the power-on / off pins of the controlled device. The second end of the capacitor C is connected to a preset voltage V.

[0008] Preferably, the first control branch includes at least a first control branch A, a first control branch B, and a first control branch C; When it is required that the pins connected to the first control branch A be powered on before the pins connected to the first control branch B, and the pins connected to the first control branch B be powered on before the pins connected to the first control branch C, and the pins connected to the first control branch A are powered on before the pins connected to the first control branch B, and the pins connected to the first control branch B are powered on before the pins connected to the first control branch C; the sum of resistors R1 and R2 included in the first control branch A is set to be greater than the sum of resistors R1 and R2 included in the first control branch B, the sum of resistors R1 and R2 included in the first control branch B is greater than the sum of resistors R1 and R2 included in the first control branch C, and the resistor R2 included in the first control branch A is less than the resistor R2 included in the first control branch B, and the resistor R2 included in the first control branch B is less than the resistor R2 included in the first control branch C; The second control branch includes at least the second control branch A and the second control branch B; When the pin connected to the second control branch A is required to be powered on after the pin connected to the first control branch B, and the pin connected to the second control branch A is powered on before the pin connected to the second control branch B, then the resistor R4 included in the second control branch A is greater than the resistor R4 included in the second control branch B, and the sum of the resistors R3 and R4 included in the second control branch A is less than the sum of the resistors R3 and R4 included in the second control branch B.

[0009] Preferably, a Schmitt switch U1 is connected between the second end of resistor R2 in the first control branch and the upper and lower power pins of the controlled device, a Schmitt switch U2 is connected between the second end of resistor R4 and the upper and lower power pins of the controlled device, and a Schmitt switch US is provided between the second end of resistor RS and the upper and lower power pins of the controlled device.

[0010] In one possible implementation, the capacitance values ​​of capacitor C in the first control branch, the second control branch, and the special control branch are selected based on their corresponding control branch.

[0011] In one possible implementation, the timing control signal module includes a Schmitt-NNO gate UA, which is connected between the output of the timing control signal module and the first terminals of resistors R1, R3, and RS. When the timing control signal module includes a Schmitt-NOT gate UA, a Schmitt-NOT gate U1N is connected between the second end of resistor R2 in the first control branch and the upper and lower power pins of the controlled device, a Schmitt-NOT gate U2N is connected between the second end of resistor R4 and the upper and lower power pins of the controlled device, and a Schmitt-NOT gate USN is provided between the second end of resistor RS and the upper and lower power pins of the controlled device.

[0012] In one possible implementation, diode D is a Schottky diode.

[0013] This invention includes a timing circuit control method, which uses the circuit of any one of claims 1-8 to implement power supply timing control of a controlled device, comprising: Connect the preset voltage V to the second terminal of all capacitors C; The timing control signal module outputs a power-on trigger signal and transmits the signal to resistor R1 in the first control branch, resistor R3 in the second control branch, and resistor RS in the special control branch. The capacitors in each control branch begin charging in a preset order based on the difference in total charging resistance. When all capacitors are charged to the preset voltage V, the corresponding power-on and power-off pins of the controlled device are triggered to a high level, and the controlled device is powered on. After a preset time, the timing control signal module outputs a power-down trigger signal; The capacitors in each control branch discharge in a preset sequence based on the difference in the resistance value of the discharge resistor; When all capacitors are discharged to 0V, the corresponding power-on and power-off pins of the controlled device are triggered to a low level, and the controlled device is powered down.

[0014] In one possible implementation, the method includes: After capacitor C is fully charged, its slowly varying voltage signal is transmitted to Schmitt switch U1, which is connected in series between R2 and the upper and lower power pins of the controlled device, and converted into a square wave signal, which is then input to the upper and lower power pins of the controlled device. After capacitor C is fully charged, its slowly varying voltage signal is transmitted to Schmitt switch U2, which is connected in series between R4 and the upper and lower power pins of the controlled device, and converted into a square wave signal, which is then input to the upper and lower power pins of the controlled device. After capacitor C is fully charged, its slowly varying voltage signal is transmitted to the Schmitt switch US connected in series between RS and the upper and lower power pins of the controlled device, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch U1, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch U2, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch US, converted into a square wave signal, and then input to the power-on / off pins of the controlled device.

[0015] The beneficial effects of this invention are: This circuit breaks through the limitations of traditional discrete RC circuits. By using RC circuits in reverse and combining the unidirectionality of Schottky diodes, it separates the charging and discharging resistors, allowing independent control of the charging and discharging time constants. It simultaneously satisfies the requirements of powering on the core voltage first and the I / O voltage later, and vice versa, resolving the timing contradictions of traditional RC circuits. Furthermore, this technical solution offers significant cost advantages. Based on discrete resistors, capacitors, and diodes, it eliminates the need for integrated chips, reducing hardware costs by 30%-50% compared to integrated solutions. It is flexible and scalable, supporting configurations of two or more channels to adapt to electronic systems of different sizes. The optional Schmitt-N gate not only reverses the timing control signal input to the control branch but also optimizes the charging and discharging curve, converting slowly changing signals into steep square waves. Timing control errors are ≤1ms, improving anti-interference capabilities and ensuring power supply stability for devices such as CPUs / FPGAs. No additional filtering modules are required, balancing reliability and economy.

[0016] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0018] Figure 1 This paper shows the topology of the power supply timing control circuit of embodiment 3 of this application; Figure 2 This application shows a topology diagram of a 6-channel power supply timing control circuit according to an embodiment of the present application; Figure 3 This paper shows the topology of an 8-channel power supply timing control circuit according to an embodiment of this application; Figure 4A This diagram shows the configuration of the timing control circuit for adding a Schmitt switching power supply in Embodiment 3 of this application; Figure 4B This diagram shows the configuration of the power supply timing control circuit with Schmitt-NOR gates in Embodiment 3 of this application; Figure 5 This paper shows a flowchart of a timing control method according to an embodiment of the present application; Figure 6 This document illustrates a flowchart of the power-on signal shaping process for a Schmitt-NNO gate according to an embodiment of this application. Figure 7 This document illustrates a flowchart of electrical signal shaping under a Schmitt NOT gate according to an embodiment of this application. Detailed Implementation

[0019] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0020] It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application or to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0023] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0024] The invention of this application is a timing control circuit and method, which is applied in the field of power management of electronic systems. It can accurately control the power-on and power-off sequence of multiple power supplies, meet the power supply requirements of devices such as CPU and FPGA to power on the core voltage first and then the I / O voltage, and to power off the I / O voltage first and then the core voltage, while reducing the implementation cost and improving the flexibility of the number of power supplies.

[0025] This invention innovatively improves upon traditional discrete RC (resistor R pull-up, capacitor C pull-down) circuits, enabling them to meet both power-on and power-off timing requirements. Specifically, the power supply that powers on first is powered off last, and the power supply that powers on last is powered off first. This satisfies the requirements of CPUs, FPGAs, and other devices where the core voltage powers on first, followed by the I / O voltage, and vice versa. Furthermore, this invention is low-cost to implement and allows for highly flexible control pin configurations ranging from 2 to over 10 channels.

[0026] In this application, "controlled device" generally refers to electronic devices such as FPGAs / CPUs that have different requirements for the power-on and power-off sequences of different pins. However, those skilled in the art will understand that the understanding of "controlled device" should not be limited to the above interpretation. In fact, any electronic device that has different requirements for the power-on and power-off sequences of different pins can be interpreted as a controlled device and controlled using the circuits and methods described in this invention.

[0027] circuit This invention includes a timing control circuit for controlling the power-on and power-off sequence of different pins of a controlled device. The timing control circuit includes a preset number of control branches, including a first control branch and / or a second control branch and / or a special control branch. The preset number of control branches is the same as the number of power-on and power-off pins of the controlled device.

[0028] The first control branch includes resistors R1 and R2, diode D, and capacitor C. The first terminal of resistor R1 is connected to the output of the timing control signal module. The second terminal of resistor R1 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first terminal of capacitor C and the power-on / off pins of the controlled device. The second terminal of capacitor C is connected to a preset voltage V. The cathode of diode D is connected to the first terminal of resistor R1, and the anode of diode D is connected to the second terminal of resistor R1. The power-on / off speed of this control branch can be controlled by adjusting the resistance and capacitance values ​​to adapt to the power-on timing requirements of the controlled device, meeting the power supply timing requirements of devices such as CPUs / FPGAs, and offering low cost and high flexibility.

[0029] The second control branch includes resistors R3 and R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the power-on / off pins of the controlled device. The second end of capacitor C is connected to a preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The power-on / off speed of this control branch can be controlled by adjusting the resistance and capacitance values ​​to adapt to the power-on timing requirements of the controlled device, meeting the power supply timing requirements of devices such as CPUs / FPGAs, and offering low cost and high flexibility. The diode D is connected in the opposite direction to the first control branch, making it easier to select the resistance and capacitance values ​​when using the second control branch as the core voltage pin of the controlled device, and when cooperating with the first control branch and special control branches to sequentially power on and off the controlled device's pins.

[0030] The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output of the timing control signal module, and the second end of the resistor RS is connected to the first end of the capacitor C and the power-on / off pins of the controlled device. The second end of the capacitor C is connected to a preset voltage V. The power-on / off speed of this control branch can be controlled by adjusting the resistance and capacitance values. This special control branch has a simple structure and extremely low cost, which can meet the needs of scenarios with low timing accuracy requirements. It can be flexibly integrated into multi-channel control schemes to supplement and expand the number of power control channels and adapt to the needs of electronic systems of different sizes.

[0031] The resistance values ​​of resistors R1 and R2 in the first control branch, resistors R3 and R4 in the second control branch, and resistor RS in the special control branch are set according to the power-on sequence of the power-on and power-off pins of the controlled device.

[0032] If the timing control circuit of this application only contains a special control branch, and the power-on sequence of the power-on pins of the controlled device is from pin N to pin 1 (N is a natural number greater than 2), then the power-off sequence must be from pin 1 to pin N.

[0033] When several first control branches and several second control branches are added to the timing circuit of this application as control branches for the power-on and power-off pins of the controlled device, its technical advantage lies in breaking through the fixed sequence limitation that when relying solely on a special control branch, the power-on and power-off pins of the controlled device can only be powered on from pin N to pin 1 and powered off from pin 1 to pin N, thus achieving free configuration of the pin power-on and power-off sequence. Specifically, this solution can more flexibly set the power-on priority and power-off priority of any control branch according to the actual working requirements of the controlled device and the system timing adaptation requirements. It gets rid of the single sequence constraint of power-on from pin N to pin 1 and power-off from pin 1 to pin N, adapting to complex timing control requirements in different scenarios.

[0034] In one possible implementation, the circuit includes a first control branch and a special control branch; When the pins connected to the first control branch are required to be powered on after the pins connected to the special control branch, and the pins connected to the first control branch are powered on before the pins connected to the special control branch, the sum of resistors R1 and R2 is set to be greater than resistor RS.

[0035] In one possible implementation, the circuit includes a first control branch, a special control branch, and a second control branch; The first control branch includes resistor R1, resistor R2, diode D, and capacitor C; the first end of resistor R1 is connected to the output of the timing control signal module, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device, the second end of capacitor C is connected to a preset voltage V, the cathode of diode D is connected to the first end of resistor R1, and the anode of diode D is connected to the second end of resistor R1. The second control branch includes resistor R3, resistor R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the power-on / off pins of the controlled device. The second end of capacitor C is connected to a preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output of the timing control signal module. The second end of the resistor RS is connected to the first end of the capacitor C and the power-on / off pins of the controlled device. The second end of the capacitor C is connected to a preset voltage V.

[0036] When the pins connected to the first control branch are required to be powered on after the pins connected to the special control branch, the pins connected to the special control branch are required to be powered on after the pins connected to the second control branch, the pins connected to the first control branch are required to be powered on before the pins connected to the special control branch, and the pins connected to the special control branch are required to be powered on before the pins connected to the second control branch, the following order applies: R1 + R2 > RS, RS > R4, R3 + R4 > RS, and RS > R2. This embodiment can accurately match the preset power-on / off sequence of the controlled device. Power-on occurs in the order of second control branch → special control branch → first control branch, and power-off occurs in the order of first control branch → special control branch → second control branch, meeting the power-on / off requirements of devices such as CPUs / FPGAs. Furthermore, it is implemented using discrete resistors, capacitors, and diodes, eliminating the need for integrated chips, resulting in low cost, flexible circuit options, and the resolution of timing contradictions in traditional RC circuits.

[0037] Based on the above implementation, in one possible implementation, the first control branch includes at least a first control branch A, a first control branch B, and a first control branch C. When it is required that the pins connected to the first control branch A be powered on before the pins connected to the first control branch B, and the pins connected to the first control branch B be powered on before the pins connected to the first control branch C, and the pins connected to the first control branch A are powered on before the pins connected to the first control branch B, and the pins connected to the first control branch B are powered on before the pins connected to the first control branch C; the sum of resistors R1 and R2 included in the first control branch A is set to be greater than the sum of resistors R1 and R2 included in the first control branch B, the sum of resistors R1 and R2 included in the first control branch B is greater than the sum of resistors R1 and R2 included in the first control branch C, and the resistor R2 included in the first control branch A is less than the resistor R2 included in the first control branch B, and the resistor R2 included in the first control branch B is less than the resistor R2 included in the first control branch C; The second control branch includes at least the second control branch A and the second control branch B; When the pin connected to the second control branch A is required to be powered on after the pin connected to the first control branch B, and the pin connected to the second control branch A is powered on before the pin connected to the second control branch B, then the resistor R4 included in the second control branch A is greater than the resistor R4 included in the second control branch B, and the sum of the resistors R3 and R4 included in the second control branch A is less than the sum of the resistors R3 and R4 included in the second control branch B.

[0038] This application illustrates three possible embodiments of the circuit, including embodiments with 3 control branches, 6 control branches, and 8 control branches. In all three technical solutions, all circuits follow a unified core rule: the pins that are powered on first are powered off last, and the pins that are powered on later are powered off first. This matches the requirement that the core voltage of controlled devices such as CPUs / FPGAs should be powered on first, followed by the I / O voltage, and vice versa. When all control branches use the same capacitor value, the power-on sequence is determined by the total charging resistance R; that is, the larger the resistance, the larger the charging time constant τ=RC, and the slower the power-on. The power-off sequence is determined by the total resistance R' of the discharge resistor combination; that is, the larger the resistance, the larger the discharge time constant τ'=R'C, and the slower the power-off. However, those skilled in the art should understand that the implementation of this circuit is not limited to the case where all control branches use the same capacitor value. In fact, those skilled in the art can flexibly adjust the resistance and capacitor values ​​based on the above principles, which will not be elaborated further here.

[0039] specifically refer to Figure 1 As a specific embodiment of the circuit of this application, when the controlled device has three power-on / off pins with power-on / off timing requirements, the circuit includes a first control branch, a special control branch, and a second control branch. The first control branch corresponds to the power-on / off pin EN1 of the controlled device, the special control branch corresponds to the power-on / off pin EN2 of the controlled device, and the second control branch corresponds to the power-on / off pin EN3 of the controlled device.

[0040] In this embodiment, the power-on sequence of the controlled device is pin EN3 → pin EN2 → pin EN1, that is, from the front-end core voltage pin to the IO voltage pin; the power-off sequence is pin EN1 → pin EN2 → pin EN3, that is, from the IO voltage pin to the core voltage pin.

[0041] Therefore, in the circuit of this embodiment, according to the above principle, resistor R1 + resistor R2 > resistor RS, resistor RS > resistor R4, resistor R3 + R4 > resistor RS, and resistor RS > resistor R2.

[0042] In one possible implementation, the resistance of resistor R1 is 5.1kΩ, the resistance of resistor R2 is 3.6kΩ, the resistance of resistor R3 is 5.1kΩ, the resistance of resistor R4 is 3.6kΩ, and the resistance of resistor RS is 6.2kΩ. This satisfies the resistance value limitations of the above embodiments.

[0043] specifically refer to Figure 2As a specific embodiment of the circuit of this application, when the controlled device has 6 power-on / off pins with power-on / off timing requirements, the circuit includes a first control branch A, a first control branch B, a first control branch C, a special control branch, a second control branch A, and a second control branch B. The first control branch A corresponds to the power-on / off pin EN1 of the controlled device, the first control branch B corresponds to the power-on / off pin EN2 of the controlled device, the first control branch C corresponds to the power-on / off pin EN3 of the controlled device, the special control branch corresponds to the power-on / off pin EN4 of the controlled device, the second control branch A corresponds to the power-on / off pin EN5 of the controlled device, and the second control branch B corresponds to the power-on / off pin EN6 of the controlled device.

[0044] In this embodiment, the power-on sequence of the controlled devices is pin EN6 → pin EN5 → pin EN4 → pin EN3 → pin EN2 → pin EN1, satisfying the power-on sequence from the core voltage pin (EN6 / EN5) to the I / O voltage pin (EN1). Similarly, the power-off sequence is pin EN1 → pin EN2 → pin EN3 → pin EN4 → pin EN5 → pin EN6, satisfying the power-off sequence from the I / O voltage pin (EN1) to the core voltage pin (EN6 / EN5). Therefore, the charging time constant τ increases sequentially from EN6 to EN1, ensuring that EN6 is powered on first and EN1 is powered on last. Furthermore, the discharging time constant τ' increases sequentially from EN1 to EN6, ensuring that EN1 is powered off first and EN6 is powered off last.

[0045] Therefore, the resistance values ​​of the control branch of this circuit satisfy the following conditions: resistance R4B of the second control branch B < resistance R4A of the second control branch A < resistance RS < resistance R1C + resistance R2C of the first control branch C < resistance R1B + resistance R2B of the first control branch B < resistance R1A + resistance R2A of the first control branch A; the resistance values ​​of the control branch of this circuit also satisfy the following conditions: resistance R2A of the first control branch A < resistance R2B of the first control branch B < resistance R2C of the first control branch C < resistance RS < resistance R3A + resistance R4A of the second control branch A < resistance R3B + resistance R4B of the second control branch B.

[0046] In one possible implementation, the first control branch A includes resistor R1A with a resistance of 15kΩ and resistor R2A with a resistance of 0.2kΩ; the first control branch B includes resistor R1B with a resistance of 10kΩ and resistor R2B with a resistance of 1kΩ; the first control branch C includes resistor R1C with a resistance of 5.1kΩ and resistor R2C with a resistance of 3.6kΩ; the second control branch A includes resistor R3A with a resistance of 5.1kΩ and resistor R4A with a resistance of 3.6kΩ; the second control branch B includes resistor R3B with a resistance of 10kΩ and resistor R4B with a resistance of 1kΩ; and resistor RS has a resistance of 6.2kΩ. This satisfies the resistance value limitations of the above embodiments.

[0047] specifically refer to Figure 3 As a specific embodiment of the circuit of this application, when the controlled device has 8 power-on and power-off pins with power-on and power-off timing requirements, the circuit includes a first control branch A, a first control branch B, a first control branch C, a special control branch, a second control branch A, a second control branch B, a second control branch C, and a second control branch D. The first control branch A corresponds to the power-on and power-off pin EN1 of the controlled device; the first control branch B corresponds to the power-on and power-off pin EN2 of the controlled device; the first control branch C corresponds to the power-on and power-off pin EN3 of the controlled device; the special control branch corresponds to the power-on and power-off pin EN4 of the controlled device; the second control branch A corresponds to the power-on and power-off pin EN5 of the controlled device; the second control branch B corresponds to the power-on and power-off pin EN6 of the controlled device; the second control branch C corresponds to the power-on and power-off pin EN7 of the controlled device; and the second control branch D corresponds to the power-on and power-off pin EN8 of the controlled device.

[0048] In this embodiment, the power-on sequence of the controlled devices is EN8 → EN7 → EN6 → EN5 → EN4 → EN3 → EN2 → EN1, satisfying the power-on order from the core voltage pin (EN8 / EN7) to the IO voltage pin (EN1). The power-off sequence is EN1 → EN2 → EN3 → EN4 → EN5 → EN6 → EN7 → EN8, satisfying the power-off order from the IO voltage pin (EN1) to the core voltage pin (EN8 / EN7). Therefore, the charging time constant τ increases sequentially from EN8 to EN1, ensuring that EN8 is powered on first and EN1 is powered on last. Similarly, the discharging time constant τ' increases sequentially from EN1 to EN8, ensuring that EN1 is powered off first and EN8 is powered off last.

[0049] Therefore, the resistance values ​​of the control branch of this circuit satisfy the following conditions: resistance R4D of the second control branch D < resistance R4C of the second control branch C < resistance R4B of the second control branch B < resistance R4A of the second control branch A < resistance RS < resistance R1C + resistance R2C of the first control branch C < resistance R1B + resistance R2B of the first control branch B < resistance R1A + resistance R2A of the first control branch A; the resistance values ​​of the control branch of this circuit also satisfy the following conditions: resistance R2A of the first control branch A < resistance R2B of the first control branch B < resistance R2C of the first control branch C < resistance RS < resistance R3A + resistance R4A of the second control branch A < resistance R3B + resistance R4B of the second control branch B < resistance R3C + resistance R4C of the second control branch C < resistance R3D + resistance R4D of the second control branch D.

[0050] In one possible implementation, the first control branch A includes resistor R1A with a resistance of 15kΩ and resistor R2A with a resistance of 0.2kΩ; the first control branch B includes resistor R1B with a resistance of 10kΩ and resistor R2B with a resistance of 1kΩ; the first control branch C includes resistor R1C with a resistance of 5.1kΩ and resistor R2C with a resistance of 3.6kΩ; the second control branch A includes resistor R3A with a resistance of 5.1kΩ and resistor R4A with a resistance of 3.6kΩ; the second control branch B includes resistor R3B with a resistance of 10kΩ and resistor R4B with a resistance of 1kΩ; the second control branch C includes resistor R3C with a resistance of 15kΩ and resistor R4C with a resistance of 0.51kΩ; the second control branch D includes resistor R3D with a resistance of 20kΩ and resistor R4D with a resistance of 0.1kΩ; and resistor RS has a resistance of 6.2kΩ. This is to meet the limitations on the resistance value in the above embodiments.

[0051] It should be noted that although three specific implementations of the circuit have been described above using 3 control branches and their corresponding FPGA / CPUs, 6 control branches and their corresponding FPGA / CPUs, and 8 control branches and their corresponding FPGA / CPUs as examples, those skilled in the art will understand that this application is not limited to these. In fact, users can flexibly configure the control branches according to the actual application scenario, as long as it conforms to the preset power-on and power-off sequence of different pins of the controlled device.

[0052] Preferably, based on the above embodiment, a Schmitt switch U1 is connected between the second end of resistor R2 in the first control branch and the upper / lower power pins of the controlled device. A Schmitt switch U2 is connected between the second end of resistor R4 and the upper / lower power pins of the controlled device. A Schmitt switch US is provided between the second end of resistor RS and the upper / lower power pins of the controlled device. Using a Schmitt-NOT gate can optimize the RC charging / discharging curve, converting the slowly changing charging / discharging voltage signal into a steep and stable switching signal, reducing voltage fluctuation interference, making the power-on / lower timing control more precise, meeting the stringent power timing requirements of devices such as CPUs / FPGAs, and simultaneously improving the circuit's anti-interference capability and ensuring power supply stability.

[0053] Preferably, the timing control signal module includes a Schmitt-NOT gate UA, which is connected between the output terminal of the timing control signal module and the first terminals of resistors R1, R3, and RS. In the timing control signal module, the Schmitt-NOT gate UA is connected between the DC power supply and the first terminals of resistors R1, R3, and RS. When the timing control signal module includes the Schmitt-NOT gate UA, a Schmitt-NOT gate U1N is connected between the second terminal of resistor R2 in the first control branch and the upper / lower power pins of the controlled device; a Schmitt-NOT gate U2N is connected between the second terminal of resistor R4 and the upper / lower power pins of the controlled device; and a Schmitt-NOT gate USN is provided between the second terminal of resistor RS and the upper / lower power pins of the controlled device.

[0054] specifically refer to Figure 4A and Figure 4B ,in Figure 4A An embodiment of a timing control circuit for three control branches with a Schmitt switch is shown. Figure 4B An embodiment of setting Schmitt-NOR gates in the timing control branch of the three control branches is shown.

[0055] exist Figure 4A The first control branch includes a Schmitt switch U1 between R2 and pin EN3, a Schmitt switch US between resistor RS and pin EN4, and the second control branch includes a Schmitt switch U2 between R4 and pin EN5.

[0056] exist Figure 4B The first control branch includes a Schmitt-NOT gate U1N between R2 and pin EN3, a Schmitt-NOT gate USN between resistor RS and pin EN4, and the second control branch includes a Schmitt-NOT gate U2N between R4 and pin EN5. A Schmitt-NOT gate UA is also provided at the output of the timing control signal module.

[0057] Preferably, the capacitance value of the capacitor C equipped in all the first control branch, the second control branch and the special control branch is selected based on the corresponding control branch.

[0058] Specifically, in one possible implementation, the capacitors C equipped in all first control branches, second control branches, and special control branches have the same capacitance value. By unifying the capacitance values ​​of all control branches, the selection and procurement process can be simplified, and supply chain management costs can be reduced. At the same time, it avoids the increased complexity of charging and discharging calculations caused by differences in capacitance values, facilitates precise matching of resistor values ​​to set power-on and power-off sequences, and reduces the workload of circuit debugging. It can also ensure the consistency of timing control logic of each branch, improve the stability and reliability of the power-on and power-off sequences of multiple power supplies, and adapt to the needs of devices such as CPUs / FPGAs.

[0059] In another possible implementation, the capacitance value of the capacitor C equipped in all the first control branches, second control branches, and special control branches is determined based on the power-on / off sequence of the controlled device pins and the resistance values ​​of the first control branches, second control branches, and special control branches in the circuit. Since the power-on / off sequence of the circuit is based on the formulas τ=RC and τ'=R'C, the capacitance C of each of the first control branches, second control branches, and special control branches can be determined based on the resistance values ​​of their charging resistor R and discharging resistor R'. The specific method for determining the capacitance C is clearly understood by those skilled in the art through reading the above embodiments in this application specification, and will not be elaborated further here.

[0060] Preferably, diode D is a Schottky diode. Choosing a Schottky diode results in a low forward voltage drop, reducing voltage loss and preventing timing deviations in the RC charging / discharging circuit due to voltage drop. Furthermore, its fast switching speed allows for rapid response to power-on / off state transitions, preventing circuit switching delays from affecting timing control. Simultaneously, the stable unidirectional conductivity of the Schottky diode enables precise separation of the charging / discharging resistors, ensuring the core logic of power-on before power-off is maintained, thus improving the reliability of timing control.

[0061] method specifically refer to Figure 5 The present invention also includes a timing circuit control method, which uses the above circuit to realize the power supply timing control of the controlled device, including step S100, connecting a preset voltage V to the second terminal of all capacitors C.

[0062] In step S200, the timing control signal module outputs a power-on trigger signal and transmits the signal to the first control branch, the second control branch, and the special control branch.

[0063] In one possible implementation, when the DC power supply starts, the Schmitt-NOR gate UA in the timing control signal module first shapes the DC power supply output signal. This transforms the smooth fluctuations and spike noise that may exist during power startup into a steep and stable digital switching signal, which serves as the power-on trigger signal. Subsequently, the shaped power-on trigger signal is transmitted to the first terminal of resistor R1 in the first control branch, resistor R3 in the second control branch, and resistor RS in the special control branch. The addition of the Schmitt-NOR gate avoids subsequent RC charging and discharging timing disorder caused by unstable power signals, ensuring the reliability of the trigger signal and providing stable triggering conditions for the synchronous start of the charging subroutine in each branch.

[0064] In step S300, the capacitors of each control branch begin charging in a preset order based on the difference in total charging resistance.

[0065] Specifically, the capacitors in each control branch begin charging in a preset order based on their differences in total charging resistance. The charging resistor combinations are defined as follows: the first control branch uses the series connection of R1 and R2; the second control branch uses the series connection of R3 and R4; and the special control branch uses the resistance of RS. According to the RC charging and discharging principle, the charging time constant τ = charging resistor value × C. With the same capacitor value C, a smaller R value results in a smaller τ, leading to faster capacitor charging and earlier high-level triggering of the corresponding controlled device's power-on / off pins.

[0066] In step S400, when all capacitors are charged to the preset voltage V, the power-on and power-off pins of the corresponding controlled device are triggered to a high level, and the controlled device is powered on.

[0067] In step S500, after a preset time, the timing control signal module outputs a power-down trigger signal.

[0068] In step S600, the capacitors of each control branch begin to discharge in a preset order based on the difference in the resistance value of the discharge resistor.

[0069] The capacitors in each control branch discharge in a preset order based on the differences in their discharge resistor values. The discharge resistor for all first control branches is its corresponding R2, the discharge resistor for all second control branches is its corresponding R4, and the discharge resistor for all special control branches is its corresponding RS. According to the discharge principle of RC circuits, the discharge time constant τ' = discharge resistor value × C. With the same capacitance value C, the smaller R is, the smaller τ' is, the faster the capacitor discharges, and the earlier the power-on / off pins of the controlled device are triggered to a low level.

[0070] In step S700, when all capacitors are discharged to 0V, the corresponding power-on and power-off pins of the controlled device are triggered to a low level, and the power-off of the controlled device is completed.

[0071] specifically refer to Figure 6 In one possible implementation, the method further includes step S310: after capacitor C is fully charged, its output gradually changing voltage signal is transmitted to Schmitt switch U1 connected in series between R2 and the upper and lower power pins of the controlled device, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. Step S320: after capacitor C is fully charged, its output gradually changing voltage signal is transmitted to Schmitt switch U2 connected in series between R4 and the upper and lower power pins of the controlled device, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. And step S330: after capacitor C is fully charged, its output gradually changing voltage signal is transmitted to Schmitt switch US connected in series between RS and the upper and lower power pins of the controlled device, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device.

[0072] Specifically, after the capacitor in the control branch completes charging, its output will generate a gradually changing voltage signal that rises smoothly from 0V to a preset voltage V. This signal is first transmitted to a Schmitt switch connected in series between resistor R2, RS, or R4 and the corresponding pin of the controlled device. The Schmitt switch shapes the gradually changing signal based on a preset threshold: when the input voltage exceeds its threshold voltage, the output is stable at a high level; when the input voltage is lower than its threshold voltage, the output is stable at a low level, thus converting the originally slowly changing analog signal into a steep digital square wave signal. Finally, the shaped square wave signal is accurately input to the corresponding power-on / off pins of the controlled device, ensuring that the pins can accurately identify the trigger signal indicating power-on completion and avoiding misjudgments caused by the gradually changing voltage.

[0073] This technical solution solves the problem that traditional RC circuits are prone to mis-triggered power-on / off pins of controlled devices due to slowly changing signals. The square wave signal can accurately match the device level recognition standard, reducing the timing control error to within 1ms. Furthermore, it unifies the shaping threshold of each branch, ensuring that multiple power supplies are powered on synchronously in a preset order, avoiding timing disorders caused by signal fluctuations. Thirdly, it improves the circuit's anti-interference capability without increasing hardware costs, and can cope with power supply noise without additional filtering modules. At the same time, it is compatible with discrete RC architecture, balancing low cost and high reliability, and providing stable technical support for flexible configurations of 2 to more than 10 channels.

[0074] specifically refer to Figure 7In one possible implementation, the sequential discharge process of the capacitors in each control branch includes step S610, where, when capacitor C begins to discharge, its output slowly varying voltage signal is transmitted to Schmitt switch U1, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. Step S620, where, when capacitor C begins to discharge, its output slowly varying voltage signal is transmitted to Schmitt switch U2, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. And step S630, where, when capacitor C begins to discharge, its output slowly varying voltage signal is transmitted to Schmitt switch US, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device.

[0075] Specifically, after the capacitor in the control branch begins to discharge, it releases electrical energy through the discharge resistor, outputting a slowly changing voltage signal. This signal is transmitted to a Schmitt switch connected in series between resistor R2, resistor RS, or resistor R4 and the power-on / off pins of the controlled device. The Schmitt switch processes the slowly changing signal quickly: U2 maintains a high-level output until the voltage drops to the threshold voltage; once the voltage exceeds the threshold voltage, the output immediately jumps to a low level and remains stable, avoiding the problem of pin misjudging the power-off state due to the slow voltage transition in traditional RC discharge.

[0076] It is worth mentioning that when the output of the timing signal control module includes a Schmitt-NOT gate UA, the Schmitt switch U1 in the above method is adapted to be replaced with a Schmitt-NOT gate U1N, the Schmitt switch U2 in the above method is adapted to be replaced with a Schmitt-NOT gate U2N, and the Schmitt switch US in the above method is adapted to be replaced with a Schmitt-NOT gate USN, in order to achieve the above-mentioned technical effect.

[0077] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A timing control circuit, characterized in that, The timing control circuit is used to control the power-on and power-off sequence of different pins of the controlled device. It includes a preset number of control branches and timing control signal modules. The control branches include a first control branch and / or a second control branch and / or a special control branch. The first control branch includes resistor R1, resistor R2, diode D, and capacitor C; the first end of resistor R1 is connected to the output terminal of the timing control signal module, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of capacitor C and the power pins of the controlled device, the second end of capacitor C is connected to a preset voltage V, the cathode of diode D is connected to the first end of resistor R1, and the anode of diode D is connected to the second end of resistor R1; The second control branch includes resistor R3, resistor R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output terminal of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device. The second end of capacitor C is connected to the preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output terminal of the timing control signal module. The second end of the resistor RS is connected to the first end of the capacitor C and the upper and lower power pins of the controlled device. The second end of the capacitor C is connected to the preset voltage V. The resistance values ​​of resistors R1 and R2 in the first control branch, resistors R3 and R4 in the second control branch, and resistor RS in the special control branch are set according to the power-on sequence of the power-on and power-off pins of the controlled device.

2. The circuit according to claim 1, characterized in that, The circuit includes a first control branch and the special control branch; When the pin connected to the first control branch is required to be powered on after the pin connected to the special control branch, and the pin connected to the first control branch is powered on before the pin connected to the special control branch, the sum of the resistors R1 and R2 is set to be less than the resistor RS.

3. The circuit according to claim 1, characterized in that, The circuit includes a first control branch, the special control branch, and a second control branch; The first control branch includes resistor R1, resistor R2, diode D, and capacitor C; the first end of resistor R1 is connected to the output terminal of the timing control signal module, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of capacitor C and the power pins of the controlled device, the second end of capacitor C is connected to a preset voltage V, the cathode of diode D is connected to the first end of resistor R1, and the anode of diode D is connected to the second end of resistor R1; The second control branch includes resistor R3, resistor R4, diode D, and capacitor C. The first end of resistor R3 is connected to the output terminal of the timing control signal module. The second end of resistor R3 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the first end of capacitor C and the upper and lower power pins of the controlled device. The second end of capacitor C is connected to the preset voltage V. The anode of diode D is connected to the first end of resistor R3, and the cathode of diode D is connected to the second end of resistor R3. The special control branch includes a resistor RS and a capacitor C. The first end of the resistor RS is connected to the output terminal of the timing control signal module, the second end of the resistor RS is connected to the first end of the capacitor C and the upper and lower power pins of the controlled device, and the second end of the capacitor C is connected to the preset voltage V.

4. The circuit according to claim 1, characterized in that, The first control branch includes at least a first control branch A, a first control branch B, and a first control branch C; When the pins connected to the first control branch A are required to be powered on before the pins connected to the first control branch B are powered on, and the pins connected to the first control branch B are required to be powered on before the pins connected to the first control branch C are powered on, and the pins connected to the first control branch A are powered on before the pins connected to the first control branch B are powered on, and the pins connected to the first control branch B are powered on before the pins connected to the first control branch C are powered on. The sum of resistors R1 and R2 in the first control branch A is greater than the sum of resistors R1 and R2 in the first control branch B, the sum of resistors R1 and R2 in the first control branch B is greater than the sum of resistors R1 and R2 in the first control branch C, and the resistor R2 in the first control branch A is less than the resistor R2 in the first control branch B, and the resistor R2 in the first control branch B is less than the resistor R2 in the first control branch C. The second control branch includes at least the second control branch A and the second control branch B; When the pins connected to the second control branch A are required to be powered on after the pins connected to the first control branch B, and the pins connected to the second control branch A are powered on before the pins connected to the second control branch B; The resistor R4 in the second control branch A is set to be greater than the resistor R4 in the second control branch B, and the sum of the resistors R3 and R4 in the second control branch A is less than the sum of the resistors R3 and R4 in the second control branch B.

5. The circuit according to claim 1, characterized in that, A Schmitt switch U1 is connected between the second end of the resistor R2 in the first control branch and the upper and lower power pins of the controlled device; a Schmitt switch U2 is connected between the second end of the resistor R4 and the upper and lower power pins of the controlled device; and a Schmitt switch US is provided between the second end of the resistor RS and the upper and lower power pins of the controlled device.

6. The circuit according to claim 3, characterized in that, The capacitance value of the capacitor C of the first control branch, the second control branch, and the special control branch is selected based on the control branch to which it corresponds.

7. The circuit according to claim 1, characterized in that, The timing control signal module includes a Schmitt-NOT gate UA, which is connected between the output terminal of the timing control signal module and the first terminal of the resistor R1, the first terminal of the resistor R3, and the first terminal of the resistor RS. When the timing control signal module includes a Schmitt-NOT gate UA, a Schmitt-NOT gate U1N is connected between the second end of the resistor R2 in the first control branch and the upper and lower power pins of the controlled device, a Schmitt-NOT gate U2N is connected between the second end of the resistor R4 and the upper and lower power pins of the controlled device, and a Schmitt-NOT gate USN is provided between the second end of the resistor RS and the upper and lower power pins of the controlled device.

8. The circuit according to claim 1, characterized in that, The diode D is a Schottky diode.

9. A timing circuit control method, characterized in that, Using the circuit according to any one of claims 1-8 to implement power supply timing control of a controlled device includes: Connect the preset voltage V to the second terminal of all capacitors C; The timing control signal module outputs a power-on trigger signal and transmits the signal to resistor R1 of the first control branch, resistor R3 of the second control branch, and resistor RS of the special control branch. The capacitors in each control branch begin charging in a preset order based on the difference in total charging resistance. When all capacitors are charged to the preset voltage V, the corresponding power-on and power-off pins of the controlled device are triggered to a high level, and the controlled device is powered on. After a preset time, the timing control signal module outputs a power-down trigger signal; The capacitors in each control branch discharge in a preset sequence based on the difference in the resistance value of the discharge resistor; When all capacitors are discharged to 0V, the corresponding power-on and power-off pins of the controlled device are triggered to a low level, and the controlled device is powered down.

10. The method according to claim 9, characterized in that, The method includes: After capacitor C is fully charged, its slowly changing voltage signal is transmitted to Schmitt switch U1, which is connected in series between R2 and the upper and lower power pins of the controlled device, and converted into a square wave signal, which is then input to the upper and lower power pins of the controlled device. After capacitor C is fully charged, its slowly varying voltage signal is transmitted to Schmitt switch U2, which is connected in series between R4 and the upper and lower power pins of the controlled device, and converted into a square wave signal, which is then input to the upper and lower power pins of the controlled device. After capacitor C is fully charged, its slowly varying voltage signal is transmitted to the Schmitt switch US connected in series between RS and the upper and lower power pins of the controlled device, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch U1, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch U2, converted into a square wave signal, and then input to the upper and lower power pins of the controlled device. When capacitor C begins to discharge, its slowly changing voltage signal is transmitted to Schmitt switch US, converted into a square wave signal, and then input to the power-on / off pins of the controlled device.

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