A 3D NAND flash memory system

Abstract

The application provides a 3D NAND flash memory system, relating to the technical field of integrated circuit structure design. By integrating MAC computation macros, local sensitive hash computation macros, and ternary content addressable memory macros in layered data storage arrays, a high degree of fusion of computation and storage is achieved, enabling parallel execution of feature extraction, hash code generation, and vector query update operations within the same physical location, significantly improving data processing speed and efficiency. Since the functional modules are distributed in different layered data storage arrays, the system can flexibly adjust the use of each functional module according to the needs of specific application scenarios, such as increasing or decreasing the number or type of specific functional modules, to adapt to different data processing tasks and data volumes, thereby improving the scalability and flexibility of the system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit structure design technology, and in particular to a 3D NAND flash memory system. Background Technology

[0002] Current research on in-memory computing primarily focuses on deep neural networks (DNNs). However, DNN training relies on massive amounts of sample data, making it difficult to learn quickly on new tasks. Inspired by the human brain, a new type of memory-augmented neural network (MANNs) has been proposed. It enhances the model's memory and learning capabilities by introducing external or internal memory components. This type of neural network is particularly suitable for tasks requiring long-term memory and complex reasoning, such as few-time learning, language understanding, sequence prediction, and complex decision-making.

[0003] However, existing MANN implementations primarily rely on traditional computing architectures, such as those based on GPUs and external memory, which face numerous challenges when processing large-scale data. First, traditional von Neumann computing architectures suffer from bottlenecks in storage bandwidth and capacity, particularly when deployed in energy-constrained edge devices. As data volumes continue to increase, frequent access to external memory modules is required to retrieve learned knowledge, significantly increasing memory overhead and limiting system performance. Second, existing MANN implementations are inadequate in feature extraction and storage. Feature extraction is a crucial step in MANNs, determining the types of information the model can learn and remember. However, traditional feature extraction methods often rely on complex algorithms and substantial computational resources, limiting the application of MANNs in real-time applications and energy-constrained environments. Furthermore, existing storage solutions are insufficient in terms of storage efficiency and read / write speed, failing to meet the demands of MANNs for efficient storage and fast read / write speeds. Summary of the Invention

[0004] To address the above problems, this application provides a 3D NAND flash memory system, including the following:

[0005] This application provides a 3D NAND flash memory system, including multiple layered data storage arrays, the system comprising:

[0006] A MAC computation macro, configured within at least one of the plurality of hierarchical data storage arrays, is used to perform feature extraction operations;

[0007] A Locality Sensitive Hash (LSH) computation macro is configured in another array among the plurality of hierarchical data storage arrays to generate hash code vectors based on extracted features;

[0008] The Ternary Content Addressable Memory (TCAM) macro is configured in one of the plurality of hierarchical data storage arrays and is used to perform query and update operations on vectors in memory.

[0009] The control unit is used to activate only one layer of the multiple hierarchical data storage arrays within a computing cycle, and control the functional modules in the activated layer to execute the corresponding computing tasks, while keeping the functional modules in other layers in an inactive or low-power state.

[0010] Optionally, the 3D NAND flash memory array is divided into multiple regions, each region is mapped to a convolution kernel, and two adjacent rows of cells are used to store the positive and negative values ​​of the weight bits respectively.

[0011] Optionally, the MAC calculation macro includes:

[0012] The input receiving module is used to receive the calculation results from the upper-level data storage array, convert the calculation results into vector form input, and transmit them to the local buffer via the bus.

[0013] A voltage conversion module is used to convert each vector element into a bit-line (BL) voltage sequence;

[0014] The source selection line SSL switch matrix is ​​used to select the rows that participate in the MAC calculation;

[0015] The calculation result acquisition module acquires the calculation result at the source line SL when the BL voltage is conducted to all cells corresponding to the input vector. The current of a single SL represents part and result.

[0016] The differential amplification and sample-and-hold module is used to differentially amplify the voltage obtained by each pair of adjacent SL lines and sample and hold the difference through the sample-and-hold circuit.

[0017] The multiplexer and quantization module selects a voltage result sequentially within a single calculation cycle using the multiplexer, and then quantizes the voltage result into a fixed-point result using a successive approximation analog-to-digital converter (SAR ADC).

[0018] The result processing module is used to shift and add the quantized partial results to obtain the complete MAC result, and to process the MAC result through the ReLU activation function;

[0019] The output transmission module is used to transmit the activated MAC result to the local buffer, and then transmit the MAC result in the local buffer to the chip-level accumulator via the bus to complete the shift and addition operations, thereby obtaining the final result.

[0020] Optionally, the Locality Sensitive Hash (LSH) calculation macro includes:

[0021] The real-valued eigenvector conversion module is used to convert real-valued eigenvectors into analog voltage values ​​ranging from 0 to 0.3V via an 8-bit DAC, and apply the analog voltage values ​​to selected cells in the 3D NAND flash memory array, so that the cells are in the deep linear region, where each cell acts as a constant conductance;

[0022] The random Gaussian distribution matrix construction module utilizes the inherent inter-cell variations and program interference in the 3D NAND flash memory array to achieve an approximate normal distribution when programming the cells to the target threshold voltage, thereby constructing a random Gaussian distribution matrix, which is then mapped to the conductance value of the cell array with the same target threshold voltage.

[0023] The MAC operation execution module is used to encode the input vector into a bit line voltage vector, perform MAC operations in the 3D NAND flash array, and reflect the result of each row multiplication in the source line SL current.

[0024] The differential function implementation module is used to convert the SL current into a voltage through a transimpedance amplifier (TIA), and then process the voltage through a differential amplifier.

[0025] The hash code encoding module encodes the hash code bits based on the comparison results between the output voltage of the differential amplifier and preset thresholds Vcm and Vth; where Vcm represents the common-mode output voltage of the differential amplifier, and Vth is the threshold for encoding the output voltage Vout of the differential amplifier into X.

[0026] The output module is used to output the encoded ternary hash code vector.

[0027] Optionally, encoding the hash code bits based on the comparison results of the differential amplifier's output voltage with preset thresholds Vcm and Vth includes:

[0028] The hash code bits are encoded as 0, 1, or the wildcard X;

[0029] When Vout is less than Vcm-Vth, the hash code bit is encoded as 1; when Vout is greater than Vcm+Vth, the hash code bit is encoded as 0; if the magnitude of Vout falls between these two thresholds, it is encoded as the wildcard X.

[0030] Optionally, the ternary content-addressable memory (TCAM) macro includes:

[0031] The TCAM function macro module is used to implement the read / write head function of the external memory of the MANN neural network learning model;

[0032] The SSL switch matrix module is used to select and switch to the appropriate storage row when writing update vectors;

[0033] The register module is used to maintain the switching rules of the SSL switch matrix to correctly select and open the corresponding store row in subsequent search operations.

[0034] Optionally, the ternary content-addressable memory (TCAM) macro further includes a read head circuit, which includes:

[0035] The BL decoder module is used to decode the query hash code vector generated by the locality-sensitive hash macro and control the charging of the corresponding bit line voltage.

[0036] The parallel computing module is used to calculate the Hamming distance between the query hash code vector and the support set hash code vector of each stored in the array within one search cycle;

[0037] The quantization module, including the TIA, the sample and hold module S&H, the multiplexer MUX, and the analog-to-digital converter ADC, is used to convert the SL current into a partial Hamming distance.

[0038] Optionally, the ternary content-addressable memory (TCAM) macro further includes a write head circuit, which includes:

[0039] The updated vector generation module is used to generate the updated vector by averaging elements and to determine whether the stored vector needs to be updated based on the ternary hash code vector update method.

[0040] The SSL switch matrix selection module is used during the training phase to select the row containing the storage vectors with the minimum Hamming distance and the same label.

[0041] The encoder module is used to read the stored vector and the new vector, and generate an updated hash code vector according to the encoding rules;

[0042] The free row selection module is used to select a free row to write the updated vector when a vector needs to be updated, and to update the register so that the corresponding storage row can be correctly selected and opened in subsequent search operations.

[0043] Optionally, the system further includes: peripheral circuitry, which includes bit lines, word lines, source select line drivers, decoders, digital-to-analog converters, update / search modules, and analog-to-digital converters, accumulators, and sensing blocks for quantization and computation purposes, to enable switching between different functions and power consumption control.

[0044] Optionally, the peripheral circuitry also includes a multiplexer and a transmission gate for switching between different computing functions, as well as a power gating system for shutting down inactive circuitry when not in use.

[0045] This application provides a 3D NAND flash memory system that integrates MAC computation macros, Locality Sensitive Hash (LSH) computation macros, and Ternary Content Addressable Memory (TCAM) macros into multiple hierarchical data storage arrays. This system achieves a high degree of integration between computation and storage, enabling parallel execution of operations such as feature extraction, hash code generation, and vector query updates within the same physical location, significantly improving data processing speed and efficiency. By controlling the control unit to activate only one layer of the multiple hierarchical data storage arrays within a single computation cycle and controlling the functional modules in the activated layer to execute corresponding computational tasks, while keeping functional modules in other layers in an inactive or low-power state, the system effectively reduces overall energy consumption, extends device battery life, or reduces power consumption. Since the functional modules are distributed across different hierarchical data storage arrays, the system can flexibly adjust the usage of each functional module according to the needs of specific application scenarios, such as increasing or decreasing the number or type of specific functional modules to adapt to different data processing tasks and data volumes, thereby improving the system's scalability and flexibility. By integrating feature extraction, hash code generation, and vector query updates into a single system and achieving efficient parallel processing, this system significantly shortens the data processing time and improves the real-time performance and response speed of data processing, making it particularly suitable for applications requiring rapid processing of large amounts of data. Utilizing 3D NAND flash memory technology, this system can achieve higher storage density within a limited physical space. Furthermore, by integrating computation and storage, it reduces data transfer overhead between computing and storage units in traditional systems, thereby lowering the overall system cost and complexity. In summary, the 3D NAND flash memory system provided in this application offers a more efficient, energy-saving, and flexible solution for data storage and processing through its high integration, parallel processing, energy optimization, flexible scalability, and accelerated data processing flow. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1This is a schematic diagram of the structure of a 3D NAND flash memory system provided in an embodiment of this application;

[0048] Figure 2 A schematic diagram of a fully differential weight mapping method for 3D NAND flash memory provided in an embodiment of this application;

[0049] Figure 3 A schematic diagram of a MAC computing macrostructure of 3D NAND flash memory provided in this application embodiment;

[0050] Figure 4 A schematic diagram of a locality-sensitive hashing method provided in an embodiment of this application;

[0051] Figure 5 A schematic diagram of an LSH computational macrostructure of 3D NAND flash memory provided in an embodiment of this application;

[0052] Figure 6 A schematic diagram of a TCAM computational macrostructure for 3D NAND flash memory provided in this application embodiment;

[0053] Figure 7 A schematic diagram of a read head search rule and a TCAM data storage rule provided for an embodiment of this application;

[0054] Figure 8 This is a schematic diagram of TCAM entry updating in a 3D NAND flash memory, provided as an embodiment of this application. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0056] Figure 1 This is a schematic diagram of the structure of a 3D NAND flash memory system provided in an embodiment of this application, combined with... Figure 1 As shown, the 3D NAND flash memory system provided in this application embodiment may include:

[0057] Multiple hierarchical data storage arrays are used to store data in three-dimensional space. The arrays of different layers are assigned parameter mappings of their respective modules, which include MAC calculation macros, Locality Sensitive Hash (LSH) calculation macros, and Ternary Content Addressable Memory (TCAM) macros.

[0058] A MAC computation macro, configured within at least one of the plurality of hierarchical data storage arrays, is used to perform feature extraction operations;

[0059] A Locality Sensitive Hash (LSH) macro is configured in another array among the plurality of hierarchical data storage arrays to generate hash code vectors based on extracted features.

[0060] The Tri-State Content Addressable Memory Macro (TCAM) is configured in one of the multiple hierarchical data storage arrays and is used to perform query and update operations on vectors in memory.

[0061] The control unit is used to activate only one layer of the multiple hierarchical data storage arrays within the same computing cycle, and control the functional modules in the activated layer to execute the corresponding computing tasks, while keeping the functional modules in other layers in an inactive or low-power state.

[0062] In addition, the 3D NAND flash memory system also includes peripheral circuits, including bit line (BL), word line (WL) and select signal line (SSL) drivers for controlling data read and write operations; and a decoder for parsing received instructions and generating corresponding control signals.

[0063] The system includes a digital-to-analog converter (DAC) to convert digital signals to analog signals; an update / search module to support data update and query operations; an analog-to-digital converter (ADC) to convert analog signals to digital signals for quantization and computation; accumulators and sensing blocks to process and detect data in the storage unit to enable switching between different functions and power consumption control. To facilitate switching between functions, the peripheral circuitry also includes a multiplexer (MUX) and transmission gates to control the connection and disconnection of wiring in the peripheral circuitry according to instructions from the control unit, enabling switching between different functional modules; and a power management unit containing a power gating mechanism to dynamically shut down unused circuit modules when a specific functional module is enabled, thereby reducing the overall power consumption of the system.

[0064] The 3D NAND flash memory system improves system performance and energy efficiency by sequentially activating functional modules of different layers and utilizing peripheral circuits to achieve efficient data processing and storage.

[0065] The specific structure of the 3D NAND flash memory system in this application will be described below with reference to the accompanying drawings. In one implementation of the embodiment of this application, the 3D NAND flash memory array is divided into multiple regions, each region is mapped to a convolution kernel, and two rows of adjacent cells are used to store the positive and negative values ​​of the weight bits respectively.

[0066] This application's 3D NAND flash memory system involves Memory Augmentation Networks (MANNs) circuitry and architecture. MANNs comprise two main modules: a Convolutional Neural Network Controller (CNN Controller) and External Memory. The CNN Controller extracts sample features, while the External Memory stores these features. During inference queries, the distance between the feature vector of the query sample and the feature vector stored in the External Memory is calculated to arrive at the query result. In the MANN, the trained CNN extracts features from the input samples. Because the training process is not based on a single specific task but rather on multiple sets of tasks with different objectives, it exhibits strong generalization ability. The feature vector of the CNN output image contains key features for recognizing the input data and is used for subsequent classification. The CNN used in this application comprises 6 convolutional layers, 6 ReLU activation layers, 2 pooling layers, and 1 fully connected layer. The NAND cell array is divided into multiple regions, each mapped to a convolutional kernel; that is, each region is responsible for storing the weight data of a specific convolutional kernel. Figure 2 This diagram illustrates a fully differential weight mapping method for 3D NAND flash memory provided in this application embodiment. The NAND cell array in the macro is divided into multiple regions, each mapped to a convolutional kernel. To quantize the model without significantly reducing system accuracy, the weight precision is set to 10 bits. To resist the effect of cell VTH (threshold voltage) drift caused by long-term data retention, two adjacent rows of cells are used to store the positive and negative values ​​of the weight bits, respectively. For example, if the weight W3 is negative, all P3[i] are 0, and N3[i] is used to map W3. Each cell stores 1 bit of data, so a single 10-bit weight consumes 18 cells. For a convolutional layer with m input channels and n output channels, in a single computation cycle, the convolutional kernel samples the input data as a 3*3*m tensor and performs a MAC operation using an n convolutional kernel of size 3*1*m, ultimately obtaining a 1*1*n output tensor. Therefore, every 18 rows are used to map the convolutional kernel, and every 9 columns are used for the input. Highly parallel convolution operations can be achieved by expanding multiple convolution kernels along the row direction of the array and expanding different channels of a single convolution kernel along the column direction.

[0067] Figure 3 This application provides a schematic diagram of a MAC calculation macro structure for a 3D NAND flash memory. In one implementation of this application, the MAC calculation macro includes:

[0068] The input receiving module is used to receive the calculation results from the upper-level data storage array as inputs expanded into vector form, convert the calculation results into vector form inputs, and transmit them to the local buffer LocalBuffer via the bus;

[0069] A voltage conversion module is used to convert each vector element into a bit-line (BL) voltage sequence;

[0070] The source selection line SSL switch matrix is ​​used to select the rows that participate in the MAC calculation;

[0071] The calculation result acquisition module acquires the calculation result at the source line SL when the BL voltage is conducted to all cells corresponding to the input vector. The current of a single SL represents part and result.

[0072] The differential amplification and sample-and-hold module is used to differentially amplify the voltage obtained by each pair of adjacent SL lines and sample and hold the difference through the sample-and-hold circuit.

[0073] The multiplexer and quantization module selects a voltage result sequentially within a single calculation cycle using the multiplexer, and then quantizes the voltage result into a fixed-point result using a successive approximation analog-to-digital converter (SAR ADC).

[0074] The result processing module is used to shift and add the quantized partial results to obtain the complete MAC result, and to process the MAC result through the ReLU activation function;

[0075] The output transmission module is used to transmit the activated MAC result to the local buffer, and then transmit the MAC result in the local buffer to the chip-level accumulator via the bus to complete the shift and addition operations, thereby obtaining the final result.

[0076] Figure 4 This illustration illustrates a Locality Sensitive Hashing (LSH) method, a technique that maps high-dimensional real-valued feature vectors to low-dimensional binary hash codes to preserve the similarity relationships of the original feature space within the hash code space. For LSH based on cosine similarity, the core concept involves using a random hyperplane to divide the feature space into different regions. Feature vectors falling into the same region are likely to be encoded with the same hash value. For example... Figure 4 In the pattern, red and black pentagrams falling into the same area are encoded with the same hash value. However, they are encoded differently from other patterns that do not fall into the same area.

[0077] The LSH hash function based on cosine similarity can be expressed as: h(v) = sign(v·r), where · represents the inner product operation, sign represents the sign function, and r is a d-dimensional random vector, with each component independently sampled from a zero-mean normal distribution. The sign function sign maps the inner product result to -1 or +1. Intuitively, r defines a random hyperplane, and the inner product of v and r represents the projection of v onto the direction of r. If the projection value is greater than 0, the corresponding hash bit is assigned a value of +1; otherwise, it is assigned a value of -1. Through this random projection, vectors with high cosine similarity in the original space are more likely to lie on the same side of the random hyperplane, thus increasing the probability that their hash codes are the same.

[0078] In this embodiment, a distance threshold TH is defined. If the distance between a feature vector v and a random hyperplane r is less than TH, the corresponding hash bit is encoded as a wildcard "X", indicating that the bit will not help distinguish the vector from other vectors. When v·r>TH, the value of the corresponding hash bit is still determined according to sign(v·r). By introducing wildcards, feature dimensions that are close to the hyperplane and have weak distinguishing power can be ignored, thereby improving the overall quality of the hash code.

[0079] Specifically, Figure 5 This illustration shows a schematic diagram of an LSH computation macro structure for 3D NAND flash memory provided in an embodiment of this application. The LSH computation macro converts a real-valued feature vector into a ternary hash code vector containing only 0, 1, and X by constructing multiple random hyperplanes. In one implementation of this application embodiment, the Locality Sensitive Hash (LSH) computation macro includes:

[0080] The Real-Valued Vector Conversion Module is used to convert the Real-Valued VectorN into an analog voltage value ranging from 0 to 0.3V through an 8-bit DAC, and apply the analog voltage value to selected cells in the 3D NAND flash memory array so that the cells are in the deep linear region, where each cell acts as a constant conductance;

[0081] The random Gaussian distribution matrix construction module utilizes the inherent inter-cell variations and program interference in the 3D NAND flash memory array to achieve an approximate normal distribution when programming the cells to the target threshold voltage, thereby constructing a random Gaussian distribution matrix, which is then mapped to the conductance value of the cell array with the same target threshold voltage.

[0082] The MAC operation execution module is used to encode the input vector into a bit line voltage vector, perform MAC operations in the 3D NAND flash array, and reflect the result of each row multiplication in the source line SL current.

[0083] The differential function implementation module is used to convert the SL current into a voltage through a transimpedance amplifier (TIA), and then process the voltage through a differential amplifier.

[0084] The hash code encoding module encodes the hash code bits based on the comparison results between the output voltage of the differential amplifier and preset thresholds Vcm and Vth; where Vcm represents the common-mode output voltage of the differential amplifier, and Vth is the threshold for encoding the output voltage Vout of the differential amplifier into X.

[0085] The output module is used to output the encoded ternary hash code vector.

[0086] In one implementation of this application, encoding the hash code bits based on the comparison results of the output voltage of the differential amplifier with preset thresholds Vcm and Vth includes:

[0087] The hash code bits are encoded as 0, 1, or the wildcard X;

[0088] When Vout is less than Vcm-Vth, the hash code bit is encoded as 1; when Vout is greater than Vcm+Vth, the hash code bit is encoded as 0; if the magnitude of Vout falls between these two thresholds, it is encoded as the wildcard X.

[0089] Figure 6 This application provides a schematic diagram of a TCAM computational macrostructure for 3D NAND flash memory. In one implementation of this application, the ternary content-addressable memory (TCAM) macro includes:

[0090] The TCAM function macro module is used to implement the read / write head function of the external memory of the MANN neural network learning model;

[0091] The SSL switch matrix module is used to select and switch to the appropriate storage row when writing update vectors;

[0092] The register module is used to maintain the switching rules of the SSL switch matrix to correctly select and open the corresponding store row in subsequent search operations.

[0093] In one implementation of this application, the ternary content-addressable memory (TCAM) macro further includes a read head circuit, which includes:

[0094] The BL decoder module is used to decode the query hash code vector generated by the locality-sensitive hash macro and control the charging of the corresponding bit line voltage.

[0095] The parallel computing module is used to calculate the Hamming distance between the query hash code vector and the support set hash code vectors stored in the array within a search cycle.

[0096] The quantization module, including the TIA, the sample and hold module S&H, the multiplexer MUX, and the analog-to-digital converter ADC, is used to convert the SL current into a partial Hamming distance.

[0097] The TCAM function macro module is used to implement the read head function of the external memory of the MANN neural network learning model. During the evaluation phase, the query hash code vector generated by the LSH macro is decoded by the BL decoder in the diagram, controlling the voltage charging of BL. The decoding rules are as follows: Figure 7 As shown, Figure 7 This diagram illustrates a search rule for a read head and a TCAM data storage rule for an embodiment of this application. Within one search cycle, the BL voltage is passed to each selected cell in the array, and the Hamming distance between the query hash code vector and the hash code vector of each stored support set in the array is calculated in parallel. Then, the SL current passes through the TIA, S&H, and MUX, and is finally quantized into a partial Hamming distance by the ADC.

[0098] The TCAM function macro module also implements the write-head function for the external memory of the neural network learning model MANN. It obtains the updated vector by averaging the elements of the old and new vectors and replacing the old vector in memory with the updated vector. To eliminate division in the floating-point domain, this application employs a ternary hash code vector update method. For a ternary vector, if the new support set vector Sn+1 has the minimum Hamming distance to the existing support set vector M(k) in TCAM and has the same label, then an update vector must be generated to replace M(k). The rules for generating the update vector are shown in Table 1. To implement the ternary hash code vector update method, this application proposes a low-overhead write-head implementation scheme. During the training phase, for the new support set hash code vector Sn+1, the read-head function is used to confirm that the Hamming distance between Sn+1 and M(k) is minimum and that their labels are the same. Then, the row containing M(k) is selected by controlling the SSL switch matrix. Next, the BL decoder controls all BLs to be turned on and reads M(k). Figure 3 The encoder in the memory is used. Simultaneously, Sn+1 will also be read into the encoder. The encoder will encode the updated hash code vector based on the values ​​of each bit of Sn+1 and M(k). The encoding rules of the encoder are shown in Table 1. The write-head scheme involves only two steps: a regular memory search to determine the nearest neighbor hash vector and its label; the second step only requires a regular read operation to generate the updated hash code vector. Figure 8 As shown, Figure 8This is a schematic diagram of TCAM entry update in 3D NAND provided in an embodiment of this application. First, a search is performed to find an entry that matches a given hash code vector. Then, the entry that is most similar to the given hash code vector is found in the hash table, as shown in the pentagram pattern in the figure. Finally, the data in the last blank column is updated, which may involve modifying existing entries or replacing them with new data.

[0099] Since the erase cells of 3D NAND flash memory are blocks, this application proposes using registers to maintain the switching rules of the SSL switch matrix. When M(k) needs to be updated, an empty row (e.g., row l) is selected to write the updated vector M'(l), and then the register is updated. In subsequent search operations, SSLk is no longer enabled, but SSLl is enabled, which is equivalent to masking the old vector M(k). If the Hamming distance between Sn+1 and M(k) is the smallest, but their labels are different, Sn+1 is directly written to the empty row l, and the register is updated. In subsequent searches, both SSLk and SSLl are enabled.

[0100] Table 1: Rules for generating update vectors

[0101] Enter hash code Store hash code Updated hash code 0 0 0 0 1 X 1 0 X 1 1 1 0 X 0 X 0 0 1 X 1 X 1 1 X X X

[0102] Specifically, in one implementation of this application, the ternary content-addressable memory (TCAM) macro further includes a write head circuit, which includes:

[0103] The updated vector generation module is used to generate the updated vector by averaging elements and to determine whether the stored vector needs to be updated based on the ternary hash code vector update method.

[0104] The SSL switch matrix selection module is used during the training phase to select the row containing the storage vectors with the minimum Hamming distance and the same label.

[0105] The encoder module is used to read the stored vector and the new vector, and generate an updated hash code vector according to the encoding rules;

[0106] The free row selection module is used to select a free row to write the updated vector when a vector needs to be updated, and to update the register so that the corresponding storage row can be correctly selected and opened in subsequent search operations.

[0107] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0109] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A 3D NAND flash memory system, characterized in that, The system includes multiple hierarchical data storage arrays. A MAC computation macro, configured within at least one of the plurality of hierarchical data storage arrays, is used to perform feature extraction operations; A Locality Sensitive Hash (LSH) computation macro is configured in another array among the plurality of hierarchical data storage arrays to generate hash code vectors based on extracted features; The Ternary Content Addressable Memory (TCAM) macro is configured in one of the plurality of hierarchical data storage arrays and is used to perform query and update operations on vectors in memory. The control unit is used to activate only one layer of the multiple hierarchical data storage arrays within a computing cycle, and control the functional modules in the activated layer to perform corresponding computing tasks, while keeping the functional modules in other layers in an inactive or low-power state.

2. The system according to claim 1, characterized in that, The 3D NAND flash memory array is divided into multiple regions, each region is mapped to a convolution kernel, and two adjacent rows of cells are used to store the positive and negative values ​​of the weight bits respectively.

3. The system according to claim 2, characterized in that, The MAC calculation macro includes: The input receiving module is used to receive the calculation results from the upper-level data storage array, convert the calculation results into vector form input, and transmit them to the local buffer via the bus. A voltage conversion module is used to convert each vector element into a bit-line (BL) voltage sequence; The source selection line SSL switch matrix is ​​used to select the rows that participate in the MAC calculation; The calculation result acquisition module acquires the calculation result at the source line SL when the BL voltage is conducted to all cells corresponding to the input vector. The current of a single SL represents part and result. The differential amplification and sample-and-hold module is used to differentially amplify the voltage obtained by each pair of adjacent SL lines and sample and hold the difference through the sample-and-hold circuit. The multiplexer and quantization module selects a voltage result sequentially within a single calculation cycle using the multiplexer, and then quantizes the voltage result into a fixed-point result using a successive approximation analog-to-digital converter (SAR ADC). The result processing module is used to shift and add the quantized partial results to obtain the complete MAC result, and to process the MAC result through the ReLU activation function; The output transmission module is used to transmit the activated MAC result to the local buffer, and then transmit the MAC result in the local buffer to the chip-level accumulator via the bus to complete the shift and addition operations, thereby obtaining the final result.

4. The system according to claim 1, characterized in that, The Locality Sensitive Hash (LSH) calculation macro includes: The real-valued eigenvector conversion module is used to convert real-valued eigenvectors into analog voltage values ​​ranging from 0 to 0.3V via an 8-bit DAC, and apply the analog voltage values ​​to selected cells in the 3D NAND flash memory array, so that the cells are in the deep linear region, where each cell acts as a constant conductance; The random Gaussian distribution matrix construction module utilizes the inherent inter-cell variations and program interference in the 3D NAND flash memory array to achieve an approximate normal distribution when programming the cells to the target threshold voltage, thereby constructing a random Gaussian distribution matrix, which is then mapped to the conductance value of the cell array with the same target threshold voltage. The MAC operation execution module is used to encode the input vector into a bit line voltage vector, perform MAC operations in the 3D NAND flash array, and reflect the result of each row multiplication in the source line SL current. The differential function implementation module is used to convert the SL current into a voltage through a transimpedance amplifier (TIA), and then process the voltage through a differential amplifier. The hash code encoding module encodes the hash code bits based on the comparison results between the output voltage of the differential amplifier and preset thresholds Vcm and Vth; where Vcm represents the common-mode output voltage of the differential amplifier, and Vth is the threshold for encoding the output voltage Vout of the differential amplifier into X. The output module is used to output the encoded ternary hash code vector.

5. The system according to claim 4, characterized in that, The step of encoding the hash code bits based on the comparison results between the output voltage of the differential amplifier and preset thresholds Vcm and Vth includes: The hash code bits are encoded as 0, 1, or the wildcard X; When Vout is less than Vcm-Vth, the hash code bit is encoded as 1; when Vout is greater than Vcm+Vth, the hash code bit is encoded as 0. If the magnitude of Vout falls between these two thresholds, it is encoded as the wildcard X.

6. The system according to claim 5, characterized in that, The ternary content-addressable memory (TCAM) macros include: The TCAM function macro module is used to implement the read / write head function of the external memory of the MANN neural network learning model; The SSL switch matrix module is used to select and switch to the appropriate storage row when writing update vectors; The register module is used to maintain the switching rules of the SSL switch matrix to correctly select and open the corresponding store row in subsequent search operations.

7. The system according to claim 6, characterized in that, The ternary content-addressable memory (TCAM) macro also includes a read head circuit, which includes: The BL decoder module is used to decode the query hash code vector generated by the locality-sensitive hash macro and control the charging of the corresponding bit line voltage. The parallel computing module is used to calculate the Hamming distance between the query hash code vector and the support set hash code vector of each stored in the array within one search cycle; The quantization module, including the TIA, the sample and hold module S&H, the multiplexer MUX, and the analog-to-digital converter ADC, is used to convert the SL current into a partial Hamming distance.

8. The system according to claim 6, characterized in that, The ternary content-addressable memory (TCAM) macro also includes a write head circuit, which includes: The updated vector generation module is used to generate the updated vector by averaging elements and to determine whether the stored vector needs to be updated based on the ternary hash code vector update method. The SSL switch matrix selection module is used during the training phase to select the row containing the storage vectors with the minimum Hamming distance and the same label. The encoder module is used to read the stored vector and the new vector, and generate an updated hash code vector according to the encoding rules; The free row selection module is used to select a free row to write the updated vector when a vector needs to be updated, and to update the register so that the corresponding storage row can be correctly selected and opened in subsequent search operations.

9. The system according to claim 1, characterized in that, The system also includes peripheral circuitry, which includes bit lines, word lines, source select line drivers, decoders, digital-to-analog converters, update / search modules, and analog-to-digital converters, accumulators, and sensing blocks for quantization and computation purposes, enabling switching between different functions and power consumption control.

10. The system according to claim 9, characterized in that, The peripheral circuitry also includes multiplexers and transmission gates for switching between different computing functions, as well as power gating for shutting down inactive circuits when not in use.

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