Instruction interaction method and system for double-suspension-arm parallel of chip mounter and medium

Abstract

The present application relates to electronic manufacturing equipment technical field, specifically to a kind of double-cantilever parallel instruction interaction method, system and medium of chip mounter, method includes: receiving one or more instructions from host computer in advance, the instruction includes the two mounting process instructions of corresponding double-cantilever, two mounting process instructions are cached in two cache FIFO respectively;Two cache FIFOs are monitored respectively until empty, sequentially take out instruction to parse the execution object of instruction;If the execution object of instruction is subordinate board, then issue subordinate board in the time of arbitration distribution;If the execution object of instruction is main control board, then issue to main control board execution.This scheme each mounting process control logic is independent of each other, whereby both can realize the synchronization function between different mounting processes, also can monitor whether a certain event occurs in the same mounting process, to ensure that double-arm mounting head in high-speed parallel operation instruction real-time synchronization.

Description

Technical Field

[0001] This invention relates to the field of electronic manufacturing equipment technology, and more specifically to a method, system, and medium for parallel instruction interaction of a dual-cantilever placement machine. Background Technology

[0002] Dual-arm pick-and-place machines, by independently mounting the left and right placement heads on dual X-axis beams and coordinating with dual conveyor tracks, can achieve production in various scenarios, including single-track large board production, dual-track synchronous production, and anomaly handling, with a theoretical capacity up to twice that of single-arm machines. However, in high-speed parallel operation, the instruction interaction bottleneck limits its performance. In existing technologies, dual-arm pick-and-place machines mostly use a single CPU for serial distribution or a fixed-timing binding mode for instruction processing. A single CPU must simultaneously process the motion instructions of both arms and vision tasks, which can easily lead to instruction delays, causing misalignment of the two arms, resulting in collision risks or decreased accuracy. The fixed-timing binding mode is difficult to adapt to the placement needs of multiple types and mixed components. When one arm experiences an anomaly such as material picking delay or recognition failure, the other arm must wait unconditionally, causing the actual capacity to be far lower than the theoretical value. Therefore, there is an urgent need for an instruction interaction solution adapted to the high-speed parallel operation of dual-arm pick-and-place machines to achieve accurate instruction synchronization, efficient scheduling, and conflict avoidance. Summary of the Invention

[0003] To address the problems in the existing technology, the present invention aims to provide a method, system, and medium for parallel instruction interaction of dual cantilever placement heads in a pick-and-place machine. This method enables real-time synchronization of instructions, intelligent conflict avoidance, and precise cycle time adaptation for dual-arm placement heads during high-speed parallel operation, thereby maximizing capacity utilization and meeting the SMT production needs of multiple scenarios and component types.

[0004] To achieve the above objectives, the first aspect of the present invention provides a method for instruction interaction in parallel operation of a pick-and-place machine with two cantilever arms, comprising the following steps: Receive one or more instructions from the host computer in advance, the instructions include two placement process instructions corresponding to the double cantilever, and cache the two placement process instructions into two buffer FIFOs respectively; After monitoring the two buffer FIFOs until they are no longer empty, instructions are retrieved one by one in sequence to parse the execution object of the instructions; If the instruction is to be executed on a lower-level board, it will be sent to the lower-level board within the time allocated by arbitration. If the instruction is to be executed on the main control board, it will be sent to the main control board for execution. During execution, instructions cannot be retrieved from the buffer FIFO.

[0005] Preferably, after parsing the instruction, the first byte of the instruction is obtained, and the execution target of the instruction is determined based on the number of the first byte, specifically as follows: If the first byte contains any number from 1 to 8, it is determined that the instruction is executed on a lower-level board. Here, 1 to 8 correspond to different encoded lower-level modules, including two mounting modules, an automatic tray module, an XY module, a feeder ATC module, a PCB module, and a peripheral module. Otherwise, it is determined that the instruction is executed by the main control board.

[0006] Preferably, the instructions executed by the main control board include a wait-for-motion-completion instruction, which contains an instruction code, a wait-for-object code, a wait-for-instruction sequence code, and a wait-for-motion-completion sequence number. When the waiting motion is complete, the instruction code is stored. After the host computer reads it, it is stored in the log to confirm that the corresponding waiting motion completion instruction has been executed. The waiting object is determined by the waiting object code to determine whether it is a module or an axis. If the waiting object is a module, it is necessary to wait for the corresponding waiting instruction sequence code to confirm that the waiting is complete. If the waiting object is an axis, it is determined by the waiting instruction sequence code that all waiting axes are stationary to confirm that the waiting is complete. The instructions for the two placement processes are synchronized based on the completion sequence number of the waiting motion.

[0007] Preferably, in the waiting motion completion instruction, Bytes 2-5 are set as the instruction code; Byte 6 is set as the waiting object code, where Byte 6 being 0 indicates that the waiting object is an axis; Bytes 7-10 are set as the waiting instruction sequence code; Byte 11 is set as the waiting motion completion sequence number, where bits 0-6 of Byte 11 are sequence number values. When bit 7 is 1, it indicates that the instruction corresponding to the sequence number value of bits 0-6 is waiting to be completed; when bit 7 is 0, it indicates that the corresponding instruction has been completed. The corresponding sequence number value is recorded, and the same sequence number value is recorded in pairs to achieve instruction synchronization of the two mounting processes; wherein, Byte11 is used in conjunction with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 1, the corresponding waiting instruction sequence code and sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 1, it is necessary to wait for the corresponding action to be completed and receive the sequence number value before determining that the waiting action completion instruction has been executed. Byte11 is used in combination with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 0, when the corresponding waiting instruction sequence code is received, it is determined that the waiting movement completion instruction has been executed and the corresponding sequence number value is recorded. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 0, after the corresponding action is completed, it is determined that the waiting action completion instruction has been executed and the corresponding sequence number value is recorded. When Byte11 is used alone, if Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 1, the corresponding sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used alone. When Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 0, the corresponding sequence number value is recorded.

[0008] Preferably, the execution rules for the waiting motion completion instruction include: When executing the "wait for motion completion" instruction, it is not allowed to fetch the instruction from the corresponding buffer FIFO; When Byte6 is not 0, wait to receive the corresponding wait instruction sequence code, confirm that the wait is completed, and then give the end completion code; When Byte6 is 0 and Byte7~Byte10 are not 0, wait for the specified axis to stop or for the action to complete, and then give the completion code.

[0009] Preferably, the debug process instruction received from the host computer is not stored in the cache and is directly sent to the lower-level board for execution. Each lower-level board has a separate debug process. The debug process instruction is used to deal with emergency stop events and has a higher priority than the mounting process instruction.

[0010] Preferably, the method is implemented based on FPGA. The host computer and FPGA transmit data through memory mapping. The address corresponding to each bit of each instruction is agreed upon in advance, and the host computer writes the instructions to the corresponding addresses in a specified order.

[0011] A second aspect of the present invention provides a parallel instruction interaction system for a dual-cantilever pick-and-place machine, comprising: The caching module is used to receive one or more instructions from the host computer in advance. The instructions include two placement process instructions corresponding to the double cantilever, and the two placement process instructions are cached into two buffer FIFOs respectively. The parsing module is used to monitor the two buffer FIFOs until they are not empty, and then retrieve the instructions one by one in sequence to parse the execution object of the instructions; An arbitrator is used to control the delivery of instructions to a lower-level board within the time allocated by the arbitrator if the target of the instruction is a lower-level board. The main control board is used to send instructions to the main control board for execution if the target of the instruction is the main control board. During the execution, instructions are not allowed to be retrieved from the buffer FIFO.

[0012] A third aspect of the present invention provides a machine-readable storage medium storing instructions that cause a machine to execute the instruction interaction method for parallel dual-cantilever placement of a pick-and-place machine described in this application.

[0013] A fourth aspect of the present invention provides a processor for running a program, wherein the program is run to execute the steps of the above-described parallel instruction interaction method for a dual-cantilever pick-and-place machine.

[0014] The above technical solution establishes two placement process instruction buffer FIFOs. The host computer can pre-issue instructions to these two FIFOs based on instruction execution requirements, and the actual execution timing of the instructions is determined by the placement process control logic. This mechanism effectively reduces the time delay between instruction issuance and execution, improving instruction execution efficiency and pick-and-place machine capacity. The instruction design allows for flexible combination of the two placement processes; at any given time, only one process can be activated, or both processes can be used simultaneously, thus adapting to the SMT production needs of multiple scenarios and component types. Each placement process control logic is independent and can execute waiting-for-move-to-completion instructions. This enables synchronization between different placement processes and allows monitoring of events within the same placement process, ensuring real-time synchronization of instructions during high-speed parallel operation of the dual-arm placement heads.

[0015] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the method flow of an embodiment of the present invention; Figure 2 This is a schematic diagram of the instruction execution flow according to an embodiment of the present invention; Figure 3 This is a flowchart of the control logic for each mounting process in an embodiment of the present invention. Detailed Implementation

[0017] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0018] The method in this embodiment of the invention is implemented based on an FPGA. The host computer is responsible for issuing instructions, and the FPGA is responsible for receiving and executing the instructions. The host computer and the FPGA communicate directly using a PCIe interface, exemplarily using a PCIe 2.0 x4 interface. Based on SMT production requirements, the host computer pre-issues the instructions that the dual-arm placement machine needs to execute to the FPGA. The FPGA controls the placement machine to perform corresponding actions according to the instruction content, realizing high-speed parallel operation of the dual-arm placement heads.

[0019] The FPGA receives instructions from the host computer and processes them in two separate processes, such as... Figure 2 As shown, one type serves as the main process for implementing the mounting process of the double cantilever, while the other type serves as a debug process to quickly react to emergencies such as sudden stops, allowing instructions to be executed rapidly without waiting.

[0020] The first aspect of this invention provides a method for instruction interaction in parallel operation of a dual-cantilever placement machine, for instructions in the main process, such as... Figure 1 As shown, it includes the following steps: Receive one or more instructions from the host computer in advance, the instructions include two placement process instructions corresponding to the double cantilever, and cache the two placement process instructions into two buffer FIFOs respectively; Since each arm has a placement head A and a placement head B, two placement processes are set up, corresponding to Placement Process 1 and Placement Process 2 respectively. The main process controls these two placement processes to execute placement actions at high speed and in parallel. To meet the high-speed parallel requirements of the two arms, two placement process instruction buffer FIFOs are set up in the main process. The host computer sends instructions to these two FIFOs according to the instruction execution requirements, and can send multiple instructions at once. Since the instructions are sent to the FPGA in advance, the instruction latency problem can be effectively solved, and the execution efficiency can be improved.

[0021] The two placement process instruction buffer FIFOs correspond to the two placement heads respectively: instructions related to placement head A are executed by placement process 1, and instructions related to placement head B are executed by placement process 2, thereby ensuring that the two-arm placement heads can perform placement actions in parallel at high speed.

[0022] The control logic of the two mounting processes in this embodiment of the invention is independent of each other, and the main logic functions include: (1) Fetch instructions from the instruction buffer FIFO to ensure that instructions in the same FIFO are executed in order; (2) Within the same mounting process, wait for the specific action to be completed; (3) Achieve instruction synchronization between different mounting processes; (4) Forward the instructions to the next-level board; (5) Allow the mounting process to wait for a specified time, during which no operation is performed.

[0023] After monitoring the two buffer FIFOs until they are no longer empty, instructions are retrieved one by one in sequence to parse the execution object of the instructions; Instructions are divided into two categories based on their execution target: one category consists of logical instructions executed within the main control board, which do not require the arbitrator; the other category consists of instructions that need to be forwarded to lower-level boards, which can only be issued based on the time allocated by the arbitrator—that is, they can only be forwarded to lower-level boards after the arbitrator has allocated execution time for the control logic. Each placement process has independent control logic, and its execution flow is as follows: Figure 3 As shown. The control logic continuously checks whether the instruction buffer FIFO is empty: if it is empty, it continues to wait until it is not empty; if it is not empty, it retrieves an instruction from it and parses its content, determining the action to be executed based on the first byte of the instruction.

[0024] If the instruction is to be executed on a lower-level board, it will be sent to the lower-level board within the time allocated by arbitration. Further, after parsing the instruction, the first byte of the instruction is obtained, and the execution target of the instruction is determined based on the number of the first byte. For example, when the content of the first byte of the instruction is 1-8, it is determined that the main process will not execute the instruction and will forward the instruction to the lower-level board. The first byte 1-8 respectively corresponds to encoding different lower-level modules, including two placement modules, an automatic tray module, an XY module, a feeder ATC module, a PCB module, and a peripheral module; otherwise, it is determined that the main control board will execute the instruction to wait for the movement to complete or the instruction to wait for a period of time. Such instructions need to be timed and allocated by an arbitrator, and can only be sent to the lower-level board within the time allocated by the arbitrator, such as... Figure 2 As shown: The arbitrator is used to allocate execution time for the two placement process control logics, employing a time-slice round-robin scheduling algorithm to allocate a fixed-length time slice to each control logic. Only within the allocated time slice is the corresponding placement process control logic allowed to issue instructions to the lower-level board. If the current control logic is blocked or completes execution before the time slice ends, it immediately switches over, allocating the time slice to the other placement process control logic. When a control logic exhausts its time slice, it is moved to the end of the queue. The purpose is to prevent instruction conflicts between the two placement processes when issuing instructions to the lower-level board, which could lead to instruction execution problems.

[0025] If the instruction is to be executed by the main control board, the main control board will execute the corresponding action according to the content of the instruction. During the execution, instructions cannot be retrieved from the buffer FIFO.

[0026] Furthermore, the main control board executes instructions including a "wait for motion completion" instruction, used to monitor whether the axis movement is complete, whether the instruction is completed, and to synchronize the instructions for the two placement processes. These three functions enable the dual-arm pick-and-place machine to achieve real-time instruction synchronization, conflict instruction avoidance, and orderly instruction execution during high-speed parallel operation. Specifically, the "wait for motion completion" instruction includes an instruction code, a waiting object code, a waiting instruction sequence code, and a waiting motion completion sequence number. When the waiting motion is complete, the instruction code is stored. After the host computer reads it, it is stored in the log to confirm that the corresponding waiting motion completion instruction has been executed. The waiting object is determined by the waiting object code to determine whether it is a module or an axis. If the waiting object is a module, it is necessary to wait for the corresponding waiting instruction sequence code to confirm that the waiting is complete. If the waiting object is an axis, it is determined by the waiting instruction sequence code that all waiting axes are stationary to confirm that the waiting is complete. The instructions for the two placement processes are synchronized based on the completion sequence number of the waiting motion.

[0027] For example, when the first byte of the instruction is 0x15, it is determined to be the waiting motion completion instruction. In the waiting motion completion instruction, Bytes 2 to 5 are set as the instruction code; Byte 6 is set as the waiting object code, and its value can only be the first byte content of the lower-level board or 0. When Byte 6 is 0, it indicates that the waiting object is an axis; Bytes 7 to 10 are set as the waiting instruction sequence code; Byte 11 is set as the waiting motion completion sequence number. Bits 0 to 6 of Byte 11 are sequence number values. When bit 7 is 1, it indicates that the instruction corresponding to the sequence number value of bit 0 to bit 6 needs to be completed; when bit 7 is 0, it indicates that the corresponding instruction has been executed. The corresponding sequence number value is recorded, and the same sequence number value is recorded in pairs to realize the instruction synchronization of the two placement processes. Byte11 is used in conjunction with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 1, the corresponding waiting instruction sequence code and sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 1, it is necessary to wait for the corresponding action to be completed and receive the sequence number value before determining that the waiting action completion instruction has been executed. Byte11 is used in combination with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 0, when the corresponding waiting instruction sequence code is received, it is determined that the waiting movement completion instruction has been executed and the corresponding sequence number value is recorded. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 0, after the corresponding action is completed, it is determined that the waiting action completion instruction has been executed and the corresponding sequence number value is recorded. When Byte11 is used alone, if Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 1, the corresponding sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used alone. When Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 0, the corresponding sequence number value is recorded.

[0028] The execution rules for the waiting motion completion instruction include: When executing the "wait for motion completion" instruction, it is not allowed to fetch the instruction from the corresponding buffer FIFO; When Byte6 is not 0, wait to receive the corresponding wait instruction sequence code, confirm that the wait is completed, and then give the end completion code; When Byte6 is 0 and Byte7~Byte10 are not 0, wait for the specified axis to stop or for the action to complete, and then give the completion code.

[0029] Through the instruction design in this embodiment of the invention, the FPGA can automatically process data based on the issued instructions and their execution completion status, without the need for host computer intervention. By combining Bytes 6, 7-10, and 11 in the waiting-for-motion-completion instruction, instruction synchronization between different placement processes can be achieved. It also ensures that within the same placement process, the next instruction is retrieved from the placement process buffer FIFO only after the specific action is completed. This instruction mechanism effectively guarantees real-time synchronization and intelligent conflict avoidance of dual-arm placement head instructions, enabling parallel operation under high-speed motion.

[0030] When the first byte of an instruction is 0x16, the FPGA recognizes it as an instruction to wait for a certain period. During this time, the FPGA waits according to the specified wait time parameter in the instruction. During this period, the placement process control logic must not perform other operations, nor can it retrieve instructions from the placement process buffer FIFO. If the first byte of the instruction contains other defined content, the corresponding defined action is executed; if the first byte is undefined, the instruction is ignored.

[0031] In another embodiment of the present invention, when the FPGA receives the debug process instruction from the host computer, it does not store it in the cache but directly sends it to the lower-level board for execution, with a higher priority than the mounting process instruction.

[0032] The host computer and FPGA transmit data via memory mapping. The address corresponding to each bit of each instruction is pre-defined, and the host computer writes the instructions sequentially to the corresponding addresses in a specified order. This allows for real-time judgment of instruction writing time and completion time, with simple logic. For example, to enable the dual-arm placement head to operate in high-speed parallel processing, the order in which the host computer writes the main process instructions must be specified as follows: as shown in Table 1, the 512-bit instruction is written first, and the data at address 26'h3040 is written last. After writing the data at address 26'h3040, the FPGA stores the instruction in the corresponding buffer FIFO. Bit 0 of address 26'h3040 is used to specify the target FIFO: when Bit 0 is 1, the instruction is stored in the instruction buffer FIFO of placement process 1; when Bit 0 is 0, the instruction is stored in the instruction buffer FIFO of placement process 2.

[0033] Table 1 Main Flow Instruction Format

[0034] For the debug process, the address mapping relationship between the host computer and the FPGA is shown in Table 2.

[0035] Table 2 Debugging Procedure Command Format

[0036] The contents of instructions issued to lower-level boards are shown in Table 3. The first byte, Byte0, is the slave address, and its value is based on the contents of the first byte in Table 1. If the host computer issues instructions to the FPGA through the main process, the slave address needs to be specified; if it issues through the debug process, it does not need to be specified. Byte1 is function code A, and Byte2 is function code B, which together determine the specific operation executed by the instruction. Byte3 is the message length n, indicating that the instruction number and message body occupy n bytes in total. The instruction number is an optional field, determined by the host computer: when the instruction number is included, the lower-level board needs to return the number twice—the first time immediately upon receiving the instruction, indicating that it has been received; the second time after the action required by the instruction is completed, indicating that the execution is complete. If there is no instruction number, the lower-level board considers the instruction as completed upon receiving the instruction. The message body is used to specify relevant parameters. CRC16 for MODBUS is used to verify the instruction data to prevent data errors during transmission.

[0037] Table 3. Instructions issued to lower-level boards

[0038] The existing solution lacks instruction hierarchical and conflict prediction mechanisms, and cannot perform real-time instruction verification and dynamic adjustment for the spatial envelope, resource occupation and process progress of the two arms, making it difficult to meet the requirements of SMT production lines for high capacity and high stability.

[0039] The technical solution of this invention is classified into main process and debug process, and the instructions are distributed in layers. The instruction format design of the main process is implemented to distribute the instructions level by level and conduct conflict research. Combined with the instruction format design for the lower level boards, the instructions are further distributed in layers. This not only solves the above problems, but also realizes real-time synchronization of instructions, intelligent conflict avoidance and precise rhythm adaptation of the dual-arm placement head in high-speed parallel operation.

[0040] Based on the same inventive concept, a second aspect of the present invention provides a command interaction system for a dual-cantilever parallel placement machine, comprising: The caching module is used to receive one or more instructions from the host computer in advance. The instructions include two placement process instructions corresponding to the double cantilever, and the two placement process instructions are cached into two buffer FIFOs respectively. The parsing module is used to monitor the two buffer FIFOs until they are not empty, and then retrieve the instructions one by one in sequence to parse the execution object of the instructions; An arbitrator is used to control the delivery of instructions to a lower-level board within the time allocated by the arbitrator if the target of the instruction is a lower-level board. The main control board is used to send instructions to the main control board for execution if the target of the instruction is the main control board. During the execution, instructions are not allowed to be retrieved from the buffer FIFO.

[0041] A third aspect of the present invention provides a machine-readable storage medium storing instructions that cause a machine to execute the instruction interaction method for parallel dual-cantilever placement machine described in this application.

[0042] A fourth aspect of the present invention provides a processor for running a program, wherein the program is executed to perform the steps of the above-described parallel instruction interaction method for a dual-cantilever pick-and-place machine.

[0043] In summary, the technical solution of the present invention has the following beneficial effects: (1) Two instruction flows, the main flow and the debug flow, are set up, providing multiple options for the upper-level machine to issue instructions. At the same time, by setting priorities for the two flows, it is ensured that emergency instructions can be responded to quickly. (2) Two placement flow instruction buffer FIFOs are set up in the main flow. The upper-level machine can issue instructions to these two FIFOs in advance according to the instruction execution requirements. The actual execution time of the instructions is determined by the placement flow control logic. This mechanism effectively reduces the time delay between instruction issuance and execution, and improves the instruction execution efficiency and the pick-and-place machine capacity. (3) Two placement flows are set up, each corresponding to two placement heads. The two flows can be used in combination. At a certain time, only one placement flow can be activated, or both flows can be used at the same time, thereby adapting to the SMT production needs of multiple scenarios and multiple component types. (4) Each placement flow has its own control logic, and each can execute the waiting motion completion instruction. This design can realize the synchronization function between different placement processes, and can also monitor whether a certain event has occurred within the same placement process, thereby ensuring the real-time synchronization of instructions when the dual-arm placement head is operating in parallel at high speed. (5) The two placement processes share an arbitration logic, and each lower-level board has a debug process. This mechanism solves the problem of instruction conflict failure and ensures that instructions can be executed in an orderly manner. (6) The specific format and address mapping relationship of the instructions are specified, which makes it convenient for the host computer to send instructions to the FPGA. The slave address is set in the instruction, which makes it convenient for the FPGA to execute the instruction or forward the instruction to a specific lower-level module; function code A and function code B are set so that the lower-level board can perform different operations; instruction encoding is set so as to know the completion status of the instruction; CRC16 for MODBUS is set to ensure that there are no errors in the data transmission process.

[0044] It should also be noted that the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0045] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for instruction interaction in parallel operation of a dual-cantilever pick-and-place machine, characterized in that, Includes the following steps: Receive one or more instructions from the host computer in advance, the instructions include two placement process instructions corresponding to the double cantilever, and cache the two placement process instructions into two buffer FIFOs respectively; After monitoring the two buffer FIFOs until they are no longer empty, instructions are retrieved one by one in sequence to parse the execution object of the instructions; If the instruction is to be executed on a lower-level board, it will be sent to the lower-level board within the time allocated by arbitration. If the instruction is to be executed on the main control board, it will be sent to the main control board for execution. During execution, instructions cannot be retrieved from the buffer FIFO.

2. The method according to claim 1, characterized in that, After parsing the instruction, the first byte of the instruction is obtained. The target of the instruction is determined based on the number in the first byte. Specifically: If the first byte contains any number from 1 to 8, it is determined that the instruction is executed on a lower-level board. Here, 1 to 8 correspond to different encoded lower-level modules, including two mounting modules, an automatic tray module, an XY module, a feeder ATC module, a PCB module, and a peripheral module. Otherwise, it is determined that the instruction is executed by the main control board.

3. The method according to claim 1, characterized in that, The main control board executes instructions including a wait-for-motion-completion instruction, which contains an instruction code, a wait-for-object code, a wait-for-instruction sequence code, and a wait-for-motion-completion sequence number. When the waiting motion is complete, the instruction code is stored. After the host computer reads it, it is stored in the log to confirm that the corresponding waiting motion completion instruction has been executed. The waiting object is determined by the waiting object code to determine whether it is a module or an axis. If the waiting object is a module, it is necessary to wait for the corresponding waiting instruction sequence code to confirm that the waiting is complete. If the waiting object is an axis, it is determined by the waiting instruction sequence code that all waiting axes are stationary to confirm that the waiting is complete. The instructions for the two placement processes are synchronized based on the completion sequence number of the waiting motion.

4. The method according to claim 3, characterized in that, In the waiting motion completion instruction, Bytes 2-5 are set as the instruction code; Byte 6 is set as the waiting object code, and when Byte 6 is 0, it indicates that the waiting object is an axis; Bytes 7-10 are set as the waiting instruction sequence code; Byte 11 is set as the waiting motion completion sequence number, where bits 0-6 of Byte 11 are sequence number values. When bit 7 is 1, it indicates that the instruction corresponding to the sequence number value of bits 0-6 needs to be completed; when bit 7 is 0, it indicates that the corresponding instruction has been executed. The corresponding sequence number value is recorded, and the same sequence number value is recorded in pairs to achieve instruction synchronization of the two placement processes; wherein, Byte11 is used in conjunction with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 1, the corresponding waiting instruction sequence code and sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 1, it is necessary to wait for the corresponding action to be completed and receive the sequence number value before determining that the waiting action completion instruction has been executed. Byte11 is used in combination with Byte6. When Byte6 is not 0 and bit7 of Byte11 is 0, when the corresponding waiting instruction sequence code is received, it is determined that the waiting movement completion instruction has been executed and the corresponding sequence number value is recorded. Byte11 is used in conjunction with Byte7~Byte10. When Byte6 is 0 and Byte7~Byte10 are not 0 and bit7 of Byte11 is 0, after the corresponding action is completed, it is determined that the waiting action completion instruction has been executed and the corresponding sequence number value is recorded. When Byte11 is used alone, if Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 1, the corresponding sequence number value must be received before it can be determined that the waiting motion completion instruction has been executed. Byte11 is used alone. When Byte6 is 0, Byte7~Byte10 are 0, and bit7 of Byte11 is 0, the corresponding sequence number value is recorded.

5. The method according to claim 4, characterized in that, The execution rules for the waiting motion completion instruction include: When executing the "wait for motion completion" instruction, it is not allowed to fetch the instruction from the corresponding buffer FIFO; When Byte6 is not 0, wait to receive the corresponding wait instruction sequence code, confirm that the wait is completed, and then give the end completion code; When Byte6 is 0 and Byte7~Byte10 are not 0, wait for the specified axis to stop or for the action to complete, and then give the completion code.

6. The method according to any one of claims 1-5, characterized in that, The system receives debug process instructions from the host computer and sends them directly to the lower-level boards for execution without storing them in the cache. Each lower-level board has its own debug process. The debug process instructions are used to deal with emergency stop events and have a higher priority than the mounting process instructions.

7. The method according to claim 6, characterized in that, The method is implemented based on FPGA. The host computer and FPGA transmit data through memory mapping. The address corresponding to each bit of each instruction is agreed upon in advance, and the host computer writes the instructions to the corresponding addresses in a specified order.

8. A parallel instruction interaction system for a pick-and-place machine with two cantilever arms, characterized in that, include: The caching module is used to receive one or more instructions from the host computer in advance. The instructions include two placement process instructions corresponding to the double cantilever, and the two placement process instructions are cached into two buffer FIFOs respectively. The parsing module is used to monitor the two buffer FIFOs until they are not empty, and then retrieve the instructions one by one in sequence to parse the execution object of the instructions; An arbitrator is used to control the delivery of instructions to a lower-level board within the time allocated by the arbitrator if the target of the instruction is a lower-level board. The main control board is used to send instructions to the main control board for execution if the target of the instruction is the main control board. During the execution, instructions are not allowed to be retrieved from the buffer FIFO.

9. A machine-readable storage medium storing instructions that cause a machine to perform the method described in any one of claims 1-7 of this application.

10. A processor, characterized in that, Used to run a program, wherein the program is run to execute the steps of the instruction interaction method for a dual-cantilever parallel placement machine as described in any one of claims 1-7.

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