A method and system for testing an HBM PHY chip based on segmented FIFO control SRE / SRX commands

Abstract

The application aims to provide a HBM PHY chip test method and system based on segmented FIFO control SRE / SRX command, which comprises the following steps: storing the command to be sent to the DFI interface of the HBM PHY in the FIFO according to the timing and operation of the DRAM; reading out the command stored in the FIFO and sending it to the DFI bus of the HBM PHY; and writing the executed command back to the FIFO. The application separates the parts of SRE / SRX by using the segmented FIFO mode, and determines whether to execute SRE / SRX based on the switching of Power State, PPT, frequency point switching, lane repair or the requirement of entering the sleep state, so as to meet the requirements of HBM3 PHY and DRAM particles for these test scenarios.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to an HBM PHY chip testing method and system based on segmented FIFO control of SRE / SRX commands. Background Technology

[0002] Due to advancements in manufacturing technology, memory systems have developed rapidly in recent years. High-bandwidth memory (HBM) is an example of a recent type of memory system, supporting low power consumption, ultra-wide communication channels, and stacked configurations. HBM subsystems involve different types of memory controllers (full-speed, half-speed, quarter-speed), HBM PHYs, and HBM DRAMs. HBM subsystems are suitable for applications involving high-performance graphics and computing, high-end networking and communication devices, and processors requiring large amounts of memory. Due to their critical role in the end-application, validating all components involved in the HBM subsystem is essential. The HBM PHY is a key element of the entire HBM system solution. The HBM PHY typically receives HBM DRAM row-col commands, data, parity checks, etc., from the memory controller interface via the DFI interface and passes them together to the HBM memory. HBM PHYs can be verified through simulation and post-silicon validation at the subsystem or system level. This high-speed interface PHY IP requires thorough post-silicon validation before mass commercialization.

[0003] However, currently, the test chip solutions for designing HBM PHY IP from various IP vendors are generally produced through... Figure 2 The proposed solution implements a system of HBM PHY test chips, which includes a memory controller (commercial controller), PHY, and HBMDRAM. The controller needs to send various row-col instructions to the DFI interface of the HBM PHY, including SRE / SRX instructions. While traditional HBM PHY test chip solutions can effectively verify the functionality, performance, and power consumption of the HBM PHY, they also have significant disadvantages. The integration of a commercial controller requires purchase, significantly increasing the cost of the test chip. Furthermore, the controller requires substantial logic resources; for example, a major IP vendor's controller on a certain Samsung process has over 8M standard cells. This lengthens the development cycle and increases the complexity of the test chip, significantly increasing its area and further incurring time and economic costs. Summary of the Invention

[0004] The purpose of this invention is to provide an HBM PHY chip testing method and system based on segmented FIFO control of SRE / SRX commands. This method uses a segmented FIFO to separate the SRE / SRX parts and decides whether to execute SRE / SRX based on the needs of Power State switching, PPT, frequency switching, lane repair, or entering sleep state, thereby meeting the needs of HBM3 PHY and DRAM chips for these testing scenarios.

[0005] A testing method for HBM PHY chips based on segmented FIFO control of SRE / SRX commands includes: The commands to be sent to the DFI interface of the HBM PHY are stored in the FIFO according to the timing and operation of the DRAM. Read the commands stored in the FIFO and send them to the DFI bus of the HBM PHY; Write the executed commands back into the FIFO.

[0006] Preferably, storing the commands to be sent to the DFI interface of the HBM PHY in the FIFO according to the timing and operation of the DRAM includes: The commands stored in the FIFO include: commands related to SRX, commands related to SRE, and commands unrelated to SRE and SRX.

[0007] Preferably, reading the commands stored in the FIFO and sending them to the DFI bus of the HBM PHY includes: Execute SRX-related commands; Execute commands unrelated to SRE and SRX; The counter will be incremented by 1, and the current loop will be determined by combining the counter and the register to see if it has reached its final iteration. If the current loop is not the last round, there is no need to execute SRE-related commands; the SRX / SRE instructions read from the FIFO are replaced by register configuration commands. If the current loop is the last round, then execute the SRE instruction read from the FIFO.

[0008] Preferably, before reading the command stored in the FIFO and sending it to the DFI bus of the HBM PHY, the method further includes: Configure and control the FIFO via the SPI interface; Configure the front entry of the FIFO control table to SRX-related commands; Configure the intermediate item controlling the FIFO to use the Write / Read / Active / etc command; Configure the control FIFO end entry as an SRE-related command; Configure the startup register to start the DFI controller and begin reading and writing operations on the control FIFO and DFI interface.

[0009] Preferably, the DFI controller includes: controlling the FIFO; The control FIFO stores commands to be sent to the DFI interface of the HBM PHY, including: Write, Read, MRR, MRW, PRECHARGE, REFRESH, ACTIVE, and NOP instructions.

[0010] Preferably, after writing the executed command back to the FIFO, the method further includes: Perform operations such as Power State switching, PPT, frequency switching, lane repair, or entering hibernation.

[0011] An HBM PHY chip testing system based on segmented FIFO control of SRE / SRX commands includes: The storage module is used to store commands to be sent to the DFI interface of the HBM PHY in a FIFO according to the timing and operation of the DRAM. The read module is used to read the commands stored in the FIFO and send them to the DFI bus of the HBM PHY; The transmission module is used to write the executed commands back to the FIFO.

[0012] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions. When the chip executes the computer instructions, the electronic device performs an HBM PHY chip testing method based on segmented FIFO control SRE / SRX commands.

[0013] A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform an HBM PHY chip testing method based on segmented FIFO control SRE / SRX commands.

[0014] The beneficial effects of this invention are as follows: 1. This invention, through the design of this segmented FIFO, can effectively send SRE / SRX commands without affecting the execution of other instructions; 2. In the design of MDC, in order to facilitate timing and save area in the digital backend, the FIFO depth is often not very large, and the number of operations that can be stored is also relatively small. Therefore, it is insufficient to meet the needs of scenarios such as power state switching, PPT (Retraining), frequency switching, lane repair operations, or entering sleep mode. Therefore, without a segmented FIFO design, the test scenarios and test efficiency will be greatly limited; 3. Under the premise of limited FIFO depth, the solution of this invention can flexibly adjust the SRE / SRX time during chip testing; 4. Compared with the commercial version of the controller, the solution of controlling SRE / SRX commands through a self-designed segmented FIFO can effectively save the area of ​​logic resources and greatly reduce the implementation time and investment cost of the backend and HBM PHY. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of an HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to the present invention. Figure 2 This is a schematic diagram of an existing HBM PHY test chip scheme for the present invention; Figure 3 This is a flowchart illustrating the read / write operation of the FIFO of the present invention. Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0020] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0021] Currently, most IP vendors implement HBM PHY IP test chip solutions using the following approach. This HBM PHY test chip system solution includes a memory controller (commercial controller), PHY, and HBM DRAM. The controller needs to perform the function of sending various row-col instructions to the HBM PHY's DFI interface, including sending SRE / SRX instructions to the DFI interface. While traditional HBM PHY test chip solutions can fully verify the functionality, performance, power consumption, etc., of the HBM PHY, they also have significant disadvantages. The integrated commercial controller requires purchase, significantly increasing the cost of the test chip. Furthermore, the controller requires substantial logic resources; for example, a major IP vendor's controller on a certain Samsung process has over 8M standard cells. This lengthens the development cycle and increases the complexity of the test chip, significantly increasing its area and further incurring time and economic costs.

[0022] This invention, through the design of a segmented FIFO, can effectively send SRE / SRX commands without affecting the execution of other instructions. In the design of MDC, to facilitate timing and save area in the digital backend, the FIFO depth is often not very large, and the number of operations that can be stored is also relatively small. Therefore, it is insufficient to meet the requirements of scenarios such as power state switching, PPT (Retraining), frequency switching, lane repair operations, or entering sleep mode. Therefore, without a segmented FIFO design, the test scenarios and test efficiency will be significantly limited. Under the premise of limited FIFO depth, the present invention's solution can flexibly adjust the timing of two SRE / SRX operations during chip testing. Compared with commercial controllers, the solution of controlling SRE / SRX commands through a self-designed segmented FIFO can effectively save the area of ​​logic resources and greatly reduce the implementation time and investment cost of the backend PHY.

[0023] Example 1 A test method for HBM PHY chips based on segmented FIFO control of SRE / SRX commands, referenced Figure 1 ,include: S100 stores commands to be sent to the DFI interface of the HBM PHY in the FIFO according to the timing and operation of the DRAM; S200 reads the commands stored in the FIFO and sends them to the DFI bus of the HBM PHY; S300 writes the executed commands back to the FIFO.

[0024] Based on the HBM DRAM protocol requirements, before the HBM3 PHY and DRAM chips perform power state switching, PPT (Retraining), frequency switching, lane repair operations, or enter sleep mode, the controller must send an SRE command to the HBM PHY and DRAM chips to put the chips into Self Refresh mode. Before ending the operation and sending read / write operations, an SRX command must be sent, i.e., Power Down and Self Refresh Exit. By developing a MiniDFI Controller (MDC), control of the DFI interface can also be achieved. This invention mainly solves the problem of how to handle the sending of SRE / SRX commands.

[0025] The MDC contains a CTRL FIFO, which stores commands to be sent to the HBM PHY's DFI interface, including Write, Read, MRR, MRW, PRECHARGE, REFRESH, ACTIVE, NOP, and other instructions. The order in which these commands are stored in the FIFO is related to the DRAM timing and operational requirements. When a pattern is read from the FIFO, the corresponding command is sent to the HBM PHY's DFI Bus, and the executed pattern is written back to the FIFO. This process continues until the next cycle, thus supporting long-term command transmission or stress testing of the HBM PHY and DRAM.

[0026] refer to Figure 3 Preferably, in step S100, storing the commands to be sent to the DFI interface of the HBM PHY in the FIFO according to the timing and operation of the DRAM includes: The commands stored in the FIFO include: commands related to SRX, commands related to SRE, and commands unrelated to SRE and SRX.

[0027] In this embodiment of the invention, the initial command configuration of the SPI interface includes: SRX-related commands, also considered as the Start instruction to start the DRAM; commands unrelated to SRE and SRX, i.e., Write / Read / Active / etc., also considered as Non-First / End-Command instructions; and SRE-related commands. The CTRL_FIFO.start_exe command executes SRX-related commands. The CSR command executes instructions that do not yet require SRE-related commands, so these are replaced by other commands such as MR / NOP commands. The specific commands executed can be configured using registers. The CTRL_FIFO.end_exe command executes SRE-related commands. Preferably, in step S200, reading the command stored in the FIFO and sending it to the DFI bus of the HBM PHY includes: S210 executes SRX-related commands; S220 executes commands unrelated to SRE and SRX; S230 will increment the counter by 1, and determine whether the current loop has reached its last iteration based on the counter and the register. S240, if the current loop is not the last round, then the SRE-related commands do not need to be executed, and the SRX / SRE instructions read from the FIFO are replaced by the commands configured in the registers. S250, if the current loop is the last round, execute the SRE instruction read from the FIFO.

[0028] In this embodiment of the invention, the DFI Command transmission controlled by a segmented CTRL FIFO includes the following specific process: Execute the SRX-related commands corresponding to the yellow entity in CTRL_FIFO; Execute the Write / Read / Active / etc command corresponding to the blue entity in the CTRL FIFO; After a blue entity in the CTRL FIFO completes execution, the counter EXT_LOOP_CNT is incremented by 1. Simultaneously, based on EXT_LOOP_CNT and the CTRL_FIFO_SRX_SRE_SUB_VALUE register (configured by the MCU to describe the number of loops before SRE execution), it is determined whether the current loop has reached its final iteration. If the current loop is not the final iteration, SRE-related commands do not need to be executed; instead, the SRE-related commands read from the FIFO are replaced with MR / NOP commands. If the current loop is the final iteration, the SRE instructions read from the CTRL FIFO are executed.

[0029] Preferably, S200, before reading the command stored in the FIFO and sending it to the DFI bus of the HBM PHY, further includes: Configure and control the FIFO via the SPI interface; Configure the front entry of the FIFO control table to SRX-related commands; In chip design, verification, and testing, SRX is typically associated with scan chains and DFTs to control scan test operations, including data loading, data capture, and result reading.

[0030] Configure the intermediate item controlling the FIFO to use the Write / Read / Active / etc command; Configure the control FIFO end entry as an SRE-related command; In chip design, testing, and verification, SREs are operation commands related to scan testing and DFT, primarily used to control data loading, execution, and reading in the scan chain. These commands are typically used with ATEs (Automatic Test Equipment) or EDA tools (such as Tessent, Synopsys DFT, etc.).

[0031] Configure the startup register to start the DFI controller and begin reading and writing operations on the control FIFO and DFI interface.

[0032] In this embodiment of the invention, system parameters and instructions need to be configured before executing instructions. This invention configures the CTRL FIFO via the SPI interface; the first entry of the CTRL FIFO is configured with SRX-related commands; the middle entries of the CTRL FIFO are configured with Write / Read / Active / etc.; and the last entry of the CTRL FIFO is configured with SRE-related commands.

[0033] Preferably, the DFI controller includes: a control FIFO; The commands stored in the FIFO that will be sent to the DFI interface of the HBM PHY include: Write, Read, MRR, MRW, PRECHARGE, REFRESH, ACTIVE, and NOP instructions.

[0034] FIFO (First-In, First-Out) is a data storage structure commonly used for data caching or as a medium for asynchronous data exchange. FIFO's FIFO characteristic allows for efficient buffering and exchange of data at different speeds. FIFO has registers or memory addresses for storage space. It writes and reads data sequentially, without external read / write address lines; the data address is automatically incremented by an internal read / write pointer. FIFO is primarily used to solve speed mismatches or timing asynchronies between data producers and consumers, and is widely used in digital systems such as FPGAs, processors, and communication protocols.

[0035] Preferably, in step S300, after writing the executed command back to the FIFO, the process further includes: Perform operations such as Power State switching, PPT, frequency switching, lane repair, or entering hibernation.

[0036] Power State switching refers to the process of switching between different power states to optimize device power consumption and performance. Power State typically refers to the power supply configuration and power consumption state of a device in different operating modes. Power State defines which power domains are on or off. By switching Power State, device power consumption can be controlled, thereby optimizing battery life and system performance. For example, in low-power designs, turning off unused power domains can significantly reduce static power consumption. Frequency switching refers to cell handover at different frequencies, typically occurring in wireless communication systems, especially in mobile communication networks. In HBM3, frequency switching is compatible with various versions of HBM PHY and controls power consumption. Lane Repair is a critical fault-tolerance mechanism in high-speed data transmission systems (such as DDR, PCIe, SerDes, HBM, etc.) used to detect and repair damaged or failed data lanes, ensuring reliable communication even with partial hardware failures. Its core objective is to bypass faulty lanes using software or hardware means and utilize redundant resources to restore functionality.

[0037] Example 2 An HBM PHY chip testing system based on segmented FIFO control of SRE / SRX commands includes: The storage module is used to store commands to be sent to the DFI interface of the HBM PHY in a FIFO according to the timing and operation of the DRAM. The read module is used to read the commands stored in the FIFO and send them to the DFI bus of the HBM PHY; The transmission module is used to write the executed commands back to the FIFO.

[0038] The segmented FIFO method of this invention separates the SRE / SRX portions and determines whether to execute SRE / SRX based on the needs of Power State switching, PPT, frequency switching, lane repair, or entering sleep mode. This satisfies the requirements of HBM3 PHY and DRAM chips for these test scenarios. Furthermore, this invention can also support the loop mechanism well and support long-term stress testing during silicon testing.

[0039] Example 3 An electronic device includes a chip, a processor, and a memory. The memory stores computer program code, which includes computer instructions. When the chip executes the computer instructions, the electronic device executes an HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands.

[0040] refer to Figure 4 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, memory 22, input device 23, and output device 24 are coupled together via connectors, which may include various interfaces, transmission lines, or buses, etc., and are not limited in this embodiment of the invention. It should be understood that in the various embodiments of the invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices, such as through various interfaces, transmission lines, buses, etc.

[0041] The processor 21 can be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Optionally, the processor can also be other types of processors, etc., and this embodiment of the invention is not limited thereto.

[0042] The memory 22 can be used to store computer program instructions, as well as various types of computer program code, including program code for executing the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), which is used for related instructions and data.

[0043] Input device 23 is used to input data and / or signals, and output device 24 is used to output data and / or signals. Output device 24 and input device 23 can be independent devices or an integrated device.

[0044] Example 4 A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to execute an HBM PHY chip testing method based on segmented FIFO control SRE / SRX commands.

[0045] This invention, through the design of a segmented FIFO, can effectively send SRE / SRX commands without affecting the execution of other instructions. In the design of MDC, to facilitate timing and save area in the digital backend, the FIFO depth is often not very large, and the number of operations that can be stored is also relatively small. Therefore, it is insufficient to meet the requirements of scenarios such as power state switching, PPT (Retraining), frequency switching, lane repair operations, or entering sleep mode. Therefore, without a segmented FIFO design, the test scenarios and test efficiency will be significantly limited. Under the premise of limited FIFO depth, the present invention's solution can flexibly adjust the timing of two SRE / SRX operations during chip testing. Compared with commercial controllers, the solution of controlling SRE / SRX commands through a self-designed segmented FIFO can effectively save the area of ​​logic resources and greatly reduce the implementation time and investment cost of the backend PHY.

[0046] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A testing method for HBM PHY chips based on segmented FIFO control of SRE / SRX commands, characterized in that, include: The commands to be sent to the DFI interface of the HBM PHY are stored in the FIFO according to the timing and operation of the DRAM. Read the commands stored in the FIFO and send them to the DFI bus of the HBM PHY; Write the executed commands back into the FIFO.

2. The HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to claim 1, characterized in that, The process of storing commands in the FIFO, based on DRAM timing and operation, for the DFI interface to be sent to the HBM PHY includes: The commands stored in the FIFO include: commands related to SRX, commands related to SRE, and commands unrelated to SRE and SRX.

3. The HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to claim 1, characterized in that, The process of reading commands stored in the FIFO and sending them to the DFI bus of the HBM PHY includes: Execute SRX-related commands; Execute commands unrelated to SRE and SRX; The counter will be incremented by 1, and the current loop will be determined by combining the counter and the register to see if it has reached its final iteration. If the current loop is not the last round, there is no need to execute SRE-related commands; the SRX / SRE instructions read from the FIFO are replaced by register configuration commands. If the current loop is the last round, then execute the SRE instruction read from the FIFO.

4. The HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to claim 1, characterized in that, Before reading the command stored in the FIFO and sending it to the DFI bus of the HBM PHY, the process also includes: Configure and control the FIFO via the SPI interface; Configure the front entry of the FIFO control table to SRX-related commands; Configure the intermediate item controlling the FIFO to use the Write / Read / Active / etc command; Configure the control FIFO end entry as an SRE-related command; Configure the startup register to start the DFI controller and begin reading and writing operations on the control FIFO and DFI interface.

5. The HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to claim 1, characterized in that, The DFI controller includes: controlling the FIFO; The control FIFO stores commands to be sent to the DFI interface of the HBM PHY, including: Write, Read, MRR, MRW, PRECHARGE, REFRESH, ACTIVE, and NOP instructions.

6. The HBM PHY chip testing method based on segmented FIFO control of SRE / SRX commands according to claim 1, characterized in that, After writing the executed commands back to the FIFO, the process also includes: Perform operations such as Power State switching, PPT, frequency switching, lane repair, or entering hibernation.

7. An HBM PHY chip testing system based on segmented FIFO control of SRE / SRX commands, characterized in that, include: The storage module is used to store commands to be sent to the DFI interface of the HBM PHY in a FIFO according to the timing and operation of the DRAM. The read module is used to read the commands stored in the FIFO and send them to the DFI bus of the HBM PHY; The transmission module is used to write the executed commands back to the FIFO.

8. An electronic device, characterized in that, include: A chip, a processor, and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs an HBM PHY chip testing method based on segmented FIFO control SRE / SRX commands as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor of an electronic device, cause the processor to perform an HBM PHY chip testing method based on segmented FIFO control SRE / SRX commands as described in any one of claims 1 to 6.

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