Non-continuous data transmission techniques with multiple digital interfaces

Abstract

The present disclosure relates to non-contiguous data transfer techniques with multiple digital interfaces. A data transfer controller connected to a first digital interface of a computer system receives instructions to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of aggregated transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows aggregated transactions using a subset of overhead data of the first digital interface. The data elements are written to contiguous data blocks in a buffer. An indication is provided to the peripheral device via the first digital interface that the contiguous data blocks are available for transfer from the buffer to the peripheral device via the first digital interface.

Description

Technical Field

[0001] Various aspects and embodiments of this disclosure relate to data transmission in computer systems, and more particularly to non-continuous data transmission techniques with multiple digital interfaces. Background Technology

[0002] Direct Memory Access (DMA) enables devices on a computer system to transfer data to or from system memory without occupying the CPU, freeing up the CPU to perform other tasks during the transfer. DMA can provide high throughput for data-intensive input / output transactions such as memory read / write or network communication. DMA can also be used to copy data from one memory location to another. DMA controllers can provide various parameters for controlling data transfers, such as start address, end address, and step size. The computer system can access these parameters via a communication library or driver. Attached Figure Description

[0003] Various embodiments according to this disclosure will now be described with reference to the accompanying drawings, in which:

[0004] Figure 1A This is a block diagram of an example system architecture providing a non-continuous data transmission technology with multiple digital interfaces according to one embodiment;

[0005] Figure 1B This is a block diagram of an example system architecture providing a non-continuous data transmission technology with multiple digital interfaces according to one embodiment;

[0006] Figure 2A-2B A communication protocol and corresponding communication protocol packet for a digital interface according to one embodiment are shown;

[0007] Figure 2C-2D A modified communication protocol and corresponding modified communication protocol packets for a modified digital interface according to one embodiment are shown;

[0008] Figure 3A This is a block diagram illustrating a distributed-aggregated data transmission operation with a data transmission controller and peripheral devices according to one embodiment;

[0009] Figure 3B This is a block diagram illustrating a memory-to-memory non-contiguous data transfer operation with a data transfer controller according to one embodiment;

[0010] Figure 4A This is a flowchart of an example method for providing non-continuous data transmission with multiple digital interfaces, according to one embodiment;

[0011] Figure 4BThis is a flowchart of an example method for providing non-continuous data transmission with multiple digital interfaces, according to one embodiment;

[0012] Figure 4C This is a flowchart of an example method for providing non-continuous data transmission with multiple digital interfaces, according to one embodiment;

[0013] Figure 5 An example computer system according to one embodiment is shown;

[0014] Figure 6 It is a block diagram of a computing system according to at least one embodiment, the system having two processing devices coupled to each other and multiple networks;

[0015] Figure 7 This is a block diagram of a computing system according to at least one embodiment, the system having a central processing unit (CPU) and a graphics processing unit (GPU) in a single integrated circuit; and

[0016] Figure 8 It is a block diagram of a computing system according to at least one embodiment, the system having a Tensor Core GPU. Detailed Implementation

[0017] Various aspects of this disclosure relate to non-continuous data transfer techniques with multiple digital interfaces. Computer systems typically contain a variety of devices connected to the CPU via one or more digital interfaces. For example, a memory module may be connected to the CPU via a Double Data Rate (DDR) interface, a hard disk drive may be connected via a Serial AT Attach (SATA) interface, and a network interface controller (NIC) may be connected via a Peripheral Component Interconnect High Speed ​​(PCIe) interface. Each interface may be associated with information overhead that provides error correction, destination addressing, and other functions, but at the cost of data throughput.

[0018] Devices can use DMA technology to transfer data with system memory via a connection interface. For example, a network interface card (NIC) connected via PCIe can use DMA to transfer network data to memory (or vice versa) without CPU intervention. The NIC can encapsulate data elements and their destination addresses (along with other DMA-related parameters) in a PCIe packet and send the packet to the system's memory controller (e.g., the memory management unit (MMU)) via the PCIe interface. The NIC's communication library or driver can provide a software interface to enable and coordinate these DMA transactions.

[0019] The aforementioned system may face numerous challenges when transferring data to or from non-contiguous addresses in system memory via a digital interface. These challenges include, but are not limited to: (i) the interface overhead associated with non-contiguous transfers; (ii) the operational complexity of alternative data paths for non-contiguous data transfers; and (iii) the incompatibility of alternative data paths with virtual addressing schemes. These example challenges and others will be further described below.

[0020] First, the aforementioned systems may encounter excessive interface overhead when transferring non-contiguous data elements to or from system memory. Again, taking NIC / PCIe as an example, if data elements cannot be transferred in a single transaction (e.g., when DMA step size parameters cannot address all non-contiguous data elements), the NIC may initiate a separate DMA transaction for each non-contiguous data element. The NIC can encapsulate these DMA transactions in separate PCIe packets, which can incur considerable overhead (e.g., from the transaction layer, data link layer, and physical layer) compared to the smaller number of DMA transactions and PCIe packets available for contiguous data elements. Other devices and other digital interfaces may also encounter similar informational overhead. Due to this challenge, the system may experience inefficient data transfers, consuming excessive resources (e.g., interface bandwidth, power consumption) and potentially leading to excessive latency. These inefficient data transfers may also further interfere with other devices on the system, for example, if the digital interface is a shared bus.

[0021] Secondly, the solutions to the first challenge, which involves alternative data paths for non-continuous data transfer, may present excessive operational complexity for the aforementioned systems. For example, alternative data paths could include a second device that communicates with the first device (e.g., a NIC) and system memory via an alternative digital interface, thereby reducing some of the interface overhead associated with the first challenge. However, introducing alternative data paths into the system can introduce additional complexity related to synchronization between the involved devices, as well as complexity related to software-level orchestration. For example, alternative data paths may require additional drivers and communication libraries. Due to this challenge, system developers and users may need to spend significant time and resources configuring these systems to accommodate alternative data paths.

[0022] Third, related to the second challenge, the aforementioned systems may encounter incompatibilities between alternative data paths and Shared Virtual Addressing (SVA) or other virtual addressing schemes that enable devices and CPUs to operate in the same address space. Recalling the previous NIC / PCIe example, alternative data paths operating outside the PCIe interface (e.g., addressing certain aspects of the first challenge by avoiding PCIe overhead) may be incompatible with SVA because they may not be able to transmit the Process Address Space ID (PASID), which is typically included as a prefix in PCIe packets. Due to this challenge, devices using alternative data paths may be unable to use application virtual addresses or perform DMA transactions without pinning memory pages. Similar to the second challenge, system developers and users may need to spend significant time and resources adapting to alternative data paths in an SVA environment.

[0023] Certain aspects of this disclosure address the aforementioned and other challenges by employing discontinuous data transmission techniques with multiple digital interfaces. An example system may provide one or more of the following aspects: (i) efficient discontinuous data transmission using a data transmission controller connected to the system via independent control plane and data plane digital interfaces; (ii) seamless coordination between the data transmission device and peripheral devices from a software perspective; and (iii) compatibility of the data transmission device with the virtual addressing scheme of the control plane digital interface. These aspects will be further described below.

[0024] In one embodiment, a computer system includes a data transfer controller connected to the computer system via a control plane digital interface and a data plane digital interface. The data plane digital interface enables the data transfer controller to copy non-contiguous data from system memory into a contiguous block of data without significant overhead. Therefore, peripheral devices connected to the system via a more expensive digital interface can transfer this contiguous block of data more efficiently. A similar process can be performed in reverse to move data from a peripheral device to a non-contiguous address in memory. Recalling the NIC / PCIe example, data transfer devices using low-overhead interfaces (e.g., DDR) can copy non-contiguous data to and from non-contiguous addresses in memory without incurring the same amount of overhead as a NIC via PCIe. Therefore, the NIC can read / write the contiguous block of data with fewer PCIe transactions. Accordingly, a computer system employing this technique can perform efficient data transfers with reduced overhead, which in turn reduces power consumption, latency, and bandwidth usage. These transfers can place a smaller burden on other devices (e.g., the PCIe bus) and on the system as a whole.

[0025] In one embodiment, a communication library accessible to both peripheral drivers and accelerator drivers allows for seamless coordination between data transfer devices using a control plane digital interface and peripheral devices using the same digital interface. From a software perspective, the data transfer controller can behave similarly to a peripheral device used for control purposes, where the underlying data plane digital interface is transparent. Therefore, software tools and principles associated with the control plane digital interface can be reused to control the data transfer controller. The data transfer controller and peripheral devices can be coordinated at the hardware, driver, or library level, and the communication library can present a unified interface for initiating continuous and discontinuous data transfers in software. Therefore, this technique can reduce the time and resource requirements for configuring these systems.

[0026] In one embodiment, the same digital interface as the peripheral device is used for the data transmission device in the control plane, compatible with the virtual addressing scheme of that digital interface. The control plane digital interface may have aspects related to virtual addressing (e.g., PASID data), while the data plane digital interface may allow the use of less overhead data to provide the aforementioned efficiency. Therefore, the data transmission controller can be used with the virtual addressing scheme in the same way as the peripheral device. Accordingly, computer systems employing this technology can improve compatibility with virtual addressing schemes and other virtualization environments. Furthermore, this technology can reduce the time and resource requirements for managing virtualization environments on the aforementioned systems.

[0027] Figure 1A This is a block diagram of an example system architecture 100A according to one embodiment, which provides a non-continuous data transmission technology with multiple digital interfaces. System architecture 100A (also referred to herein as the "system") includes a processor 102, a system agent 110, a memory 120, peripheral devices 130, and a data transmission controller 140. In one embodiment, system 100A may include more than Figure 1A The system may include more or fewer components. For example, system 100A may include additional processors or additional peripheral devices (e.g., as shown in reference). Figure 1B (as described above). In various embodiments, system architecture 100A may be a computer system (such as...). Figure 5 The computer system 500 in the middle may include a computer system (such as Figure 5 Computer systems 500 or may be included in computer systems (such as...) Figure 5The system architecture 100A may be a personal computer (PC), laptop computer, notebook computer, mobile phone, smartphone, tablet computer, digital assistant, rack server, router, system-on-a-chip (SoC), or similar computing device. In various embodiments, the system architecture 100A may be an acceleration device (such as a graphics processing unit (GPU), data processing unit (DPU), or similar device), may include an acceleration device (such as a graphics processing unit (GPU), data processing unit (DPU), or similar device), or may be included within an acceleration device (such as a graphics processing unit (GPU), data processing unit (DPU), or similar device).

[0028] Processor 102 and memory 120 can store and execute data and operations. Processor 102 may include one or more processor cores, or one or more discrete processor modules linked together. Memory 120 may include one or more memory modules (e.g., DRAM or SRAM modules). Memory 120 may also include process memories 124A-n, which may be virtual address spaces associated with corresponding processes executed by processor 102. The corresponding process may be, for example, an application running on a different processor core or in different threads managed by an operating system. In another example, the corresponding process may be associated with a kernel running on a GPU. Further examples and descriptions of processors and memory can be found in [reference needed]. Figure 5 supply.

[0029] System agent 110 can connect various components of system 100A to processor 102 and provide various functions for processor 102 and other components. System agent 110 may include various submodules for these and other purposes. Figure 1A The example submodules shown include cache 112, memory controller 114, root complex 116, and digital interface switch 118. In various embodiments, system agent 110 may include more or fewer submodules.

[0030] In one embodiment, system agent 110 includes submodules for memory management, such as cache 112 and memory controller 114. Cache 112 may be a cache in a single-level or multi-level cache system. For example, cache 112 may be an L1, L2, L3, or other level cache. Cache 112 or other caches may be contained in processor 102, system agent 110, or other locations in system 100A. Memory controller 114 may manage memory 120 and the data flow between memory 120, processor 102, and other components of system 100A. For example, memory controller 114 may include logic for reading, writing, and refreshing DRAM cells of memory 120. In another example, memory controller 114 may provide memory management unit (MMU) functions, such as virtual addressing.

[0031] In one embodiment, system agent 110 includes a digital interface for communicating with other components or for facilitating communication between submodules of system agent 110. Figure 1A Digital interfaces 104, 122A-122B, 132A-132B, and 142A-142B are shown, and other digital interfaces may also be included in various embodiments. Examples of digital interfaces that system agent 110 may use include DDR (and related types such as LPDDR, GDDR, etc.), PCIe, and Compute Express Link. TM (CXL), NVLink TM NVSwitch TM InfiniBand TM Thunderbolt TM Ethernet, Universal Serial Bus (USB), Serial Peripheral Interface (SPI), or similar interfaces. For the corresponding digital interface, system agent 110 may include a root complex (e.g., root complex 116), a host bridge, or similar submodule for coordinating communication between the CPU and other components on the corresponding digital interface. System agent 110 may include a digital interface switch (e.g., switch 118), a router, or similar submodule for coordinating communication between components on the corresponding digital interface. System agent 110 may include multiple root complexes, digital interface switches, or other related submodules for managing one or more digital interfaces.

[0032] Components of system 100A can be connected to system agent 110, processor 102, and / or other components via one or more digital interfaces. In one embodiment, components may use digital interfaces for control plane connectivity, such as for sending and receiving commands and signals. Components may use the same or different digital interfaces for data plane connectivity, such as for sending and receiving data in response to commands and signals on the control plane. In one embodiment, digital interfaces 122A, 132A, and 142A may correspond to control plane digital interfaces, while digital interfaces 122B, 132B, and 142B may correspond to data plane digital interfaces. In one embodiment, control plane interfaces and data plane interfaces 122A-122B are DDR interfaces, control plane interfaces and data plane interfaces 132A-132B are PCIe interfaces, and control plane interface 142A is a PCIe interface (or as referenced). Figure 2A-2D The modified PCIe interface is described above, while the data plane interface 142 is a DDR interface. The modified digital interface will refer to... Figure 2A-2B Further description.

[0033] Peripheral device 130 can provide data input / output or data processing functions for system 100A. For example, peripheral device 130 can be a network interface controller (NIC) that connects system 100A to a network (e.g., network 136). In another example, peripheral device 130 can be a storage device, such as a solid-state drive, hard disk drive, RAID controller, or similar device. In yet another example, peripheral device 130 can provide dedicated processing capabilities to complement processor 102, such as a GPU, DPU, or cryptographic processor. In various embodiments, system 100A may also include other types of peripheral devices.

[0034] In one embodiment, peripheral device 130 includes a DMA engine 134 for transferring data to or from memory 120. For example, the NIC peripheral device can directly transfer streaming data from network 136 to memory 120 (and vice versa) without the involvement of processor 102. DMA controller 134 can transfer data to memory 120 by encapsulating data in packets (or other non-packet media) compatible with the communication protocols of digital interfaces 132A-132B and providing these packets to system agent 110 (e.g., memory controller 114), where data can be forwarded to memory 120. In various embodiments, system agent 110 can extract data from packets and / or repackage data for use by digital interfaces 122A-B. Data transfer from memory 120 to peripheral device 130 can occur in reverse. DMA engine 134 can also provide or receive transfer metadata, such as source / destination addresses, length and step parameters, semaphore requests and releases, etc. Such metadata can be included along with data in digital interface packets or can be contained in separate packets. The DMA engine 134 can also provide or receive overhead data associated with the digital interfaces 132A-132B, such as packet headers, CRC values, etc.

[0035] In one embodiment, peripheral device 130 is associated with a software component, such as a driver or communication library. This software component can expose the functionality and configuration of peripheral device 130 to the operating system, applications, or other software components of system 100A. The software component can also expose the functionality and configuration of DMA controller 134, enabling other software to configure and initiate DMA transactions. In one embodiment, the software component conforms to a standardized interface (e.g., an API), allowing other software to interact with peripheral device 130 using standard technologies. In one embodiment, the software component can communicate with peripheral device 130 using control plane interface 132A.

[0036] Data transfer controller 140 provides data transfer functionality for discontinuous data and other types of irregular data that peripheral devices (or other components) may not be able to transfer efficiently. For example, DMA controller 134 may be unable to address certain types of discontinuous data with step size parameters or similar parameters, thus requiring multiple DMA transactions, each incurring overhead on digital interfaces 132A-132B. In one embodiment, data transfer controller 140 includes DMA controller 144, which may be similar in some aspects to the DMA controller 134 of peripheral device 130. Data transfer controller 140 can communicate with memory 120 and transfer / receive data from memory 120 (e.g., via root complex 116 and memory controller 114). Data transfer controller 140 can also communicate with peripheral device 130 and transfer / receive data from peripheral device 130 (e.g., via digital interface switch 118). Data transfer controller 140 can communicate with other components via control plane interface 142A, which may be a modified digital interface with lower overhead than an unmodified digital interface. For example, digital interface 142A can be a modified version of digital interface 132A-132B. The modified digital interface and the corresponding modified communication protocol will refer to... Figure 2C Further description. The data transmission controller 140 can send data to and receive data from other components via a data plane interface 142B. In one embodiment, the control plane interface 142A and the data plane interface 142B can correspond to different digital interfaces. For example, the overhead of the data plane interface 142B (e.g., a subset of the overhead) can be lower than that of the control plane interface 142A, while the control plane interface 142A enables the data transmission controller 140 to communicate directly with other components on the same digital interface, using virtual addressing and other features associated with the digital interface of the control plane interface 142A.

[0037] In one embodiment, the data transfer controller 140 and / or the DMA controller 144 may perform the following operation: collect non-contiguous data elements from memory 120 (e.g., from process memory 124A) into a contiguous data block in buffer 146 for transfer to peripheral device 130. In another embodiment, the data transfer controller 140 and / or the DMA controller 144 may perform the following operation: distribute data elements from the contiguous data block in buffer 146 to non-contiguous locations in memory 120 (e.g., process memory 124A). This contiguous data block may have been previously placed into buffer 146 by peripheral device 130 and / or the DMA controller 134. In yet another embodiment, the data transfer controller 140 and / or the DMA controller 144 may perform the operation of transferring non-contiguous data elements from one memory region (e.g., process memory 124A) to another memory region (e.g., process memory 124n). Figure 1A As indicated by the thickness (e.g., bandwidth) of interfaces 132B and 142B shown, these scattering, aggregation, and memory-to-memory operations can be performed more efficiently (e.g., with less overhead) via data plane interface 142B than via data plane interface 132B. Therefore, peripheral device 130 can offload inefficient operations to data transfer controller 140 and instead operate on contiguous blocks of data in buffer 146. In various embodiments, buffer 146 may be located in data transfer controller 140 (e.g., device cache), memory 120 (e.g., dedicated virtual memory region), or other locations within system 100A (e.g., in cache 112 of system agent 110).

[0038] In one embodiment, the data transfer controller 140 is associated with a software component (e.g., a driver or communication library). This software component can expose the functionality and configuration of the data transfer controller 140 to the operating system, applications, or other software components of system 100A. The software component can also expose the functionality and configuration of the DMA controller 144, enabling other software to configure and initiate DMA transactions. In one embodiment, the software component conforms to a standardized interface (e.g., an API), allowing other software to interact with the data transfer controller 140 using standardized techniques. In various embodiments, the peripheral device 130 and the data transfer controller 140 may share the same software component, or their respective software components may be integrated with each other. The peripheral device 130 and the data transfer controller 140 can also communicate directly with each other to exchange information about ongoing data transfers (e.g., semaphores). Therefore, the operation of the data transfer controller 140 and / or its coordination with the peripheral device 130 can be transparent to other software components (such as the operating system or applications). In one embodiment, software components can communicate with the data transfer controller 140 using a control plane interface 142A.

[0039] In one embodiment, the components of system 100A may be discrete components. For example, system agent 110 may correspond to a northbridge chip and / or southbridge chip separate from processor 102 on a motherboard, memory 120 may correspond to one or more DIMM modules, and peripheral device 130 and data transfer controller 140 may correspond to discrete PCIe cards. In one embodiment, the components of system 100A may also be integrated components. For example, system 100A may correspond to a system-on-a-chip (SoC), wherein processor 102, system agent 110, memory 120, peripheral device 130, and data transfer controller 140 are integrated on a single die within a single package or on multiple dies bonded together by bonding wires. Various embodiments may include a combination of discrete and integrated components. For example, another type of SoC may include processor 102 and system agent 110 in a single package, wherein memory 120, peripheral device 130, and data transfer controller 140 are externally connected (e.g., as chips on a printed circuit board or pluggable cards). In another example, some submodules of system agent 110 may be included in a package along with processor 102 (e.g., cache 112 and memory controller 114), while other submodules of system agent 110 may be included in an external discrete chipset (e.g., root complex 116 and digital interface switch 118).

[0040] In one embodiment, the data transfer controller 140 may be physically, architecturally, or otherwise located close to the memory 120 and / or system agent 110, which allows for additional, reduced-overhead modifications to the control plane interface 142A. In one example, the data transfer controller 140 may reside on a single die or within a single package alongside the processor 102 and / or system agent 110. This allows for modifications to the physical layer of the digital interface 142 (e.g., as referenced). Figure 2A-2B (As shown), for example, using a more efficient encoding / decoding scheme or similar method. In another example, the data transmission controller 140 may be located within the system agent 110, such as near or within the memory controller 114 (e.g., bypassing the root complex 116 and / or the digital interface switch 118). This allows for modification of the data link layer of the digital interface 142 (e.g., as shown in the reference). Figure 2A-2B (as mentioned above), such as reducing error correction or addressing overhead.

[0041] Figure 1B This is a block diagram of an example system architecture 100B according to one embodiment, which provides a non-continuous data transmission technology with multiple digital interfaces. System architecture 100B (also referred to herein as the "system") includes a processor 102, a system agent 110, a memory 120, one or more peripheral devices 150A-150n, and one or more data transmission controllers 160A-160n. In one embodiment, the number of components in system 100B may be more or less than... Figure 1B The components are shown. In various embodiments, system architecture 100B may be a computer system (e.g., Figure 5 The computer system 500 in the middle may include a computer system (e.g., Figure 5 Computer system 500) or may be included in computer system (e.g. Figure 5 In a computer system 500. For example, system 100B may be a personal computer (PC), laptop, notebook computer, mobile phone, smartphone, tablet computer, digital assistant, rack server, router, or similar computing device. In various embodiments, system architecture 100B may be an acceleration device, may include an acceleration device, or may be included in an acceleration device, such as a graphics processing unit (GPU), a data processing unit (DPU), or similar device.

[0042] Peripheral devices 150A-150n (and their respective DMA controllers 154A-154n) can be respectively referred to reference Figure 1APeripheral devices 130 (and their respective DMA controllers 134) are described. Data transfer controllers 160A-160n (and their respective DMA controllers 164A-164n and buffers 166A-166n) may correspond to data transfer controller 140 (and their respective DMA controllers 144 and buffers 146A-146n), respectively. Similarly, control plane digital interfaces and data plane digital interfaces 152A-152n may correspond to digital interfaces 132A-132B, and control plane digital interfaces and data plane digital interfaces 162A-162n may correspond to digital interfaces 142A-142B.

[0043] In one embodiment, one peripheral device 150A-150n is associated with one or more data transmission controllers 160A-160n. For example, a NIC may include one or more network interfaces, and each interface may be associated with a corresponding data transmission controller. In one embodiment, a data transmission controller in data transmission controllers 160A-160-n is associated with one or more peripheral devices 150A-150n. For example, a data transmission controller may serve a storage device array. In one embodiment, each peripheral device 150A-150n is associated with a corresponding data transmission controller in data transmission controllers 160A-n in a one-to-one relationship. In various embodiments, other combinations of peripheral devices and data transmission controllers may be used.

[0044] Figure 2A-2B A communication protocol 200A and a corresponding communication protocol packet 208A for a digital interface according to one embodiment are shown. Communication protocol 200A may correspond to... Figure 1A-1B One or more of the digital interfaces 104, 122A-122B, 132A-132B or 142A-142B.

[0045] refer to Figure 2ACommunication protocol 200A may be a layered protocol comprising one or more protocol layers 202A-202n. One of the protocol layers 202A-202n within communication protocol 200A may have a specific function and may interact with other layers (e.g., its upper and lower layers) and other aspects of the system. For example, lower layers (e.g., 202A-202B) may interact with system hardware, while upper layers (e.g., 202n) may interact with application software. One or more of the protocol layers 202A-202n may correspond to one or more layers of the Open Systems Interconnection (OSI) model. The OSI model comprises seven layers: (i) Physical Layer, (ii) Data Link Layer, (iii) Network Layer, (iv) Transport Layer, (v) Session Layer, (vi) Presentation Layer, and (vii) Application Layer. Lower layers (e.g., layers (i) and (ii)) can interact with the hardware, while upper layers (e.g., layers (vi) and (vii)) can interact with the application software. An example of a layered protocol is the PCIe protocol, which comprises three layers: (i) the physical layer, (ii) the data link layer, and (iii) the transaction layer. The Internet Protocol suite is another example of a multi-layered communication protocol.

[0046] refer to Figure 2B Communication protocol packet 208A includes data 210 and layer overhead data 212A-212n. Layer overhead 212A can correspond to layer 202A of communication protocol 200A, layer overhead 212B can correspond to layer 202B, and so on. Layer overhead can include various information such as source / destination address, parity bit, CRC value, timestamp, version number, data type, etc.

[0047] Communication protocol 200A may include Figure 2B Additional overhead data not shown. For example, overhead data in the physical layer (e.g., layer 202A) may include coding overhead, such as 2-bit overhead in 8b / 10b encoding or clock embedding / recovery overhead. Such overhead can be transparent at the packet level. Thus, in this example, layer overhead 212A may correspond to layer 202B, layer overhead 212B may correspond to layer 202C, and so on. In another example, the upper protocol layer may define acknowledgment (e.g., ACK) packets to be sent in response to data packets. Such packets may constitute the overhead of a set of packets in a communication sequence. Various other types of overhead data may be associated with communication protocol 200A.

[0048] Figure 2C-2D A modified communication protocol 200B and a corresponding modified communication protocol packet 208B for a modified digital interface according to one embodiment are shown. The modified communication protocol 200B can correspond to Figure 1A-1BThe modified communication protocol 200B may be one or more of the digital interfaces 104, 122A-122B, 132A-132B, or 142A-142B. The modified communication protocol 200B may be a modified version of the communication protocol 200A. The modified digital interface corresponding to the modified communication protocol 200B may be similar to a modified version of the digital interface corresponding to the communication protocol 200A.

[0049] refer to Figure 2C The modified communication protocol 200B includes a subset of layers 202A-202n, some of which may be missing or modified relative to layers in protocol 200A (e.g., as shown by dashed lines). Reference Figure 2D As shown, the modified communication protocol packet 208B may contain fewer layer overhead data 212A-212n associated with the missing or modified layer (e.g., as shown by dashed lines). Other types of overhead not shown in the modified communication protocol 200B may also be omitted or reduced (e.g., encoding overhead, ACK overhead).

[0050] In one embodiment, in the modified communication protocol 200B, lower protocol layers (e.g., physical layer or data link layer) are missing or modified. See reference... Figure 1A The data transmission controller may be located near or within the system agent 110 and / or memory 120, which allows for modifications to lower protocol layers. For example, the encoding scheme may be changed to a more efficient one (e.g., 128b / 130b encoding), clock signals may be separated from data signals, error correction may be reduced or removed, and so on. In another example, if the data transmission controller is placed in a point-to-point topology (e.g., directly connected to the memory controller) rather than a switched topology (e.g., indirectly connected to the memory controller and other components via a digital interface switch), addressing in the data link layer can be removed.

[0051] In one embodiment, the modified communication protocol 200B omits or modifies an intermediate or upper protocol layer. For example, an ACK or other type of response / acknowledgment may be removed from a certain layer.

[0052] In one embodiment, the upper protocol layer remains unchanged in the modified communication protocol 200B. For example, the protocol layer that interacts with drivers, communication libraries, application software, etc., can remain unchanged to provide an interface consistent with communication protocol 200A. Therefore, from a software perspective, the modified communication protocol 200B can be indistinguishable from communication protocol 200A, while providing less overhead than communication protocol 200A.

[0053] In one embodiment, the communication protocol of a digital interface may be a single-layer protocol or may not be associated with a layered architecture. For example, protocols such as USB may not define explicitly defined layers. Other protocols, such as Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver-Transmitter (UART), may define signaling and timing requirements but may not define application-layer behavior like the OSI layers (vii) or PCIe layers (iii). Therefore, a modified version of a single-layer or non-layered communication protocol may include other modifications rather than missing or modified layers. For example, clock signals, parity bits, or other aspects of the protocol may be removed if the characteristics of the data transfer controller (e.g., its location near memory on the modified interface) provide unnecessary overhead.

[0054] In one embodiment, the communication protocol of the digital interface may not be a packet-based protocol. For example, some serial protocols (such as I...) 2 S) can support streaming continuous data (e.g., audio data encoded with Pulse Code Modulation (PCM)) without discrete packet boundaries. As previously mentioned, protocol elements such as clock signals and parity bits can constitute overhead and can be removed or otherwise modified in modified versions of the protocol. More generally, various types of hierarchical packetization, non-hierarchical packetization, hierarchical non-packetization, or non-hierarchical non-packetization communication protocols and their modified versions can be used in various embodiments.

[0055] Figure 3A This is a block diagram illustrating a distributed-aggregated data transmission operation according to one embodiment, including a data transmission controller and peripheral devices. The memory 120, peripheral devices 130, and data transmission controller 140 may correspond to... Figure 1A Each of them corresponds to a specific component. For clarity, Figure 1A-1BOther components have been omitted. The data transfer controller 140 may be associated with an accelerator library or driver 312, which provides a software interface to the data transfer controller 140 for the operating system, other libraries, or application software. The peripheral device 130 may be associated with a peripheral device library or driver 314, which provides a software interface to the peripheral device 130 for the operating system, other libraries, or application software. A communication library is accessible to drivers 312 and 314 and provides a unified interface for various communication workflows involving continuous or non-continuous data. In one embodiment, therefore, driver 312 and / or data transfer controller 140 may be transparent to other software interfaced with communication library 310. In various embodiments, other driver and library structures may be used. For example, a unified driver may provide aspects of drivers 312 and 314 as well as aspects of communication library 310. Therefore, the communication library may be omitted. In another example, driver 312 may be a plug-in module or modification of driver 314. In various embodiments, communication channels 320-334 may be hardware (e.g., digital interface) and / or software (e.g., API) communication channels.

[0056] In one embodiment, the data transfer controller 140 performs a collection operation to prepare data for transmission to the peripheral device 130. Software (e.g., operating system, application) can initiate peripheral data operations via the communication library 310, such as sending data to a network or writing data to a storage device. The communication library 310 can be used by the instruction driver 312 and / or the data transfer controller 140 (e.g., via communication channels 320 and / or 324, which may correspond to digital interface 142A) to collect non-contiguous data elements 302A from process memory 124A and place them in contiguous data blocks 304 in buffer 146 (as previously described, buffer 146 may be located in memory 120 or the data transfer controller 140). The data transfer controller 140 can receive these instructions and perform these reads and writes using multiple digital interfaces and / or modified digital interfaces, as previously described (e.g., via communication channels 330 and 332, which may correspond to digital interface 142B).

[0057] After transferring non-contiguous data elements 302A-302n to data block 304, data transfer controller 140 can indicate to peripheral device 130 that the data block is ready for transfer (e.g., to a network, disk). Data transfer controller 140 can provide the indication via hardware (e.g., communication channel 328A), such as semaphores, mutexes, or other locks. Alternatively, data transfer controller 140 can provide the indication via software using drivers 312 and 314 (e.g., via communication channels 324, 328B, and 326) or using communication library 310 (e.g., via communication channels 324, 320, 322, and 326). Data transfer controller 140 can provide hardware and / or software indication via control plane interface 142A. Peripheral device 130 can then transfer data block 304 using the digital interface as described above (e.g., via communication channel 334, which may correspond to digital interfaces 132A-132B). The collection operation will refer to... Figure 4A Further description.

[0058] In one embodiment, the data transfer controller 140 performs a distribution operation to distribute data transmitted to the buffer by the peripheral device 130. Software can initiate peripheral data operations, such as receiving data from a network or reading data from storage, via communication library 310. The peripheral device 130 can transmit data to data block 304 in buffer 146 using a digital interface as described above (e.g., via communication channel 334, which may correspond to digital interfaces 132A-132B). After transmission to data block 304 is complete, the peripheral device 130 can indicate to the data transfer controller 140 that the data block is ready to be distributed to process memory 124A. The peripheral device 130 can provide the indication via hardware (e.g., communication channel 328A), such as a semaphore, mutex, or other lock. Alternatively, the peripheral device 130 can use drivers 312 and 314 (e.g., via communication channels 326, 328B, and 324) or communication library 310 (e.g., via communication channels 326, 322, 320, and 324) to provide the indication via software. The data transmission controller 140 can receive hardware and / or software instructions via the control plane interface 142A.

[0059] Upon receiving an instruction from peripheral device 130, data transfer controller 140 can read data elements 302A-302n from data block 304 and distribute them to non-contiguous addresses in process memory 124A. Data transfer controller 140 can receive these instructions and perform these reads and writes using multiple digital interfaces and / or modified digital interfaces as previously described (e.g., via communication channels 330 and 332, which may correspond to digital interface 142B). The distribution operation will refer to... Figure 4B Further description.

[0060] Figure 3B This is a block diagram illustrating a memory-to-memory non-contiguous data transfer operation using a data transfer controller according to one embodiment. The components shown can be used with... Figure 3A The corresponding components in the system are as follows. Peripheral device 130 and driver 314 may not participate in memory-to-memory operations (as shown by the dashed lines), but the same system architecture can be used for both distributed-aggregate operations and memory-to-memory operations. Therefore, from a software perspective, data transfer controller 140 can provide transparent acceleration for various data transfer operations.

[0061] In one embodiment, the data transfer controller 140 performs a memory-to-memory transfer operation to copy non-contiguous data elements 302A-302n from process memory 124A to process memory 124B. Software can initiate the memory-to-memory operation via a communication library 310. The communication library 310 can be used by the instruction driver 312 and / or the data transfer controller 140 (e.g., via communication channels 320 and / or 324, which may correspond to control plane interface 142A) to collect non-contiguous data elements 302A from process memory 124A and distribute them to non-contiguous addresses within process memory 124A. The data transfer controller 140 can receive these instructions and perform these reads and writes using multiple digital interfaces and / or modified digital interfaces as described above (e.g., via communication channels 330 and 336, which may correspond to digital interface 142B). The memory-to-memory operation will refer to... Figure 4C Further description.

[0062] Figure 4A This is a flowchart of an example method 400 according to one embodiment, used to provide non-continuous data transmission having multiple digital interfaces. Method 400 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions (such as software or firmware, e.g., running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, the example system may include a memory and a processing device coupled to the memory to perform operations comprising various blocks of method 400. Method 400 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, these instructions cause the processing device to perform operations comprising various blocks of method 400. In one embodiment, method 400 is performed by… Figure 1A-1B The system or its components (e.g., processor 102, system agent 110, memory controller 114, data transfer controller 140, etc.) are executed. In one embodiment, method 400 is performed by... Figure 5 The computing system 500 is used to execute this. In some embodiments, Figure 4A The boxes shown can be executed simultaneously, or in a different order than shown. Various embodiments may include... Figure 4A Other boxes not shown in the image, or Figure 4A The subset shown in the box.

[0063] At box 402, the processing logic of a data transfer controller connected to a first digital interface of the computer system receives instructions to prepare multiple non-contiguous data elements in the computer system's memory for transmission to a peripheral device connected to the first digital interface. This data transfer controller may be... Figure 1A The data transfer controller 140 is included. The computer system's memory may be memory 120 and / or process memory 124A-124n. Peripheral devices may be peripheral devices 130. As previously described, in various embodiments, peripheral devices may be NICs, GPUs, DPUs, data storage devices, or other types of devices. The first digital interface may be digital interfaces 132A-132B and / or 142A (e.g., a data transfer controller control plane interface). Non-contiguous data elements may be... Figure 3A Data elements 302A-302n (e.g., as shown in process memory 124A) are included. The instruction can be received from software (e.g., a driver or communication library). The instruction can be received via a first digital interface. In one embodiment, the instruction can be received via a second digital interface described below.

[0064] In one embodiment, the received instruction includes multiple non-contiguous virtual memory addresses, each addressable by the computer system's processor, data transfer controller, and peripheral devices. For example, the virtual memory addresses may be associated with a shared virtual addressing (SVA) scheme, a shared virtual memory (SVM) scheme, or a similar virtual addressing scheme. The virtual addresses may be associated with one or more process address space IDs (PASIDs) allocated and managed by the operating system. Each of the multiple non-contiguous virtual memory addresses may be associated with a corresponding data element among multiple non-contiguous data elements.

[0065] In block 404, processing logic reads multiple non-contiguous data elements from the computer system's memory via multiple aggregated transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the computer system's memory, and wherein the second digital interface allows multiple aggregated transactions using a subset of the overhead data of the first digital interface. The second digital interface may be digital interfaces 122A-122B and / or 142B (e.g., a data plane interface of the data transfer controller). The reads may be performed by the DMA controller of the data transfer controller (e.g., DMA controller 144).

[0066] In one embodiment, the first digital interface corresponds to the control plane of the data transfer controller, while the second digital interface corresponds to the data plane of the data transfer controller. The first digital interface also corresponds to the control plane and data plane of a peripheral device. The second digital interface also corresponds to the control plane and data plane of the computer system's memory. Compared to the first digital interface, the second digital interface can provide higher bandwidth, lower latency, and / or less overhead.

[0067] In one embodiment, the first digital interface is a modified Peripheral Component Interconnect High-Speed ​​(PCIe) interface. The PCIe interface may include a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer. In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer may be omitted or modified. The transaction layer may remain unchanged to provide transparency and compatibility with system software and to reduce overhead in lower layers. In various embodiments, the first digital interface may be other types of interfaces or the previously described modified interface.

[0068] In block 406, the processing logic writes multiple non-contiguous data elements into a contiguous block of data in a buffer. This buffer may be buffer 146. In one embodiment, the buffer is memory of a computer system (e.g., buffer 146 in memory 120), and writing multiple non-contiguous data elements into the contiguous block of data includes initiating one or more write transactions on a second digital interface. In one embodiment, the buffer is a cache of a data transfer controller (e.g., buffer 146 in data transfer controller 140). The write may be performed by the DMA controller of the data transfer controller.

[0069] At block 408, the processing logic provides an indication to a peripheral device via a first digital interface that a continuous block of data is available for transfer from the buffer to the peripheral device via the first digital interface. In one embodiment, providing an indication that a continuous block of data is available for transfer includes releasing a semaphore, mutex, or other lock. In another embodiment, providing an indication that a continuous block of data is available for transfer includes setting a flag or triggering an interrupt (e.g., in hardware or software). In one embodiment, the continuous block of data may be structured to allow the peripheral device to transfer the data block using a single DMA transaction. The DMA transaction may be performed by the peripheral device's DMA controller (e.g., DMA controller 134).

[0070] Figure 4BThis is a flowchart of an example method 420 according to one embodiment, used to provide non-contiguous data transfer with multiple digital interfaces. Method 420 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions (e.g., software or firmware, for example, running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, an example system may include a memory and a processing device coupled to the memory device for performing operations comprising various blocks of method 420. Method 420 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). These instructions, when executed by the processing device, cause the processing device to perform operations comprising various blocks of method 420. In one embodiment, method 420 is performed by… Figure 1A-1B The system or its components (e.g., processor 102, system agent 110, memory controller 114, data transfer controller 140, etc.) execute the method. In one embodiment, method 420 is performed by... Figure 5 The computing system 500 is used to execute this. In some embodiments, Figure 4B The various blocks shown can be executed simultaneously, or in a different order than shown. Various embodiments may include... Figure 4B Other boxes not shown in the image, or Figure 4B The subset shown in the box.

[0071] At block 422, the processing logic of a data transfer controller connected to a first digital interface of the computer system receives instructions to distribute multiple data elements of a contiguous data block to multiple non-contiguous addresses in the computer system's memory, wherein the contiguous data block is associated with a peripheral device connected to the first digital interface. The data transfer controller may be... Figure 1A The data transfer controller 140 is included. The computer system's memory may be memory 120 and / or process memory 124A-124n. Peripheral devices may be peripheral devices 130. As previously described, in various embodiments, peripheral devices may be NICs, GPUs, DPUs, data storage devices, or other types of devices. The first digital interface may be digital interfaces 132A-132B and / or 142A (e.g., a data transfer controller control plane interface). A continuous block of data may be... Figure 3A Data block 304. Data elements may be data elements 302A-302n (e.g., as shown in data frame 304). Instructions may be received from software (e.g., a driver or communication library). Instructions may be received via a first digital interface. In one embodiment, instructions may be received via a second digital interface as described below.

[0072] In one embodiment, each of the plurality of non-contiguous addresses is a virtual memory address, addressable by the computer system's processor, data transfer controller, and peripheral devices. For example, these virtual memory addresses may be associated with a shared virtual addressing (SVA) scheme, a shared virtual memory (SVM) scheme, or a similar virtual addressing scheme. These virtual addresses may be associated with one or more process address space IDs (PASIDs) allocated and managed by the operating system.

[0073] At block 424, the processing logic receives an indication from the peripheral device via a first digital interface that a write transaction using the first digital interface has been completed, where the write transaction corresponds to the transfer of a contiguous block of data from the peripheral device to a buffer. In one embodiment, receiving the indication that a write transaction has been completed includes acquiring a semaphore, mutex, or other lock. In another embodiment, receiving the indication that a write transaction has been completed includes observing a flag or triggering an interrupt (e.g., in hardware or software). In one embodiment, the contiguous block of data may be structured such that the peripheral device can transfer the block of data using a single DMA transaction. The DMA transaction may be performed by the peripheral device's DMA controller (e.g., DMA controller 134). The buffer may be buffer 146.

[0074] At block 426, the processing logic reads multiple data elements from a contiguous block of data in a buffer. In one embodiment, the buffer is a memory of the computer system (e.g., buffer 146 in memory 120), and reading multiple data elements from a contiguous block of data involves initiating one or more read transactions on a second digital interface (e.g., data plane interface 142B). In one embodiment, the buffer is a cache of a data transfer controller (e.g., buffer 146 in data transfer controller 140). The reads may be performed by a DMA controller of the data transfer controller (e.g., DMA controller 144).

[0075] At block 428, processing logic writes multiple data elements to multiple non-contiguous addresses in the computer system's memory via multiple distributed transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the computer system's memory, and wherein the second digital interface allows multiple distributed transactions using a subset of the overhead data of the first digital interface. The second digital interface may be digital interfaces 122A-122B and / or 142B (e.g., a data plane interface of the data transfer controller). The writes may be performed by the DMA controller of the data transfer controller (e.g., DMA controller 144).

[0076] In one embodiment, the first digital interface corresponds to the control plane of the data transfer controller, while the second digital interface corresponds to the data plane of the data transfer controller. The first digital interface also corresponds to the control plane and data plane of a peripheral device. The second digital interface also corresponds to the control plane and data plane of the computer system's memory. Compared to the first digital interface, the second digital interface can provide higher bandwidth, lower latency, and / or less overhead.

[0077] In one embodiment, the first digital interface is a modified Peripheral Component Interconnect High-Speed ​​(PCIe) interface. The PCIe interface may include a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer. In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer may be omitted or modified. The transaction layer may remain unchanged to provide transparency and compatibility with system software and to reduce overhead in lower layers. In various embodiments, the digital interface may be other types of interfaces described above.

[0078] Figure 4C This is a flowchart of an example method 440 according to one embodiment, used to provide non-continuous data transfer having multiple digital interfaces. Method 440 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions (e.g., software or firmware, for example, running on a general-purpose computing system or a dedicated computer), or a combination thereof. For example, an example system may include a memory and a processing device coupled to the memory to perform operations comprising the respective blocks of method 440. Method 440 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, these instructions cause the processing device to perform operations comprising the respective blocks of method 440. In one embodiment, method 440 is performed by… Figure 1A-1B The system or its components (e.g., processor 102, system agent 110, memory controller 114, data transfer controller 140, etc.) execute the method. In some embodiments, method 440 is performed by... Figure 5 The computing system 500 executes. In some embodiments, Figure 4C The boxes shown can be executed simultaneously, or in a different order than shown. Various embodiments may include... Figure 4C Other boxes not shown in the image, or Figure 4C A subset of the boxes shown.

[0079] At block 442, the processing logic of a data transfer controller connected to the first digital interface of the computer system receives instructions to transfer multiple non-contiguous data elements from a first process memory space in the computer system's memory to multiple corresponding non-contiguous addresses in a second process memory space in the computer system's memory. The data transfer controller may be... Figure 1A The data transfer controller 140 is included. The computer system's memory may be memory 120. The first process memory and the second process memory may be process memories among process memories 124A-124n. The first digital interface may be digital interfaces 132A-132B and / or 142A (e.g., a data transfer controller control plane interface). Non-contiguous data elements may be... Figure 3B Data elements 302A-302n are shown in process memory 124A. Each non-contiguous address may correspond to data elements 302A-302n as shown in process memory 124B. Instructions may be received from software (e.g., a driver or communication library). Instructions may be received via a first digital interface. In one embodiment, instructions may be received via a second digital interface described below.

[0080] In one embodiment, each of the plurality of corresponding non-contiguous addresses is a virtual memory address, addressable by the computer system's processor, data transfer controller, and peripheral devices. For example, these virtual memory addresses may be associated with a shared virtual addressing (SVA) scheme, a shared virtual memory (SVM) scheme, or a similar virtual addressing scheme. These virtual addresses may be associated with one or more process address space IDs (PASIDs) allocated and managed by the operating system. The peripheral device may be peripheral device 130. As previously described, in various embodiments, the peripheral device may be a NIC, GPU, DPU, data storage device, or other types of device.

[0081] At block 444, the processing logic reads multiple non-contiguous data elements from the first process memory space via multiple aggregated transactions on a second digital interface, wherein the second digital interface is connected to the memory of the data transfer controller and the computer system, and wherein the second digital interface allows multiple aggregated transactions using a subset of the overhead data of the first digital interface. The second digital interface may be digital interfaces 122A-122B and / or 142B (e.g., a data plane interface of the data transfer controller). The reads may be performed by the DMA controller of the data transfer controller (e.g., DMA controller 144).

[0082] In one embodiment, the first digital interface corresponds to the control plane of the data transfer controller, while the second digital interface corresponds to the data plane of the data transfer controller. The second digital interface also corresponds to the control plane and data plane of the computer system's memory. Compared to the first digital interface, the second digital interface can provide higher bandwidth, lower latency, and / or less overhead. In one embodiment, a peripheral device (e.g., NIC, GPU, DPU, etc.) is connected to the first digital interface, and the peripheral device's data transactions use the first digital interface. The first digital interface may correspond to the control plane and data plane of the peripheral device.

[0083] In one embodiment, the first digital interface is a modified Peripheral Component Interconnect High-Speed ​​(PCIe) interface. The PCIe interface may include a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer. In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer may be omitted or modified. The transaction layer may remain unchanged to provide transparency and compatibility with system software and to reduce overhead in lower layers. In various embodiments, the digital interface may be other types of interfaces described above.

[0084] At block 446, the processing logic writes multiple non-contiguous data elements to multiple corresponding non-contiguous addresses in the second process memory space via multiple distributed transactions on the second digital interface. The write can be performed by the DMA controller of the data transfer controller. In one embodiment, the processing logic provides an indication of transfer completion to software (e.g., a driver or communication library). This indication can be provided via the first digital interface and can correspond to a semaphore, flag, interrupt, or other types of indications previously described.

[0085] Figure 5 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The computer system may be a system 500 having interconnect devices and components, a system-on-a-chip (SOC), or some combination thereof. The system 500 includes a processor, which may include execution units for executing instructions. In at least one embodiment, according to this disclosure, the computer system 500 may include, but is not limited to, components such as a processor 502, which is used to execute algorithms for processing data using execution units containing logic, such as those described herein. In at least one embodiment, the computer system 500 may include a processor, such as those provided by Intel Corporation (located in Santa Clara, California). Processor series, Xeon™ XScale™ and / or StrongARM™ Core TM or NervanaTM The microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 500 can run a version of the Windows operating system provided by Microsoft Corporation, located in Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0086] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, an edge device, an Internet of Things (“IoT”) device, or any other system capable of executing one or more instructions according to at least one embodiment.

[0087] In at least one embodiment, the computer system 500 may include, but is not limited to, a processor 502, which may include, but is not limited to, one or more execution units 508 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 500 is a single-processor desktop or server system, but in another embodiment, the computer system 500 may be a multiprocessor system. In at least one embodiment, the processor 502 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computer (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 502 may be coupled to a processor bus 510, which can transmit data signals between the processor 502 and other components in the computer system 500.

[0088] In at least one embodiment, processor 502 may include, but is not limited to, a level-one (“L1”) internal cache memory (“cache”) 504. In at least one embodiment, processor 502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may be located external to processor 502. Other embodiments may also include a combination of both internal and external caches, depending on specific implementation and requirements. In at least one embodiment, register file 506 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0089] In at least one embodiment, an execution unit 508, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 502. In at least one embodiment, the processor 502 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, the execution unit 508 may include logic for processing a packaged instruction set 509. In at least one embodiment, by including the packaged instruction set 509 and associated circuitry for executing instructions in the instruction set of the general-purpose processor 502, operations used by numerous multimedia applications can be performed using packaged data in the general-purpose processor 502. In one or more embodiments, by using the full width of the processor’s data bus to perform operations on packaged data, the execution of numerous multimedia applications can be accelerated and made more efficient, eliminating the need to transfer smaller units of data across the processor’s data bus to perform one or more operations on a data element at a time.

[0090] In at least one embodiment, execution unit 508 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 500 may include, but is not limited to, memory 520. In at least one embodiment, memory 520 may be implemented as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), flash memory, or other storage devices. In at least one embodiment, memory 520 may store instructions 519 and / or data 521 represented by data signals, which may be executed by processor 502.

[0091] In at least one embodiment, the system logic chip may be coupled to a processor bus 510 and a memory 520. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 516, and the processor 502 may communicate with the MCH 516 via the processor bus 510. In at least one embodiment, the MCH 516 may provide a high-bandwidth memory path 518 to the memory 520 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 516 may direct data signals between the processor 502, the memory 520, and other components in the computer system 500, and bridge data signals between the processor bus 510, the memory 520, and system I / O 522. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 516 may be coupled to the memory 520 via the high-bandwidth memory path 518, and the graphics / video card 512 may be coupled to the MCH 516 via an Accelerated Graphics Port (“AGP”) interconnect 514.

[0092] In at least one embodiment, computer system 500 may use system I / O 522 (which is a proprietary hub interface bus) to couple MCH 516 to I / O controller hub (“ICH”) 530. In at least one embodiment, ICH 530 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 520, chipset, and processor 502. Examples may include, but are not limited to, an audio controller 529, a firmware hub (“flash BIOS”) 528, a wireless transceiver 526, a data storage device 524, a conventional I / O controller 523 including a user input and keyboard interface 525, a serial expansion port 527 (such as a universal serial bus (“USB”)), and a network controller 534 (in some embodiments, the network controller may include a data processing unit). Data storage device 524 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0093] In at least one embodiment, Figure 5 One embodiment is shown that includes interconnected hardware devices or "chips"; while in other embodiments, Figure 5An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the devices may be interconnected via proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 500 are interconnected using a compute fast link (CXL) interconnect.

[0094] Figure 6 This is a block diagram of a computing system 600 according to at least one embodiment, having two mutually coupled processing devices and multiple networks. The computing system 600 is designed with multiple integrated circuits (referred to as processing devices), each including one CPU and two GPUs, forming a powerful and flexible architecture. These processing devices are interconnected via NVLink (or other high-speed interconnects) to enable high-speed communication between them and connected via network interface cards (NICs) or data processing units (DPUs) to ensure efficient data transfer within the computing system 600. The NVLink coupling enables seamless data exchange and parallel processing, thereby improving overall computing performance. Furthermore, these processing devices are connected to multiple networks via one or more NICs or DPUs, enabling the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration makes the computing system 600 ideal for demanding applications requiring powerful processing capabilities, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring strong connectivity and scalability in various network environments. The integrated circuits of the computing system 600 may contain one or more CPUs and one or more GPUs. Figure 6 An example architecture for a multi-GPU architecture is shown in the figure.

[0095] like Figure 6 As shown, computing system 600 includes a processing device 602 employing a multi-GPU architecture. Specifically, processing device 602 includes a CPU 606, a GPU 608, and a GPU 610. CPU 606 may be coupled to GPU 608 via die-to-die (D2D) or chip-to-chip (C2C) interconnects 612 (such as a Ground Reference Signalling Interconnect (GRS interconnect)). CPU 606 may be coupled to GPU 610 via D2D or C2C interconnects 614. CPU 606 may also be coupled to GPU 608 and GPU 610 via PCIe interconnects. CPU 606 may be coupled to one or more network interface cards (NICs) or data processing units (DPUs), which in turn are coupled to one or more networks. For example, as... Figure 6As shown, CPU 606 can be coupled to a first NIC / DPU 626, which is coupled to network 630. CPU 606 is also coupled to a second NIC / DPU 628, which is coupled to network 630. NIC / DPU 626 and NIC / DPU 628 can be coupled to network 630 via Ethernet (ETH) or InfiniBand (IB) connections.

[0096] The computing system 600 also includes a processing device 604 with a multi-GPU architecture. Specifically, the processing device 604 includes a CPU 616, a GPU 618, and a GPU 620. The CPU 616 may be coupled to the GPU 618 via a D2D or C2C interconnect 622. The CPU 616 may be coupled to the GPU 620 via a D2D or C2C interconnect 624. The CPU 616 may also be coupled to the GPU 618 and GPU 620 via a PCIe interconnect. The CPU 616 may be coupled to one or more NICs or DPUs, which are coupled to one or more networks. For example, as... Figure 6 As shown, CPU 616 is coupled to a first NIC / DPU 632, which in turn is coupled to network 636. CPU 616 is also coupled to a second NIC / DPU 634, which is also coupled to network 636. NIC / DPU 632 and NIC / DPU 634 can be coupled to network 636 via Ethernet (ETH) or InfiniBand (IB).

[0097] In at least one embodiment, processing device 602 and processing device 604 can communicate with each other via NIC / DPU 638, for example, via PCIe interconnect. Processing device 602 and processing device 604 can also communicate with each other via high-bandwidth communication interconnect 640, such as NVLink interconnect or other high-speed interconnects.

[0098] In at least one embodiment, the computing system 600 is used for high-speed network communication and includes a processing unit (e.g., CPU 606, GPU 608, GPU 610, CPU 616, GPU 618, GPU 620, NIC / DPU 626, NIC / DPU 628, NIC / DPU 632, NIC / DPU 634, or NIC / DPU 638), a network interface coupled to the processing unit, and a data transmission controller coupled to the processing unit and / or the network interface. The data transmission controller may provide data transmission functionality for discontinuous data and other types of irregular data that may not be effectively transmitted by the network interface (or other peripheral components). An exemplary data transmission controller reference is provided. Figure 1AFurther description.

[0099] Figure 7 This is a block diagram of a computing system 700 according to at least one embodiment, which has a CPU 702 and a GPU 704 in a single integrated circuit. The computing system 700 can be a highly integrated design, where the CPU 702 and GPU 704 are connected on a single integrated circuit, utilizing NVLink C2C (chip-to-chip) interconnect 706 to enable fast, low-latency communication between the two processing units. This tight integration enables efficient data transfer and parallel processing between the CPU 702 and GPU 704, thereby optimizing performance for complex computing tasks. The GPU elements in the computing system 700 can be interconnected using an NVLink network, scalable to up to 256 GPU elements, creating a powerful unified processing environment ideal for large-scale AI, ML, and high-performance computing applications. The NVLink network can be a GPU architecture with a high-bandwidth communication interconnect 710. Furthermore, the computing system 700 can be designed to connect to high-speed I / O interfaces via a PCIe interconnect 708, ensuring fast data transfer to and from external devices, further enhancing the system's ability to handle data-intensive tasks and providing reliable connectivity for peripheral components. It is important to note that since the CPU 702 and GPU 704 reside on the same integrated circuit, the C2C interconnect 706 can be considered a D2D interconnect. This integrated circuit may contain CPU memory (also known as main memory) and GPU memory, which the CPU 702 and GPU 704 can access respectively via high-speed interconnects. The computing system 700 can combine the high performance of the GPU 704 with the versatility of the CPU 702. The CPU 702 can be connected via the high-bandwidth and memory-coherent C2C interconnect 706 within a single integrated circuit. The computing system 700 can support link-switching systems.

[0100] In at least one embodiment, the computing system 700 is used for high-speed network communication and includes a processing unit (e.g., CPU 702, GPU 704, NVLink network), a network interface coupled to the processing unit, and a data transmission controller coupled to the processing unit and / or the network interface. The data transmission controller can provide data transmission functionality for discontinuous data and other types of irregular data that may not be effectively transmitted via the network interface (or other peripheral components). An exemplary data transmission controller reference is provided. Figure 1A Further description.

[0101] Figure 8This is a block diagram of a computing system 800 according to at least one embodiment, the system having a tensor core GPU 808. The computing system 800 may be a DGX H100 system, a high-performance computing platform designed to meet the needs of AI, ML, and deep learning (DL) workloads. The computing system 800 may include multiple tensor core GPUs 808 (e.g., NVIDIA H100 tensor core GPUs). Each tensor core GPU 808 may be as described above. Figure 7 One of the integrated circuits described. The Tensor Core GPU 808 is optimized for AI / ML / DL applications, delivering superior performance for deep learning training, inference, and high-performance computing tasks. The Tensor Core GPUs 808 in the Computing System 800 interconnect using high-speed communication interfaces such as NVLink, enabling rapid data transfer between them, which is crucial for processing large-scale AI models and datasets with low latency. The Computing System 800 is designed for scalability, allowing for the integration of additional GPUs as needed, making it versatile for research, development, and deployment in data centers to handle production AI workloads. Each GPU is equipped with a Tensor Core (a dedicated processing unit for accelerating matrix operations), a fundamental component of AI and deep learning algorithms. These Tensor Cores enable the system to perform mixed-precision computations efficiently, balancing speed and accuracy. Considering the power consumption and heat generation of multiple Tensor Core GPUs 808, the Computing System 800 may include advanced thermal solutions and power management features to ensure safe operation while maintaining optimal performance. It is powered by a comprehensive software ecosystem, including NVIDIA's CUDA programming model, AI frameworks such as TensorFlow and PyTorch, and other HPC and AI software tools, enabling developers and researchers to fully leverage the power of the Tensor Core GPU 808 to develop their specific applications. The Computing System 800 is ideal for large-scale AI model training, real-time inference, scientific simulations, data analysis, and other computationally intensive tasks that require significant parallel processing power.

[0102] The Tensor Core GPU 808 can be coupled to multiple CPUs (such as CPU 802 and CPU 804) via a switch 806 (e.g., a CX7HCA / NIC with a PCIe switch). The Tensor Core GPU 808 can be coupled to each other via a switch 810 (e.g., an NVSwitch). Switches 806 and 810 can be coupled to a high-speed transceiver module 812. The high-speed transceiver module 812 can be an eight-way small form factor pluggable (OSFP) module. OSFP modules are high-speed transceiver modules designed for fast data communication, particularly suitable for environments requiring high bandwidth, such as data centers and high-performance computing systems. These modules support extremely high data rates, typically up to 400Gbps per module, and can be expanded to 800Gbps or higher in the future. OSFP modules connect to the system interface via a PCIe interface, enabling fast and efficient data transfer between the integrated CPU-GPU components and external networks or other connected systems. Their hot-swappable nature allows for easy insertion or removal without shutting down the system, providing flexibility and ease of maintenance, which is crucial in critical uptime environments. Furthermore, OSFP modules are designed for high density, maximizing the number of high-speed connections within limited space, such as in densely packed server racks. By adhering to the latest networking standards, OSFP modules ensure that the Compute System 800 can meet ever-increasing data demands and can be upgraded to support future network speed increases, thus contributing to the overall system performance and scalability.

[0103] In at least one embodiment, the computing system 800 can be viewed as a data network configuration with full-bandwidth in-server NVLinks. In this example, all eight tensor core GPUs 808 can simultaneously saturate eighteen NVLinks from the server to other GPUs. Bandwidth is limited by oversubscription from multiple other GPUs. In another embodiment, the data network configuration can be half-bandwidth in-server NVLinks. In this example, all eight tensor core GPUs 808 can half-subscribe to eighteen NVLinks of GPUs on other servers. Four tensor core GPUs 808 can saturate to eighteen NVLinks of GPUs on other servers. This is equivalent to full bandwidth on a full reduce using the Scalable Hierarchical Aggregation and Reduction Protocol (SHARP). The all-to-all (all-2-all) bandwidth reduction is a balance between server complexity and cost. In at least one embodiment, all eight Tensor Core GPU 808s can independently transmit data in a multi-track InfiniBand / Ethernet configuration via their respective dedicated switches (e.g., 400Gb / s HCA / NICs) using the Remote Direct Memory Access (RDMA) protocol. In this example, aggregated full-duplex 800Gbps is provided to non-NVLink network devices.

[0104] In at least one embodiment, the computing system 800 is used for high-speed network communication and includes a processing unit (e.g., CPU 802, switch 806, Tensor Core GPU 808, switch 810, high-speed transceiver module 812), a network interface coupled to the processing unit, and a data transmission controller coupled to the processing unit and / or the network interface. The data transmission controller can provide data transmission functionality for discontinuous data and other types of irregular data that may not be efficiently transmitted by the network interface (or other peripheral components). An exemplary data transmission controller is referenced. Figure 1A Further description.

[0105] All other variations are within the spirit of this disclosure. Therefore, although the disclosed technology can be modified and alternatively constructed in various ways, certain illustrative embodiments are shown in the accompanying drawings and described in detail above. However, it should be understood that this disclosure is not intended to limit it to the specific forms disclosed, but rather, its purpose is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure, as set forth in the appended claims.

[0106] In the context of describing the disclosed embodiments (especially in the context of the following claims), unless otherwise stated herein or the context explicitly states otherwise, the use of the terms “a,” “an,” “the,” and similar designations should be interpreted to cover both singular and plural forms, rather than as definitions of the terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection,” when unmodified and referring to a physical connection, should be interpreted as being partially or wholly contained in, attached to, or connected together, even in the presence of intermediates. Unless otherwise stated herein, the range of values ​​listed herein is intended only as a shorthand method to refer to each individual value falling within that range, and each individual value is incorporated into the specification as if it were separately listed herein. Unless otherwise stated or the context specifies otherwise, the use of the terms “set” (e.g., “set of items”) or “subset” should be interpreted as a non-empty set containing one or more members. Furthermore, unless otherwise stated or the context specifies otherwise, the term “subset” for a corresponding set does not necessarily mean a proper subset of the corresponding set, but a subset and a corresponding set may be equal.

[0107] Unless explicitly stated otherwise or the context clearly contradicts it, conjunctions such as “at least one of A, B, and C” or “at least one of A, B, and C” are generally understood in context to indicate that an item, term, etc., can be A, B, or C, or any non-empty subset of the set of A, B, and C. For example, in an illustrative example of a set containing three members, the conjunctions “at least one of A, B, and C” and “at least one of A, B, and C” refer to any one of the following sets: {A}, {B}, {C}, {A,B}, {A,C}, {B,C}, {A,B,C}. Therefore, such conjunctions are generally not intended to imply that some embodiments require the presence of at least one of A, at least one of B, and at least one of C. Furthermore, unless explicitly stated otherwise or the context otherwise specifies, the term “multiple” indicates a plural state (e.g., “multiple items” means multiple items). Multiple means at least two items, but more may be specified when explicitly stated or the context otherwise specifies. Furthermore, unless otherwise stated or the context clearly indicates otherwise, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0108] Unless otherwise stated herein or explicitly defined by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and implemented in the form of code (e.g., executable instructions, one or more computer programs, or one or more application programs) that are executed jointly on one or more processors via hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program containing multiple instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not contain transient signals (e.g., propagating transient electrical or electromagnetic signals), but contains non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver containing transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a collection of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions), on which executable instructions are stored that, when executed by one or more processors of a computer system (i.e., as a result of execution), cause the computer system to perform the operations described herein. In at least one embodiment, the collection of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media, and one or more individual non-transitory computer-readable storage media lack all the code, while the multiple non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors—for example, the non-transitory computer-readable storage media stores the instructions, and the main central processing unit (“CPU”) executes some of the instructions, while the graphics processing unit (“GPU”) executes others. In at least one embodiment, different components of the computer system have independent processors, and the different processors execute different subsets of instructions.

[0109] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer systems are configured with suitable hardware and / or software to support the performance of these operations. Furthermore, the computer system implemented according to at least one embodiment of this disclosure is a single device, while in another embodiment it is a distributed computer system comprising multiple devices operating in different ways, such that the distributed computer system performs the operations described herein, and such that the single device does not perform all the operations.

[0110] The use of any and all examples or exemplary language (such as "such as") provided herein is intended only to better illustrate embodiments of this disclosure and, unless otherwise required, does not constitute a limitation on the scope of this disclosure. No language in the specification should be construed as indicating that any unrequired element is necessary for the implementation of this disclosure.

[0111] All references cited in this article, including publications, patent applications and patents, are incorporated herein by reference and have the same effect as if each reference were individually and explicitly cited and listed in full in this article.

[0112] In the specification and claims, the terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms are not synonyms. Rather, in certain examples, “connected” or “coupled” may be used to indicate direct or indirect physical or electrical contact between two or more elements. “Coupled” may also indicate that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0113] Unless otherwise expressly stated, it should be understood that throughout this specification, terms such as “processing,” “calculating,” and “determining” refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or convert data represented as physical quantities (such as electronic quantities) in the registers and / or memory of the computing system into other data similarly represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0114] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can contain one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Furthermore, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein because a system can embody one or more methods, and a method can be considered a system.

[0115] This document may refer to the acquisition, collection, reception, or input of analog or digital data into a subsystem, computer system, or computer-implemented machine. Acquiring, collecting, receiving, or inputting analog and digital data can be achieved in various ways, such as by receiving data as a parameter to a function call or by calling an application programming interface (API). In some implementations, the process of acquiring, collecting, receiving, or inputting analog or digital data can be implemented by transmitting data via a serial or parallel interface. In another implementation, the process of acquiring, collecting, receiving, or inputting analog or digital data can be implemented by transmitting data from a providing entity to a receiving entity via a computer network. Furthermore, the provision, output, transmission, sending, or presentation of analog or digital data may also be mentioned. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as an input or output parameter to a function call, a parameter to an application programming interface, or a parameter to an inter-process communication mechanism.

[0116] While the above discussion provides example implementations of the described technologies, other architectures can also be used to implement the same functionality, all within the scope of this disclosure. Furthermore, although specific responsibility assignments have been defined above for ease of discussion, the allocation and division of various functions and responsibilities may differ depending on the specific circumstances.

[0117] Furthermore, although the subject matter has been described using specific language for structural features and / or methodological behavior, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, these specific features and actions are disclosed only as exemplary forms of implementing the claims.

Claims

1. A method comprising: A data transmission controller connected to a first digital interface of a computer system receives instructions for preparing multiple non-contiguous data elements in the memory of the computer system for transmission to a peripheral device connected to the first digital interface. The plurality of non-contiguous data elements are read from the memory of the computer system via a plurality of aggregated transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, and wherein the second digital interface allows the plurality of aggregated transactions to be performed using a subset of the overhead data of the first digital interface; Write the plurality of non-contiguous data elements into a contiguous data block in the buffer; and An indication is provided to the peripheral device via the first digital interface, indicating that the continuous data block is available for transfer from the buffer to the peripheral device via the first digital interface.

2. The method of claim 1, wherein: The first digital interface corresponds to the control plane of the data transmission controller, while the second digital interface corresponds to the data plane of the data transmission controller; The first digital interface corresponds to the control plane and data plane of the peripheral device; and The second digital interface corresponds to the control plane and data plane of the memory of the computer system.

3. The method of claim 2, wherein: The first digital interface is a modified high-speed PCIe interface for peripheral component interconnection; The PCIe interface includes the PCIe physical layer, the PCIe data link layer, and the PCIe transaction layer. as well as In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer is missing or modified.

4. The method of claim 1, wherein: The received instructions include multiple non-contiguous virtual memory addresses, each of which can be addressed by the computer system's processor, the data transfer controller, and the peripheral devices; as well as Each of the plurality of non-contiguous virtual memory addresses is associated with a corresponding data element among the plurality of non-contiguous data elements.

5. The method of claim 1, wherein, The buffer is one of the following: The memory of the computer system, wherein writing the plurality of non-contiguous data elements into the contiguous data block comprises: initiating one or more write transactions on the second digital interface; or The data transmission controller's cache.

6. The method of claim 1, wherein, Indications that make the continuous data blocks available for transmission include one of the following: releasing a semaphore, setting a flag, or triggering an interrupt.

7. The method of claim 1, wherein, The peripheral device is a Network Interface Controller (NIC).

8. A method comprising: A data transmission controller connected to a first digital interface of a computer system receives instructions to distribute multiple data elements of a consecutive data block to multiple non-consecutive addresses in the memory of the computer system, wherein the consecutive data block is associated with a peripheral device connected to the first digital interface. Receive an indication from the peripheral device via the first digital interface, indicating that a write transaction using the first digital interface has been completed, wherein the write transaction corresponds to transferring the consecutive data blocks from the peripheral device to the buffer; Read the plurality of data elements from the consecutive data blocks in the buffer; and The plurality of data elements are written to the plurality of non-contiguous addresses in the memory of the computer system via a plurality of distributed transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, and wherein the second digital interface allows the plurality of distributed transactions to be performed using a subset of the overhead data of the first digital interface.

9. The method of claim 8, wherein: The first digital interface corresponds to the control plane of the data transmission controller, and the second digital interface corresponds to the data plane of the data transmission controller; The first digital interface corresponds to the control plane and data plane of the peripheral device; and The second digital interface corresponds to the control plane and data plane of the memory of the computer system.

10. The method of claim 9, wherein: The first digital interface is a modified high-speed PCIe interface for peripheral component interconnection; The PCIe interface includes the PCIe physical layer, the PCIe data link layer, and the PCIe transaction layer. as well as In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer is missing or has been modified.

11. The method of claim 8, wherein, Each of the plurality of non-contiguous addresses is a virtual memory address that can be addressed by the processor of the computer system, the data transfer controller, and the peripheral devices.

12. The method of claim 8, wherein, The buffer is one of the following: The memory of the computer system, wherein reading the plurality of data elements from the contiguous data block includes initiating one or more read transactions on the second digital interface; or The data transmission controller's cache.

13. The method of claim 8, wherein, The indication that the write transaction has been completed includes one of the following: acquiring a semaphore, reading a flag, or receiving an interrupt.

14. The method of claim 8, wherein, The peripheral device is a Network Interface Controller (NIC).

15. A method comprising: A data transfer controller connected to a first digital interface of a computer system receives instructions to transfer multiple non-contiguous data elements from a first process memory space in the memory of the computer system to multiple corresponding non-contiguous addresses in a second process memory space in the memory of the computer system. Multiple non-contiguous data elements are read from the first process memory space via multiple aggregated transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, and wherein the second digital interface allows the multiple aggregated transactions to be performed using a subset of the overhead data of the first digital interface; and The multiple non-contiguous data elements are written into the multiple corresponding non-contiguous addresses in the second process memory space via multiple distributed transactions on the second digital interface.

16. The method of claim 15, wherein: The first digital interface corresponds to the control plane of the data transmission controller, and the second digital interface corresponds to the data plane of the data transmission controller; and The second digital interface corresponds to the control plane and data plane of the memory of the computer system.

17. The method of claim 16, wherein, The peripheral device is connected to the first digital interface, and the data transactions of the peripheral device use the first digital interface.

18. The method of claim 16, wherein: The first digital interface is a modified high-speed PCIe interface for peripheral component interconnection; The PCIe interface includes the PCIe physical layer, the PCIe data link layer, and the PCIe transaction layer. In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer is missing or has been modified.

19. The method of claim 15, wherein, Each of the plurality of corresponding non-contiguous addresses is a virtual memory address that can be addressed by the processor, the data transfer controller, and the peripheral devices of the computer system.

20. The method of claim 19, wherein, The peripheral device is a Network Interface Controller (NIC).

21. A system for high-speed network communication in a data center, the system comprising: One or more processing units; A memory coupled to the one or more processing units; A network interface coupled to the one or more processing units and the memory; as well as A data transmission controller, coupled to the one or more processing units, the memory, and the network interface, wherein the data transmission controller is configured to perform operations including: Instructions are received from one or more processing units via a first digital interface to prepare multiple non-contiguous data elements in the memory for transmission to the network interface, wherein the network interface is connected to the first digital interface. The plurality of non-contiguous data elements are read from the memory via a plurality of aggregated transactions on a second digital interface, wherein the second digital interface is connected to the data transfer controller and the memory, and wherein the second digital interface allows the plurality of aggregated transactions to be performed using a subset of the overhead data of the first digital interface; Write the plurality of non-contiguous data elements into a contiguous data block in the buffer; and An indication is provided to the network interface via the first digital interface, indicating that the consecutive data blocks are available for transfer from the buffer to the network interface via the first digital interface.

22. The system of claim 21, wherein: The first digital interface corresponds to the control plane of the data transmission controller, and the second digital interface corresponds to the data plane of the data transmission controller; The first digital interface corresponds to the control plane and data plane of the network interface; and The second digital interface corresponds to the control plane and data plane of the memory.

23. The system of claim 22, wherein: The first digital interface is a modified high-speed PCIe interface for peripheral component interconnection; The PCIe interface includes the PCIe physical layer, the PCIe data link layer, and the PCIe transaction layer. as well as In the modified PCIe interface, either the PCIe physical layer or the PCIe data link layer is missing or has been modified.

24. The system of claim 21, wherein: The received instructions include multiple non-contiguous virtual memory addresses, each addressable by the one or more processing units, the data transfer controller, and the network interface; and Each of the plurality of non-contiguous virtual memory addresses is associated with a corresponding data element among the plurality of non-contiguous data elements.

25. The system of claim 21, wherein, The buffer is one of the following: The memory, wherein writing the plurality of non-contiguous data elements into the contiguous data block includes initiating one or more write transactions on the second digital interface; or The data transmission controller's cache.

26. The system of claim 21, wherein, The indication that the continuous data blocks are available for transmission includes one of the following: releasing a semaphore, setting a flag, or triggering an interrupt.

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