An ethernet-based high-performance chip system and device

Abstract

The application provides an Ethernet-based high-performance chip system and device, including at least one processing unit; the processing unit includes one or more of a graphics processor, a field programmable gate array, an application-specific integrated circuit, and other domain-specific acceleration chips or other types of chips that can be used to accelerate computing; a chip internal interconnection bus connected to the at least one processing unit; an Ethernet communication module including an Ethernet controller and an Ethernet physical layer interface, a first end of the Ethernet controller being connected to the chip internal interconnection bus, and a second end being connected to the Ethernet physical interface. The application can provide greater data throughput and take advantage of the scalability of Ethernet to address the scalability limitations of traditional chip designs.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a high-performance chip system and device based on Ethernet. Background Technology

[0002] With the rapid development of artificial intelligence (AI) technology, the demand for efficient processing of massive amounts of data is growing. This has spurred a continuous increase in the demand for high-performance computing chips that can provide powerful computing capabilities. Currently, high-performance computing chips are mainly divided into several types: graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). These chips each have their own characteristics and play important roles in different application scenarios.

[0003] Traditional chip designs are primarily constrained by the PCIe bus in terms of scalability and bandwidth. While PCIe meets the data transfer requirements between chips to some extent, its bandwidth limitations become increasingly apparent as data volume and transmission rates continue to rise. This severely impacts the efficiency of data transfer between chips, thereby hindering overall system performance improvement. Summary of the Invention

[0004] In view of this, this application provides a high-performance chip system and device based on Ethernet, which aims to solve the limitations of existing high-computing-power chips in terms of scalability, bandwidth and flexibility, and improve the overall performance and flexibility of the system.

[0005] In a first aspect, embodiments of this application provide a high-performance chip system based on Ethernet, comprising:

[0006] At least one processing unit; the processing unit includes one or more of a graphics processor, a field-programmable gate array, and an application-specific integrated circuit;

[0007] An internal interconnect bus is connected to the at least one processing unit;

[0008] An Ethernet communication module, comprising an Ethernet controller and an Ethernet physical layer interface, wherein the first end of the Ethernet controller is connected to the internal interconnect bus of the chip, and the second end is connected to the Ethernet physical interface.

[0009] Optionally, the processing unit includes, but is not limited to, one or more of a graphics processing unit (GPU), a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and other domain-specific acceleration chips (DSA) or other types of chips that can be used to accelerate computing.

[0010] Optionally, a virtualization layer is also included, located between the at least one processing unit and the Ethernet communication module, for mapping physical resources in the at least one processing unit and the Ethernet communication module to virtual resources, and allocating the virtual resources according to the load.

[0011] Optionally, the Ethernet physical layer interface supports one or more of the GMII, RGMII, and SGMII physical layer interface protocols.

[0012] Optionally, the Ethernet physical layer interface is configured to send a first fast connection pulse and receive a second fast connection pulse in response to initiating auto-negotiation; the first fast connection pulse includes its own connectivity information; the second fast connection pulse includes connectivity information of the peer connected to the Ethernet physical layer interface.

[0013] Based on its own connectivity information and the connectivity information of the peer, it selects one of the GMII, RGMII, and SGMII physical layer interface protocols to establish a communication link.

[0014] Optionally, the Ethernet physical layer interface includes one or more of a first sub-Ethernet physical layer interface, a second sub-Ethernet physical layer interface, and a third sub-Ethernet physical layer interface; wherein,

[0015] The first sub-Ethernet physical layer interface supports the GMII physical layer interface protocol;

[0016] The second sub-Ethernet physical layer interface supports the RGMII physical layer interface protocol;

[0017] The third sub-Ethernet physical layer interface supports the SGMII physical layer interface protocol.

[0018] Optionally, it also includes a PCIe communication module, which includes a PCIe controller and a PCIe physical layer interface. The first end of the PCIe controller is connected to the chip's internal interconnect bus, and the second end of the PCIe controller is connected to the PCIe physical layer interface.

[0019] Optionally, it also includes an intelligent bandwidth management module, which is used to monitor the network status of the Ethernet communication module and the PCIe communication module; the network status includes one or more of bandwidth utilization, latency, and packet loss rate;

[0020] When the network status of any communication module is detected to meet the preset switching conditions, the transmission data of the communication module that meets the preset switching conditions is redirected to another communication module according to the preset switching strategy. The preset switching strategy is configured based on the priority, bandwidth utilization threshold, latency threshold and packet loss rate threshold of the transmission data.

[0021] Optionally, it also includes an Ethernet acceleration card for hardware acceleration of large packet processing, encryption / decryption, and data decompression.

[0022] Optionally, it also includes a network communication protocol stack, the network communication protocol stack comprising:

[0023] The header overhead control module reduces the header overhead of data packets by using header compression technology, simplified header format technology, and batch processing technology.

[0024] The fast path processing module determines the processing path of data packets in the protocol stack based on pre-configured rules.

[0025] Secondly, this application provides an electronic device, which includes the high-performance Ethernet-based chip system described in any of the embodiments of the first aspect above.

[0026] This application provides a high-performance chip system based on Ethernet. It includes at least one processing unit; the processing unit includes one or more of a graphics processor, a field-programmable gate array (FPGA), and an application-specific integrated circuit (ASIC); an internal interconnect bus connected to the at least one processing unit; and an Ethernet communication module including an Ethernet controller and an Ethernet physical layer interface. The first end of the Ethernet controller is connected to the internal interconnect bus, and the second end is connected to the Ethernet physical interface. Because Ethernet technology supports data transmission speeds up to 100Gbps or even higher, and Ethernet inherently possesses excellent network scalability, it can connect multiple nodes to form large clusters. By using Ethernet to replace PCIe, greater data throughput can be provided, and the scalability advantages of Ethernet can overcome the limitations of traditional chip design in terms of scalability. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a high-performance chip system architecture based on Ethernet is provided for an embodiment of this application;

[0029] Figure 2 A schematic diagram of the structure of a high-performance chip system based on Ethernet provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of another high-performance chip system based on Ethernet provided in this application embodiment;

[0031] Figure 4 This application provides a schematic diagram of an Ethernet physical layer interface structure.

[0032] Figure 5 This is a schematic diagram of a switching interface structure provided in an embodiment of this application. Detailed Implementation

[0033] As mentioned earlier, PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. On one hand, PCIe linearly expands bandwidth by increasing the number of lanes. On the other hand, PCIe's layered architecture allows operation and communication at different hardware and software levels, supporting broader scalability. However, despite these scalability features, PCIe's scalability is limited in practical applications due to physical constraints, cost considerations, and the complexity of system design. On the other hand, while PCIe's transmission rate increases with each version upgrade—for example, the latest PCIe 5.0 and PCIe 6.0 standards support transmission rates of 32GT / s and 64GT / s respectively—each version of PCIe has its maximum transmission rate limit. Furthermore, PCIe uses specific encoding methods (such as 8 / 10 encoding or 128 / 130 encoding) when transmitting data on serial lanes. While these encoding methods help the receiving device detect data transitions and restore the clock, they also reduce the actual data transmission rate. Therefore, in chip design, when it is necessary to process large amounts of data or perform high-speed data transmission, such as in high-end computing, graphics processing, big data centers, etc., the bandwidth of PCIe may not be able to meet these needs.

[0034] Research has shown that Ethernet technology has developed to support data transmission speeds of up to 100Gbps or even higher, and Ethernet inherently has good network scalability, which can connect multiple nodes to form large clusters.

[0035] In view of this, embodiments of this application provide a high-performance chip system based on Ethernet. It includes at least one processing unit; the processing unit includes one or more of a graphics processor, a field-programmable gate array (FPGA), and an application-specific integrated circuit (ASIC); an internal interconnect bus connected to the at least one processing unit; and an Ethernet communication module including an Ethernet controller and an Ethernet physical layer interface, wherein a first end of the Ethernet controller is connected to the internal interconnect bus, and a second end is connected to the Ethernet physical interface.

[0036] In this way, by replacing PCIe with Ethernet, greater data throughput can be provided, and the scalability advantages of Ethernet can be leveraged to overcome the scalability limitations of traditional chip designs.

[0037] Figure 1 This is a schematic diagram of a high-performance chip system architecture based on Ethernet, provided as an embodiment of this application. (Combined with...) Figure 1 As shown, a high-performance Ethernet-based chip system may include a switching structure 1 for data switching and transmission. The switching structure 1 connects different components or devices and includes a switching interface 11, a memory 12, a tensor control module 13, and an FMAC data path 14. The switching interface 11 connects the memory 12, the tensor control module 13, and the FMAC data path 14; the memory 12 connects the tensor control module 13 and the FMAC data path 14; and the tensor control module 13 and the FMAC data path 14 are interconnected.

[0038] The switching interface 11 can be an Ethernet communication interface, specifically including a data module 111 and a control module 112. The arrows indicate the direction of data transmission between these components. Switching interface 11 represents the interface portion connected to the switching structure. Data module 111 represents the function or path of data transmission. Control module 112 represents control signals for the switching structure or other components. Memory 12 is used to store data. In an optional embodiment, the memory 12 may include multiple data storage devices, including one or more of solid-state drives, static random access memory, and dynamic random access memory. It should be noted that the data storage device can also be other high-speed storage media, which is not limited herein.

[0039] Tensor control module 13 is used to control and process tensor-related data. FMAC data path 14 refers to the data path for floating-point multiplication operations, used to perform mathematical operations.

[0040] It should be noted that the embodiments of this application do not limit the execution entity of the Ethernet-based high-performance chip system. For example, the Ethernet-based high-performance chip system of this application can be applied to data processing devices such as terminal devices or servers. The terminal device can be a smartphone, computer, personal digital assistant (PDA), or tablet computer, etc. The server can be a standalone server, a cluster server, or a cloud server.

[0041] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their illustration to simplify the drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] See Figure 2 , Figure 2 This application provides a schematic diagram of the structure of a high-performance chip system based on Ethernet, combined with... Figure 2 As shown, the high-performance Ethernet-based chip system provided in this application embodiment includes:

[0043] At least one processing unit 21; the processing unit 21 includes one or more of a graphics processor, a field-programmable gate array, and an application-specific integrated circuit.

[0044] In this embodiment, the Graphics Processing Unit (GPU) is a highly parallelized architecture used to perform complex mathematical operations and image rendering tasks. GPUs are widely used to accelerate the training process in fields such as machine learning and deep learning. Field Programmable Gate Arrays (FPGAs) provide a flexible way to implement specific functions; users can reconfigure their logic circuits through programming to adapt to different application requirements. Application Specific Integrated Circuits (ASICs) are dedicated chips optimized for a specific task or algorithm. Compared to general-purpose processors, ASICs achieve significant improvements in energy efficiency, but they also sacrifice flexibility; once manufactured, their functionality cannot be changed.

[0045] The chip internal interconnect bus 22 is connected to at least one processing unit.

[0046] In this implementation, the chip internal interconnect bus is an internal communication channel connecting various processing units, used to transmit data and instructions between processing units.

[0047] Ethernet communication module 23, which includes Ethernet controller 231 and Ethernet physical layer interface 232. The first end of the Ethernet controller is connected to the internal interconnect bus of the chip, and the second end is connected to the Ethernet physical interface.

[0048] In this embodiment, the Ethernet controller is responsible for handling network communication protocols and the sending and receiving of data packets. The Ethernet physical layer interface provides a connection interface with the Ethernet physical medium (such as network cable, fiber optic cable, etc.) to realize the physical transmission of data.

[0049] In this embodiment, a high-performance chip system is built by replacing the traditional PCIe architecture with Ethernet. Ethernet technology has evolved to support data transmission speeds of up to 100Gbps or even higher. Compared to standard PCIe connections (such as PCIe 4.0, which offers a maximum theoretical speed of 64GB / s), Ethernet-based solutions can provide significantly greater data throughput. Furthermore, Ethernet inherently possesses excellent network scalability, allowing multiple nodes to be connected to form large clusters. This architecture makes adding new computing resources simple and quick, without worrying about physical limitations. Simultaneously, it supports more flexible topology design, allowing network layout adjustments based on actual needs.

[0050] In an optional embodiment, to further improve the bandwidth and scalability of the high-performance chip system in this application embodiment, a virtualization layer is introduced between the processing unit and the Ethernet communication module to achieve flexible resource allocation and dynamic expansion. Figure 3 This is a schematic diagram of another high-performance Ethernet-based chip system provided in an embodiment of this application. (Combined with...) Figure 3 As shown, the system also includes a virtualization layer 25, which is located between at least one processing unit and the Ethernet communication module. The virtualization layer is used to map the physical resources in the at least one processing unit and the Ethernet communication module to virtual resources and allocate virtual resources according to the load.

[0051] In this embodiment, the virtualization layer sits between the physical hardware and the upper-layer application. It abstracts the details of the physical hardware and provides the upper-layer application with a unified, virtualized view of resources. The main functions of the virtualization layer include resource abstraction, resource allocation and scheduling, and resource isolation and protection.

[0052] Specifically, resource abstraction refers to the virtualization layer abstracting physical hardware resources (such as CPU, memory, storage, and network) into virtual resources. These virtual resources can be allocated to different virtual machines or containers on demand, enabling flexible resource configuration and dynamic adjustment. Resource allocation and scheduling refers to the virtualization layer pooling physical resources into a unified resource pool. From this resource pool, resources can be allocated to different virtual machines or containers on demand, achieving flexible resource sharing and efficient utilization. In other words, the virtualization layer has dynamic resource scheduling capabilities, which can adjust resource allocation in real time according to application needs and system load. For example, when an application needs more CPU resources, the virtualization layer can automatically reclaim some CPU resources from other applications or virtual machines and allocate them to that application.

[0053] In this implementation, the virtualization layer can dynamically expand. That is, the virtualization layer supports elastic scaling, automatically increasing or decreasing the number of virtual resources based on application needs and system load. For example, when application load increases, the virtualization layer can automatically increase the number of virtual machines to meet the application's performance requirements. Additionally, the virtualization layer supports hot-swapping, allowing physical hardware resources to be dynamically added or removed while the system is running. This enables the system to flexibly expand hardware resources according to actual needs without service interruption. Furthermore, the virtualization layer is typically equipped with automated management tools that simplify resource allocation, scheduling, and management. These tools can automatically adjust resource allocation and expansion strategies based on preset policies and rules, improving system flexibility and scalability.

[0054] For example, in an AI computing cluster, multiple physical servers equipped with high-performance Ethernet-based chip systems (such as GPUs and ASICs) are deployed. These servers need to handle a large number of AI training and inference tasks, such as training deep learning models, image recognition, and natural language processing. The virtualization layer abstracts the high-performance chip resources (such as GPU computing power and memory) on each physical server into virtual resources. These virtual resources are integrated into a unified resource pool for flexible management and allocation.

[0055] Based on the workload and priority of AI tasks, the virtualization layer can dynamically adjust resource allocation. For example, when an AI training task requires more GPU computing power, the virtualization layer can automatically allocate more GPU resources from the resource pool to that task. Simultaneously, the virtualization layer can also dynamically reclaim and reallocate resources based on task execution progress and real-time load to improve the resource utilization of the entire cluster.

[0056] When the load on the AI ​​computing cluster increases, the virtualization layer can automatically start new physical servers and deploy high-performance Ethernet-based chip systems and corresponding virtualization layer components on them. This allows new virtual resources to be added to the resource pool to handle the increased load. When the load decreases, the virtualization layer can shut down some physical servers to save energy and costs.

[0057] In this embodiment, through the flexible allocation and dynamic expansion capabilities of the virtualization layer, the AI ​​computing cluster can efficiently utilize the resources of the Ethernet-based high-performance chip system, achieving flexible allocation and dynamic expansion of the Ethernet-based high-performance chip system to meet the needs of various AI tasks. At the same time, the virtualization layer can also improve the resource utilization and scalability of enterprises, and reduce operating costs.

[0058] In summary, in this embodiment, virtualization technology can be used to map multiple physical devices as virtual devices, thereby improving the scalability and flexibility of Ethernet-based high-performance chip systems.

[0059] In an optional embodiment, when data transmission is performed via an Ethernet communication module, to ensure stable and high-speed physical transmission, it is necessary to select a physical layer interface standard (e.g., GMII, RGMII, or SGMII) that is compatible with the Ethernet speed, and connect the selected interface to an external Ethernet physical layer device. Generally, to improve scalability and data transmission efficiency, the Ethernet physical layer interface typically supports one or more of the GMII, RGMII, and SGMII physical layer interface protocols.

[0060] GMII, RGMII, and SGMII are three different Ethernet physical layer interface standards, each with unique characteristics and applicable scenarios. The GMII interface provides full-duplex operation and high-speed data transmission, suitable for Gigabit Ethernet systems. It is a Gigabit Media Independent interface, primarily used for the connection between the Gigabit Ethernet MAC (Media Access Controller) and PHY (Physical Layer). RGMII is a simplified version of the GMII interface, maintaining GMII performance while reducing cost and complexity by decreasing the number of signal lines and employing dual-edge sampling technology. SGMII is a serial Gigabit Media Independent interface that converts the parallel signals of the GMII interface into serial signals for transmission, suitable for long-distance transmission or applications with limited space.

[0061] In an optional embodiment, to further improve the performance of the Ethernet-based high-performance chip system, the Ethernet physical layer interface typically also includes an auto-negotiation mechanism. This mechanism allows devices to automatically detect the interface standards and speeds supported by the other party during connection and select the optimal configuration for communication. Therefore, in response to initiating auto-negotiation, the Ethernet physical layer interface sends a first fast connection pulse and receives a second fast connection pulse; the first fast connection pulse includes its own connectivity information; the second fast connection pulse includes the connectivity information of the peer connected to the Ethernet physical layer interface; and based on its own connectivity information and the peer's connectivity information, it selects one of the GMII, RGMII, and SGMII physical layer interface protocols to establish a communication link.

[0062] In this embodiment, the Ethernet auto-negotiation function is implemented entirely by the physical layer chip design, without using dedicated data packets or incurring any higher-level protocol overhead. It relies on Fast Connection Pulses (FLPs) to transmit negotiation information. These FLP sequences encapsulate negotiation information, including supported rate capabilities, duplex capabilities, flow control capabilities, etc.

[0063] Specifically, the Ethernet physical layer interface sends a Fast Connection Pulse (FLP) containing its own connectivity information. This pulse includes the physical layer interface protocols supported by the interface, such as GMII, RGMII, and SGMII, as well as possible communication speeds and duplex modes. Simultaneously, the interface also receives Fast Connection Pulses from the peer device. This pulse contains the connectivity information of the peer device connected to the Ethernet physical layer interface, namely the physical layer interface protocols supported by the peer device, communication speeds, and duplex modes. Based on the received connectivity information from the peer device and its own connectivity information, the Ethernet physical layer interface performs a matching process and selects a physical layer interface protocol supported by both parties to establish a communication link. This selection process is based on the maximum connectivity capabilities of both parties to ensure communication compatibility and optimal performance.

[0064] In an optional embodiment, a parallel detection mechanism is introduced to ensure connection establishment even when the other end does not support auto-negotiation. With auto-negotiation enabled at one end and disabled at the other, connection establishment relies on the parallel detection function. If the auto-negotiating end detects a normal connection pulse (NLP) sent by the other end, it can determine that the other end is a 10M device. If it detects a 4B / 5B encoded idle symbol, it can determine that the other end is a 100M device. It should be noted that connections established through parallel detection typically only allow the auto-negotiating end to negotiate in half-duplex mode.

[0065] In this embodiment, the auto-negotiation mechanism of the Ethernet physical layer interface realizes automatic detection and configuration selection between devices by sending and receiving FLP, which improves the flexibility and efficiency of network connection.

[0066] In an optional embodiment, to accommodate different network requirements and hardware conditions, different Ethernet physical layer interfaces can support different protocols and standards. Therefore, Figure 4 This is a schematic diagram of an Ethernet physical layer interface structure provided in an embodiment of this application. Figure 4 As shown, the Ethernet physical layer interface 232 includes one or more of a first sub-Ethernet physical layer interface 2321, a second sub-Ethernet physical layer interface 2322, and a third sub-Ethernet physical layer interface 2323; wherein, the first sub-Ethernet physical layer interface supports the GMII physical layer interface protocol; the second sub-Ethernet physical layer interface supports the RGMII physical layer interface protocol; and the third sub-Ethernet physical layer interface supports the SGMII physical layer interface protocol.

[0067] In this embodiment, by providing multiple Ethernet physical layer interface options, the high-performance chip system can adapt to different network environments and hardware requirements. Whether a high-speed parallel interface (GMII, RGMII) or a serial interface (SGMII) is required, the system can provide corresponding support. Secondly, by supporting multiple standard physical layer interface protocols, the system is compatible with a wide range of Ethernet devices and network media on the market, improving the system's versatility and scalability.

[0068] Furthermore, selecting the appropriate physical layer interface based on the specific application scenario can reduce costs while ensuring performance. For example, the RGMII interface can be chosen when space is limited, or the SGMII interface can be chosen when long-distance transmission is required. Moreover, new physical layer interface standards may emerge as network technology advances. The system design takes into account support for multiple interfaces, facilitating future upgrades and expansions.

[0069] In another alternative embodiment, while replacing PCIe with Ethernet can solve the bandwidth and scalability issues, there is a situation where traditional chip designs coexist with high-performance Ethernet-based chip systems. In view of this, Figure 5 This is a schematic diagram of a switching interface structure provided in an embodiment of this application. (In conjunction with...) Figure 5 As shown, it also includes a PCIe communication module 24, which includes a PCIe controller 241 and a PCIe physical layer interface 242. The first end of the PCIe controller is connected to the chip's internal interconnect bus, and the second end of the PCIe controller is connected to the PCIe physical layer interface.

[0070] In this embodiment, the PCIe controller is responsible for handling data encapsulation, decoding, error detection, and correction related to the PCIe protocol. It receives data requests from upper-layer software, converts them into PCIe protocol data packets, and sends them to the target device through the PCIe physical layer interface. Simultaneously, it is also responsible for receiving response data from the target device, decoding it, and passing it to the upper-layer software.

[0071] The PCIe physical layer interface is responsible for converting digital signals output by the PCIe controller into physical signals suitable for PCIe bus transmission, and for converting received physical signals back into digital signals. It implements the transmission of the PCIe protocol at the physical layer, including functions such as signal amplification, shaping, and clock recovery.

[0072] In an optional embodiment, the system is configured with both an Ethernet communication module and a PCIe communication module, which are logically redundant. During normal operation, the system can select one path for data communication, while the other path remains in standby mode. The system has a built-in fault detection mechanism that monitors the status of the communication paths in real time. Once a fault is detected in a path (such as packet loss, excessive transmission delay, etc.), the system will immediately trigger switching logic to switch data transmission to the other standby path.

[0073] For example, during normal operation, the system selects the Ethernet communication module as the primary communication path because Ethernet has broad compatibility and low cost. However, at some point, due to network congestion or hardware failure, the transmission latency of the Ethernet communication module suddenly increases, leading to a decrease in data transmission efficiency.

[0074] At this point, the system's fault detection mechanism detects this change and immediately triggers the switching logic, switching data transmission to the PCIe communication module. Because the PCIe communication module has higher bandwidth and lower latency, the system can quickly restore normal data transmission efficiency, thereby ensuring the smooth operation of AI computing tasks.

[0075] It should be noted that, to ensure data integrity, the system attaches verification information (such as checksums and CRC codes) when transmitting data. Upon receiving the data, the receiving end uses this verification information to verify its correctness. Furthermore, when switching communication modules, the system ensures data synchronization between the two modules. This is achieved by temporarily storing data in a shared storage area before the switch and retrieving data from that area after the switch.

[0076] In this way, the Ethernet-based high-performance chip system achieves diversified communication path selection and high reliability by introducing a PCIe communication module as redundancy. Furthermore, since some devices or applications can only communicate via the PCIe communication module, the system achieves compatibility with these devices and applications by including the PCIe module. This enables the high-performance chip system to communicate with a wider variety of devices and applications, improving system flexibility and scalability.

[0077] In an optional embodiment, to enable the system to intelligently switch between the Ethernet communication module and the PCIe communication module based on the current network conditions, device status, or user configuration, an intelligent bandwidth management module is further included. The intelligent bandwidth management module is used to monitor the network conditions of the Ethernet communication module and the PCIe communication module. The network conditions include one or more of bandwidth utilization, latency, and packet loss rate. When the network conditions of any communication module are detected to meet the preset switching conditions, the transmission data of the communication module that meets the preset switching conditions is redirected to the other communication module according to the preset switching strategy. The preset switching strategy is configured based on the priority of transmission data, bandwidth utilization threshold, latency threshold, and packet loss rate threshold.

[0078] In this embodiment, the intelligent bandwidth management module is responsible for monitoring the network status of the Ethernet communication module and the PCIe communication module. These network statuses include, but are not limited to: bandwidth utilization: the proportion of currently used bandwidth to the total available bandwidth; latency: the time required for data to travel from the sending point to the receiving point; and packet loss rate: the proportion of data packets lost during data transmission out of the total number of data packets.

[0079] The intelligent bandwidth management module continuously monitors the aforementioned network status indicators of these two communication modules. This ensures that the system can understand the current network performance in real time and make the optimal communication path selection.

[0080] Specifically, the system predefines a series of switching conditions based on network condition thresholds. When the network condition of any communication module is detected to meet these preset conditions, the system will trigger a switching action. These preset conditions may include:

[0081] Bandwidth utilization threshold: For example, when the bandwidth utilization of the Ethernet communication module exceeds 80%, a switchover may be triggered.

[0082] Latency threshold: If the latency of the PCIe communication module exceeds a certain value (such as 10 milliseconds), a switchover may also be triggered.

[0083] Packet loss rate threshold: If the packet loss rate of any module is detected to be too high, a switchover may also be triggered.

[0084] In addition, the preset switching strategy also takes into account the priority of the transmitted data. For example, high-priority data (such as live video streams) may require a more stable, low-latency transmission path, while low-priority data (such as background downloads) may be less sensitive to network conditions.

[0085] When the switching conditions are met, the intelligent bandwidth management module will execute a switching action according to a preset strategy. This may involve redirecting data currently being transmitted via the Ethernet communication module to the PCIe communication module, or vice versa. This switching aims to optimize data transmission efficiency, reduce latency, lower packet loss rates, or ensure the smooth transmission of high-priority data.

[0086] For example, suppose a system is simultaneously handling two data transmission tasks: a high-priority real-time video conference (via the Ethernet communication module) and a low-priority file download (via the PCIe communication module). Initially, the Ethernet communication module has moderate bandwidth utilization, low latency, and low packet loss, making it ideal for real-time video conferencing. The PCIe communication module handles the less sensitive file download task. Due to network congestion, the bandwidth utilization of the Ethernet communication module increases sharply, and latency also begins to rise, approaching the preset switching condition. The intelligent bandwidth management module detects this change and, based on a preset strategy (considering the high priority of video conferencing), decides to switch the real-time video conferencing data transmission from the Ethernet communication module to the PCIe communication module. At this point, the PCIe communication module may have higher available bandwidth and lower latency, better meeting the needs of real-time video conferencing. After the switch, the video conferencing quality is maintained, while the file download task may be temporarily affected, but due to its low priority, this impact is acceptable.

[0087] In this way, the intelligent bandwidth management module can dynamically adjust the data transmission path to adapt to changes in network conditions, ensuring the stability and efficiency of critical data transmission.

[0088] In an optional embodiment, to further improve bandwidth, the Ethernet-based high-performance chip system also includes an Ethernet acceleration card for hardware acceleration of large packet processing, encryption / decryption, and data decompression.

[0089] In this embodiment, the Ethernet accelerator card typically functions as a network interface card (NIC), connecting to the server motherboard via a high-speed bus architecture such as PCIe. This connection method allows the Ethernet accelerator card to perform high-speed data transmission with components such as processing units and memory. The Ethernet accelerator card not only provides basic network communication functions but also enhances network communication performance through hardware acceleration technologies such as large packet processing, encryption / decryption, and decompression. While using Ethernet as the communication bus, it retains the hardware acceleration capabilities of the Ethernet accelerator card, thereby improving the network communication performance of high-performance Ethernet-based chip systems.

[0090] In an optional embodiment, the Ethernet-based high-performance chip system further includes a network communication protocol stack, which includes: a header overhead control module that reduces the header overhead of data packets by using header compression technology, simplified header format technology, and batch processing technology; and a fast path processing module that determines the processing path of data packets in the protocol stack according to pre-configured rules.

[0091] In this embodiment, to further improve the efficiency and reliability of data transmission, unnecessary header information is reduced by optimizing the packet header format. Furthermore, pre-configured rules reduce the processing time of packets within the protocol stack.

[0092] Specifically, header compression techniques such as ROHC (Robust Header Compression) are used to compress IP / UDP / TCP headers, reducing the header size of each data packet. Simplified custom header formats are designed, removing unnecessary fields and retaining only essential control information. For example, more concise proprietary protocol headers can be used. Batch processing is employed to merge multiple small data packets into a single large data packet, reducing the proportion of header overhead. For instance, GSO (Generic Segmentation Offload) technology can be used to merge multiple small TCP segments into a single large segment at the sending end.

[0093] In this embodiment, by leveraging Ethernet's support for high bandwidth, the header overhead of each data packet can be reduced, increasing the effective payload ratio of data transmission and thus improving bandwidth utilization. This also reduces the processing time for each data packet and lowers the overall transmission latency.

[0094] Pre-configured rules refer to a series of rules pre-configured in the network communication protocol stack. These rules determine the processing path of data packets based on information such as packet type, source address, and destination address. Hardware accelerators (such as hardware offload functionality in a NIC) can also be used to process specific types of data packets, reducing the CPU load. For example, TOE (TCP Offload Engine) technology can be used to offload some functions of the TCP / IP protocol stack to the NIC. Additionally, flow classification techniques can be used to divide data packets into different flows and set different processing strategies for each flow. For example, high-priority data flows can be directly forwarded through the Ethernet communication module, while low-priority data flows are processed through the PCIe communication module.

[0095] In this embodiment, by pre-configuring rules and hardware offloading, the processing time of data packets in the protocol stack is reduced, thereby improving the data transmission speed. Furthermore, in this embodiment, by combining hardware acceleration and software expansion, high bandwidth is supported, which can be increased by more than three times compared to traditional methods. It also exhibits good scalability, increasing scalability by up to ten times compared to traditional solutions.

[0096] This application also provides corresponding devices for implementing the solutions provided in this application.

[0097] The device includes a high-performance Ethernet-based chip system as described in any of the preceding embodiments.

[0098] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0099] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods of various embodiments or some parts of the embodiments of this application.

[0100] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0101] The above are merely exemplary embodiments of this application and are not intended to limit the scope of protection of this application.

Claims

1. A high-performance chip system based on Ethernet, characterized in that, include: At least one processing unit; the processing unit includes one or more of a graphics processor, a field-programmable gate array, an application-specific integrated circuit, and other domain-specific acceleration chips or other types of chips that can be used to accelerate computing; An internal interconnect bus is connected to the at least one processing unit; An Ethernet communication module, comprising an Ethernet controller and an Ethernet physical layer interface, wherein the first end of the Ethernet controller is connected to the internal interconnect bus of the chip, and the second end is connected to the Ethernet physical interface.

2. The high-performance Ethernet-based chip system according to claim 1, characterized in that, It also includes a virtualization layer, which is located between the at least one processing unit and the Ethernet communication module, for mapping physical resources in the at least one processing unit and the Ethernet communication module to virtual resources, and allocating the virtual resources according to the load.

3. The high-performance Ethernet-based chip system according to claim 1, characterized in that, The Ethernet physical layer interface supports one or more of the GMII, RGMII, and SGMII physical layer interface protocols.

4. The high-performance Ethernet-based chip system according to claim 3, characterized in that, The Ethernet physical layer interface is used to send a first fast connection pulse and receive a second fast connection pulse in response to initiating auto-negotiation; the first fast connection pulse includes its own connection capability information. The second fast connection pulse includes connectivity capability information of the peer connected to the Ethernet physical layer interface; Based on its own connectivity information and the connectivity information of the peer, it selects one of the GMII, RGMII, and SGMII physical layer interface protocols to establish a communication link.

5. The high-performance Ethernet-based chip system according to claim 3, characterized in that, The Ethernet physical layer interface includes one or more of a first sub-Ethernet physical layer interface, a second sub-Ethernet physical layer interface, and a third sub-Ethernet physical layer interface; wherein... The first sub-Ethernet physical layer interface supports the GMII physical layer interface protocol; The second sub-Ethernet physical layer interface supports the RGMII physical layer interface protocol; The third sub-Ethernet physical layer interface supports the SGMII physical layer interface protocol.

6. The high-performance Ethernet-based chip system according to claim 1, characterized in that, It also includes a PCIe communication module, which includes a PCIe controller and a PCIe physical layer interface. The first end of the PCIe controller is connected to the chip's internal interconnect bus, and the second end of the PCIe controller is connected to the PCIe physical layer interface.

7. The high-performance Ethernet-based chip system according to claim 6, characterized in that, It also includes an intelligent bandwidth management module, which is used to monitor the network status of the Ethernet communication module and the PCIe communication module; the network status includes one or more of bandwidth utilization, latency, and packet loss rate. When the network status of any communication module is detected to meet the preset switching conditions, the transmission data of the communication module that meets the preset switching conditions is redirected to another communication module according to the preset switching strategy. The preset switching strategy is configured based on the priority, bandwidth utilization threshold, latency threshold and packet loss rate threshold of the transmission data.

8. The high-performance Ethernet-based chip system according to claim 1, characterized in that, It also includes an Ethernet acceleration card, which is used to provide hardware acceleration for large data packet processing, encryption / decryption, and data decompression.

9. The high-performance Ethernet-based chip system according to claim 1, characterized in that, It also includes a network communication protocol stack, which includes: The header overhead control module reduces the header overhead of data packets by using header compression technology, simplified header format technology, and batch processing technology. The fast path processing module determines the processing path of data packets in the protocol stack based on pre-configured rules.

10. An electronic device, characterized in that, The electronic device includes the Ethernet-based high-performance chip system according to any one of claims 1-9.

Images