A signal recovery method, system, electronic device and storage medium

Abstract

Embodiments of the present application disclose a signal recovery method and system, electronic equipment and storage medium, and relate to the technical field of integrated circuit verification, which can improve verification efficiency. The method comprises: determining a plurality of scattered unit signals corresponding to a multi-bit-width signal in a netlist level based on a target signal list and a signal naming mapping table, the target signal list comprising a multi-bit-width signal to be processed, and the signal naming mapping table being used to record a mapping relationship between a hierarchical path from a register transfer level to the netlist level and a signal name; performing operation on a reset initial value of each bit-width signal at the register transfer level and a waveform initial value corresponding to the netlist level to generate a logic polarity correction sequence; and generating a debugging configuration file according to the logic polarity correction sequence, the debugging configuration file being used to instruct recovery of the plurality of scattered unit signals into the multi-bit-width signal consistent with the register transfer level logic. The present application is applicable to a scenario of netlist timing simulation debugging.

Description

Technical Field

[0001] This application relates to the field of integrated circuit verification technology, and in particular to a signal restoration method, system, electronic device and storage medium. Background Technology

[0002] In integrated circuit verification, timing simulation based on netlists is a crucial step in ensuring the correct timing of the chip. Netlists are generated by Register-Transfer Level (RTL) code synthesis, but timing optimizations during synthesis can lead to changes in signal names, adjustments to hierarchical paths, and even the insertion of units such as inverters, making it impossible for netlist signals to directly correspond to the original RTL signals.

[0003] Existing solutions optimize netlist simulation in three ways: accelerating simulation by replacing modules, unifying the pre- and post-simulation environments, and reusing RTL simulation values ​​to accelerate initialization. However, existing solutions focus on improving simulation speed and do not solve the problem of automatic mapping between netlist signals and RTL signals in netlist simulation. When simulation errors occur, it is necessary to manually identify and reconstruct the multi-bit wide signals corresponding to the RTL from the netlist. Manual recovery is time-consuming and error-prone, which seriously affects verification efficiency. Summary of the Invention

[0004] In view of this, embodiments of this application provide a signal recovery method, system, electronic device, and storage medium, which can improve verification efficiency.

[0005] In a first aspect, embodiments of this application provide a signal restoration method, comprising: determining multiple dispersed unit signals corresponding to a multi-bit-width signal in a netlist layer based on a target signal list and a signal naming mapping table, wherein the target signal list includes the multi-bit-width signal to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist layer and the signal name; performing calculations on the initial reset value of each bit-width signal at the register transfer level and the initial waveform value corresponding to it at the netlist layer to generate a logic polarity correction sequence; and generating a debug configuration file based on the logic polarity correction sequence, wherein the debug configuration file is used to instruct the multiple dispersed unit signals to be restored into a multi-bit-width signal consistent with the logic of the register transfer level.

[0006] According to a specific implementation of an embodiment of this application, determining multiple scattered unit signals corresponding to a multi-bit-width signal in the netlist hierarchy based on a target signal list and a signal naming mapping table includes: selecting a current multi-bit-width signal from the target signal list; querying the signal naming mapping table according to the hierarchical path and signal name of the current multi-bit-width signal in the register transfer level to determine the hierarchical path and scattered unit signals corresponding to the current multi-bit-width signal in the netlist hierarchy; wherein, the target signal list includes at least the hierarchical path, signal name, signal bit width, and reset initial value of the multi-bit-width signal in the register transfer level.

[0007] According to a specific implementation of this application, after determining the multiple dispersed unit signals corresponding to the multi-bit wide signal in the netlist hierarchy, the method includes: based on the hierarchical path of the netlist hierarchy and the names of the multiple dispersed unit signals, extracting the values ​​of each unit signal within a time interval comparable to the reset initial value from the waveform database generated by the netlist simulation as the waveform initial value.

[0008] According to a specific implementation of this application, the step of performing a calculation on the initial reset value of each wide signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence includes: performing an XOR operation on the initial reset value of the current multi-bit wide signal at the register transfer level and the initial waveform value; and generating a logic mapping sequence based on the calculation result; wherein each element in the logic mapping sequence is used to indicate whether the logic level of the corresponding cell signal at the netlist level is inverted relative to the original signal at the register transfer level.

[0009] According to a specific implementation of an embodiment of this application, generating a logical mapping sequence based on the operation result includes: when the XOR operation result is 0, recording a first identifier in the logical mapping sequence, the first identifier being used to indicate that the current bit-width signal has not undergone logical inversion at the netlist level; when the XOR operation result is 1, recording a second identifier in the logical mapping sequence, the second identifier being used to indicate that the current bit-width signal has undergone logical inversion at the netlist level.

[0010] According to a specific implementation of an embodiment of this application, generating a debug configuration file based on the logic polarity correction sequence includes: traversing the logic polarity correction sequence; directly writing the netlist layer cell signal path corresponding to the bit width signal into the debug configuration file according to a first identifier; and writing the netlist layer cell signal path corresponding to the bit width signal into the debug configuration file in an inverted form according to a second identifier.

[0011] According to a specific implementation of an embodiment of this application, after generating the debug configuration file, the method includes: loading the debug configuration file, recombining and displaying multiple scattered unit signals in the netlist level that are scattered and have consistent or inconsistent logic levels as multi-bit wide signal values ​​consistent with the register transfer level logic.

[0012] Secondly, embodiments of this application also provide a signal restoration system, comprising: a determining unit, configured to determine multiple dispersed unit signals corresponding to a multi-bit-width signal in a netlist layer based on a target signal list and a signal naming mapping table, wherein the target signal list includes the multi-bit-width signal to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist layer and the signal name; a calculation unit, configured to perform calculations on the reset initial value of each bit-width signal at the register transfer level and the corresponding waveform initial value at the netlist layer to generate a logic polarity correction sequence; and a generating unit, configured to generate a debugging configuration file based on the logic polarity correction sequence, wherein the debugging configuration file is used to instruct the multiple dispersed unit signals to be restored into a multi-bit-width signal consistent with the logic of the register transfer level.

[0013] According to a specific implementation of an embodiment of this application, the determining unit includes: a selection module, configured to select a current multi-bit-width signal from the target signal list; and a determining module, configured to query the signal naming mapping table based on the hierarchical path and signal name of the current multi-bit-width signal at the register transfer level, to determine the hierarchical path and scattered unit signals corresponding to the current multi-bit-width signal at the netlist level; wherein the target signal list includes at least the hierarchical path, signal name, signal bit width, and reset initial value of the multi-bit-width signal at the register transfer level.

[0014] According to a specific implementation of an embodiment of this application, the system is used to: extract the values ​​of each unit signal within a time interval comparable to the reset initial value from the waveform database generated by the netlist simulation, based on the hierarchical path of the netlist level and multiple dispersed unit signal names, as the waveform initial value.

[0015] According to a specific implementation of an embodiment of this application, the operation unit includes: an XOR operation module, used to perform an XOR operation on the initial reset value and the initial waveform value of the current multi-bit wide signal at the register transfer level; and a generation module, used to generate a logical mapping sequence based on the operation result; wherein each element in the logical mapping sequence is used to indicate whether the logic level of the corresponding cell signal in the netlist level is inverted relative to the original signal at the register transfer level.

[0016] According to a specific implementation of an embodiment of this application, the generation module includes: a first recording submodule, configured to record a first identifier in the logical mapping sequence when the XOR operation result is 0, wherein the first identifier is used to indicate that the current bit-width signal has not undergone logical inversion at the netlist level; and a second recording submodule, configured to record a second identifier in the logical mapping sequence when the XOR operation result is 1, wherein the second identifier is used to indicate that the current bit-width signal has undergone logical inversion at the netlist level.

[0017] According to a specific implementation of an embodiment of this application, the generation unit includes: a traversal module for traversing the logic polarity correction sequence; a first writing module for directly writing the netlist hierarchical unit signal path corresponding to the bit width signal into the debug configuration file according to a first identifier; and a second writing module for writing the netlist hierarchical unit signal path corresponding to the bit width signal into the debug configuration file in an inverted form according to a second identifier.

[0018] According to a specific implementation of an embodiment of this application, the system is further configured to: load the debug configuration file, reassemble and display multiple scattered unit signals in the netlist level that are dispersed and have consistent or inconsistent logic levels as multi-bit wide signal values ​​consistent with the register transfer level logic.

[0019] Thirdly, embodiments of this application also provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the signal restoration method provided in any embodiment of this application.

[0020] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the signal restoration method provided in any embodiment of this application.

[0021] The signal recovery method, system, electronic device, and storage medium provided in this application determine multiple dispersed unit signals corresponding to multi-bit-width signals in the netlist level by using a target signal list and a signal naming mapping table. The target signal list includes the multi-bit-width signals to be processed, and the signal naming mapping table records the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal names. This eliminates the need for tedious and error-prone manual signal tracing and piecing together, and automates and quantifies signal positioning, laying a reliable foundation for subsequent processes. Secondly, by calculating the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level, a logic polarity correction sequence is generated. This automatically and accurately identifies and quantifies logic inversion problems caused by comprehensive optimization, solving the core pain point of misleading debugging direction due to inconsistent logic polarity during verification, and ensuring the correctness and reliability of data analysis. Finally, based on the logic polarity correction sequence, a debug configuration file is generated. This configuration file is used to instruct the restoration of multiple scattered unit signals into multi-bit wide signals consistent with the register transfer level logic. It can convert internal correction data into instructions executable by the debug tool, enabling the correct display of the recombined signal values ​​in the debug environment. This avoids time-consuming and repetitive manual operations, allowing for further focus on higher-level design logic analysis and problem root cause localization, thereby accelerating the debug process and significantly improving the verification efficiency and quality of netlist simulation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic flowchart of the signal recovery method provided in the embodiments of this application; Figure 2 A schematic diagram of the distributed unit signals before and after synthesis, provided for embodiments of this application; Figure 3 This is a schematic diagram illustrating the specific process of signal mapping provided in the embodiments of this application; Figure 4 A schematic diagram of a signal recovery system provided for an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0026] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0027] Firstly, embodiments of this application provide a signal recovery method that can improve verification efficiency.

[0028] like Figure 1 As shown, an embodiment of this application provides a signal recovery method, including: S11. Based on the target signal list and the signal naming mapping table, determine the multiple scattered unit signals corresponding to the multi-bit wide signal in the netlist layer. The target signal list includes the multi-bit wide signal to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal name. In the process of simulating and debugging integrated circuit netlists, the signal location problem is usually based on the signal defined in the RTL code. However, after the design is processed by logic synthesis tools, the original RTL hierarchical structure is flattened or optimized, and the generated gate-level netlist no longer retains the intuitive multi-bit-width signal form. For example, a signal that is logically unified in RTL, such as a 32-bit bus, will be decomposed into multiple scattered unit signals with a bit width of 1 in the netlist hierarchy, and the signal names and hierarchical paths will also change due to optimization.

[0029] Therefore, in the actual netlist simulation and debugging process, locating and analyzing the physical composition of RTL signals in the netlist becomes the first step. To achieve this goal, in some examples, two key inputs need to be prepared: one is the target signal list, and the other is the signal naming mapping table generated by the back-end synthesis process. The target signal list clearly lists the original attributes of the multi-bit wide signals to be restored at the RTL level; the signal naming mapping table records the correspondence between signal names and paths from the RTL level to the netlist level, and is a key bridge connecting the two abstract levels.

[0030] Based on the aforementioned target signal list and signal naming mapping table, the debugging system or script automatically resolves a multi-bit wide RTL signal into multiple distributed unit signals corresponding to it at the netlist level by querying the mapping table. Specifically, the system uses the path and name of the RTL signal as an index to search the mapping table, thereby accurately identifying the physical unit corresponding to each bit of the signal in the netlist. This step maps the abstract signal identifier of RTL to a series of specific physical nodes in the netlist that can be directly identified and accessed by simulation tools, laying a solid foundation for subsequent signal value extraction and logic reconstruction.

[0031] S12. Perform calculations on the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence. After successfully mapping the multi-bit wide RTL signals to the distributed cell signals at the netlist level, the debugging process faces another core challenge: the inconsistency of logic polarity. Specifically, in netlist simulation, synthesis tools insert logic units such as inverters to optimize timing and area, which can cause the actual logic values ​​of the located cell signals to have opposite polarities to the original RTL level definition. For example... Figure 2 For a schematic diagram of the distributed cell signals before and after synthesis provided in the embodiments of this application, please refer to [link / reference]. Figure 2 At the RTL level, the logic of a cell signal is directly expressed as C=A&B. The code and logic diagram are completely consistent with the expected behavior. However, after optimization by synthesis tools, although the final logic function remains theoretically unchanged, the internal logic structure changes. The logic equation is transformed into C'=~(~(A&B)), introducing two stages of inverters. This causes the logic value of the intermediate signal C in the netlist to be completely opposite in phase to the original signal C at the RTL level. Although the final output value can still be consistent with the RTL expectation after two stages of inversion, this structural change makes it easy to misunderstand and misjudge the debugging process, or even cover up the real design defects, if the C' signal is observed directly during netlist simulation and debugging.

[0032] Therefore, to address this critical issue, in some cases, a logical automatic correction mechanism can be introduced to obtain a corresponding correction sequence based on each unit signal as defined above. Specifically, firstly, the initial reset value defined by the design at the RTL level for each unit signal is obtained. Simultaneously, the initial waveform value of the unit signal after the reset operation is extracted from the acquired netlist simulation waveform. This initial reset value represents the correct logical state that the target multi-bit wide signal to be restored should be in after reset. Subsequently, the theoretical initial reset value of the unit signal at the RTL level is XORed with the actual initial waveform value from the netlist. By traversing all bit widths of the target multi-bit wide signal and performing XOR operations, the system ultimately generates a logical polarity correction sequence of equal length to the signal bit width, thus providing an accurate correction basis for finally restoring a multi-bit wide signal that is completely consistent with the RTL design intent.

[0033] S13. Generate a debugging configuration file according to the logic polarity correction sequence. The debugging configuration file is used to instruct the restoration of multiple scattered unit signals into multi-bit wide signals consistent with the register transfer level logic.

[0034] After generating the logic polarity correction sequence, since the sequence itself is only a set of data identifying logic polarity states, it cannot be directly recognized and applied by waveform debugging tools. Therefore, it is necessary to convert the automated analysis results into specific, executable instructions. In some examples, the system can automatically generate a specific debugging configuration file based on the obtained logic polarity correction sequence to guide the tool to correctly reassemble the scattered and inconsistent logic polarity unit signals into a configuration consistent with the RTL design intent. Figure 1 The resulting multi-bit wide signal, in which, in the Verdi tool of the automated debugging system, the debug configuration file is usually a run command (RC) file.

[0035] Specifically, the debugging configuration file generation process follows preset restoration rules. The script iterates through each element in the correction sequence. For bits marked as not requiring inversion, the configuration file directly writes them to the corresponding netlist-level cell signal path; for bits marked as requiring inversion, the configuration file writes them to the path using an inverted syntax. Ultimately, the debugging configuration file defines a new signal alias, combining a series of scattered, polarity-corrected netlist nodes into a logically correct multi-bit wide signal. After loading the debugging configuration file in the debugging environment, the debugging tool dynamically restores and displays the scattered cell signals as a unified multi-bit wide signal value consistent with the RTL-level logic, according to the instructions in the file, in the waveform window or code window.

[0036] Viewing uniform, multi-bit wide signal values ​​consistent with RTL hierarchical logic in the waveform or code window allows for intuitive observation of the restored signals in the netlist simulation, much like viewing RTL simulation waveforms. This enables the debugging focus to be entirely on the logic analysis of the circuit function, rather than the tedious manual reassembly and polarity verification of the underlying signals, thus improving verification efficiency.

[0037] The signal recovery method provided in this application determines multiple dispersed unit signals corresponding to multi-bit-width signals in the netlist level based on a target signal list and a signal naming mapping table. The target signal list includes the multi-bit-width signals to be processed, and the signal naming mapping table records the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal names. This eliminates the need for tedious and error-prone manual signal tracing and piecing together, automating and accurately locating signals and laying a reliable foundation for subsequent processes. Secondly, by calculating the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level, a logic polarity correction sequence is generated. This automatically and accurately identifies and quantifies logic inversion problems caused by comprehensive optimization, solving the core pain point of misleading debugging direction due to inconsistent logic polarity during verification, and ensuring the correctness and reliability of data analysis. Finally, based on the logic polarity correction sequence, a debug configuration file is generated. This configuration file is used to instruct the restoration of multiple scattered unit signals into multi-bit wide signals consistent with the register transfer level logic. It can convert internal correction data into instructions executable by the debug tool, enabling the correct display of the recombined signal values ​​in the debug environment. This avoids time-consuming and repetitive manual operations, allowing for further focus on higher-level design logic analysis and problem root cause localization, thereby accelerating the debug process and significantly improving the verification efficiency and quality of netlist simulation.

[0038] The primary obstacle to netlist simulation and debugging lies in the fact that multi-bit-width signals, which are logically unified in RTL, are no longer a directly observable whole in the netlist, but rather a set of disassembled, renamed, and scattered cell signals. Therefore, identifying the multiple scattered cell signals corresponding to the multi-bit-width signals in the netlist hierarchy is a prerequisite for sorting out the multi-bit-width signals from the chaotic netlist and performing any meaningful analysis.

[0039] In some embodiments, determining the multiple scattered unit signals corresponding to a multi-bit-width signal in the netlist hierarchy based on a target signal list and a signal naming mapping table includes: selecting a current multi-bit-width signal from the target signal list; querying the signal naming mapping table according to the hierarchical path and signal name of the current multi-bit-width signal at the register transfer level to determine the hierarchical path and scattered unit signals corresponding to the current multi-bit-width signal in the netlist hierarchy; wherein, the target signal list includes at least the hierarchical path, signal name, signal bit width, and reset initial value of the multi-bit-width signal at the register transfer level.

[0040] Figure 3 For a detailed flowchart of signal restoration provided in this application embodiment, please refer to [link / reference]. Figure 3 To achieve a precise correspondence between the register-transfer level behavior model and the gate-level netlist structure, the system works in conjunction with a predefined list of target signals and a signal naming mapping table generated by the synthesis tool.

[0041] Specifically, since the target signal list records in detail the original attributes of the multi-bit wide signal to be processed at the RTL level, including the complete hierarchical path, signal name, signal bit width, and initial reset value, a current multi-bit wide signal is first selected from the target signal list as the processing object. Then, the RTL hierarchical path and signal name of the current signal are used as the joint lookup key to search the signal naming map table. The signal naming map table acts as a bridge between the RTL world and the netlist world, and records the correspondence between signal names and paths before and after synthesis optimization. By querying the signal naming map table, the new hierarchical path of the current multi-bit wide signal in the netlist level after optimization by the synthesis tool can be obtained, as well as the set of names of multiple dispersed unit signals formed after the current multi-bit wide signal bit width is decomposed.

[0042] In summary, this application can convert a logically unified signal identifier in RTL into a set of physical nodes that are uniquely addressed and accessed in the netlist, laying a solid foundation for subsequent waveform data extraction and logic polarity correction.

[0043] In some embodiments, after determining the multiple dispersed cell signals corresponding to the multi-bit wide signal in the netlist hierarchy, the method includes: based on the hierarchical path of the netlist hierarchy and the names of the multiple dispersed cell signals, extracting the values ​​of each cell signal within a time interval comparable to the reset initial value from the waveform database generated by the netlist simulation as the waveform initial value.

[0044] After successfully mapping RTL signals to netlist cell signals, to correct for potential logic polarity inconsistencies caused by synthesis optimization, the system needs to perform precise initial value comparison. For this purpose, see [link to relevant documentation]. Figure 3 Furthermore, this application also requires extracting the initial waveform values ​​of the unit signals from the simulation results as a comparison benchmark.

[0045] Specifically, the system uses the determined hierarchical path of the netlist and the cell signal name as unique identifiers to access and parse the waveform database generated by the netlist simulation. In order to effectively compare with the RTL reset initial value, a specific timing interval is first located, namely the initial stage after the global reset signal is released and the circuit enters stable operation. Within the time window of the initial stage, the first stable logic value presented by each cell signal is sampled and recorded, and the first stable logic value is formally defined as the waveform initial value of the cell signal.

[0046] The data extracted in the above steps can accurately reflect the actual behavior of the netlist from reset to startup, providing accurate and consistent input for subsequent XOR operations and generation of logic polarity correction sequences, thus forming the data foundation for the reliable operation of the automated correction process.

[0047] In some embodiments, the step of performing a calculation on the initial reset value of each wide signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence includes: performing an XOR operation on the initial reset value of the current multi-bit wide signal at the register transfer level and the initial waveform value; and generating a logic mapping sequence based on the calculation result; wherein each element in the logic mapping sequence is used to indicate whether the logic level of the corresponding cell signal at the netlist level is inverted relative to the original signal at the register transfer level.

[0048] After successfully obtaining the two sets of key data, namely the initial reset value at the RTL level and the initial waveform value at the netlist level, we can proceed to the logic polarity determination stage. The logic polarity determination aims to systematically identify whether an inverter has been inserted into each wide signal during the synthesis process, and whether the logic polarity has been inverted compared to the original design.

[0049] Specifically, the system performs an XOR operation on the initial reset value of each bit width of the current multi-bit wide signal at the RTL level and the corresponding initial waveform value extracted from the netlist waveform. The system then constructs the final logic polarity correction sequence based on the operation result. The final generated logic polarity correction sequence is a binary sequence that is completely consistent with the original signal bit width length, and each element in the binary sequence is a clear instruction that precisely indicates whether the corresponding netlist level cell signal needs to be inverted during the subsequent signal reconstruction and display process, thereby ensuring that the final displayed logic value is consistent with the original RTL definition.

[0050] In some embodiments, generating a logical mapping sequence based on the operation result includes: when the XOR operation result is 0, recording a first identifier in the logical mapping sequence, the first identifier being used to indicate that the current bit-width signal has not undergone logical inversion at the netlist level; when the XOR operation result is 1, recording a second identifier in the logical mapping sequence, the second identifier being used to indicate that the current bit-width signal has undergone logical inversion at the netlist level.

[0051] After performing the XOR operation on each bit width, the system obtains a set of raw binary comparison results. In order to convert the binary comparison results into explicit instructions that can be directly recognized and executed in subsequent processes, encoding is required to obtain a standardized control sequence.

[0052] Specifically, based on the XOR operation result of each bit width, a defined encoding rule is executed to generate the final logic polarity correction sequence. For example, when the XOR operation result of a certain bit width is 0, the system records a first identifier, such as binary 0, at the corresponding position in the logic polarity correction sequence. The first identifier is an explicit instruction indicating that the currently processed bit width signal has not undergone logical inversion at the netlist level, and the physical level is consistent with the logic definition at the RTL level. Therefore, no correction is required during subsequent reconstruction and display. Conversely, when the XOR operation result is 1, the system records a second identifier in the sequence, such as binary 1. The second identifier indicates that the current bit width signal has undergone logical inversion at the netlist level, that is, the physical level is opposite to the RTL definition. In subsequent steps, an inversion operation must be performed to restore the original logic.

[0053] By transforming the abstract comparison results into a logical polarity correction sequence consisting of a first identifier and a second identifier, with clearly defined element meanings, accurate input can be provided for generating the final executable configuration file.

[0054] In some embodiments, generating a debug configuration file based on the logical polarity correction sequence includes: traversing the logical polarity correction sequence; directly writing the netlist layer cell signal path corresponding to the bit width signal into the debug configuration file according to a first identifier; and writing the netlist layer cell signal path corresponding to the bit width signal into the debug configuration file in an inverted form according to a second identifier.

[0055] Since the logic polarity correction sequence is only a set of internal data, it must be converted into a configuration file that conforms to the syntax rules of the debugging tool in order to actually be applied to the display of waveform signals. Therefore, it is necessary to further convert the polarity correction instructions into executable commands for the debugging tool.

[0056] Specifically, each element in the logic polarity correction sequence is traversed, and the corresponding file write operation is performed according to the element's identifier type. When the first identifier is read, it indicates that the logic polarity of the netlist cell signal corresponding to the bit width signal is correct. At this time, the complete cell signal path of the bit width signal in the netlist hierarchy is directly written to the debug configuration file. When the second identifier is read, it indicates that the bit width signal is inverted in the netlist. The system will write the netlist hierarchy cell signal path corresponding to the bit width signal in the inverted form to the configuration file. This can be achieved by adding a specific invert operator before the signal path.

[0057] By automatically generating debug configuration files, all scattered unit signal paths are combined, and the bits that are inverted in the netlist are forcibly corrected. This ensures that after loading the debug configuration file, the debug tool can dynamically restore these low-level nodes and display them as a multi-bit wide signal that is completely consistent with the RTL layer logic, thereby greatly improving the efficiency and accuracy of netlist debugging.

[0058] In some embodiments, after generating the debug configuration file, the method includes: loading the debug configuration file, recombining and displaying multiple scattered cell signals in the netlist level that are scattered and have consistent or inconsistent logic levels as multi-bit wide signal values ​​consistent with the register transfer level logic.

[0059] After the debug configuration file is generated, the automated process enters the final application and presentation stage. Specifically, the debug configuration file is loaded and parsed in the waveform debugging tool. Regardless of whether the original logic levels of the scattered cell signals in the netlist level are consistent with or inconsistent with the RTL definition, the physical paths and their inverted attributes of all scattered cell signals listed in the debug configuration file are read. Subsequently, the read information is dynamically combined according to the configuration, and logical inversion operations are performed on the bits marked for inversion. Finally, in the waveform window or data view of the tool, a single, multi-bit wide signal value consistent with the register transfer level logic is reconstructed and displayed.

[0060] This application, by recombining and displaying multi-bit wide signal values ​​consistent with register transfer level logic, can completely bypass the tedious and error-prone manual signal tracing and piecing together, and directly observe and analyze the results of netlist simulation from the perspective of RTL, thereby focusing on higher-level functional and timing problem diagnosis, significantly improving the efficiency and accuracy of netlist simulation debugging.

[0061] Secondly, embodiments of this application provide a signal recovery system that can improve verification efficiency.

[0062] like Figure 4 As shown, embodiments of this application also provide a signal restoration system, including: a determination unit 31, a calculation unit 32, and a generation unit 33.

[0063] The determining unit 31 is used to determine multiple scattered unit signals corresponding to multi-bit wide signals in the netlist layer based on the target signal list and the signal naming mapping table. The target signal list includes multi-bit wide signals to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal name. The arithmetic unit 32 is used to perform calculations on the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence. The generation unit 33 is used to generate a debugging configuration file according to the logic polarity correction sequence. The debugging configuration file is used to instruct the multiple scattered unit signals to be restored into multi-bit wide signals consistent with the register transfer level logic.

[0064] The signal recovery system provided in this application determines multiple dispersed unit signals corresponding to multi-bit-width signals in the netlist layer based on a target signal list and a signal naming mapping table. The target signal list includes the multi-bit-width signals to be processed, and the signal naming mapping table records the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal names. This eliminates the need for tedious and error-prone manual signal tracing and piecing together, automating and accurately locating signals and laying a reliable foundation for subsequent processes. Secondly, by calculating the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level, a logic polarity correction sequence is generated. This automatically and accurately identifies and quantifies logic inversion problems caused by comprehensive optimization, solving the core pain point of misleading debugging direction due to inconsistent logic polarity during verification, and ensuring the correctness and reliability of data analysis. Finally, based on the logic polarity correction sequence, a debug configuration file is generated. This configuration file is used to instruct the restoration of multiple scattered unit signals into multi-bit wide signals consistent with the register transfer level logic. It can convert internal correction data into instructions executable by the debug tool, enabling the correct display of the recombined signal values ​​in the debug environment. This avoids time-consuming and repetitive manual operations, allowing for further focus on higher-level design logic analysis and problem root cause localization, thereby accelerating the debug process and significantly improving the verification efficiency and quality of netlist simulation.

[0065] In some embodiments, the determining unit includes: a selection module, configured to select a current multi-bit-width signal from the target signal list; and a determining module, configured to query the signal naming mapping table based on the hierarchical path and signal name of the current multi-bit-width signal at the register transfer level, to determine the hierarchical path and scattered unit signals corresponding to the current multi-bit-width signal at the netlist level; wherein the target signal list includes at least the hierarchical path, signal name, signal bit width, and reset initial value of the multi-bit-width signal at the register transfer level.

[0066] In some embodiments, the system is configured to: extract the values ​​of each unit signal within a time interval comparable to the reset initial value from the waveform database generated by the netlist simulation, based on the hierarchical path of the netlist level and multiple dispersed unit signal names, as the waveform initial value.

[0067] In some embodiments, the arithmetic unit includes: an XOR operation module, configured to perform an XOR operation on the initial reset value and the initial waveform value of the current multi-bit wide signal at the register transfer level; and a generation module, configured to generate a logical mapping sequence based on the operation result; wherein each element in the logical mapping sequence is used to indicate whether the logic level of the corresponding cell signal in the netlist level is inverted relative to the original signal at the register transfer level.

[0068] In some embodiments, the generation module includes: a first recording submodule, configured to record a first identifier in the logical mapping sequence when the XOR operation result is 0, the first identifier indicating that the current bit-width signal has not undergone logical inversion at the netlist level; and a second recording submodule, configured to record a second identifier in the logical mapping sequence when the XOR operation result is 1, the second identifier indicating that the current bit-width signal has undergone logical inversion at the netlist level.

[0069] In some embodiments, the generation unit includes: a traversal module for traversing the logic polarity correction sequence; a first writing module for directly writing the netlist hierarchical unit signal path corresponding to the bit width signal into the debug configuration file according to a first identifier; and a second writing module for writing the netlist hierarchical unit signal path corresponding to the bit width signal into the debug configuration file in an inverted form according to a second identifier.

[0070] In some embodiments, the system is further configured to: load the debug configuration file, reassemble and display multiple scattered cell signals in the netlist level that are scattered and have consistent or inconsistent logic levels as multi-bit wide signal values ​​consistent with the register transfer level logic.

[0071] Thirdly, embodiments of this application also provide an electronic device that can improve verification efficiency.

[0072] like Figure 5 As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the signal restoration method provided in any of the foregoing embodiments.

[0073] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0074] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the signal restoration methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0075] This application solution can significantly reduce the amount of manual processing time caused by signal dispersion and changes in logic polarity in netlist simulation, allowing engineers to focus their efforts on a deeper understanding of the netlist circuit logic itself. It simplifies the originally complex and inefficient netlist debugging process into a debugging experience similar to the RTL level, greatly reducing the time consumed in signal identification and correction, thereby improving the overall efficiency and operability of netlist debugging.

[0076] In practical applications, the application's process can be executed on all critical registers in the netlist, facilitating rapid tracking of data path changes during debugging. Furthermore, comprehensive mapping can be implemented for specific submodules, i.e., all registers within a specific submodule are processed uniformly, thus clearly presenting the complete register path from module input to output, enabling engineers to locate key issues through simple tracing.

[0077] Furthermore, in RTL simulation, the netlist-based timing constraint file can also be automatically translated based on the signal naming mapping table and converted into a timing constraint format that meets the requirements of RTL simulation. This effectively solves the compatibility problem of constraint files in simulations at different levels and further expands the application value of the solution proposed in this application.

[0078] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0079] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0080] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0081] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0082] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal restoration method, characterized in that, include: Based on the target signal list and the signal naming mapping table, multiple scattered unit signals corresponding to multi-bit wide signals in the netlist level are determined. The target signal list includes multi-bit wide signals to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal name. The initial reset value of each bit-width signal at the register transfer level is calculated with the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence. Based on the logic polarity correction sequence, a debug configuration file is generated, which is used to instruct the multiple scattered unit signals to be restored into multi-bit wide signals consistent with the register transfer level logic.

2. The signal restoration method according to claim 1, characterized in that, The process of determining multiple dispersed unit signals corresponding to multi-bit-width signals in the netlist hierarchy based on the target signal list and signal naming mapping table includes: Select the current multi-bit width signal from the target signal list; Based on the hierarchical path and signal name of the current multi-bit wide signal at the register transfer level, the signal naming mapping table is queried to determine the hierarchical path and scattered unit signals corresponding to the current multi-bit wide signal at the netlist level; wherein, the target signal list includes at least the hierarchical path, signal name, signal width, and reset initial value of the multi-bit wide signal at the register transfer level.

3. The signal restoration method according to claim 1, characterized in that, After determining the multiple dispersed cell signals corresponding to the multi-bit wide signal in the netlist hierarchy, the process includes: Based on the hierarchical path of the netlist hierarchy and multiple dispersed unit signal names, the values ​​of each unit signal within a time interval comparable to the reset initial value are extracted from the waveform database generated by the netlist simulation as the waveform initial value.

4. The signal restoration method according to claim 1, characterized in that, The step of performing calculations on the initial reset value of each wide signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence includes: Perform an XOR operation between the initial reset value of the current multi-bit wide signal at the register transfer level and the initial waveform value; Based on the calculation results, a logical mapping sequence is generated; wherein each element in the logical mapping sequence is used to indicate whether the logic level of the corresponding cell signal in the netlist level is inverted relative to the original signal in the register transfer level.

5. The signal restoration method according to claim 4, characterized in that, The step of generating a logical mapping sequence based on the calculation result includes: When the XOR operation result is 0, a first identifier is recorded in the logical mapping sequence. The first identifier is used to indicate that the current bit width signal has not undergone logical inversion in the netlist level. When the result of the XOR operation is 1, a second identifier is recorded in the logical mapping sequence. The second identifier is used to indicate that the current bit-width signal has been logically inverted at the netlist level.

6. The signal restoration method according to claim 1, characterized in that, Based on the logical polarity correction sequence, a debug configuration file is generated, including: Traverse the logical polarity correction sequence; Based on the first identifier, the netlist level cell signal path corresponding to the bit width signal is directly written into the debug configuration file; Based on the second identifier, the netlist level cell signal path corresponding to the bit width signal is written into the debug configuration file in an inverted form.

7. The signal restoration method according to claim 1, characterized in that, After generating the debug configuration file, the following is included: The debug configuration file is loaded, and multiple scattered unit signals in the netlist level that are scattered and have the same or different logic levels are reorganized and displayed as multi-bit wide signal values ​​that are consistent with the logic of the register transfer level.

8. A signal restoration system, characterized in that, include: The determination unit is used to determine multiple scattered unit signals corresponding to multi-bit wide signals in the netlist layer based on the target signal list and the signal naming mapping table. The target signal list includes multi-bit wide signals to be processed, and the signal naming mapping table is used to record the mapping relationship between the hierarchical path from the register transfer level to the netlist level and the signal names. The arithmetic unit is used to perform calculations on the initial reset value of each bit-width signal at the register transfer level and the corresponding initial waveform value at the netlist level to generate a logic polarity correction sequence. A generation unit is used to generate a debug configuration file based on the logic polarity correction sequence. The debug configuration file is used to instruct the restoration of the plurality of dispersed unit signals into multi-bit wide signals consistent with the register transfer level logic.

9. The signal restoration system according to claim 8, characterized in that, The determining unit includes: The selection module is used to select a current multi-bit width signal from the target signal list; The determination module is used to query the signal naming mapping table based on the hierarchical path and signal name of the current multi-bit wide signal at the register transfer level, and determine the hierarchical path and scattered unit signals corresponding to the current multi-bit wide signal at the netlist level; wherein, the target signal list includes at least the hierarchical path, signal name, signal bit width, and reset initial value of the multi-bit wide signal at the register transfer level.

10. The signal restoration system according to claim 8, characterized in that, The system is used for: Based on the hierarchical path of the netlist hierarchy and multiple dispersed unit signal names, the values ​​of each unit signal within a time interval comparable to the reset initial value are extracted from the waveform database generated by the netlist simulation as the waveform initial value.

11. The signal restoration system according to claim 8, characterized in that, The arithmetic unit includes: The XOR operation module is used to perform an XOR operation between the initial reset value and the initial waveform value of the current multi-bit wide signal at the register transfer level. The generation module is used to generate a logical mapping sequence based on the calculation result; wherein, each element in the logical mapping sequence is used to indicate whether the logic level of the corresponding cell signal in the netlist level is inverted relative to the original signal in the register transfer level.

12. The signal restoration system according to claim 11, characterized in that, The generation module includes: The first recording submodule is used to record a first identifier in the logical mapping sequence when the XOR operation result is 0. The first identifier is used to indicate that the current bit width signal has not undergone logical inversion in the netlist level. The second recording submodule is used to record a second identifier in the logical mapping sequence when the result of the XOR operation is 1. The second identifier is used to indicate that the current bit width signal has been logically inverted at the netlist level.

13. The signal restoration system according to claim 8, characterized in that, The generation unit includes: The traversal module is used to traverse the logical polarity correction sequence; The first writing module is used to directly write the netlist hierarchical cell signal path corresponding to the bit width signal into the debug configuration file according to the first identifier. The second writing module is used to write the netlist level cell signal path corresponding to the bit width signal into the debug configuration file in an inverted form according to the second identifier.

14. The signal restoration system according to claim 8, characterized in that, The system is also used for: The debug configuration file is loaded, and multiple scattered unit signals in the netlist level that are scattered and have the same or different logic levels are reorganized and displayed as multi-bit wide signal values ​​that are consistent with the logic of the register transfer level.

15. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the signal restoration method of any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the signal restoration method according to any one of claims 1 to 7.

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