A top module timing library fast construction method and system supporting incremental update

Abstract

The application discloses a kind of top module timing library fast construction method and system supporting incremental update, it is related to data processing technical field.The method includes: obtaining the hardware description language file of target top module and multiple process angle information, identifying port information in hardware description language file, generate multiple empty timing library files, wherein, empty timing library file only includes port information;Obtain the bottom module timing information and port mapping relationship file contained in target top module;Based on port mapping relationship file, map bottom module timing information to corresponding top module port, synchronously complete the parallel incremental update of multiple empty timing library, generate top module timing library file containing timing information;Read the capacitance and maximum slope information of port, update to the corresponding field in top module timing library file containing timing information, obtain complete top module timing library file.The application effectively improves the efficiency and accuracy of timing library generation.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically to a method and system for rapidly constructing a top-level module time series library that supports incremental updates. Background Technology

[0002] As integrated circuit chips evolve towards advanced process nodes and circuit scale continues to expand, timing libraries, as core databases that accurately characterize the electrical properties of circuits, have become a prerequisite for the entire digital design process. Current mainstream timing library generation tools all rely on the SPICE simulation engine, which generates standardized timing library files by performing multi-process-angle simulations on the module netlist.

[0003] However, existing technologies face significant bottlenecks: on the one hand, the increased process complexity and circuit size of advanced nodes lead to a significant increase in the time required for a single simulation, while the superposition of multi-process corner requirements and a massive number of timing arc simulation sampling points further exacerbates the risk of convergence time for timing library files; on the other hand, for complex simulation top-level modules, if problems occur in the simulation process or results, debugging is difficult and time-consuming, and the iterative process will affect the project schedule, making it difficult to balance the efficiency and accuracy of timing library generation. Summary of the Invention

[0004] This invention provides a method and system for rapidly constructing a top-level module time series library that supports incremental updates, aiming to solve the technical problem of balancing the efficiency and accuracy of time series library generation in the prior art.

[0005] In view of the above problems, the present invention provides a method and system for rapidly constructing a top-level module time series library that supports incremental updates.

[0006] In a first aspect, the present invention provides a method for rapidly constructing a top-level module time-series library that supports incremental updates, comprising: The hardware description language file and multiple process corner information of the target top-level module are obtained, the port information in the hardware description language file is identified, and multiple empty timing library files are generated, wherein the empty timing library files only contain port information. Obtain the timing information and port mapping relationship file of the underlying modules contained in the target top-level module; Based on the port mapping relationship file, the timing information of the underlying module is mapped to the corresponding top-level module port, and the parallel incremental update of multiple empty timing libraries is completed synchronously to generate a top-level module timing library file containing timing information. The capacitance and maximum slope information of the port are read and updated to the corresponding fields in the top-level module timing library file containing timing information to obtain the complete top-level module timing library file.

[0007] Secondly, this invention provides a system for rapidly building a top-level module time-series library that supports incremental updates, comprising: An empty timing library generation module is used to obtain the hardware description language file and multiple process corner information of the target top-level module, identify the port information in the hardware description language file, and generate multiple empty timing library files, wherein the empty timing library files only contain port information; The underlying information acquisition module is used to acquire the timing information and port mapping relationship file of the underlying modules contained in the target top-level module; The timing mapping update module is used to map the timing information of the lower-level module to the corresponding top-level module port based on the port mapping relationship file, and synchronously complete the parallel incremental update of multiple empty timing libraries to generate a top-level module timing library file containing timing information. The parameter supplementation and improvement module is used to read the capacitance and maximum slope information of the port and update the corresponding fields in the top-level module timing library file containing timing information to obtain the complete top-level module timing library file.

[0008] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention provides a method and system for rapidly constructing a top-level module timing library that supports incremental updates. First, an empty timing library containing only port information is generated based on the hardware description language file of the target top-level module and multi-process corner information. Then, a file mapping the timing information of the lower-level modules to the port information is obtained. Relying on direct data reuse without logically directly connected ports and a multi-process corner parallel incremental update mechanism, a top-level timing library containing timing information is rapidly generated. Finally, port capacitance and maximum slope information are added. This not only effectively solves the problems of long simulation time, high convergence risk in multi-process corners, and cumbersome debugging and iteration caused by full-scale simulation of complex top-level modules, but also ensures the original accuracy of the timing data, ultimately generating a complete top-level module timing library, achieving a dual improvement in timing library construction efficiency and data accuracy. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A flowchart illustrating a method for rapidly constructing a top-level module time-series library that supports incremental updates, provided in an embodiment of the present invention; Figure 2This is a schematic diagram illustrating the port mapping relationship between the top-level module and the bottom-level module in a method for rapidly constructing a top-level module time-series library that supports incremental updates, as provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a system for rapidly building a top-level module time-series library that supports incremental updates, provided in an embodiment of the present invention. The components represented by each number in the attached diagram are explained below: Empty time series library generation module 11, underlying information acquisition module 12, time series mapping update module 13, parameter supplementation and improvement module 14. Detailed Implementation

[0011] This invention provides a method and system for rapidly constructing a top-level module time series library that supports incremental updates, addressing the technical problem of balancing efficiency and accuracy in time series library generation in existing technologies.

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0013] It should be noted that the terms "comprising" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to these processes, methods, products, or devices.

[0014] Example 1, as Figure 1 As shown, this invention provides a method for rapidly constructing a top-level module time-series library that supports incremental updates. The method includes: S100: Obtain the hardware description language file and multiple process corner information of the target top-level module, identify the port information in the hardware description language file, and generate multiple empty timing library files, wherein the empty timing library files only contain port information.

[0015] In this embodiment of the invention, the hardware description language file and multiple process corner information of the target top-level module are obtained, the port information in the hardware description language file is identified, and multiple empty timing library files are generated, wherein the empty timing library files only contain port information. In the construction of timing libraries for complex simulation top-level modules, existing technologies directly perform full multi-process corner simulation of the top-level module, which requires processing massive transistors and netlist logic, resulting in lengthy simulation time and high convergence risk. Therefore, this step builds a multi-process corner empty timing library framework containing only port information in advance, and automatically extracts port information through scripts, avoiding the errors and inefficiencies of manual parsing of hardware description language files; the timing library carrier is split according to process corner, providing a basis for direct reuse and parallel incremental updates of subsequent low-level timing information, simplifying the timing library construction process of complex top-level modules from the source, and reducing the resource consumption caused by full simulation.

[0016] Step S100 in the method provided in this embodiment of the invention includes: Obtain the hardware description language file of the target top-level module, and automatically parse the hardware description language file to extract port information using the port recognition algorithm built into the script; Acquire multiple process corner information, wherein the process corner information includes at least the process deviation range, the power supply voltage range, and the operating temperature range; Based on the port information, the corresponding port information is matched for the multiple process corner information and a timing library framework is constructed, generating multiple empty timing library files that only contain port information.

[0017] The port information includes port type and signal transmission direction information, and the port type includes clock port and data port.

[0018] First, the hardware description language (HDL) file of the target top-level module is obtained. The script's built-in port identification algorithm automatically parses the HDL file to extract port information. This port information includes port type and signal transmission direction information; the port type includes clock ports and data ports. A hardware description language (HDL) file is a top-level module design file written in a hardware description language such as Verilog or VHDL. It describes the module's port definitions, internal logic connections, and other core information, serving as the foundational file for chip design. The port identification algorithm is a built-in automated parsing algorithm that quickly identifies key information in the HDL file, such as port name, type, signal transmission direction, and bit width, avoiding omissions during manual extraction. The port information, including port type and signal transmission direction information, serves as the basic index for timing library files, used to associate subsequent timing data. The script retrieves the HDL file corresponding to the target top-level module from the chip design project folder, starts the automated script, and uses the built-in port identification algorithm to scan the port definition statements in the file, automatically parsing and extracting complete port information.

[0019] For example, the target top-level module is the signal conversion top-level module shown in the figure. The hardware description language file of the signal conversion top-level module is retrieved, and after being parsed by the port identification algorithm built into the script, the extracted port information includes: a clock port CK, input direction, 1 bit width; an input data port DQ, input direction, 1 bit width; an output clock port O_CK, output direction, 1 bit width; and an output data port O_DQ, output direction, 1 bit width.

[0020] Secondly, multiple process corner information is obtained, which includes at least the process deviation range, supply voltage range, and operating temperature range. Process corner information refers to the process-voltage-temperature (PVT) combination parameters for chip operation, representing a key operating scenario that must be covered in chip design approval. The process deviation range refers to the fluctuation range of process parameters during chip manufacturing, directly affecting chip performance. The supply voltage range refers to the voltage threshold range required for stable module operation. The operating temperature range refers to the ambient temperature range to which the module adapts; for example, automotive-grade and industrial-grade modules have different temperature ranges. Based on the chip design approval requirements, multiple process corner information corresponding to the target process is retrieved from the process library document, clarifying the process deviation range, supply voltage range, and operating temperature range for each process corner, forming a complete set of process corner parameters.

[0021] For example, the target top-level module is an automotive-grade chip that needs to cover wide temperature and wide voltage scenarios. Three core process corners are selected: the typical process corner TT has a process deviation range of ±5%, a supply voltage range of 1.2V±0.1V, and an operating temperature range of -40℃ to 85℃; the slow process corner SS has a process deviation range of -10%, a supply voltage range of 1.0V±0.05V, and an operating temperature range of 60℃ to 125℃; and the fast process corner FF has a process deviation range of +10%, a supply voltage range of 1.4V±0.05V, and an operating temperature range of -55℃ to 40℃.

[0022] Finally, based on the port information, corresponding port information is matched for the multiple process corners, and a timing library framework is constructed, generating multiple empty timing library files containing only port information. An empty timing library file is a standardized timing library file containing only port information, serving as the carrier framework for subsequent incremental updates of timing information. The standardized timing library format (.lib) is a common timing library file format in the chip design field, recognizable by mainstream design tools such as Cadence and Synopsys toolchains, ensuring file compatibility. A script matches the port information with each process corner, constructs the timing library framework according to the standardized timing library format, retains only the port index field, and does not populate timing data, ultimately generating empty timing library files corresponding to the number of process corners.

[0023] For example, the script matches the port information of the target top-level module with the three process corners TT, SS, and FF respectively, constructs a time-series library framework in a standardized time-series library format (.lib), and generates three empty time-series library files: File 1 contains the name, type, and signal transmission direction information of all the above ports, without any timing data, and corresponds to the TT process corner; File 2 has the same port information as File 1, except that the process corner is identified as SS; File 3 has the same port information, but the process corner is identified as FF.

[0024] In this embodiment of the invention, port information of the target top-level module is automatically extracted via script, avoiding omissions and errors caused by manual parsing and effectively ensuring the efficiency and accuracy of port information extraction. Simultaneously, empty timing library files categorized by process corner are generated, allowing subsequent low-level timing information to be directly matched and written. Furthermore, the empty timing library is a lightweight design that retains only core port information. This not only provides an adaptation carrier for the direct copying and reuse of subsequent low-level timing information but also creates conditions for parallel incremental updates through the multi-process corner classification design, ultimately reducing the convergence risk of complex top-level module timing libraries from the source.

[0025] S200: Obtain the timing information and port mapping relationship file of the underlying modules contained in the target top-level module.

[0026] In this embodiment of the invention, the timing information and port mapping relationship file of the underlying modules contained in the target top-level module are obtained. In the construction of timing libraries for complex top-level modules, directly performing semiconductor device simulation on the top-level module requires processing a massive number of logic units, resulting in a lengthy simulation process and a high risk of non-convergence. However, a top-level module is essentially composed of multiple underlying modules with independent functions. The underlying modules are smaller in scale, have simpler logic, and offer higher simulation efficiency and more accurate convergence. Furthermore, the connection relationship between the ports of the top-level and underlying modules is a core prerequisite for timing information reuse. If the port correspondence is not clearly defined, timing data mismatch is highly likely. Therefore, this step obtains the underlying module list, simulates to obtain the underlying timing library file, and compiles a port mapping file containing no direct logical connections. This provides a data foundation and connection basis for the accurate reuse of subsequent timing information, further avoiding the drawbacks of full simulation of the top-level module.

[0027] Step S200 in the method provided in this embodiment of the invention includes: Obtain all the underlying modules contained in the target top-level module, form a list of underlying modules, and label the function of each underlying module; For each underlying module in the underlying module list, the underlying module timing library file under each process corner is obtained through semiconductor device simulation. The underlying module timing library file contains the setup time, hold time or circuit delay data of the timing-related ports of the corresponding underlying module. Compile a port mapping relationship file in the form of a table containing the top-level module port name, the corresponding bottom-level module name, and the corresponding bottom-level module port name. The top-level module port and the corresponding bottom-level module port are not logically directly connected.

[0028] First, all underlying modules contained in the target top-level module are obtained, and a list of underlying modules is formed, with the function of each underlying module labeled. Underlying modules are the basic functional units that constitute the top-level module; each underlying module has an independent and specific function and is a core component of the top-level module. The underlying module list is a list recording the names and corresponding functions of all underlying modules contained in the target top-level module, and is the core basis for subsequent simulation operations. By parsing the hardware description language file of the target top-level module, all underlying modules referenced in the file are identified, the names of all underlying modules are compiled, and the function corresponding to each underlying module is labeled one by one, ultimately forming a complete list of underlying modules.

[0029] For example, after parsing the hardware description language file of the top-level module of the signal conversion class, it is identified that it contains bottom-level module A, bottom-level module B, and bottom-level module C. The resulting list labels the functions as follows: bottom-level module A is a data receiving module, responsible for receiving external input signals; bottom-level module B is a signal conversion module, responsible for outputting the processed signals to the outside; bottom-level module C is an auxiliary function module, responsible for the logical coordination between modules.

[0030] Secondly, for each underlying module in the underlying module list, the underlying module timing library file under each process corner is obtained through semiconductor device simulation. The underlying module timing library file contains the setup time, hold time or circuit delay data of the timing-related ports of the corresponding underlying module.

[0031] Specifically, for each underlying module in the underlying module list, the timing library file for each process corner is obtained through semiconductor device simulation, including: Randomly select the first bottom module in the list of bottom modules, retrieve its corresponding hardware description language file, associate the multiple process corner information, clarify the process deviation, power supply voltage and operating temperature parameters corresponding to each process corner, and form a simulation parameter comparison table. Set up a semiconductor device simulation environment, import the hardware description language file of the first underlying module and the process library file that matches the process corner, and configure the simulation environment variables for each process corner according to the simulation parameter reference table. Design a suitable simulation excitation signal based on the port type of the first bottom module, start the simulation and execute the simulation tasks under each process corner one by one, and collect timing data such as setup time, hold time, and circuit delay of the bottom module port. Valid simulation data under each process corner are selected, the data are organized according to the standard timing library format and the corresponding process corner information is labeled, and the first bottom-level module timing library file is generated. The timing library files for the remaining underlying modules in the underlying module list are generated sequentially to form a set of underlying module timing libraries.

[0032] First, a first bottom-level module is randomly selected from the bottom-level module list. Its corresponding hardware description language file is retrieved, and the information from multiple process corners is associated to clarify the process deviation, power supply voltage, and operating temperature parameters corresponding to each process corner, forming a simulation parameter reference table. The first bottom-level module refers to the first module to be simulated randomly selected from the bottom-level module list, which is the starting unit for step-by-step simulation. The simulation parameter reference table is a reference table that integrates the process deviation, power supply voltage, and operating temperature parameters of each process corner, and serves as the basis for configuring the simulation environment. A bottom-level module is randomly selected from the bottom-level module list as the first bottom-level module. Its hardware description language file is retrieved, and the information from multiple process corners that have been obtained is associated to clarify the process deviation range, power supply voltage range, and operating temperature range corresponding to each process corner, and the simulation parameter reference table is formed.

[0033] For example, a bottom-level module A is randomly selected as the first bottom-level module. Its hardware description language file is retrieved, and the information of the three process corners TT, SS, and FF is associated. The parameters of each process corner are defined and a reference table is formed: the process corner TT corresponds to a process deviation of ±5%, a power supply voltage of 1.2V±0.1V, and an operating temperature of -40℃ to 85℃; the process corner SS corresponds to a process deviation of -10%, a power supply voltage of 1.0V±0.05V, and an operating temperature of 60℃ to 125℃; the process corner FF corresponds to a process deviation of +10%, a power supply voltage of 1.4V±0.05V, and an operating temperature of -55℃ to 40℃.

[0034] Next, a semiconductor device simulation environment is set up. The hardware description language file of the first underlying module and the process library file matching the process corner are imported. The simulation environment variables for each process corner are configured according to the simulation parameter lookup table. The semiconductor device simulation environment refers to a simulation platform built using professional simulation tools such as SPICE and HSPICE, which can simulate the electrical characteristics of semiconductor devices. The process library file is a file containing semiconductor device process parameters, which must be matched with the corresponding process corner to ensure simulation accuracy. Simulation environment variables refer to parameters such as process, voltage, and temperature that need to be configured during the simulation process, determined by the simulation parameter lookup table. The semiconductor device simulation tool is started to set up the simulation environment. The hardware description language file of the first underlying module and the process library file matching each process corner are imported. The simulation environment variables for each process corner are configured according to the parameters in the simulation parameter lookup table.

[0035] For example, start the HSPICE simulation tool to build the environment, import the hardware description language file of the underlying module A, and import the process library files corresponding to the TT, SS, and FF process corners; then configure the environment variables according to the reference table: configure the TT process corner with process deviation ±5%, supply voltage 1.2V, and operating temperature 25℃; configure the SS process corner with process deviation -10%, supply voltage 1.0V, and operating temperature 85℃; configure the FF process corner with process deviation +10%, supply voltage 1.4V, and operating temperature 0℃.

[0036] Furthermore, based on the port types of the first underlying module, suitable simulation excitation signals are designed. Simulation is initiated and simulation tasks under each process corner are executed sequentially, collecting timing data such as setup time, hold time, and circuit delay of the underlying module ports. Simulation excitation signals refer to input signals designed according to the module port types, used to trigger the module's electrical response, and are a prerequisite for obtaining timing data. Timing data includes parameters characterizing the module's timing characteristics, such as setup time, hold time, and circuit delay. Based on the port types of the first underlying module, suitable simulation excitation signals are designed, such as using square waves for clock signals and pulse signals for data signals. The simulation tool is initiated, and simulation tasks under each process corner are executed sequentially, collecting real-time data such as setup time, hold time, and circuit delay of the module's timing-related ports.

[0037] For example, the underlying module A includes a clock port clk and a data port din. A 100MHz square wave excitation signal is designed for the clock port, and a pulse excitation signal is designed for the data port. After starting the simulation, the TT process corner simulation is executed first to collect the hold time of the clk port, the setup time of the din port, and the circuit delay data of signal transmission. Then, the SS and FF process corner simulations are executed in sequence to complete the acquisition of all timing data.

[0038] Subsequently, valid simulation data for each process corner is screened, organized according to the standard timing library format, and labeled with the corresponding process corner information to generate the timing library file for the first bottom-level module. Valid simulation data refers to timing data that meets the simulation accuracy requirements after removing abnormal data caused by non-convergence and signal glitches. The timing data collected for each process corner is screened, and valid data is retained; the data is organized according to the standard timing library format, and labeled with the corresponding process corner information to generate the timing library file for the first bottom-level module. For example, abnormal setup time data of the DIN port caused by signal glitches under the SS process corner is screened out, and valid timing data of the TT, SS, and FF process corners are retained; the data is organized according to the standard timing library format, and the corresponding process corner of each data point is labeled to generate the timing library file for bottom-level module A. The file contains the hold time of the clk port, the setup time of the DIN port, and circuit delay data under different process corners.

[0039] Then, the timing library files for the remaining underlying modules in the underlying module list are generated sequentially to form a set of underlying module timing libraries. This set of underlying module timing libraries contains timing library files for all underlying modules at each process corner and is the core data source for subsequent timing information reuse. Following the above steps, simulation operations are performed on underlying module B and underlying module C in the underlying module list to generate their respective timing library files. Finally, all files are integrated to form the set of underlying module timing libraries. For example, simulation is performed on underlying module B to generate its timing library file containing the CLKO port circuit delay and DOUT port hold time; simulation is performed on underlying module C to generate its corresponding port timing library file; the timing library files of underlying modules A, B, and C are integrated to form the set of underlying module timing libraries for this signal transition top-level module.

[0040] Finally, a port mapping relationship file is compiled in tabular form, containing the top-level module port name, the corresponding bottom-level module name, and the corresponding bottom-level module port name. The top-level module ports and their corresponding bottom-level module ports are not logically directly connected. The port mapping relationship file records the correspondence between top-level ports and bottom-level ports. "No logical direct connection" means that there are no intermediate logic gates between the top-level and bottom-level ports; signals are transmitted directly, such as... Figure 2 The connection method between the top-level module DQ and the bottom-level module din. Based on the port connection relationship between the top-level and bottom-level modules, the correspondence between modules without logical direct connections is sorted out, and a file is compiled in the format of top-level port name - corresponding bottom-level module name - corresponding bottom-level port name.

[0041] For example, such as Figure 2 As shown, based on the port mapping relationship between the top-level module and the bottom-level module, the compiled port mapping relationship file includes: top-level port DQ corresponds to the din port of bottom-level module A, top-level port CK corresponds to the clk port of bottom-level module A, top-level port O_CK corresponds to the clk port of bottom-level module B, and top-level port O_DQ corresponds to the dout port of bottom-level module B. The file clearly indicates that there is no logical direct connection between the ports.

[0042] In this embodiment of the invention, this step obtains the list of underlying modules by parsing the top-level file, providing a clear operational basis for subsequent simulations; by using small-scale simulations of the underlying modules, the lengthy process of full simulation of the top-level modules is avoided, while ensuring the accuracy of the timing data; combined with the port mapping relationship file, the logical direct connection correspondence between the top-level and bottom-level ports is clarified, providing a key basis for the accurate reuse of subsequent timing information and effectively avoiding the risk of data mismatch.

[0043] S300: Based on the port mapping relationship file, the timing information of the underlying module is mapped to the corresponding top-level module port, and the parallel incremental update of multiple empty timing libraries is completed synchronously to generate a top-level module timing library file containing timing information.

[0044] In this embodiment of the invention, based on the port mapping relationship file, the timing information of the underlying modules is mapped to the corresponding top-level module ports, and multiple empty timing libraries are updated incrementally in parallel simultaneously to generate a top-level module timing library file containing timing information. The timing library files of the underlying modules and the top-level-bottom-level ports without logical direct connections have been obtained, while the empty timing libraries only contain port information without timing data. Traditional methods use a serial approach to write the underlying timing data into the empty timing libraries, which is not only inefficient but also prone to data mismatch or distortion due to process corner mismatches and oversights in port correspondence verification. Furthermore, manually mapping timing data requires port-by-port operations, making it difficult to guarantee completeness. Therefore, this step, by establishing a process corner association index, accurately matching and directly mapping timing data, and performing parallel incremental updates across multiple process corners, ensures both the accuracy and completeness of timing data mapping and improves the timing library update efficiency, ultimately generating a top-level module timing library file containing complete timing information.

[0045] Step S300 in the method provided in this embodiment of the invention includes: Load the port mapping relationship file, underlying module timing information and multiple empty timing libraries, and establish an association index between empty timing libraries and underlying module timing information under the same process corner; Parse the port mapping relationship file and match the establishment time, hold time, and circuit delay data in the timing information of the underlying module with the corresponding top-level module ports in the empty timing library. Map the matched timing information of the underlying modules to the preset fields of the corresponding top-level module ports; A multi-process-angle parallel execution method is adopted to synchronously complete the incremental update of all empty timing libraries and generate the top-level module timing library file containing timing information.

[0046] First, load the port mapping relationship file, underlying module timing information, and multiple empty timing libraries, and establish an association index between empty timing libraries and underlying module timing information under the same process corner. This index establishes a one-to-one correspondence between empty timing libraries and underlying module timing information under the same process corner, used for quickly matching data sources and carriers within the same process corner. Start the automated processing tool, load the port mapping relationship file, all underlying module timing library files, and multiple empty timing library files, categorize them by process corner dimension, and establish an association index between empty timing libraries and underlying module timing information for each process corner, forming an index table. For example, load the port mapping relationship file, the TT / SS / FF process corner timing library files for underlying modules A / B, and the three previously generated empty timing library files; after categorizing by process corner, establish an association index: file 1 is associated with the underlying module A / B timing library files for the TT process corner, file 2 is associated with the underlying module A / B timing library files for the SS process corner, and file 3 is associated with the underlying module A / B timing library files for the FF process corner.

[0047] Secondly, the port mapping file is parsed, and the setup time, hold time, and circuit delay data in the timing information of the underlying modules are matched with the corresponding top-level module ports in the empty timing library. Attribute matching refers to matching the setup time, hold time, and circuit delay data in the timing information of the underlying modules with the timing attributes of the corresponding top-level ports in the empty timing library, such as clock ports corresponding to hold time and data ports corresponding to setup time. The port mapping file is parsed to extract the correspondence between top-level ports and underlying ports; then the underlying module timing library file is parsed to extract the setup time, hold time, and circuit delay data of each underlying port; finally, according to the port correspondence, the underlying timing data is matched with the top-level ports in the empty timing library to form a matching table.

[0048] For example, the port mapping file is parsed to extract the corresponding relationships: the top-level CK port corresponds to the clk port of the bottom-level module A, the top-level DQ port corresponds to the din port of the bottom-level module A, the top-level O_CK port corresponds to the clko port of the bottom-level module B, and the top-level O_DQ port corresponds to the doout port of the bottom-level module B; the timing library file of the bottom-level module A in the TT process corner is parsed to extract the hold time of the clk port and the setup time of the din port; the timing library file of the bottom-level module B is parsed to extract the circuit delay of the clko port and the hold time of the doout port; then the extracted bottom-level module timing data is matched with the corresponding top-level ports in the empty timing library of the TT process corner: the top-level CK port matches the hold time of the bottom-level module Aclk port, the top-level DQ port matches the setup time of the bottom-level module Adin port, the top-level O_CK port matches the circuit delay of the bottom-level module Bclko port, and the top-level O_DQ port matches the hold time of the bottom-level module Bdout port.

[0049] Furthermore, the matched timing information of the underlying modules is mapped to the preset fields of the corresponding top-level module ports.

[0050] The process of mapping the timing information of the matched lower-level modules to the corresponding top-level module ports includes the following preset fields: Based on the port mapping relationship file, check the non-logical direct connection correspondence between the bottom port corresponding to the timing information of the bottom module and the top module port in the empty timing library, and confirm that the two belong to the same process angle. The empty timing library file is parsed, and the preset timing fields corresponding to the top-level module ports are located according to the parameter types of setup time, hold time, and circuit delay. Extract the valid underlying time series data after matching, and write it into the preset time series field using a direct mapping method.

[0051] First, based on the port mapping relationship file, the system checks the direct logical connection between the underlying ports corresponding to the timing information of the underlying modules and the ports of the top-level modules in the empty timing library, while confirming that the process corners of the two are consistent. Checking for direct logical connection means confirming that there are no intermediate logic gates between the underlying ports and the top-level ports, ensuring that timing data can be directly mapped without correction. Based on the port mapping relationship file, the system checks whether the direct logical connection between the matched underlying ports and the top-level ports is valid; simultaneously, it checks whether the process corners of the underlying timing data are consistent with the process corners of the empty timing library, eliminating matches that do not meet the conditions. For example, the check found that: the top-level CK port and the underlying module Aclk port are directly logically connected, and both are in the TT process corner; the top-level DQ port and the underlying module Adin port are directly logically connected, and their process corners are consistent; the direct logical connection and process corner consistency between the top-level O_CK / O_DQ ports and the corresponding ports of the underlying module B are both valid, and all the above matches meet the requirements.

[0052] Next, the empty timing library file is parsed, and the preset timing fields corresponding to the top-level module ports are located according to the parameter types of setup time, hold time, and circuit delay. The empty timing library file contains fields such as port name, setup time, hold time, and circuit delay. The preset timing fields are dedicated fields reserved for each port in the empty timing library to store setup time, hold time, and circuit delay data. The file structure of the empty timing library is parsed, and the preset timing fields corresponding to each top-level port are found according to the parameter types of setup time, hold time, and circuit delay, and the field positions are recorded. For example, parsing the structure of file 1, the preset hold time field of the top-level CK port, the preset setup time field of the top-level DQ port, the preset circuit delay field of the top-level O_CK port, and the preset hold time field of the top-level O_DQ port are located.

[0053] Further, the matched valid underlying timing data is extracted and written into the preset timing fields using a direct mapping method. Valid underlying timing data refers to the filtered underlying timing data that meets the accuracy requirements. The direct mapping method means directly writing the underlying timing data into the preset fields without data fitting or correction. The verified valid underlying timing data is extracted and written into the preset timing fields of the corresponding top-level ports one by one using a direct mapping method. For example, the hold time data of the Aclk port of the underlying module under the TT process corner is extracted and directly written into the preset hold time field of the CK port of the top-level module; the setup time data of the Adin port of the underlying module is extracted and directly written into the preset setup time field of the DQ port of the top-level module; similarly, the timing data of the corresponding port of the underlying module B is written into the preset fields of the O_CK and O_DQ ports of the top-level module.

[0054] Based on this, a multi-process angle parallel execution method is adopted to synchronously complete the incremental update of all empty timing libraries and generate the top-level module timing library file containing timing information.

[0055] The process employs a multi-process-angle parallel execution method to synchronously complete incremental updates of all empty timing libraries, generating top-level module timing library files containing timing information, including: Initialize a multi-threaded parallel execution environment, synchronously associate the semi-completed multi-process corner timing library files, process corner list and dynamic load balancing configuration rules that have been processed by timing data writing, and establish a process corner-semi-completed timing library file association index; Based on the task volume evaluation index in the dynamic load balancing configuration rules, the incremental update task volume corresponding to each process corner is quantitatively evaluated, and a list containing the task weights of each process corner is generated. Computing resources are dynamically allocated based on the task weight list, incremental update tasks for all process corners are started synchronously, the progress of each task is monitored in real time, and idle computing resources are automatically added to tasks that are lagging behind. The system collects progress data of update tasks in real time for each process corner, triggers restarts for threads that experience lag and resumes from breakpoints, and pauses the corresponding task, marks the exception, and generates a report for detected data writing errors. After all process corner update tasks are completed, the parallel environment is terminated, integrity checks are performed on the timing library files of each process corner, and the files are classified, named, and marked as updated as complete according to the process corner type. The timing library files of the top-level module are then integrated and output.

[0056] First, initialize the multi-threaded parallel execution environment, synchronously associate the semi-completed multi-process corner time series library files, process corner lists, and dynamic load balancing configuration rules after time series data writing processing, and establish a process corner-semi-completed time series library file association index. The multi-threaded parallel execution environment is a parallel processing platform built on multi-threaded technology, capable of handling update tasks for multiple process corners simultaneously. A semi-completed time series library file refers to a time series library file that has completed partial data writing but has not yet undergone final verification. Dynamic load balancing configuration rules are rules used to allocate computing resources, adjusting resource allocation based on task volume. Start the multi-threaded processing tool, initialize the multi-threaded parallel execution environment, load the process corner semi-completed time series library files, process corner lists, and dynamic load balancing configuration rules, and establish a process corner-semi-completed time series library file association index. For example, initialize a parallel environment with 3 threads, load the semi-completed time series library files for TT, SS, and FF process corners, and the dynamic load balancing configuration rules; establish an index: thread 1 corresponds to the TT process corner, thread 2 corresponds to the SS process corner, and thread 3 corresponds to the FF process corner.

[0057] Secondly, based on the task volume evaluation metrics in the dynamic load balancing configuration rules, the incremental update task volume corresponding to each process corner is quantitatively evaluated, generating a list containing the task weights for each process corner. Task volume evaluation metrics are used to quantify the incremental update task volume, such as the number of ports and the amount of data. The task weight list records the update task weights for each process corner, with the weights being positively correlated with the task volume. Based on the task volume evaluation metrics in the dynamic load balancing configuration rules, the incremental update task volume corresponding to each process corner is quantitatively evaluated, and a list containing the task weights for each process corner is generated according to the task volume. For example, using the number of ports as the evaluation metric, it is found that the update tasks for the TT, SS, and FF process corners all involve 4 ports, with the same task volume. Therefore, in the generated task weight list, the weights for the three process corners are all 1:1:1.

[0058] Then, computing resources are dynamically allocated according to the task weight list, incremental update tasks for all process corners are started simultaneously, and the progress of each task is monitored in real time. Idle computing resources are automatically added to tasks that are lagging behind. For example, one CPU core is allocated to each of the TT, SS, and FF process corners, and update tasks are started simultaneously. If monitoring reveals that the task progress for the SS process corner is slightly slower, an idle CPU core is automatically added to it to speed up task processing.

[0059] Furthermore, the system collects progress data for update tasks in each process corner in real time. For threads experiencing lag, it triggers a restart and resumes execution from the breakpoint. For detected data write errors, the corresponding task is paused, an exception is marked, and a report is generated. Resuming from a breakpoint means that after a task lags and restarts, execution continues from the last interrupted position without restarting. The system collects progress data for update tasks in each process corner in real time. If a thread lags, it triggers a restart and resumes execution from the breakpoint. If a data write error is detected, the corresponding task is paused, an exception is marked, and an error report is generated, awaiting manual handling. For example, when collecting progress data, a brief lag was detected in the thread of the FF process corner. After triggering a restart, execution resumed from the breakpoint without affecting the task progress; no data write errors occurred in any task, and no exceptions were marked.

[0060] Finally, after all process corner update tasks are completed, the parallel environment is terminated, and integrity checks are performed on the timing library files for each process corner. The files are then categorized and named according to process corner type, and their update completion status is marked. The top-level module timing library files are then integrated and output. Integrity checks refer to a comprehensive verification of the port information and timing data of each process corner timing library file to ensure there are no missing or incorrect entries. After all process corner update tasks are completed, the parallel execution environment is terminated; integrity checks are performed on the timing library files for each process corner. If the checks pass, the files are categorized and named according to process corner type, and their update completion status is marked. Finally, the top-level module timing library file set is integrated and output. For example, after all three process corner update tasks are completed, the parallel environment is terminated; integrity checks are performed on the timing library files for the TT, SS, and FF process corners to confirm that the timing data for all ports is complete and accurate; then, the files are categorized and named: file 1 is named "Signal Transfer Top-Level Module_TT.lib", file 2 is named "Signal Transfer Top-Level Module_SS.lib", and file 3 is named "Signal Transfer Top-Level Module_FF.lib", and their update completion status is marked. These three files are then integrated and output as the final top-level module timing library files.

[0061] In this embodiment of the invention, by establishing an associated index under the same process corner, the problem of data confusion across process corners is avoided from the source. By using port attribute matching and verification of no logical direct connections, combined with direct mapping, timing data is written, ensuring both the accuracy and completeness of data mapping while avoiding the distortion risks associated with traditional data fitting. Simultaneously, a multi-process corner parallel execution approach, coupled with dynamic load balancing and exception handling mechanisms, not only improves the incremental update efficiency of the empty timing library but also promptly handles task exceptions, ensuring the stability of the update process. The resulting top-level module timing library file containing timing information can accurately characterize the timing characteristics of signal transition-type top-level modules, providing reliable timing data support for subsequent chip design processes.

[0062] S400: Read the capacitance and maximum slope information of the port, update the corresponding fields in the top-level module timing library file containing timing information, and obtain the complete top-level module timing library file.

[0063] In this embodiment of the invention, the capacitance and maximum slope information of the ports are read and updated to the corresponding fields in the top-level module timing library file containing timing information, resulting in a complete top-level module timing library file. Port capacitance and maximum slope are key physical parameters characterizing the electrical characteristics of the module. Port capacitance directly affects the signal driving capability assessment, while maximum slope relates to signal integrity and timing convergence accuracy. Both are essential data for subsequent logic synthesis, placement and routing, and verification. Existing technologies often rely on manual parameter input, which is prone to numerical errors, inconsistent units, or missing ports, limiting the usability of the timing library. Therefore, this step supplements key parameters by standardizing parameter extraction, accurately locating fields, writing them sequentially, and verifying them, making the timing library information more complete and ensuring the accuracy and reliability of subsequent chip design processes.

[0064] Step S400 in the method provided in this embodiment of the invention includes: Extract port capacitance and maximum slope information from semiconductor process libraries, device manuals, or underlying module physical parameter documents. Based on the top-level module port list, establish a parameter lookup table of top-level module ports, capacitance values, and maximum slope values ​​to ensure that parameters are accurately associated with ports. Parse the timing library file of the top-level module to locate the preset fields of capacitor and maximum slope corresponding to each port of the top-level module. Read the values ​​from the parameter lookup table in the order of individual process corners and individual top-level module ports, and write them directly into the corresponding preset fields; Verify that all parameter fields in the top-level module ports are free of empty fields, and verify the consistency of the written values ​​with the original parameters and the uniformity of units to ensure that there is no data distortion. Save the verified timing library file to obtain the complete top-level module timing library file.

[0065] First, extract port capacitance and maximum slope information from semiconductor process libraries, device datasheets, or low-level module physical parameter documents. Based on the top-level module port list, establish a parameter lookup table for top-level module ports, capacitance values, and maximum slope values ​​to ensure accurate correlation between parameters and ports. Semiconductor process libraries are standardized library files storing device physical parameters at specific process nodes, serving as the fundamental data source for chip design. Device datasheets are technical documents provided by device suppliers, recording port electrical characteristic parameters. Low-level module physical parameter documents record physical parameter data obtained from actual testing or simulation of low-level module ports. A parameter lookup table is a table that uses top-level module ports as an index to associate corresponding capacitance and maximum slope values, ensuring a one-to-one correspondence between parameters and ports. Extract capacitance and maximum slope values ​​for all ports of the target top-level module at each process corner from the semiconductor process library, device datasheets, or low-level module physical parameter documents. Based on the top-level module port list generated by S100, establish a parameter lookup table according to the dimensions of process corner - top-level port name - capacitance value - maximum slope value to ensure accurate correlation between parameters and ports, and process corners.

[0066] For example, for this signal switching top-level module, port parameters under the TT, SS, and FF process corners are extracted from the semiconductor process library of the target process. These parameters are then verified using the device datasheet, and a parameter comparison table is established: Under the TT process corner, the CK port capacitance is 1.2pF with a maximum slope of 0.8V / ns; the DQ port capacitance is 1.0pF with a maximum slope of 0.7V / ns; the O_CK port capacitance is 1.3pF with a maximum slope of 0.9V / ns; and the O_DQ port capacitance is 1.1pF with a maximum slope of 0.75V / ns. Under the SS process corner, the capacitance values ​​of each port increase by 10%, and the maximum slope decreases by 15%. Under the FF process corner, the capacitance values ​​of each port decrease by 8%, and the maximum slope increases by 20%.

[0067] Next, the top-level module timing library file is parsed to locate the preset capacitor and maximum slope fields corresponding to each top-level module port. The top-level module timing library file contains setup time, hold time, and circuit delay data, and reserves dedicated storage fields for capacitance and maximum slope. The preset capacitor field is a dedicated field in the timing library reserved for the port to store the capacitance value. The preset maximum slope field is a dedicated field in the timing library reserved for the port to store the maximum slope value. The automated parsing tool is started to parse the top-level module timing library files containing timing information for the TT, SS, and FF process corners generated by S300; it matches the port names one by one to locate the preset capacitor and maximum slope fields corresponding to each top-level port, and records the storage location of each field in the file.

[0068] For example, by parsing the "Signal Transfer Top-Level Module_TT.lib" file of the TT process corner, the following fields are located: the capacitor preset field and the maximum slope preset field of the CK port. The corresponding fields of the DQ, O_CK, and O_DQ ports are also identified one by one. Using the same method, the capacitor and maximum slope preset fields of the four ports in the "Signal Transfer Top-Level Module_SS.lib" file of the SS process corner and the "Signal Transfer Top-Level Module_FF.lib" file of the FF process corner are located respectively.

[0069] Furthermore, the values ​​in the parameter lookup table are read sequentially for each process corner and each top-level module port, and then directly written into the corresponding preset fields. First, a process corner is selected, and the capacitance and maximum slope values ​​of the corresponding ports under that process corner are read from the parameter lookup table in the order of the port list. Based on the positions of the preset capacitance and maximum slope fields, the parameters are directly written into the corresponding preset fields. After writing all ports for that process corner, the remaining process corners are processed sequentially. For example, the TT process corner is processed first. The parameters for the TT process corner are read from the parameter lookup table in the order of CK, DQ, O_CK, O_DQ: 1.2pF is written into the capacitance field of the CK port, and 0.8V / ns into its maximum slope field; 1.0pF is written into the capacitance field of the DQ port, and 0.7V / ns into its maximum slope field; similarly, the parameters for the O_CK and O_DQ ports are written. Then, following the same process, the SS and FF process corners are processed sequentially, and the corresponding parameters are written into the preset fields of each port.

[0070] Next, verify that all parameter fields of the top-level module ports are free of empty fields, and verify the consistency of the written values ​​with the original parameters and the uniformity of units to ensure no data distortion. Value consistency means that the written parameter values ​​are completely consistent with the original parameters in the parameter lookup table, without tampering or distortion. Unit uniformity means that the units of all parameters conform to industry standards, with no unit misuse. Traverse the timing library files of all process corners of the top-level module, checking one by one whether the capacitance and maximum slope fields of each port have empty values; compare the written parameter values ​​with the original data in the parameter lookup table to confirm consistency; check whether the units of all parameters are uniform and conform to standards. If empty fields, numerical deviations, or unit errors are found, immediately return to the correction process. For example, the inspection revealed that none of the four ports of the three process corners (TT, SS, and FF) had empty fields; the written 1.2pF capacitance of the TT process corner on the CK port matched the original data in the reference table, and the 1.32pF capacitance (1.2pF × 110%) of the SS process corner and the 1.104pF capacitance (1.2pF × 92%) of the FF process corner also matched; all parameters were uniformly in units of pF and V / ns, with no unit misuse, and the inspection results were qualified.

[0071] Finally, save the verified timing library files to obtain the complete top-level module timing library files. Verified timing library files are those that have been checked and meet the requirements for completeness, accuracy, and unit consistency. Complete top-level module timing library files are standardized files containing basic port information, core timing data, and key physical parameters, and can be directly used in subsequent chip design processes. Rename the process-corner verified timing library files, clearly marking them as complete and including process-corner information; save them to the specified project directory to form a complete set of top-level module timing library files. For example, rename the TT process-corner verified file to "Signal Transition Top-Level Module_TT_Complete.lib", the SS process-corner file to "Signal Transition Top-Level Module_SS_Complete.lib", and the FF process-corner file to "Signal Transition Top-Level Module_FF_Complete.lib"; save these three files to the top-level module timing library directory to ultimately form a complete set of timing library files for this signal transition type top-level module.

[0072] In this embodiment of the invention, port capacitance and maximum slope parameters are extracted from standardized data sources, avoiding errors and inefficiencies caused by manual input. A precise correlation table between process corner, port, and parameter is established to ensure that parameters are not mismatched with ports or process corners. Completeness, accuracy, and unit consistency are verified by writing in a fixed order, eliminating empty fields, data distortion, and unit misuse issues. The resulting complete top-level module timing library file not only contains core timing data but also supplements key physical parameters, fully meeting the needs of subsequent chip design processes such as logic synthesis, placement and routing, and verification. This improves the smoothness of the design process and the reliability of the final product. Furthermore, the standardized process provides a reusable solution for building similar module timing libraries in the future.

[0073] Through the specific implementation methods described above, the embodiments of the present invention achieve the following technical effects: This invention provides a method and system for rapidly constructing a top-level module timing library that supports incremental updates. By splitting complex top-level modules into small-scale bottom-level modules for simulation, a standardized empty timing library is automatically generated. Based on port mapping relationships, the bottom-level timing data is mapped to the top-level ports in parallel and accurately. Then, key parameters such as port capacitance and maximum slope are added. This solves the pain points of long simulation time, high convergence risk, easy data mismatch, and incomplete information in the construction of timing libraries for complex top-level modules. Ultimately, it shortens the construction cycle of timing libraries for multiple process corners, generates a standardized timing library with accurate data and comprehensive information, which can be directly adapted to the entire chip design process, while reducing the cost and risk of constructing timing libraries for similar modules.

[0074] Example 2, as Figure 3 As shown, this invention provides a rapid construction system for a top-level module time-series library that supports incremental updates. The system includes: The empty timing library generation module 11 is used to obtain the hardware description language file and multiple process corner information of the target top-level module, identify the port information in the hardware description language file, and generate multiple empty timing library files, wherein the empty timing library files only contain port information; The underlying information acquisition module 12 is used to acquire the timing information and port mapping relationship file of the underlying modules contained in the target top-level module; The timing mapping update module 13 is used to map the timing information of the lower-level module to the corresponding top-level module port based on the port mapping relationship file, and synchronously complete the parallel incremental update of multiple empty timing libraries to generate a top-level module timing library file containing timing information. The parameter supplementation and improvement module 14 is used to read the capacitance and maximum slope information of the port and update the corresponding fields in the top-level module timing library file containing timing information to obtain the complete top-level module timing library file.

[0075] In one embodiment, the empty time series library generation module 11 is further configured to: Obtain the hardware description language file of the target top-level module, and automatically parse the hardware description language file to extract port information using the port recognition algorithm built into the script; Acquire multiple process corner information, wherein the process corner information includes at least the process deviation range, the power supply voltage range, and the operating temperature range; Based on the port information, the corresponding port information is matched for the multiple process corner information and a timing library framework is constructed, generating multiple empty timing library files that only contain port information.

[0076] The port information includes port type and signal transmission direction information, and the port type includes clock port and data port.

[0077] In one embodiment, the underlying information acquisition module 12 is further configured to: Obtain all the underlying modules contained in the target top-level module, form a list of underlying modules, and label the function of each underlying module; For each underlying module in the underlying module list, the underlying module timing library file under each process corner is obtained through semiconductor device simulation. The underlying module timing library file contains the setup time, hold time or circuit delay data of the timing-related ports of the corresponding underlying module. Compile a port mapping relationship file in the form of a table containing the top-level module port name, the corresponding bottom-level module name, and the corresponding bottom-level module port name. The top-level module port and the corresponding bottom-level module port are not logically directly connected.

[0078] Specifically, for each underlying module in the underlying module list, the timing library file for each process corner is obtained through semiconductor device simulation, including: Randomly select the first bottom module in the list of bottom modules, retrieve its corresponding hardware description language file, associate the multiple process corner information, clarify the process deviation, power supply voltage and operating temperature parameters corresponding to each process corner, and form a simulation parameter comparison table. Set up a semiconductor device simulation environment, import the hardware description language file of the first underlying module and the process library file that matches the process corner, and configure the simulation environment variables for each process corner according to the simulation parameter reference table. Design a suitable simulation excitation signal based on the port type of the first bottom module, start the simulation and execute the simulation tasks under each process corner one by one, and collect timing data such as setup time, hold time, and circuit delay of the bottom module port. Valid simulation data under each process corner are selected, the data are organized according to the standard timing library format and the corresponding process corner information is labeled, and the first bottom-level module timing library file is generated. The timing library files for the remaining underlying modules in the underlying module list are generated sequentially to form a set of underlying module timing libraries.

[0079] In one embodiment, the timing mapping update module 13 is further configured to: Load the port mapping relationship file, underlying module timing information and multiple empty timing libraries, and establish an association index between empty timing libraries and underlying module timing information under the same process corner; Parse the port mapping relationship file and match the establishment time, hold time, and circuit delay data in the timing information of the underlying module with the corresponding top-level module ports in the empty timing library. Map the matched timing information of the underlying modules to the preset fields of the corresponding top-level module ports; A multi-process-angle parallel execution method is adopted to synchronously complete the incremental update of all empty timing libraries and generate the top-level module timing library file containing timing information.

[0080] The process of mapping the timing information of the matched lower-level modules to the corresponding top-level module ports includes the following preset fields: Based on the port mapping relationship file, check the non-logical direct connection correspondence between the bottom port corresponding to the timing information of the bottom module and the top module port in the empty timing library, and confirm that the two belong to the same process angle. The empty timing library file is parsed, and the preset timing fields corresponding to the top-level module ports are located according to the parameter types of setup time, hold time, and circuit delay. Extract the valid underlying time series data after matching, and write it into the preset time series field using a direct mapping method.

[0081] The process employs a multi-process-angle parallel execution method to synchronously complete incremental updates of all empty timing libraries, generating top-level module timing library files containing timing information, including: Initialize a multi-threaded parallel execution environment, synchronously associate the semi-completed multi-process corner timing library files, process corner list and dynamic load balancing configuration rules that have been processed by timing data writing, and establish a process corner-semi-completed timing library file association index; Based on the task volume evaluation index in the dynamic load balancing configuration rules, the incremental update task volume corresponding to each process corner is quantitatively evaluated, and a list containing the task weights of each process corner is generated. Computing resources are dynamically allocated based on the task weight list, incremental update tasks for all process corners are started synchronously, the progress of each task is monitored in real time, and idle computing resources are automatically added to tasks that are lagging behind. The system collects progress data of update tasks in real time for each process corner, triggers restarts for threads that experience lag and resumes from breakpoints, and pauses the corresponding task, marks the exception, and generates a report for detected data writing errors. After all process corner update tasks are completed, the parallel environment is terminated, integrity checks are performed on the timing library files of each process corner, and the files are classified, named, and marked as updated as complete according to the process corner type. The timing library files of the top-level module are then integrated and output.

[0082] In one embodiment, the parameter completion module 14 is further configured to: Extract port capacitance and maximum slope information from semiconductor process libraries, device manuals, or underlying module physical parameter documents. Based on the top-level module port list, establish a parameter lookup table of top-level module ports, capacitance values, and maximum slope values ​​to ensure that parameters are accurately associated with ports. Parse the timing library file of the top-level module to locate the preset fields of capacitor and maximum slope corresponding to each port of the top-level module. Read the values ​​from the parameter lookup table in the order of individual process corners and individual top-level module ports, and write them directly into the corresponding preset fields; Verify that all parameter fields in the top-level module ports are free of empty fields, and verify the consistency of the written values ​​with the original parameters and the uniformity of units to ensure that there is no data distortion. Save the verified timing library file to obtain the complete top-level module timing library file.

[0083] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0085] This specification and accompanying drawings are merely illustrative examples of the invention and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its scope. Therefore, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is intended to include these modifications and modifications.

Claims

1. A method for rapidly constructing a top-level module time-series library that supports incremental updates, characterized in that, include: The hardware description language file and multiple process corner information of the target top-level module are obtained, the port information in the hardware description language file is identified, and multiple empty timing library files are generated, wherein the empty timing library files only contain port information. Obtain the timing information and port mapping relationship file of the underlying modules contained in the target top-level module; Based on the port mapping relationship file, the timing information of the underlying module is mapped to the corresponding top-level module port, and the parallel incremental update of multiple empty timing libraries is completed synchronously to generate a top-level module timing library file containing timing information. The capacitance and maximum slope information of the port are read and updated to the corresponding fields in the top-level module timing library file containing timing information to obtain the complete top-level module timing library file.

2. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 1, characterized in that, Obtain the hardware description language file and multiple process corner information of the target top-level module, identify the port information in the hardware description language file, and generate multiple empty timing library files, including: Obtain the hardware description language file of the target top-level module, and automatically parse the hardware description language file to extract port information using the port recognition algorithm built into the script; Acquire multiple process corner information, wherein the process corner information includes at least the process deviation range, the power supply voltage range, and the operating temperature range; Based on the port information, the corresponding port information is matched for the multiple process corner information and a timing library framework is constructed, generating multiple empty timing library files that only contain port information.

3. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 2, characterized in that, The port information includes port type and signal transmission direction information. The port type includes clock port and data port.

4. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 1, characterized in that, Obtain the timing information and port mapping relationship file of the underlying modules contained in the target top-level module, including: Obtain all the underlying modules contained in the target top-level module, form a list of underlying modules, and label the function of each underlying module; For each underlying module in the underlying module list, the underlying module timing library file under each process corner is obtained through semiconductor device simulation. The underlying module timing library file contains the setup time, hold time or circuit delay data of the timing-related ports of the corresponding underlying module. Compile a port mapping relationship file in the form of a table containing the top-level module port name, the corresponding bottom-level module name, and the corresponding bottom-level module port name. The top-level module port and the corresponding bottom-level module port are not logically directly connected.

5. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 4, characterized in that, For each underlying module in the aforementioned underlying module list, the timing library file for each process corner is obtained through semiconductor device simulation, including: Randomly select the first bottom module in the list of bottom modules, retrieve its corresponding hardware description language file, associate the multiple process corner information, clarify the process deviation, power supply voltage and operating temperature parameters corresponding to each process corner, and form a simulation parameter comparison table. Set up a semiconductor device simulation environment, import the hardware description language file of the first underlying module and the process library file that matches the process corner, and configure the simulation environment variables for each process corner according to the simulation parameter reference table. Design a suitable simulation excitation signal based on the port type of the first bottom module, start the simulation and execute the simulation tasks under each process corner one by one, and collect timing data such as setup time, hold time, and circuit delay of the bottom module port. Valid simulation data under each process corner are selected, the data are organized according to the standard timing library format and the corresponding process corner information is labeled, and the first bottom-level module timing library file is generated. The timing library files for the remaining underlying modules in the underlying module list are generated sequentially to form a set of underlying module timing libraries.

6. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 1, characterized in that, Based on the port mapping relationship file, the timing information of the lower-level modules is mapped to the corresponding top-level module ports, and parallel incremental updates of multiple empty timing libraries are completed synchronously, generating a top-level module timing library file containing timing information, including: Load the port mapping relationship file, underlying module timing information and multiple empty timing libraries, and establish an association index between empty timing libraries and underlying module timing information under the same process corner; Parse the port mapping relationship file and match the establishment time, hold time, and circuit delay data in the timing information of the underlying module with the corresponding top-level module ports in the empty timing library. Map the matched timing information of the underlying modules to the preset fields of the corresponding top-level module ports; A multi-process-angle parallel execution method is adopted to synchronously complete the incremental update of all empty timing libraries and generate the top-level module timing library file containing timing information.

7. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 6, characterized in that, The matched timing information of the lower-level modules is mapped to preset fields of the corresponding upper-level module ports, including: Based on the port mapping relationship file, check the non-logical direct connection correspondence between the bottom port corresponding to the timing information of the bottom module and the top module port in the empty timing library, and confirm that the two belong to the same process angle. The empty timing library file is parsed, and the preset timing fields corresponding to the top-level module ports are located according to the parameter types of setup time, hold time, and circuit delay. Extract the valid underlying time series data after matching, and write it into the preset time series field using a direct mapping method.

8. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 6, characterized in that, Employing a multi-process-angle parallel execution approach, incremental updates to all empty timing libraries are completed synchronously, generating a top-level module timing library file containing timing information, including: Initialize a multi-threaded parallel execution environment, synchronously associate the semi-completed multi-process corner timing library files, process corner list and dynamic load balancing configuration rules that have been processed by timing data writing, and establish a process corner-semi-completed timing library file association index; Based on the task volume evaluation index in the dynamic load balancing configuration rules, the incremental update task volume corresponding to each process corner is quantitatively evaluated, and a list containing the task weights of each process corner is generated. Computing resources are dynamically allocated based on the task weight list, incremental update tasks for all process corners are started synchronously, the progress of each task is monitored in real time, and idle computing resources are automatically added to tasks that are lagging behind. The system collects progress data of update tasks in real time for each process corner, triggers restarts for threads that experience lag and resumes from breakpoints, and pauses the corresponding task, marks the exception, and generates a report for detected data writing errors. After all process corner update tasks are completed, the parallel environment is terminated, integrity checks are performed on the timing library files of each process corner, and the files are classified, named, and marked as updated as complete according to the process corner type. The timing library files of the top-level module are then integrated and output.

9. The method for rapidly constructing a top-level module time-series library supporting incremental updates as described in claim 1, characterized in that, The capacitance and maximum slope information of the port are read and updated to the corresponding fields in the top-level module timing library file containing timing information, resulting in a complete top-level module timing library file, including: Extract port capacitance and maximum slope information from semiconductor process libraries, device manuals, or underlying module physical parameter documents. Based on the top-level module port list, establish a parameter lookup table of top-level module ports, capacitance values, and maximum slope values ​​to ensure that parameters are accurately associated with ports. Parse the timing library file of the top-level module to locate the preset fields of capacitor and maximum slope corresponding to each port of the top-level module. Read the values ​​from the parameter lookup table in the order of individual process corners and individual top-level module ports, and write them directly into the corresponding preset fields; Verify that all parameter fields in the top-level module ports are free of empty fields, and verify the consistency of the written values ​​with the original parameters and the uniformity of units to ensure that there is no data distortion. Save the verified timing library file to obtain the complete top-level module timing library file.

10. A system for rapidly building a top-level module time-series library that supports incremental updates, characterized in that: The system is used to implement the method for rapid construction of a top-level module time-series library supporting incremental updates as described in any one of claims 1-9, the system comprising: An empty timing library generation module is used to obtain the hardware description language file and multiple process corner information of the target top-level module, identify the port information in the hardware description language file, and generate multiple empty timing library files, wherein the empty timing library files only contain port information; The underlying information acquisition module is used to acquire the timing information and port mapping relationship file of the underlying modules contained in the target top-level module; The timing mapping update module is used to map the timing information of the lower-level module to the corresponding top-level module port based on the port mapping relationship file, and synchronously complete the parallel incremental update of multiple empty timing libraries to generate a top-level module timing library file containing timing information. The parameter supplementation and improvement module is used to read the capacitance and maximum slope information of the port and update the corresponding fields in the top-level module timing library file containing timing information to obtain the complete top-level module timing library file.

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