Design method of logic circuit, analysis platform and logic circuit

Abstract

The application discloses a design method of a logic circuit, an analysis platform and the logic circuit, and relates to the chip manufacturing field, wherein the method comprises the following steps: determining whether a timing path meets the following preset conditions: a combinational logic unit of the timing path is located in a always-on power domain, a target buffer connected with the combinational logic unit is located in a switchable power domain, and a plurality of end nodes connected with the target buffer comprise a first end node located in the always-on power domain and a second end node located in the switchable power domain; in the case that the timing path meets the preset conditions, generating an intermediate buffer, the intermediate buffer comprising a first type of buffer located in the switchable power domain; connecting the target buffer, the intermediate buffer and the first end node.

Description

Technical Field

[0001] This disclosure relates to the field of chip manufacturing technology, and more particularly to a logic circuit design method, analysis platform, and logic circuit. Background Technology

[0002] Low power consumption is a key concern in logic circuit design. Power shut-off (PSO) technology can be used to turn off the power supply to a specific area or submodule within a chip circuit, thereby reducing static power consumption. When an off-domain receives a power switch signal, it shuts down the local power supply of the standard cells (or instance cells) on their power rails, causing these standard cells to cease operation and reduce power consumption. Meanwhile, some special standard cells, such as specific types of buffers, ISOs (isolation cells), and LVLs (level shifters), are connected to the global power supply and continue to operate and transmit data. These data signals are typically sent to the always-on domain (AO domain), and this transmission is achieved through timing paths across power domains.

[0003] In practice, in some timing paths that cross power domains, the physical distance between the sink DFF in the normally-on power domain and the sink DFF in the turn-off power domain is often significant. To avoid conformal low-power (CLP) violations and further maximum level transition violations due to excessive distance, related technologies typically incorporate multiple buffers in the normally-on power domain to correct this timing path. While this approach can simultaneously satisfy the requirements of level transitions and CLP checks, it incurs additional power consumption and area requirements. Summary of the Invention

[0004] This disclosure provides a logic circuit design method, analysis platform, and logic circuit.

[0005] In a first aspect, embodiments of this disclosure provide a logic circuit design method, comprising: determining whether a timing path satisfies the following preset conditions: the combinational logic unit of the timing path is located in a normally open power domain, the target buffer connected to the combinational logic unit is located in a turn-off power domain, and a plurality of end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain; if the timing path satisfies the preset conditions, generating an intermediate buffer, the intermediate buffer including a buffer of a first type located in the turn-off power domain; and connecting the target buffer, the intermediate buffer, and the first end node.

[0006] Secondly, embodiments of this disclosure provide a logic circuit analysis platform, including an acquisition unit, an analysis unit, and an optimization unit. The acquisition unit is configured to acquire the logic circuit to be analyzed. The analysis unit is configured to analyze timing paths in the logic circuit to determine whether a timing path exists that satisfies preset conditions. The preset conditions include: the combinational logic unit of the timing path is located in a normally open power domain, the target buffer connected to the combinational logic unit is located in a turn-off power domain, and multiple end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain. The optimization unit is configured to, for a timing path that satisfies the preset conditions, disconnect the target buffer from the first end node in the timing path and process it using the logic circuit design method described in the above embodiments to generate a new timing path.

[0007] Thirdly, embodiments of this disclosure provide a logic circuit, including a timing path obtained based on the design method of the logic circuit in the above embodiments.

[0008] The logic circuit design method of this disclosure determines whether there is a violation risk due to excessive distance in the timing path across power domains in the logic circuit by using preset conditions. For timing paths that meet the preset conditions, an intermediate buffer is generated in the power-off domain, and the target buffer, the intermediate buffer and the first end node located in the normally open power domain are connected to form a shorter path branch. This not only reduces the load caused by distance and makes the timing path meet the requirements of level conversion and low power consumption check, but also eliminates the need to set a large number of buffers in the normally open power domain, thereby reducing additional power consumption and area loss.

[0009] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings are used to provide an understanding of the technical solutions disclosed herein and form part of the specification. They are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure and do not constitute a limitation on the technical solutions of the present disclosure.

[0011] Figure 1 This is a schematic diagram of timing paths across power domains in related technologies; Figure 2 This is a flowchart illustrating an embodiment of the logic circuit design method of this disclosure; Figure 3 This is a schematic diagram of a sequential circuit in one embodiment of the logic circuit design method of this disclosure; Figure 4 A schematic flowchart illustrating the generation of a second type of buffer in one embodiment of the logic circuit design method of this disclosure; Figure 5 This is a schematic diagram of the structure of an embodiment of the logic circuit analysis platform of this disclosure. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0013] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0014] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0015] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0016] Generally, the greater the physical distance between instantiated standard cells in a logic circuit, the greater the load on the timing path, and correspondingly, the greater the risk of timing path low-power check violations and level transition violations.

[0017] In related technologies, to avoid low-power check violations and level transition violations in timing paths across power domains, multiple buffers are typically set up in the normally open power domain. The path branches formed by connecting multiple buffers reduce the load on the timing path. The following section combines... Figure 1 Provide an example, such as Figure 1 As shown, the outer L-shaped area is the normally-on (AO) power domain, and the inner square area is the off-state power domain. The AO domain is powered by the global power supply, and the instantiated standard cells within it are always powered on, regardless of whether the logic circuit is powered on or off. For the off-state power domain, when the logic circuit is powered on, it is powered by the local power supply, and the instantiated standard cells within it are powered on. When the logic circuit is powered off, the local power supply is turned off, and the normal instantiated standard cells in the off-state power domain are powered off and cease operation. However, some special instantiated standard cells, such as always-on cells, are powered by the global power supply to maintain their state and continuously output signals.

[0018] Figure 1 This shows a portion of the timing path: combinational logic units located in normally open power domains (such as...) Figure 1 (comb) and P-type buffers located in the turn-off power domain (such as...) Figure 1 Connect the Pbuffs in the middle, and then connect multiple end nodes (such as...) Figure 1 The cell in the middle is connected to the P-type buffer connection, wherein part of the end node is located in the power-off domain, and part of the end node (such as...) is located in the power-off domain. Figure 1 Cell0 in the normally open power domain is located in the normally open power domain. When the distance between the end node in the normally open power domain and the P-type buffer is large, directly connecting the P-type buffer to the end node will result in a large load on the timing path, which may lead to a low-power check violation, and thus a maximum level transition violation. To address this, related technologies set up multiple series-connected ordinary type buffers (such as...) in the normally open power domain. Figure 1 The timing path can be reduced by connecting the combinational logic unit to the end node through multiple ordinary type buffers, thereby meeting the requirements of low power check and level conversion. However, the added buffers increase the hardware cost and area consumption. In addition, if the timing path is a critical path, too many buffers may make the timing path difficult to converge.

[0019] To address the aforementioned problems, embodiments of this disclosure provide a logic circuit design method, such as... Figure 2As shown, the method may include the following steps.

[0020] Step 210: Determine whether the timing path meets the preset conditions.

[0021] The preset conditions include: the combinational logic unit of the timing path is located in the normally open power domain, the target buffer connected to the combinational logic unit is located in the turn-off power domain, and the multiple end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain.

[0022] In this embodiment, the preset conditions can characterize the load of the timing path. A timing path that meets the preset conditions has a larger load pressure, and correspondingly, the risk of low-power check violations and level transition violations in that timing path is also greater. The target buffer can be a normally open instantiated standard cell, such as a P-type buffer (which can also be represented as Pbuff).

[0023] In this embodiment, the combinational logic unit can receive the signal sent by the upper-level instantiated standard unit and pass the signal to the target buffer, and then distribute it to the flip-flops (Sink DFF) of each end node through the target buffer, thereby realizing the cross-power domain transmission of the signal.

[0024] Step 220: If the timing path meets the preset conditions, generate an intermediate buffer.

[0025] The intermediate buffer includes a first type of buffer located in the power-off domain.

[0026] In this embodiment, the intermediate buffer refers to a buffer located between the target buffer and the end node in the timing path, used to connect the target buffer and the first end node. The first type of buffer can be a normally open instantiated standard cell to maintain a shop state when the local power supply of the power-off domain is turned off, so as to continuously receive the signal output by the target buffer and distribute it to each end node. As an example, the first type of buffer can be a P-type buffer.

[0027] Step 230: Connect the target buffer, intermediate buffer and first end node.

[0028] As an example, the output of the target buffer can be connected to the input of the intermediate buffer, and then the output of the intermediate buffer can be connected to each of the first end nodes. When multiple intermediate buffers exist, they can be connected in series.

[0029] The following is combined with Figure 3 For example, in Figure 3 In the timing path shown, combinational logic unit 310 (e.g. Figure 3(comb in the middle) and the first end node 320 (e.g.) Figure 3 All cells in the target buffer 330 are located in the normally open power domain (AO domain). Figure 3 (Pbuff in the middle) and multiple second end nodes 340 (such as Figure 3 The cell in the diagram is located in the off domain. When the first end node 320 is far from the target buffer 330, to avoid violations, the relevant technology adopts... Figure 1 The path branches are formed in the manner shown. In this embodiment, a first type of buffer 350 (such as...) is set in the power-off domain. Figure 3 Pbuff1 in the middle serves as an intermediate buffer connecting the target buffer 330 and the first end node 320. This maintains continuous signal transmission while shortening the distance between instantiated standard cells, thus reducing the timing path load and avoiding or mitigating low-power check violations and level transition violations. Furthermore, it is compatible with... Figure 1 In comparison, this embodiment uses fewer buffers of the first type, which reduces the hardware cost and area consumption of the logic circuit on the one hand, and reduces the logic technology of the timing path on the other hand, thus meeting the timing requirements.

[0030] In some optional implementations of this embodiment, Figure 2 The process shown may also include: step 240, connecting the second end node to the target buffer.

[0031] like Figure 2 As shown, the second end node 340 can be connected to the output of the target buffer 330.

[0032] In this embodiment, a preset condition is used to determine whether there is a risk of violation due to excessive distance in the timing path across power domains in the logic circuit. For timing paths that meet the preset condition, an intermediate buffer is generated in the power-off domain, and the target buffer, the intermediate buffer and the first end node located in the normally open power domain are connected to form a shorter path branch. This not only reduces the load caused by distance and makes the timing path meet the requirements of level conversion and low power consumption check, but also eliminates the need to set a large number of buffers in the normally open power domain, thereby reducing additional power consumption and area loss.

[0033] In some embodiments, step 220 above can generate intermediate buffers in the following manner: based on the distance between the target buffer and the end node, one or more first-type buffers are generated in series between the target buffer and the first end node, such that: when the number of first-type buffers is 1, the distance between the target buffer and the first-type buffers is less than a preset distance threshold; when the number of first-type buffers is greater than 1, the distance between the first first-type buffer closest to the target buffer and the target buffer, as well as the distance between any two adjacent first-type buffers, does not exceed the distance threshold.

[0034] As an example, if the distance between the target buffer and the first end node is greater than the distance threshold but less than twice the distance threshold, a first-type buffer can be generated between them, such that the distance between the first-type buffer and the target buffer is less than the distance threshold; if the distance between the target buffer and the first end node is greater than twice the distance threshold, multiple first-type buffers can be generated in series between them, such that the distance between the first first-type buffer closest to the target buffer and the target buffer, as well as the distance between any two adjacent first-type buffers, does not exceed the distance threshold.

[0035] In this embodiment, the distance threshold can be determined based on the correspondence between distance and load in the logic circuit. If the distance between two instantiated standard units is greater than the distance threshold, it indicates that the two instantiated standard units bring a large load to the timing path, resulting in a higher risk of low-power check violations and level transition violations in the timing path. The smaller the distance threshold, the lower the risk of low-power check violations and level transition violations in the timing path, but correspondingly, the number of intermediate buffers generated is more, and the hardware cost and area consumption are greater. For example, the distance threshold can be 90 micrometers, 80 micrometers, or others.

[0036] In some implementations of this embodiment, the distance threshold can be 100 micrometers. This ensures that the distance between two instantiated standard units does not cause a large load, and also avoids introducing more hardware costs and area consumption.

[0037] In this embodiment, one or more buffers of the first type are generated between the target buffer and the first end node according to the distance threshold. This ensures that the distance between the target buffer and the intermediate buffer or between two adjacent intermediate buffers does not exceed the distance threshold. This can prevent the timing path from being overloaded due to excessive distance and help reduce the risk of timing path violations.

[0038] In some embodiments of this example, when the number of first end nodes is greater than 1, the intermediate buffer further includes a second type of buffer; and step 220 may further include: when the number of first end nodes is greater than 1, generating a plurality of second type buffers in the normally open power domain, the plurality of second type buffers being used to connect all first end nodes to the last first type buffer furthest from the target buffer.

[0039] In this embodiment, the second type of buffer can be a regular buffer used to connect the first end node to the last first type of buffer. In this way, the signal of the target buffer can be distributed to each first end node through the first type of buffer and the second type of buffer.

[0040] In one example of this implementation, it can be achieved through Figure 4 The process shown generates multiple second-type buffers, such as Figure 4 As shown, the process may include the following steps.

[0041] Step 410: Generate multiple second-type buffers in the normally open power domain, and connect the second-type buffers to the first end node to form multiple path branches corresponding one-to-one with the multiple first end nodes.

[0042] In this system, the endpoint of each path branch corresponds to a first end node, and the starting point of each path branch is a buffer of type 2, with the distance between the starting point and the last buffer of type 1 exceeding a distance threshold.

[0043] Step 420: If the distance between the start and end points of a path branch exceeds a distance threshold, generate one or more cascaded second-type buffers in the path branch, such that the distance between the second-type buffer closest to the end point and the end point, as well as the distance between any two adjacent second-type buffers, does not exceed the distance threshold.

[0044] As an example, assuming the number of first end nodes is 3, 3 path branches are set in the normally open power domain, each path branch corresponding to one first end node and one second-type buffer. If the distance between the start and end points of a path branch is less than or equal to a distance threshold, no new second-type buffer needs to be generated in that path branch. If the distance between the start and end points of a path branch is greater than the distance threshold, one or more cascaded second-type buffers of the second type are inserted between the start and end points of the path branch, such that the distance between the nearest second-type buffer to the end point and the end point, as well as the distance between any two adjacent second-type buffers, does not exceed the distance threshold. For example, assuming the distance threshold is 100 micrometers and the distance between the start and end points is 400 micrometers, two second-type buffers can be inserted between them, such that the distance between any two instantiated standard cells is 100 micrometers. In this way, the path branch can include 3 second-type buffers and 1 first end node.

[0045] In this example, a path branch is generated for each first end node to connect each first end node to the last buffer of the first type. The number of buffers of the second type in the path branch is determined according to the distance threshold, so that the distance between any two instantiated standard units does not exceed the distance threshold. This can avoid excessive load on the path branch, thereby avoiding or reducing the risk of violations in the timing path.

[0046] according to Figure 4 As shown in the example, step 230 above may include the following steps: when the number of buffers of the first type is greater than 1 and the number of first end nodes is 1, after concatenating multiple buffers of the first type, connect the first buffer of the first type to the target buffer and connect the last buffer of the first type to the first end node; when both the number of buffers of the first type and the number of first end nodes are greater than 1, after concatenating multiple buffers of the first type, connect the first buffer of the first type to the target buffer and connect the last buffer of the first type to the starting point of each path branch.

[0047] In this example, the connection method can be adopted according to the number of first end nodes, so that each first end node can be connected to the target end node through an intermediate buffer, which can ensure the reliability of timing path signal transmission.

[0048] In practice, logic circuit design is typically accomplished using specialized tools (ARP tools), such as Innovus or ICC2. These tools usually employ [specific tools] to design timing paths that meet preset conditions. Figure 1The method shown can be used to process timing paths. For some completed logic circuits, if the designer manually identifies and optimizes such timing paths, it will take a lot of time and effort.

[0049] To address the aforementioned problems, embodiments of this disclosure also provide an analysis platform for logic circuits, such as... Figure 5 As shown, the analysis platform includes an acquisition unit 510, an analysis unit 520, and an optimization unit 530. The acquisition unit 510 is configured to acquire the logic circuit to be analyzed. The analysis unit 520 is configured to analyze the timing paths in the logic circuit to determine whether there are timing paths in the logic circuit that meet preset conditions. The preset conditions include: the combinational logic unit of the timing path is located in the normally open power domain, the target buffer connected to the combinational logic unit is located in the turn-off power domain, and the multiple end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain. The optimization unit 530 is configured to disconnect the target buffer from the first end node in the timing path for the timing path that meets the preset conditions, and process it using the logic circuit design method in any of the above embodiments to generate a new timing path.

[0050] The logic circuit analysis platform in this embodiment can automatically identify timing paths in the logic circuit that meet preset conditions, and optimize them using the logic circuit design method described in the above embodiment. This can improve the optimization efficiency and quality of the logic circuit.

[0051] This disclosure also provides a logic circuit, including a timing path obtained based on the logic circuit design method in any of the above embodiments.

[0052] In this embodiment, the logic circuit generates an intermediate buffer in the power-off domain for timing paths that meet preset conditions, and connects the target buffer, the intermediate buffer, and the first end node located in the normally-on power domain to form a shorter path branch. This not only reduces the load caused by distance and enables the timing path to meet the requirements of level conversion and low-power checks, but also eliminates the need to set up a large number of buffers in the normally-on power domain, thereby reducing additional power consumption and area loss, which helps to improve the overall performance of the logic circuit and reduce the cost of the logic circuit.

[0053] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for designing logic circuits, characterized in that, include: Determine whether the timing path meets the following preset conditions: the combinational logic unit of the timing path is located in the normally open power domain, the target buffer connected to the combinational logic unit is located in the turn-off power domain, and the multiple end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain. When the timing path satisfies the preset conditions, an intermediate buffer is generated, the intermediate buffer including a first type of buffer located in the power-off domain; Connect the target buffer, the intermediate buffer, and the first end node.

2. The method according to claim 1, characterized in that, The generation of intermediate buffers includes: Based on the distance between the target buffer and the end node, one or more first-type buffers are generated in series between the target buffer and the first end node, such that: when the number of first-type buffers is 1, the distance between the target buffer and the first-type buffer is less than a preset distance threshold; when the number of first-type buffers is greater than 1, the distance between the first first-type buffer closest to the target buffer and the target buffer, as well as the distance between any two adjacent first-type buffers, does not exceed the distance threshold.

3. The method according to claim 2, characterized in that, When the number of the first end nodes is greater than 1, the intermediate buffer further includes a second type of buffer; and, The generation of intermediate buffers further includes: when the number of the first end nodes is greater than 1, generating a plurality of second-type buffers in the normally open power domain, wherein the plurality of second-type buffers are used to connect all the first end nodes to the last first-type buffer that is furthest from the target buffer.

4. The method according to claim 3, characterized in that, Multiple buffers of the second type are generated in the normally open power domain, including: Multiple buffers of the second type are generated in the normally open power domain, and the buffers of the second type are connected to the first end node to form multiple path branches corresponding one-to-one with the multiple first end nodes; the end point of each path branch corresponds to a first end node, and the starting point of each path branch is a buffer of the second type and the distance between the starting point and the last buffer of the first type exceeds the distance threshold. If the distance between the start and end points of the path branch exceeds the distance threshold, one or more cascaded buffers of the second type are generated in the path branch such that the distance between the second type buffer closest to the end point and the end point, as well as the distance between any two adjacent second type buffers, does not exceed the distance threshold.

5. The method according to claim 4, characterized in that, Connecting the target buffer, the intermediate buffer, and the first end node includes: When the number of buffers of the first type is greater than 1 and the number of the first end nodes is 1, multiple buffers of the first type are connected in series, the first buffer of the first type is connected to the target buffer, and the last buffer of the first type is connected to the first end node. When the number of buffers of the first type and the number of the first end nodes are both greater than 1, multiple buffers of the first type are connected in series, the first buffer of the first type is connected to the target buffer, and the last buffer of the first type is connected to the starting point of each path branch.

6. The method according to claim 2, characterized in that, The distance threshold is 100 micrometers.

7. The method according to claim 3, characterized in that, The target buffer and the first type of buffer are both P-type buffers; the second type of buffer is a regular buffer.

8. The method according to claim 1, characterized in that, Also includes: Connect the second end node to the target buffer.

9. An analysis platform for logic circuits, comprising an acquisition unit, an analysis unit, and an optimization unit, wherein, The acquisition unit is configured to acquire the logic circuit to be analyzed; The analysis unit is configured to: analyze the timing path in the logic circuit and determine whether there is a timing path in the logic circuit that meets preset conditions. The preset conditions include: the combinational logic unit of the timing path is located in the normally open power domain, the target buffer connected to the combinational logic unit is located in the turn-off power domain, and the multiple end nodes connected to the target buffer include a first end node located in the normally open power domain and a second end node located in the turn-off power domain. The optimization unit is configured to: for a timing path that meets preset conditions, disconnect the connection between the target buffer and the first end node in the timing path, and process it using the logic circuit design method described in any one of claims 1 to 8 to generate a new timing path.

10. A logic circuit, characterized in that, Including timing paths obtained based on the design method of the logic circuit as described in any one of claims 1 to 8.

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