A cross-process universal reliability degradation simulation method and device

Abstract

The application provides a cross-process universal reliability degradation simulation method and device. The method comprises the following steps: obtaining a SPICE netlist and a process library of an integrated circuit to be measured; inputting the SPICE netlist and the process library into a final reaction diffusion model under a corresponding process node in a SPICE simulator to calculate a reaction diffusion equation under a time index; performing linear conversion processing on the reaction diffusion equation in a time step to obtain a linearized diffusion equation; performing time extrapolation processing on the linearized diffusion equation within a preset time to obtain an extrapolated diffusion equation; performing anti-linearization processing on the extrapolated diffusion equation to obtain a threshold voltage total degradation result; and the final reaction diffusion model is fitted based on a reaction diffusion mechanism of the integrated circuit under multiple process nodes. Based on this, the cross-process applicability is significantly improved, the prediction accuracy under actual dynamic working stress is simultaneously improved, and the repeated measurement and calibration costs required due to process changes are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit reliability simulation technology, and specifically to a universal reliability degradation simulation method and apparatus that spans multiple processes. Background Technology

[0002] With the continuous iteration of semiconductor process nodes and the increasing complexity of integrated circuit design, the long-term reliability of chips has become a key factor determining product performance and lifespan. Especially in complex design environments where advanced and diverse process platforms (such as TSMC 28nm and SMIC 55nm) coexist and commercial electronic design automation (EDA) simulation platforms vary widely, efficient and accurate reliability degradation assessment of large-scale integrated circuits faces severe challenges. Traditional simulation methods require repeated model adaptation and calibration across different process nodes and simulation tools, a cumbersome process prone to introducing errors, making it difficult to support standardized reliability assessment processes across platforms and processes. Therefore, establishing a unified reliability modeling and simulation integration method that can adapt to multiple process nodes, is compatible with mainstream simulation platforms, and comprehensively considers various degradation mechanisms, while balancing simulation accuracy and engineering efficiency, has become a core technical problem urgently needing to be solved in the field of chip reliability design.

[0003] To address the aforementioned issues, the industry has conducted numerous research studies. For example, one study proposed a dynamic simulation framework that periodically updates voltage, temperature, and workload parameters to simulate the dynamic stress conditions of circuits during actual operation, thereby more accurately predicting circuit lifetime under negative bias temperature instability effects. Furthermore, a comprehensive modeling method integrates multiple physical mechanism models to accurately predict the threshold voltage drift of transistors under different stress and recovery conditions. Focusing on large-scale digital circuits, solutions have also proposed gate-level reliability assessment frameworks compatible with commercial static timing analysis tools, improving the realism of the assessment by modifying traditional stress probability calculation models.

[0004] However, these existing technical solutions still have several limitations. First, the extraction of parameters for existing research models heavily relies on fitting experimental data to specific process platforms, resulting in a lack of transferability between different process nodes. Process changes necessitate a complete re-measurement and calibration, which is labor-intensive and costly. Second, many models are primarily built and validated based on static or averaged stress conditions. This simplification ignores the instantaneous, non-uniform dynamic stress distribution caused by rapid signal switching and complex operating modes in actual circuits. Therefore, when applied to actual circuits with highly dynamic switching activity, the prediction accuracy of such models is significantly limited, making it difficult to accurately assess the device degradation trajectory under the combined effects of dynamic stress and recovery effects. Thus, existing integrated circuit reliability simulation methods still have fundamental shortcomings in terms of cross-process platform versatility and prediction accuracy under actual dynamic operating stresses. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a universal reliability degradation simulation method and apparatus that spans multiple processes.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a universal reliability degradation simulation method across processes, comprising: Obtain the SPICE netlist and process library of the integrated circuit under test; Input the SPICE netlist and process library into the SPICE simulator to obtain the final reaction-diffusion model under the corresponding process node, and calculate the reaction-diffusion equation under the time exponential. The reaction-diffusion equation is linearized by performing a time-step transformation to obtain a linearized diffusion equation. The linearized diffusion equation is extrapolated over a preset time period to obtain the extrapolated diffusion equation. The extrapolated diffusion equation was delinearized to obtain the total degradation result of the threshold voltage; the final reaction-diffusion model was obtained by fitting the reaction-diffusion mechanism based on integrated circuits at multiple process nodes.

[0007] Secondly, the present invention provides a general reliability degradation simulation device across processes, which includes: an acquisition unit, a calculation unit, a linear transformation unit, a time extrapolation unit, and an anti-linearization processing unit. The acquisition unit is used to acquire the SPICE netlist and process library of the integrated circuit under test; The calculation unit is used to input the SPICE netlist and process library into the final reaction-diffusion model under the corresponding process node in the SPICE simulator, and calculate the reaction-diffusion equation under the time exponential. The linear transformation unit is used to perform a linear transformation of the reaction-diffusion equation in terms of time step, resulting in a linearized diffusion equation. The time extrapolation unit is used to perform time extrapolation processing on the linearized diffusion equation within a preset time to obtain the extrapolated diffusion equation. The delinearization processing unit is used to delinearize the extrapolated diffusion equation to obtain the total degradation result of the threshold voltage; the final reaction-diffusion model is obtained by fitting the reaction-diffusion mechanism based on integrated circuits at multiple process nodes.

[0008] Thirdly, the present invention provides a cross-process universal reliability degradation simulation device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the cross-process universal reliability degradation simulation device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the cross-process universal reliability degradation simulation method as described in the first aspect above.

[0009] This invention provides a universal reliability degradation simulation method and apparatus across multiple process nodes. The universal reliability degradation simulation method includes: acquiring the SPICE netlist and process library of the integrated circuit under test; inputting the SPICE netlist and process library into the final reaction-diffusion model at the corresponding process node in a SPICE simulator to calculate the reaction-diffusion equation under time exponential conditions; performing a linear transformation of the reaction-diffusion equation over a time step to obtain a linearized diffusion equation; performing time extrapolation on the linearized diffusion equation over a preset time period to obtain an extrapolated diffusion equation; performing delinearization on the extrapolated diffusion equation to obtain the total threshold voltage degradation result; and finally, the reaction-diffusion model is obtained by fitting the reaction-diffusion mechanism of the integrated circuit at multiple process nodes. In this invention, by first constructing a universal model based on the reaction-diffusion mechanism of multiple process nodes, the dependence on experimental data from a single process is eliminated, thereby significantly improving the cross-platform portability of the model. Then, by using a linear transformation of the time step and dynamic extrapolation, the model can effectively simulate instantaneous, non-uniform stress distribution and accurately capture the degradation process under dynamic switching activities. This results in a significant improvement in cross-process applicability and a simultaneous increase in prediction accuracy under actual dynamic working stress, while greatly reducing the cost of repeated measurements and calibrations required due to process changes.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 A flowchart illustrating a general reliability degradation simulation method across processes provided in an embodiment of the present invention; Figure 2The fitting results of model parameters under different stress conditions are illustrated exemplarily under the 55nm process. Figure 3 The fitting results of model parameters under different stress conditions are illustrated exemplarily under the 28nm process. Figure 4 An exemplary schematic diagram of the degradation result of any cell in a full adder under a 28nm process is shown; Figure 5 An exemplary schematic diagram of the degradation results of any cell in a full adder using a 55nm process is shown. Figure 6 A schematic diagram of a general reliability degradation simulation device across processes provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a general reliability degradation simulation device that spans multiple processes, provided as an embodiment of the present invention. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0013] To achieve a significant improvement in cross-process applicability and a simultaneous increase in prediction accuracy under actual dynamic working stress, while greatly reducing the cost of repeated measurements and calibrations required due to process changes, this invention provides a general reliability degradation simulation method across processes. Figure 1 A flowchart illustrating a general reliability degradation simulation method across processes provided in this embodiment of the invention is shown below. Figure 1 As shown, it includes: S101. Obtain the SPICE netlist and process library of the integrated circuit under test.

[0014] In this invention, the SPICE netlist describes the circuit connections and device instances of the integrated circuit under test. It lists all components in the circuit (such as transistors, resistors, capacitors, inductors, etc.), the connection nodes of these components, and the model name called for each component.

[0015] S102. Input the SPICE netlist and process library into the SPICE simulator to obtain the final reaction-diffusion model under the corresponding process node, and calculate the reaction-diffusion equation under the time exponential.

[0016] In this embodiment, a process library integrating a general reliability physical model is used to drive a SPICE simulator to perform an enhanced transient simulation of the circuit that considers the degradation physical process. While calculating the circuit's electrical response, the SPICE simulator automatically and point-by-point solves for the device degradation trajectory equations triggered by actual dynamic stresses. This perfectly overcomes the shortcomings of existing technologies that use static / average stress for estimation, achieving accurate capture of degradation behavior under real circuit operating conditions.

[0017] Optionally, the final reaction diffusion model construction process includes: Based on the reaction-diffusion mechanism of integrated circuits, an initial reaction-diffusion model under dynamic stress is constructed. The degradation parameters of the sample integrated circuit at multiple process nodes are obtained. The degradation parameters are then substituted into the initial reaction-diffusion model to obtain the final reaction-diffusion model at multiple process nodes.

[0018] Alternatively, the initial reaction-diffusion model can be expressed as: ; in, Indicates the time of degradation A changing initial reaction-diffusion model. This represents the first nonlinear coefficient. Represents the process fit coefficient. This represents the substrate current of the MOSFET in the integrated circuit under test. This represents the total carrier flux through the channel. This represents the second nonlinear coefficient. Represents the time-fit coefficients. This represents the activation energy, and k represents the Boltzmann constant. Indicates the effective temperature.

[0019] Optionally, degradation parameters of the sample integrated circuit at multiple process nodes are obtained, and these degradation parameters are substituted into the initial reaction-diffusion model to obtain the final reaction-diffusion model at multiple process nodes, including: Obtain the degradation parameters of the sample integrated circuit at multiple process nodes; By substituting the degradation parameters into the initial reaction-diffusion model and using a parameter extraction method that combines distributed parameter extraction with global optimization, the final reaction-diffusion model under multiple process nodes is obtained through fitting.

[0020] Optionally, the degradation parameters are substituted into the initial reaction-diffusion model, and a parameter extraction method combining distributed parameter extraction and global optimization is used to fit the final reaction-diffusion model for multiple process nodes, including: S201. Obtain the current fitting coefficients in the initial reaction-diffusion model; S202. Under the current process node, all fitting coefficients in the initial reaction diffusion model, except for the current fitting coefficients, are used to form a fixed coefficient set. All fitting coefficients in the fixed coefficient set are substituted with fixed values ​​to obtain the current reaction diffusion model. S203. Substitute the degradation parameters into the current reaction-diffusion model and solve for the current fitting coefficients to obtain the current fitting coefficient values; S204. Substitute the current fitting coefficient values ​​into the current reaction-diffusion model, and take the fitting coefficients in the fixed coefficient set as the current fitting coefficients in turn. Repeat steps S201-203 until the fitting coefficients in the fixed coefficient set are empty, and obtain the reaction-diffusion model with distributed parameter extraction. S205. Perform global optimization of all fitting coefficients on the distributed reaction-diffusion model to obtain the final reaction-diffusion model.

[0021] In this embodiment, a two-stage strategy of "distributed parameter extraction + global optimization" is used to accurately extract model parameters under multiple process nodes: first, the current parameter is solved by fixing other parameters one by one (distributed parameter extraction), and then global optimization is performed on all parameters, ensuring both the accuracy of local parameters and global optimality. An example is as follows: First, the process fitting coefficients in the initial reaction-diffusion model can be... As the current fitting coefficient, , , The values ​​are randomly selected and fixed within the empirical range. Then, the degradation parameters are substituted into the initial reaction-diffusion model to calculate the process fit coefficients. The specific data, and then the actual Substitute the initial reaction-diffusion model into the current reaction-diffusion model. Then... As the current fitting coefficient, , Random values ​​were selected and fixed within the empirical range. Then, another set of degenerate parameters was substituted into the current reaction-diffusion model to obtain the results. The specific data will Then, substituting into the current reaction-diffusion model, and repeating the above process, we can... , , , All the values ​​were obtained, and the reaction-diffusion model with distributed parameters was finally obtained.

[0022] Optionally, the reaction-diffusion model with distributed parameter extraction is subjected to global optimization of all fitting coefficients to obtain the final reaction-diffusion model, including: The reaction-diffusion model with distributed parameters was globally optimized under the threshold voltage-time degradation curve to obtain the final reaction-diffusion model.

[0023] S103. Perform a linear transformation of the reaction-diffusion equation based on the time step to obtain a linearized diffusion equation.

[0024] S104. Extrapolate the linearized diffusion equation over a preset time period to obtain the extrapolated diffusion equation.

[0025] S105. The extrapolated diffusion equation is delinearized to obtain the total degradation result of the threshold voltage.

[0026] The final reaction-diffusion model was obtained by fitting the reaction-diffusion mechanism based on integrated circuits at multiple process nodes.

[0027] Optionally, the total degradation result of the threshold voltage is expressed as: ; This represents the total degradation result of the threshold voltage. This represents the initial value of the threshold voltage. This indicates the type parameter of the MOSFET in the integrated circuit under test. When it is NMOS... The value is 1 when it is PMOS. It is -1. Express the extrapolated diffusion equation, Represents the time-fit coefficients. ; in, This represents the result of the linearized diffusion equation. Indicates the timeframe of degradation (in years). This represents the total number of seconds in a year. Indicates the simulation time. ; Indicates the time step. Represents the process fit coefficient. This represents the second nonlinear coefficient. Represents the time-fit coefficients. This represents the activation energy, and k represents the Boltzmann constant. Indicates the effective temperature. This represents the substrate current of the MOSFET in the integrated circuit under test. This represents the total carrier flux through the channel.

[0028] When calculating the total degradation result of the threshold voltage, the final reaction-diffusion model needs to be linearized, transforming it into a linear formula for the time step. At this point, the influence of the corresponding process nodes and dynamic stress needs to be considered. First, the fitting parameters for the corresponding process nodes are loaded by identifying parameters such as gate length and gate width through the simulation interface. Then, due to the high and low levels of dynamic stress, the reaction-diffusion model... The parameters degrade under high-level stress, while under low-level stress, Stop degradation. Therefore, a conditional statement can be set to prevent degradation when a high-level stress is applied. Normal data collection, fitting, and environmental parameter calculation; when a low level is detected, the threshold voltage... It degenerates to 0.

[0029] To verify the effectiveness of the method of this invention, simulation experiments were also conducted. Specifically, the reliability of the device-level final reaction-diffusion (HCI) model was tested and verified. HCI effect degradation experimental data at 55nm, 28nm, and 22nm processes were collected from journals and conferences such as IEEE Transactions on ElectronDevices, IRPS, and IEDM. This included degradation data on threshold voltage drift under different stress voltages, temperatures, and stress times. A total of 80% of the usable experimental data was used for model parameter extraction, and the remaining 20% ​​of the experimental data, which differed from the training set data distribution, was used as the model validation dataset, i.e., the test set, to verify the accuracy of the HCI reliability model across process nodes. The verification results are as follows: Data validation of the HCI reliability model under 55nm and 28nm processes. Figure 2 An illustrative comparison of the prediction results and measured data based on the method of this invention under a 55nm process is shown. Figure 3 An illustrative comparison of the prediction results and measured data based on the method of this invention under a 28nm process is shown, revealing a high degree of agreement.

[0030] The evaluation metric used in this invention is MAPE (Mean Absolute Percentage Error). It represents the average absolute percentage error between the predicted and actual values. A smaller MAPE value means a smaller average relative error between the predicted and actual values, indicating better model accuracy. These are experimental measurements. Here, s represents the model's predicted value, and s represents the number of data points. Indicates the first Data points. A MAPE value below 10% is considered to meet the accuracy requirements for process reliability modeling.

[0031]

[0032] Figure 2 The following examples illustrate the fitting of model parameters under different stress conditions in a 55nm process: Figure 2 As shown, under the same temperature, different Vgs and Vds stresses are applied, and the measured values ​​and model predictions of the threshold voltage drift over time have a high degree of fit. It can be seen that the model of this invention can accurately predict the degradation of the threshold voltage under the 55nm process. Figure 3 The following examples illustrate the fitting of model parameters under different stress conditions in a 28nm process: Figure 3 As shown, under the same temperature and with different Vgs and Vds stresses, the measured values ​​and model predictions of the threshold voltage drift over time show a high degree of fit. This demonstrates that the model of this invention can accurately predict the threshold voltage degradation even at the 28nm process node. Therefore, the model proposed in this invention can achieve cross-process node characteristics, predicting long-term lifetime degradation at both 55nm and 28nm process nodes.

[0033] Furthermore, this invention also validated the final reactive diffusion (HCI) model integrated into a dedicated simulation interface, verifying the simulation performance and cross-process node characteristics of the interface under different SPICE simulators. Taking a full adder in a digital circuit as an example, by configuring the netlist to enable the simulation degradation process, and utilizing the dedicated reliability model simulation interface, the long-term degradation effect can be extrapolated from the transient simulation of the circuit. Moreover, the degradation time in years can be easily modified in the netlist using the `.paramdagetime` parameter.

[0034] During the circuit-level verification of the model, the same netlist was used for simulation on different simulators (HSPICE, ALPS), and a simulation interface integrating the same HCI model was used. Expected degradation results were obtained in both 55nm and 28nm processes. Figure 4 and Figure 5 As shown.

[0035] Figure 4 An exemplary schematic diagram of the degradation results of any cell in a full adder using a 28nm process is shown. Figure 5 An exemplary schematic diagram illustrates the degradation results of any cell in a full adder using a 55nm process. From Figure 4 The results show that the same HCI model was integrated into the simulation interface, and the degradation results were obtained by calling the 28nm process library in two different SPICE simulators. It can be seen that the obtained threshold voltage degradation dVth values ​​are the same, indicating the stability of the model in the circuit-level simulation of the 28nm process. Figure 5The same HCI model was also integrated into the simulation interface. The degradation results obtained by calling the 55nm process library in two different SPICE simulators show that the threshold voltage degradation dVth values ​​are the same, indicating the stability of the model in the circuit-level simulation of the 55nm process.

[0036] This invention provides a universal reliability degradation simulation method across multiple process nodes. First, by constructing a universal model based on the reaction-diffusion mechanism of multiple process nodes, the dependence on experimental data from a single process is eliminated, significantly improving the model's cross-platform portability. Then, through linear transformation of the time step and dynamic extrapolation, the model can effectively simulate instantaneous, non-uniform stress distributions and accurately capture the degradation process under dynamic switching activities. This achieves a significant improvement in cross-process applicability and a simultaneous increase in prediction accuracy under actual dynamic operating stress, while greatly reducing the cost of repeated measurements and calibrations required due to process changes.

[0037] The method provided in this embodiment of the invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc., and this embodiment of the invention does not limit the application to such devices.

[0038] Based on the same inventive concept, embodiments of the present invention also provide a universal reliability degradation simulation device that spans multiple processes. Figure 6 This is a schematic diagram of a general reliability degradation simulation device that spans multiple processes, provided as an embodiment of the present invention. Figure 6 As shown, it includes: an acquisition unit 501, a calculation unit 502, a linear transformation unit 503, a time extrapolation unit 504, and an antilinearization processing unit 505; Acquisition unit 501 is used to acquire the SPICE netlist and process library of the integrated circuit under test; The calculation unit 502 is used to input the SPICE netlist and process library into the final reaction-diffusion model under the corresponding process node in the SPICE simulator, and calculate the reaction-diffusion equation under the time exponential. The linear transformation unit 503 is used to perform a time-step linear transformation on the reaction-diffusion equation to obtain a linearized diffusion equation. The time extrapolation unit 504 is used to perform time extrapolation processing on the linearized diffusion equation within a preset time to obtain the extrapolated diffusion equation. The delinearization processing unit 505 is used to delinearize the extrapolated diffusion equation to obtain the total degradation result of the threshold voltage; the final reaction diffusion model is obtained by fitting the reaction diffusion mechanism based on integrated circuits at multiple process nodes.

[0039] Figure 7A schematic diagram of a cross-process general reliability degradation simulation device provided in this embodiment of the invention includes: a processor 710, a storage medium 720, and a bus 730. The storage medium 720 stores machine-readable instructions executable by the processor 710. When the cross-process general reliability degradation simulation device is running, the processor 710 communicates with the storage medium 720 via the bus 730, and the processor 710 executes the machine-readable instructions to perform the steps of the above-described method embodiment. Specific implementation methods and technical effects are similar and will not be repeated here.

[0040] The storage medium may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the storage medium may also be at least one storage device located remotely from the aforementioned processor.

[0041] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0043] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In this description, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the inventive concept, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A general reliability degradation simulation method across processes, characterized in that, include: Obtain the SPICE netlist and process library of the integrated circuit under test; Input the SPICE netlist and the process library into the SPICE simulator to obtain the final reaction-diffusion model under the corresponding process node, and calculate the reaction-diffusion equation under the time exponential. The reaction-diffusion equation is linearized by performing a time step transformation to obtain a linearized diffusion equation. The linearized diffusion equation is extrapolated over a preset time period to obtain the extrapolated diffusion equation. The extrapolated diffusion equation is delinearized to obtain the total degradation result of the threshold voltage; the final reaction diffusion model is obtained by fitting the reaction diffusion mechanism based on integrated circuits at multiple process nodes.

2. The general reliability degradation simulation method across processes according to claim 1, characterized in that, The process of constructing the final reaction diffusion model includes: Based on the reaction-diffusion mechanism of integrated circuits, an initial reaction-diffusion model under dynamic stress is constructed. The degradation parameters of the sample integrated circuit at multiple process nodes are obtained, and the degradation parameters are substituted into the initial reaction-diffusion model to obtain the final reaction-diffusion model at multiple process nodes.

3. The general reliability degradation simulation method across processes according to claim 2, characterized in that, The initial reaction diffusion model is expressed as follows: ； in, Indicates the time of degradation A changing initial reaction-diffusion model. This represents the first nonlinear coefficient. Represents the process fit coefficient. This represents the substrate current of the MOSFET in the integrated circuit under test. This represents the total carrier flux through the channel. This represents the second nonlinear coefficient. Represents the time-fit coefficients. This represents the activation energy, and k represents the Boltzmann constant. Indicates the effective temperature.

4. The general reliability degradation simulation method across processes according to claim 2, characterized in that, The process of obtaining degradation parameters of the sample integrated circuit at multiple process nodes, substituting these degradation parameters into the initial reaction-diffusion model, and obtaining the final reaction-diffusion model at multiple process nodes includes: Obtain the degradation parameters of the sample integrated circuit at multiple process nodes; The degradation parameters are substituted into the initial reaction-diffusion model, and the final reaction-diffusion model under multiple process nodes is obtained by fitting a parameter extraction method that combines distributed parameter extraction with global optimization.

5. The general reliability degradation simulation method across processes according to claim 4, characterized in that, The step of substituting the degradation parameters into the initial reaction-diffusion model and fitting the final reaction-diffusion model under multiple process nodes based on a parameter extraction method combining distributed parameter extraction and global optimization includes: S201. Obtain the current fitting coefficients in the initial reaction-diffusion model; S202. At the current process node, all fitting coefficients in the initial reaction diffusion model, except for the current fitting coefficient, are used to form a fixed coefficient set. All fitting coefficients in the fixed coefficient set are substituted with fixed values ​​to obtain the current reaction diffusion model. S203. Substitute the degradation parameters into the current reaction-diffusion model and solve for the current fitting coefficients to obtain the current fitting coefficient values; S204. Substitute the current fitting coefficient value into the current reaction-diffusion model, and take the fitting coefficients in the fixed coefficient set as the current fitting coefficients in turn. Repeat steps S201-203 until the fitting coefficients in the fixed coefficient set are empty, and obtain the distributed parameter extraction reaction-diffusion model. S205. Perform global optimization of all fitting coefficients on the distributed reaction-diffusion model to obtain the final reaction-diffusion model.

6. The general reliability degradation simulation method across processes according to claim 5, characterized in that, The process of globally optimizing all fitting coefficients of the reaction-diffusion model with the parameter extraction based on the distribution to obtain the final reaction-diffusion model includes: The reaction-diffusion model with the parameter extraction of the distribution is subjected to global optimization of all fitting coefficients under the threshold voltage-time degradation curve to obtain the final reaction-diffusion model.

7. The general reliability degradation simulation method across processes according to claim 1, characterized in that, The total degradation result of the threshold voltage is expressed as follows: ； This represents the total degradation result of the threshold voltage. This represents the initial value of the threshold voltage. This indicates the type parameter of the MOSFET in the integrated circuit under test. Express the extrapolated diffusion equation, Represents the time-fit coefficients. ； in, This represents the result of the linearized diffusion equation. Indicates the timeframe of degradation (in years). This represents the total number of seconds in a year. Indicates the simulation time. ； Indicates the time step. Represents the process fit coefficient. This represents the second nonlinear coefficient. Represents the time-fit coefficients. This represents the activation energy, and k represents the Boltzmann constant. Indicates the effective temperature. This represents the substrate current of the MOSFET in the integrated circuit under test. This represents the total carrier flux through the channel.

8. A universal reliability degradation simulation device across processes, characterized in that, The cross-process general reliability degradation simulation device includes: an acquisition unit, a calculation unit, a linear transformation unit, a time extrapolation unit, and an anti-linearization processing unit; The acquisition unit is used to acquire the SPICE netlist and process library of the integrated circuit under test; The computing unit is used to input the SPICE netlist and the process library into the final reaction-diffusion model under the corresponding process node in the SPICE simulator, and calculate the reaction-diffusion equation under the time exponential. The linear transformation unit is used to perform a time-step linear transformation on the reaction-diffusion equation to obtain a linearized diffusion equation. The time extrapolation unit is used to perform time extrapolation processing on the linearized diffusion equation within a preset time to obtain the extrapolated diffusion equation. The delinearization processing unit is used to delinearize the extrapolated diffusion equation to obtain the total degradation result of the threshold voltage; the final reaction diffusion model is obtained by fitting the reaction diffusion mechanism based on integrated circuits at multiple process nodes.

9. A universal reliability degradation simulation device that spans multiple processes, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the cross-process general reliability degradation simulation device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the cross-process general reliability degradation simulation method as described in any one of claims 1-7.

Images