Optimization processing method and device of PCB panel and computer readable storage medium

Abstract

The application provides an optimization processing method of a PCB panel, comprising: obtaining a first pattern of a panel target, and rotating the first pattern based on a discrete rotation angle set to construct a single pattern rotation set; obtaining a candidate combined pattern based on pattern splicing of the single pattern rotation set, and screening based on a multi-index evaluation system to construct an optimized combined pattern set; merging the two sets to construct a to-be-arranged pattern set; constructing a layer set corresponding to a mother board based on the mother board type and the to-be-arranged pattern set; determining an extended to-be-arranged pattern set based on the to-be-arranged pattern set and the layer set; constructing a mixed integer linear programming model with the extended to-be-arranged pattern set as input and the maximum mother board material utilization rate as output under the condition of meeting the preset constraint condition, so as to optimize the layout of the PCB panel. The application can significantly reduce the search space, avoid inefficient single arrangement attempts, improve the algorithm efficiency, and explore a compact layout that cannot be realized by single piece layout, thereby improving the space utilization rate.

Description

Technical Field

[0001] This invention relates to the field of PCB (Printed Circuit Board) panel technology, and in particular to an optimization processing method, apparatus and computer-readable storage medium for PCB panels. Background Technology

[0002] With the explosive growth of 5G communications, automotive electronics, and other fields, PCB design and manufacturing processes are facing severe challenges. PCB panelization optimization, as a core part of the manufacturing process, aims to efficiently arrange multiple PCB unit boards on a larger substrate while meeting various process constraints. This arrangement directly determines raw material utilization, cutting costs, and production efficiency, significantly impacting the competitiveness of PCB manufacturers. In particular, for companies with an annual output of millions of pieces, a 1% improvement in material utilization can result in millions of dollars in cost savings.

[0003] Traditional 2D layout problems mainly focus on the arrangement of regular shapes within the smallest rectangular board material, while PCB panel optimization presents significant differences: graphic complexity (delivery units are mostly irregular 2D shapes with complex shapes, and usually allow discrete rotation); process constraint complexity (a specified number and type of "cobonds" need to be placed precisely on the motherboard according to process requirements such as electrical connections, test points, and special component positions); motherboard diversity (there are multiple sizes of motherboards available, and each motherboard has pre-set board edge graphics due to process requirements, resulting in an irregular polygonal available layout area).

[0004] Given the complexity and diversity of PCB panel optimization problems, existing technologies have the following limitations in addressing this issue: Model limitations: Most studies focus on the layout of regular rectangular graphics on a single fixed-size motherboard, lacking effective modeling of the dual-layer decision-making of motherboard size selection and graphic layout, as well as the systematic integration of Kobon process constraints.

[0005] Insufficient handling of irregular shapes: When dealing with irregular shapes, the minimum envelope rectangle approximation is often used. Although this simplifies collision detection, it ignores detailed features such as grooves and serrated edges, resulting in low space utilization.

[0006] Algorithm efficiency and adaptability bottlenecks: Existing algorithms generally lack effective preprocessing mechanisms to reduce the huge solution space, and the encoding methods are usually fixed, making it difficult to adaptively adjust the encoding structure and length according to characteristics such as multiple motherboard selection and cross-bonding constraints, which limits their optimization ability and robustness under complex heterogeneous constraints. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0008] Therefore, one objective of this invention is to propose an optimization method for PCB panelization. This method rotates a first graphic based on a discrete set of rotation angles to generate second graphics of the panelization target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm's search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. This creates higher space utilization nesting units and achieves a compact nested layout. Simultaneously, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed to determine the expanded set of graphics to be arranged. This method can integrate multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, thus improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0009] Therefore, a second objective of the present invention is to provide a computer-readable storage medium.

[0010] Therefore, a third objective of this invention is to provide an optimized processing device for PCB panels.

[0011] To achieve the above objectives, an embodiment of the first aspect of the present invention proposes an optimization method for PCB panelization, the method comprising: obtaining a first graphic of the PCB panelization target, a discrete set of rotation angles, and a motherboard type; performing a rotation operation around the centroid on the first graphic based on the discrete set of rotation angles to generate a second graphic of the panelization target under different rotation angles, thereby constructing a single graphic rotation set corresponding to the panelization target; splicing any two second graphics in the single graphic rotation set to form a candidate combination graphic, and screening the candidate combination graphic based on a multi-index evaluation system to construct an optimized combination graphic set corresponding to the panelization target; merging the single graphic rotation set and the optimized combination graphic set to construct a set of graphics to be arranged corresponding to the panelization target; constructing a layer set corresponding to the motherboard based on the motherboard type and the set of graphics to be arranged; determining an extended set of graphics to be arranged corresponding to the panelization target based on the set of graphics to be arranged and the layer set; and, under preset constraints, constructing a mixed integer linear programming model with the extended set of graphics to be arranged as input and maximizing the motherboard material utilization rate as output to optimize the layout of the PCB panelization.

[0012] The PCB panel optimization method according to embodiments of the present invention rotates a first graphic based on a discrete set of rotation angles to generate second graphics of the panel target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. This creates a more space-efficient layout unit, achieving a compact nested layout. Simultaneously, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This method integrates multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0013] In some embodiments, the step of splicing any two second graphics in the single graphic rotation set to form a candidate combined graphic includes: obtaining a combination pair after combining any two second graphics in the single graphic rotation set in pairs; calculating the feasible region of the relative position of the combination pair based on the critical polygon, and sampling multiple contact points on the boundary of the feasible region; and fitting the second graphics in the combination pair based on the multiple contact points to form the candidate combined graphic.

[0014] In some embodiments, the step of screening the candidate combination graphics based on a multi-index evaluation system to construct an optimized combination graphics set corresponding to the puzzle target includes: obtaining the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit degree, and circumscribed convex hull ratio of the orthogonal rectangle corresponding to the candidate combination graphics; and performing a weighted sorting of the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit degree, and circumscribed convex hull ratio of the orthogonal rectangle to screen the candidate combination graphics and construct an optimized combination graphics set corresponding to the puzzle target.

[0015] In some embodiments, obtaining the minimum bounding rectangle utilization rate corresponding to the candidate combined graphic includes: calculating the minimum bounding rectangle utilization rate based on the minimum bounding rectangle utilization rate formula, wherein the minimum bounding rectangle utilization rate formula is: ; in, This represents the minimum utilization rate of the enclosing rectangle. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest axis-aligned rectangle that completely encloses the candidate combination figure.

[0016] In some embodiments, obtaining the utilization rate of the circumscribed convex hull corresponding to the candidate combined graph includes: calculating the utilization rate of the circumscribed convex hull based on the formula for the utilization rate of the circumscribed convex hull, wherein the formula for the utilization rate of the circumscribed convex hull is: ; in, Indicates the utilization rate of the circumscribed convex hull. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph.

[0017] In some embodiments, obtaining the orthogonal rectangle fit degree includes: calculating the orthogonal rectangle fit degree based on the orthogonal rectangle fit degree formula, wherein the orthogonal rectangle fit degree formula is: ; in, Indicates the fit of orthogonal rectangles. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest rectangle that contains all vertices of the candidate composite graph and whose sides are parallel to the coordinate axes.

[0018] In some embodiments, obtaining the proportion of the circumscribed convex hull to the orthogonal rectangle includes: calculating the proportion of the circumscribed convex hull to the orthogonal rectangle based on a formula for the proportion of the circumscribed convex hull to the orthogonal rectangle, wherein the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle is: ; in, This indicates the proportion of the circumscribed convex hull to the orthogonal rectangle. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph. This represents the area of ​​the smallest rectangle containing its circumscribed convex hull and whose sides are parallel to the coordinate axes.

[0019] In some embodiments, constructing the layer set corresponding to the motherboard based on the motherboard type and the set of graphics to be arranged includes: obtaining the geometric information of the motherboard corresponding to the motherboard type; arranging the graphics in the set of graphics to be arranged in a predetermined direction according to a preset spacing constraint to form a layer structure; calculating the layer utilization rate corresponding to different layers in the layer structure; determining the target layer based on the layer utilization rate; and constructing the layer set corresponding to the motherboard based on the set of graphics to be arranged and the graphics corresponding to the target layer, as well as the geometric information of the motherboard.

[0020] In some embodiments, the preset spacing constraint condition is:

[0021] Among them, among them, The first one arranged in a preset direction The width of the graphic, This represents the sum of the widths of all graphics arranged in a preset direction. This indicates the number of figures in the set of figures to be arranged. This indicates the minimum allowable spacing between adjacent graphics arranged in a preset direction. i represents the available width of the motherboard.

[0022] In some embodiments, the formula for calculating the layer utilization rate is as follows: ; in, The layer utilization rate is represented by CS, which represents the candidate combined graphic, and Area (CS) represents the actual area of ​​the candidate combined graphic. This indicates the width of the layer corresponding to the motherboard. This indicates the height of the layer corresponding to the motherboard.

[0023] In some embodiments, the preset constraints include: only one type of motherboard must be selected; and, the graphics in the expanded set of graphics to be arranged can only be placed on the selected motherboard; and, each type of graphic has only one rotated graphic placed; and, if two graphics in the expanded set of graphics to be arranged are placed on the same motherboard, their relative reference points belong to a feasible partition of the other's buffered critical polygon; and, all placed graphics in the expanded set of graphics to be arranged have no overlap and satisfy the minimum spacing; and, the reference point of the graphics in the expanded set of graphics to be arranged must be located inside the buffered inner critical polygon of the motherboard; and, the graphic satisfies its specific position binding, boundary / corner, or association constraints.

[0024] To achieve the above objectives, a second aspect of the present invention provides a computer-readable storage medium storing an optimization processing program for a PCB panel, wherein when the optimization processing program for the PCB panel is executed by a processor, a device having the optimization processing program for the PCB panel installed implements the optimization processing method for the PCB panel as described in any of the above embodiments.

[0025] According to the computer-readable storage medium of the present invention, by rotating a first graphic based on a discrete set of rotation angles, a second graphic of the panel target under different rotation angles is generated. Any two second graphics are spliced ​​together, and the graphic set is optimized by screening based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics, creating a more space-efficient layout unit and achieving a compact nested layout. At the same time, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This can integrate multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and different motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0026] To achieve the above objectives, a third aspect of the present invention provides an optimization processing apparatus for PCB panelization. The apparatus includes: an acquisition module for acquiring a first graphic of the PCB panelization target, a discrete set of rotation angles, and geometric information of the motherboard; a first construction module for performing a rotation operation around the centroid on the first graphic based on the discrete set of rotation angles to generate second graphics of the panelization target at different rotation angles, thereby constructing a single-graphic rotation set corresponding to the panelization target; and a second construction module for splicing any two second graphics from the single-graphic rotation set to form candidate combined graphics, and screening the candidate combined graphics based on a multi-index evaluation system. The system comprises the following modules: a first module constructs an optimized set of combined graphics corresponding to the target panel layout; a second module merges the set of rotated single graphics with the optimized set of combined graphics to construct a set of graphics to be arranged corresponding to the target panel layout; a third module constructs a set of layers corresponding to the motherboard based on the geometric information of the motherboard and the set of graphics to be arranged; a fourth module determines an extended set of graphics to be arranged corresponding to the target panel layout based on the set of graphics to be arranged and the set of layers; and an optimization module constructs a mixed-integer linear programming model to optimize the layout of the PCB panel layout, using the extended set of graphics to be arranged as input and maximizing the utilization rate of the motherboard material as output, under preset constraints.

[0027] The PCB panel optimization processing apparatus according to an embodiment of the present invention rotates a first graphic based on a discrete set of rotation angles to generate a second graphic of the panel target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. It creates a more space-efficient layout unit, achieving a compact nested layout. Simultaneously, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This integrates multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0028] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart of an optimization processing method for PCB panels according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of bonding the second graphic in a combination pair based on multiple contact points according to an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the screening of candidate combination graphics based on a multi-index evaluation system according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the principle of constructing a layer set corresponding to a motherboard according to an embodiment of the present invention; Figure 5 This is a detailed flowchart of an optimization method for PCB panelization according to an embodiment of the present invention; Figure 6 This is a block diagram of an optimization processing apparatus for PCB panels according to an embodiment of the present invention.

[0030] Figure label: 100 - PCB panel optimization processing device; 110 - Acquisition module; 120 - First construction module; 130 - Second construction module; 140 - Third construction module; 150 - Fourth construction module; 160 - Determination module; 170 - Optimization module. Detailed Implementation

[0031] The embodiments described with reference to the accompanying drawings are exemplary, and the embodiments of the present invention are described in detail below.

[0032] The following is combined with Figure 1-6 This invention describes an optimization method for PCB panelization according to an embodiment of the present invention.

[0033] like Figure 1 The diagram shows a flowchart of an optimization method for a PCB panel according to an embodiment of the present invention. The optimization method for a PCB panel according to an embodiment of the present invention includes at least steps S1-S7.

[0034] Step S1: Obtain the first graphic of the PCB panel target, the discrete rotation angle set, and the motherboard type.

[0035] In this embodiment, during the PCB panelization optimization process, a first graphic of the PCB panelization target can be obtained. The panelization target refers to the PCB unit board to be panelized, i.e., the delivery unit, and the first graphic is the geometry of the delivery unit, which is usually a two-dimensional irregular polygon. At the same time, due to the constraint of isomorphic panelization, the motherboard can only arrange a single type of delivery unit, but each unit can choose to rotate at different angles in a discrete set of rotation angles. Therefore, the set of rotation angles can be discrete. In addition, since different motherboards have different sizes, shapes, and preset board edge graphics, they will affect the arrangement of delivery units on the motherboard and the space utilization. Therefore, the motherboard type can also be obtained.

[0036] Step S2: Based on the discrete rotation angle set, perform a rotation operation around the centroid on the first graphic to generate a second graphic of the puzzle target under different rotation angles, so as to construct a single graphic rotation set corresponding to the puzzle target.

[0037] In an embodiment, firstly, the discrete rotation angle set can be set as Among them, the typical value is =0°, 90°, 180°, 270°. Then, based on the discrete set of rotation angles, the first graphic can be rotated around its centroid (the geometric center of the polygon) to generate a second graphic of the puzzle target under different rotation angles. The geometric definition of its rotation state is:

[0038] in, Indicates rotation around the centroid The transformation, each It is considered a separate figure to be arranged (the second figure).

[0039] Furthermore, by collecting all the generated second graphics into a set, we can obtain a set of single-graphic rotations. In a specific embodiment, a graph feature hashing technique (such as vertex sequence) is used to eliminate repeated states caused by symmetry and reduce redundant calculations. For example, the hash value of each graph can be calculated. If the hash values ​​of two rotation states are the same, they are regarded as the same graph and only one is kept.

[0040] Step S3: Piece together any two second graphics from the single graphic rotation set to form a candidate combined graphic. Then, screen the candidate combined graphics based on a multi-index evaluation system to construct an optimized combined graphic set corresponding to the puzzle target.

[0041] In one embodiment, to explore the nesting potential of adjacent graphics, a set of rotations can be performed from a single graphic. Two different second graphics (i.e. graphics under different rotation angles) are selected and spliced ​​together to generate candidate combination graphics. Based on a multi-index evaluation system, the candidates are evaluated from different dimensions. The candidate combination graphics are then screened according to the evaluation results to construct an optimized combination graphic set corresponding to the puzzle target.

[0042] Step S4: Merge the single-graphic rotation set with the optimized combination graphic set to construct the graphic set to be arranged corresponding to the puzzle target.

[0043] In this embodiment, after determining the single-graphic rotation set and the optimized combined graphic set, in order to maintain the flexibility and integrity of the layout and achieve global optimization of the PCB panelization, the single-graphic rotation set and the optimized combined graphic set can be merged to construct the graphic set to be arranged corresponding to the panelization target. ,in This is the optimized combination of graphics obtained after filtering.

[0044] Step S5: Construct the layer set corresponding to the motherboard based on the motherboard type and the set of graphics to be arranged.

[0045] In the embodiments, since different motherboards have different sizes, shapes and preset edge patterns, the constraints on the process are different. Therefore, the layer set corresponding to the motherboard can be constructed based on the motherboard type and the set of patterns to be arranged. That is, based on the set of patterns to be arranged, a unique layer set can be generated independently for different motherboards.

[0046] Step S6: Determine the extended set of graphics to be arranged corresponding to the panel target based on the set of graphics to be arranged and the set of layers.

[0047] In this embodiment, after obtaining the set of graphics to be arranged and the corresponding layer set of the motherboard, the set of graphics to be arranged and the layer set can be merged to obtain an extended set of graphics to be arranged. This process can be formally expressed as: Extended set of graphics to be arranged = Set of graphics to be arranged ∪ (Layer set of motherboard 1) ∪ (Layer set of motherboard 2) ∪ … ∪ (Layer set of motherboard B), i.e. ,in, Represents the set of figures to be arranged. Represents a single set of layers. Represents a collection of template types. Indicates an index.

[0048] Step S7: Under the condition of satisfying the preset constraints, take the expanded set of graphics to be arranged as input and the maximum utilization rate of the motherboard material as output to construct a mixed integer linear programming model to optimize the layout of PCB panels.

[0049] In this embodiment, after determining the final extended set of patterns to be arranged, a mixed-integer linear programming model can be constructed using this set as input and maximizing the motherboard material utilization rate (i.e., minimizing the waste ratio) as output. This model optimizes the PCB panel layout, mapping the physical layout problem to a mathematical algorithm consisting of variables, an objective function, and constraints. The formula for the motherboard material utilization rate is as follows: It represents the proportion of the total area of ​​the delivery unit entities placed on the motherboard to the area of ​​its irregular usable area, where, Indicates motherboard type b The area of ​​the irregular available area (considering the actual available area after pre-setting the sample container). This represents all delivery unit entities in the expanded set of drawings to be arranged, by... Each shape in the diagram is copied a certain number of times to form a solid component, and the number of copies of each shape is... The indices are i, j. Graphical representation of units to be delivered area, For decision variables, it represents whether to include the entity. Placed on motherboard superior.

[0050] The PCB panel optimization method according to embodiments of the present invention rotates a first graphic based on a discrete set of rotation angles to generate second graphics of the panel target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. This creates a more space-efficient layout unit, achieving a compact nested layout. Simultaneously, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This method integrates multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0051] In some embodiments, splicing any two second graphics in the single graphic rotation set to form a candidate combined graphic includes: obtaining a combination pair after combining any two second graphics in the single graphic rotation set in pairs; The feasible region of relative position of the combination pair is calculated based on the critical polygon, and multiple contact points are sampled on the boundary of the feasible region. The second graphic in the combination pair is bonded together based on multiple contact points to form a candidate combination graphic.

[0052] In this embodiment, when splicing any two second graphics from the single graphic rotation set, the single graphic rotation set can first be obtained. The combination pairs formed by pairwise combinations of any two second figures in the middle ( ),in, ≠ .

[0053] Furthermore, a critical polygon can be determined based on a pre-defined algorithm, such as the Minkowski sum operation, to calculate the feasible region of the relative positions of the combined pairs. Simultaneously, multiple contact points are sampled on the boundary of the feasible region, each representing... Fits Candidate positions.

[0054] Furthermore, in combination Figure 2 As shown, the second graphic in the combination pair can be bonded based on multiple contact points to form a candidate combination graphic, for example, by fixing... Location, will Translate to the contact point to generate candidate combined graphics. ,in Represent geometry and perform operations.

[0055] In some embodiments, candidate combination graphics are screened based on a multi-index evaluation system to construct an optimized combination graphic set corresponding to the puzzle target, including: obtaining the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit rate, and the proportion of circumscribed convex hull to orthogonal rectangle corresponding to the candidate combination graphics. The utilization rate of the minimum bounding rectangle, the utilization rate of the circumscribed convex hull, the fit of the orthogonal rectangle, and the proportion of the circumscribed convex hull to the orthogonal rectangle are weighted and sorted to filter candidate combined graphics and construct an optimized set of combined graphics corresponding to the puzzle target.

[0056] In the embodiments, when screening candidate combination graphics based on a multi-index evaluation system, a comprehensive scoring model can be constructed by quantifying dimensions such as geometric utilization, structural compactness, and process adaptability to screen out an optimized set of combination graphics that meet the panelization objectives (such as minimizing material waste and maximizing layout density). This includes, but is not limited to, obtaining the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit, and the proportion of circumscribed convex hull to orthogonal rectangle corresponding to the candidate combination graphics, in order to construct a comprehensive scoring model.

[0057] Furthermore, the utilization rate of the minimum bounding rectangle, the utilization rate of the circumscribed convex hull, the fit of the orthogonal rectangle, and the proportion of the circumscribed convex hull to the orthogonal rectangle can be weighted and sorted. This includes, but is not limited to, normalizing each index value to the [0,1] interval, calculating the comprehensive score of each candidate combination graphic, and arranging the candidate combination graphics according to the comprehensive score, thereby filtering the candidate combination graphics and constructing the optimized combination graphic set corresponding to the puzzle target.

[0058] In a specific embodiment, when screening candidate combination graphics based on a multi-index evaluation system, the screening strategy can also adopt the Pareto optimal frontier method, retaining the top 10% of candidate combination graphics for each index to construct an optimized combination graphics set. Figure 3 The figures shown are the combined figures with the highest utilization of the minimum bounding rectangle, the highest utilization of the circumscribed convex hull, the highest fit of the orthogonal rectangle, and the highest proportion of the circumscribed convex hull to the orthogonal rectangle.

[0059] In some embodiments, obtaining the minimum bounding rectangle utilization rate corresponding to the candidate combined graphics includes: calculating the minimum bounding rectangle utilization rate based on the minimum bounding rectangle utilization rate formula, wherein the minimum bounding rectangle utilization rate formula is: ; in, This represents the minimum bounding rectangle utilization rate, indicating the compactness of the candidate combined graphic. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination graphic, i.e., the effective area. This represents the smallest, axis-aligned rectangle that completely encloses the candidate combination shape. This represents the area of ​​the rectangle. It is understandable that... The higher the value, the more densely the candidate combination graphics are filled within the given boundaries, resulting in higher efficiency in PCB layout optimization.

[0060] In some embodiments, obtaining the utilization rate of the circumscribed convex hull corresponding to the candidate combined graph includes: calculating the circumscribed convex hull utilization rate based on the circumscribed convex hull utilization rate formula, wherein the circumscribed convex hull utilization rate formula is: ; in, This represents the utilization rate of the circumscribed convex hull, which indicates the compactness of the fill within the convex hull for candidate composite graphics. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination graphic, i.e., the effective area. This represents the smallest convex polygon that contains all vertices of the candidate composite graph. This represents the area of ​​the smallest convex polygon. It is understandable that... The higher the value, the closer the candidate combination graphic is to the convex hull shape, the less internal concavity there is, and the lower the space wastage.

[0061] In some embodiments, obtaining the orthogonal rectangle fit degree includes: calculating the orthogonal rectangle fit degree based on the orthogonal rectangle fit degree formula, wherein the orthogonal rectangle fit degree formula is: ; in, This indicates the orthogonal rectangle fit, which represents how tightly the candidate combined graphic fills the orthogonal rectangle. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination graphic, i.e., the effective area. This represents the smallest rectangle that contains all vertices of the candidate composite graph and whose sides are parallel to the coordinate axes. This represents the area of ​​the smallest rectangle. It is understandable that... The higher the value, the closer the candidate combination graphic is to the smallest rectangle, the less space is wasted, and the higher the filling efficiency of the candidate combination graphic within the orthogonal rectangle.

[0062] In some embodiments, obtaining the proportion of the circumscribed convex hull to the orthogonal rectangle includes: calculating the proportion of the circumscribed convex hull to the orthogonal rectangle based on the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle, wherein the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle is: ; in, This represents the proportion of the circumscribed convex hull to the orthogonal rectangle, indicating the compactness of the circumscribed convex hull within the orthogonal rectangle of the candidate composite figure. Represents candidate combination graphics. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph. This represents the smallest rectangle containing its circumscribed convex hull and whose sides are parallel to the coordinate axes. This represents the area of ​​the smallest rectangle. It is understandable that... The higher the value, the higher the matching efficiency between the outer convex hull shape of the candidate combined graphic and the orthogonal rectangle, and the lower the potential space waste that the candidate combined graphic may cause in global nesting.

[0063] In some embodiments, constructing a layer set corresponding to the mother plate based on the mother plate type and the set of graphics to be arranged includes: obtaining the geometric information of the mother plate corresponding to the mother plate type; Based on preset spacing constraints, the graphics in the set of graphics to be arranged are arranged sequentially along a preset direction to form a layered structure; Calculate the layer utilization rate of different layers in the calculation layer structure; Determine the target layer based on layer utilization; Based on the set of graphics to be arranged and the graphics corresponding to the target layer, a set of graphics is constructed, and the geometric information of the mother plate is used to construct the set of layers corresponding to the mother plate.

[0064] In the embodiment, during the process of constructing the layer set corresponding to the mother plate based on the mother plate type and the set of graphics to be arranged, the geometric information of the mother plate corresponding to the mother plate type can be obtained first, for example, the size characteristics of multiple mother plates can be obtained.

[0065] Furthermore, in combination Figure 4 As shown, under the condition of satisfying the preset spacing constraints, the graphics (second graphics and combined graphics) in the set of graphics to be arranged are arranged sequentially along the preset direction (usually the X-axis) to generate different layer structures corresponding to different motherboard sizes.

[0066] Furthermore, the layer utilization rate of different layers in the layer structure can be calculated based on a preset algorithm, thereby measuring the degree of space utilization within the layer and evaluating the tightness of the graphic arrangement.

[0067] Furthermore, target layers can be determined based on layer utilization, including but not limited to sorting and filtering all generated layers according to their layer utilization. This typically employs an elite retention strategy, such as retaining the top 10% of layers with the highest utilization, or setting a utilization threshold and retaining only layers that exceed that threshold.

[0068] Furthermore, based on the geometric information of different motherboards, that is, based on the different size characteristics of the motherboards, the set of layers corresponding to the motherboard can be constructed using the set of graphics to be arranged and the set of graphics corresponding to the target layer. In other words, each motherboard maintains an independent set of layers tailored to its width.

[0069] In some embodiments, the preset spacing constraint condition is:

[0070] in, The first one arranged in a preset direction The width of the graphic, This represents the sum of the widths of all graphics arranged in a preset direction. This indicates the number of figures in the set of figures to be arranged. This indicates the minimum allowable spacing between adjacent graphics arranged in a preset direction. i represents the available width of the motherboard. It can be understood that the meaning of this constraint is that the total width of all graphics arranged in the preset direction (the sum of the graphic widths + the spacing) does not exceed the allowable width of the motherboard, so as to ensure that the graphics after layout do not exceed the boundary of the motherboard.

[0071] In some embodiments, the formula for calculating layer utilization is as follows: ; in, The layer utilization rate is represented by CS, which represents the candidate combined graphic, and Area (CS) represents the actual area of ​​the candidate combined graphic, i.e., the effective area. This indicates the width of the layer corresponding to the motherboard. This indicates the height of the layer corresponding to the motherboard.

[0072] In some embodiments, preset constraints include: one and only one motherboard type must be selected; And, the graphics in the expanded set of graphics to be arranged can only be placed on the selected master sheet; And, for each type of Cobon, there is one and only one rotated graphic placed; If two graphics in the expanded set of graphics to be arranged are placed on the same motherboard, their relative reference points belong to a feasible partition of the other party's buffered critical polygon. And, in the expanded set of figures to be arranged, all placed figures have no overlap and satisfy the minimum spacing; And, the reference point of the figure in the expanded set of figures to be arranged must be located inside the buffered inner critical polygon of the mother plate; And, Cobond satisfies its specific location binding, boundary / corner, or association constraints.

[0073] In this embodiment, during the panel optimization process, the preset constraints include: only one type of mother panel must be selected, i.e., only one specification of mother panel can be selected, and mixing mother panels is not allowed. The constraint formula is as follows: ,in, Indicates the selection of the motherboard type. Otherwise, it is 0.

[0074] Furthermore, the preset constraints also include: each graphic in the expanded set of graphics to be arranged can only be placed on the selected master plate, and the corresponding constraint formula is as follows: ,in, Representing graphics Placed on the motherboard If it is above, then it is 0; otherwise, it is 0.

[0075] Furthermore, the preset constraints also include: each type of Cobond has exactly one rotated graphic placed; that is, for each Cobond type, exactly one instance of a rotated state is selected and placed on the selected mother plate, and the corresponding constraint formula is as follows: ,in, The original set of polygons to be placed is the set of polygons. For Kebang A set of geometric copies at all allowed rotation angles.

[0076] Furthermore, the preset constraints also include: if two graphics in the expanded set of graphics to be arranged are placed on the same master board, then their relative reference points belong to a feasible partition of the other's buffered critical polygon, and the corresponding constraint formula is: ,in, Indicates will (Graphics) Compared to The outer feasible region of a buffered critical polygon is divided into several non-overlapping subregions, where each subregion is composed of a set of linear inequalities. Defined, its linear inequality parameters are , Its representation of graphics Is the reference point placed? The k-th partition of the buffered critical polygon, where, That is, the set of entities to be queued.

[0077] Furthermore, the preset constraints also include: all placed graphics in the expanded set of graphics to be arranged must not overlap and must satisfy the minimum spacing requirement, with the corresponding constraint formula being: ,in, The coefficients of the inequalities in the partition are given. The significance of the above constraints is that when... hour, When the value is 0, the constraint takes effect; at this point, the graphic is forced to... Relative to graphics The positions satisfy the linear inequality f of partition k, thus ensuring no overlap and satisfying the spacing, while For sufficiently large positive numbers, when When the constraint is relaxed by a huge positive number M, the constraint becomes invalid.

[0078] Furthermore, the preset constraints also include: the reference point of the graphics in the expanded set of graphics to be arranged must be located within the buffered inner critical polygon of the parent template. Internally, the corresponding constraint formula is: ,in, Representing graphics On motherboard b An inner critical polygon with a buffer zone, which can be represented by a set of linear inequalities. Characterization, its linear inequality parameters are The significance of the above constraints is that when motherboard b is selected, hour, When the value is 0, the constraint takes effect; at this point, the graphic is forced to... The reference point must meet the following requirements. The linear inequality lies within the inner critical polygon of the mother plate with buffer, while For sufficiently large positive numbers, when When the constraint is relaxed by a huge positive number M, the constraint becomes invalid.

[0079] Furthermore, the PCB layout is a key process point or structure in PCB manufacturing. As an auxiliary graphic to meet specific manufacturing requirements (such as V-cuts, stamp holes, and test point reservations), its placement is strictly constrained, primarily by position binding, boundary / corner, or associated constraints. In other words, the preset constraints also include: the PCB must meet its specific position binding, boundary / corner, or associated constraints, and the corresponding constraint formulas are as follows: The significance of the above constraints lies in: when Cobond... Placed on motherboard When, hour, When the value is 0, the constraint takes effect, forcing the reference point of the cobond to be located within its feasible region. Internally, it satisfies position binding constraints, boundary / corner constraints, or association constraints, while For sufficiently large positive numbers, when At that time, i.e., Cobon Not placed on the motherboard When the constraint is relaxed by a huge positive number M, the constraint becomes invalid. A graphical representation of a region pre-calculated based on the Cobond type. On motherboard b The placeable region on the set of linear inequalities Characterization, its linear inequality parameters are .

[0080] The following is for reference. Figure 5 The optimization processing method for PCB panelization according to embodiments of the present invention will be described in detail.

[0081] like Figure 5 The diagram shown is a detailed flowchart of a PCB panel optimization method according to an embodiment of the present invention. The PCB panel optimization method of this embodiment includes at least steps S10-S29.

[0082] Step S10: Input the original delivery unit polygon (i.e., obtain the first drawing).

[0083] Step S11: Generate a set of discrete rotation angles (i.e., obtain a set of discrete rotation angles).

[0084] Step S12: Calculate the rotation geometry (i.e., perform a rotation operation around the centroid of the first figure).

[0085] Step S13: Graphic feature hashing to eliminate symmetric repetitive states.

[0086] Step S14: Output the set of independent graphics to be arranged (i.e., construct a set of single-graphic rotations).

[0087] Step S15: Enumerate state pairs (i.e., obtain the combination pairs after combining any two second graphics in the single graphic rotation set).

[0088] Step S16: Calculate K contact points at the boundary of the NFP feasible region (i.e., calculate the relative position feasible region of the combination pair based on the critical polygon, and sample multiple contact points on the boundary of the feasible region).

[0089] Step S17: Generate a combined graphic (i.e., construct a candidate combined graphic).

[0090] Step S18: Select a multi-indicator evaluation system.

[0091] Step S19: Calculate the minimum enclosing rectangle utilization rate.

[0092] Step S20: Calculate the utilization rate of the circumscribed convex hull.

[0093] Step S21: Calculate the fit of the orthogonal rectangle.

[0094] Step S22: Calculate the proportion of the circumscribed convex hull to the orthogonal rectangle.

[0095] Step S23: Using the Pareto optimal frontier method, retain the top 10% of candidate combination graphs for each indicator.

[0096] Step S24: Update the set to be arranged (i.e., construct the set of graphs to be arranged).

[0097] Step S25: Single / combined graphics are arranged along the X-axis and the spacing is satisfied (i.e., based on the preset spacing constraint, the graphics in the set of graphics to be arranged are arranged in order along the preset direction). Step S26: Calculate layer utilization.

[0098] Step S27: Retain the top 10% of university layers (i.e., determine the target layer based on layer utilization).

[0099] Step S28: Generate a layer set for each motherboard size (i.e., construct a set of graphics based on the set of graphics to be arranged and the graphics corresponding to the target layer, and construct a set of layers corresponding to the motherboard based on the geometric information of the motherboard).

[0100] Step S29, expand the set to be arranged (i.e., determine the expanded set of graphics to be arranged corresponding to the puzzle target based on the set of graphics to be arranged and the layer set).

[0101] The PCB panel optimization method according to embodiments of the present invention rotates a first graphic based on a discrete set of rotation angles to generate second graphics of the panel target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. This creates a more space-efficient layout unit, achieving a compact nested layout. Simultaneously, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This method integrates multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0102] The present invention describes a computer-readable storage medium storing an optimization program for a PCB panel, wherein when executed by a processor, the optimization program causes a device having the optimization program installed to implement the optimization method for the PCB panel as described in any of the above embodiments.

[0103] According to the computer-readable storage medium of the present invention, by rotating a first graphic based on a discrete set of rotation angles, a second graphic of the panel target under different rotation angles is generated. Any two second graphics are spliced ​​together, and the graphic set is optimized by screening based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics, creating a more space-efficient layout unit and achieving a compact nested layout. At the same time, based on the motherboard type and the set of graphics to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded set of graphics to be arranged. This can integrate multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and different motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0104] The following is for reference. Figure 6 The PCB panel optimization processing apparatus 100 of the present invention is described.

[0105] like Figure 6 The diagram shown is a block diagram of a PCB panel optimization processing apparatus 100 according to an embodiment of the present invention. The PCB panel optimization processing apparatus 100 of this embodiment includes: an acquisition module 100, used to acquire a first graphic of the PCB panel target, a discrete rotation angle set, and geometric information of the motherboard; a first construction module 120, used to perform a rotation operation around the centroid on the first graphic based on the discrete rotation angle set to generate second graphics of the panel target under different rotation angles, thereby constructing a single graphic rotation set corresponding to the panel target; and a second construction module 130, used to splice any two second graphics in the single graphic rotation set to form a candidate combination graphic, and to screen the candidate combination graphics based on a multi-index evaluation system to construct a single graphic rotation set corresponding to the panel target. The system comprises: a first, an optimized set of combined graphics; a second, a third, a fourth, a fifth, a sixth, a seventh, a seventh, a seventh, a eleventh ...

[0106] The PCB panel optimization processing apparatus 100 according to an embodiment of the present invention rotates a first graphic based on a discrete set of rotation angles to generate a second graphic of the panel target under different rotation angles. Any two second graphics are then joined together, and the graphic set is optimized based on a multi-index evaluation system. This avoids inefficient single-unit arrangement attempts, reduces the algorithm search space, optimizes algorithm efficiency, and improves the space utilization efficiency of grooves and serrated edges when processing irregular graphics. It creates a more space-efficient layout unit, achieving a compact nested layout. Simultaneously, based on the motherboard type and the graphic set to be arranged, a layer set corresponding to the motherboard is constructed, thereby determining the expanded graphic set to be arranged. This integrates multiple motherboard sizes and various rotation combinations, enabling the mixed-integer linear programming model to adapt to different board types and motherboards, improving the adaptability and stability of the entire method in the face of complex and ever-changing actual production needs.

[0107] In some embodiments, when splicing any two second graphics in a single graphic rotation set to form a candidate combined graphic, the second construction module 130 is used to: obtain a combination pair after pairwise combination of any two second graphics in the single graphic rotation set; calculate the feasible region of the relative position of the combination pair based on the critical polygon, and sample multiple contact points on the boundary of the feasible region; and fit the second graphics in the combination pair based on the multiple contact points to form a candidate combined graphic.

[0108] In some embodiments, when screening candidate combined graphics based on a multi-index evaluation system to construct an optimized set of combined graphics corresponding to the puzzle target, the second construction module 130 is used to: obtain the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit degree, and circumscribed convex hull ratio of the orthogonal rectangle corresponding to the candidate combined graphics; and perform weighted sorting of the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit degree, and circumscribed convex hull ratio of the orthogonal rectangle to screen the candidate combined graphics and construct an optimized set of combined graphics corresponding to the puzzle target.

[0109] In some embodiments, when obtaining the minimum bounding rectangle utilization rate corresponding to the candidate combined graphics, the second construction module 130 is used to: calculate the minimum bounding rectangle utilization rate based on the minimum bounding rectangle utilization rate formula, wherein the minimum bounding rectangle utilization rate formula is: ;in, This represents the minimum utilization rate of the enclosing rectangle. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest axis-aligned rectangle that completely encloses the candidate combination figure.

[0110] In some embodiments, when obtaining the utilization rate of the circumscribed convex hull corresponding to the candidate combined graph, the second construction module 130 is configured to: calculate the circumscribed convex hull utilization rate based on the circumscribed convex hull utilization rate formula, wherein the circumscribed convex hull utilization rate formula is: ;in, Indicates the utilization rate of the circumscribed convex hull. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest axis-aligned rectangle that completely encloses the candidate combination figure.

[0111] In some embodiments, when obtaining the orthogonal rectangle fit degree, the second construction module 130 is used to: calculate the orthogonal rectangle fit degree based on the orthogonal rectangle fit degree formula, wherein the orthogonal rectangle fit degree formula is: ;in, Indicates the fit of orthogonal rectangles. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest rectangle that contains all vertices of the candidate composite graph and whose sides are parallel to the coordinate axes.

[0112] In some embodiments, when obtaining the proportion of the circumscribed convex hull to the orthogonal rectangle, the second construction module 130 is configured to: calculate the proportion of the circumscribed convex hull to the orthogonal rectangle based on the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle, wherein the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle is: ;in, This indicates the proportion of the circumscribed convex hull to the orthogonal rectangle. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph. This represents the area of ​​the smallest rectangle containing its circumscribed convex hull and whose sides are parallel to the coordinate axes.

[0113] In some embodiments, when constructing a layer set corresponding to a motherboard based on a motherboard type and a set of graphics to be arranged, the fourth construction module 150 is used to: obtain the geometric information of the motherboard corresponding to the motherboard type; arrange the graphics in the set of graphics to be arranged in a predetermined direction based on a preset spacing constraint to form a layer structure; calculate the layer utilization rate corresponding to different layers in the layer structure; determine the target layer based on the layer utilization rate; and construct the layer set corresponding to the motherboard based on the set of graphics to be arranged, the graphics corresponding to the target layer, and the geometric information of the motherboard.

[0114] In some embodiments, the preset spacing constraint condition is: in, The first one arranged in a preset direction The width of the graphic, This indicates the number of figures in the set of figures to be arranged. This indicates the minimum allowable spacing between adjacent graphics arranged in a preset direction. Indicates the available width of the motherboard.

[0115] In some embodiments, the formula for calculating layer utilization is as follows: ;in, The layer utilization rate is represented by CS, which represents the candidate combined graphic, and Area (CS) represents the actual area of ​​the candidate combined graphic. This indicates the width of the layer corresponding to the motherboard. This indicates the height of the layer corresponding to the motherboard.

[0116] In some embodiments, preset constraints include: only one type of motherboard must be selected; graphics in the expanded set of graphics to be arranged can only be placed on the selected motherboard; each type of KOB has only one rotated graphic placed; if two graphics in the expanded set of graphics to be arranged are placed on the same motherboard, their relative reference points belong to a feasible partition of the other's buffered critical polygon; all placed graphics in the expanded set of graphics to be arranged do not overlap and satisfy minimum spacing; the reference points of graphics in the expanded set of graphics to be arranged must be located inside the buffered inner critical polygon of the motherboard; and KOBs satisfy their specific position binding, boundary / corner, or association constraints.

[0117] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0118] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An optimization method for PCB panelization, characterized in that, include: Obtain the first graphic of the PCB panel target, the discrete set of rotation angles, and the motherboard type; Based on the discrete rotation angle set, the first graphic is rotated around the centroid to generate a second graphic of the puzzle target under different rotation angles, so as to construct a single graphic rotation set corresponding to the puzzle target; Any two second graphics in the single graphic rotation set are spliced ​​together to form a candidate combined graphic, and the candidate combined graphic is screened based on a multi-index evaluation system to construct an optimized combined graphic set corresponding to the puzzle target. The single-graphic rotation set is merged with the optimized combined graphic set to construct the graphic set to be arranged corresponding to the puzzle target; Construct the layer set corresponding to the motherboard based on the motherboard type and the set of graphics to be arranged; Based on the set of graphics to be arranged and the set of layers, determine the extended set of graphics to be arranged corresponding to the panel target; Under the condition of satisfying the preset constraints, a mixed integer linear programming model is constructed with the extended set of graphics to be arranged as input and the maximum utilization rate of the motherboard material as output, so as to optimize the layout of the PCB panel.

2. The PCB panel optimization method according to claim 1, characterized in that, The step of splicing any two second graphics from the single-graphic rotation set to form a candidate combined graphic includes: Obtain the pair of any two second graphics from the single graphic rotation set; The feasible region of the relative position of the combination pair is calculated based on the critical polygon, and multiple contact points are sampled on the boundary of the feasible region. The second graphic in the combination pair is bonded together based on the multiple contact points to form the candidate combination graphic.

3. The PCB panel optimization method according to claim 1, characterized in that, The step of screening the candidate combination graphics based on a multi-index evaluation system to construct an optimized combination graphics set corresponding to the puzzle target includes: Obtain the minimum bounding rectangle utilization rate, circumscribed convex hull utilization rate, orthogonal rectangle fit rate, and circumscribed convex hull ratio of orthogonal rectangle corresponding to the candidate combined graphic. The minimum bounding rectangle utilization rate, the circumscribed convex hull utilization rate, the orthogonal rectangle fit rate, and the proportion of the circumscribed convex hull to the orthogonal rectangle are weighted and sorted to filter the candidate combination graphics and construct an optimized combination graphic set corresponding to the puzzle target.

4. The PCB panel optimization method according to claim 3, characterized in that, The step of obtaining the minimum bounding rectangle utilization rate corresponding to the candidate combined graphic includes: The utilization rate of the minimum bounding rectangle is calculated based on the minimum bounding rectangle utilization rate formula, which is as follows: ; in, This represents the minimum utilization rate of the enclosing rectangle. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest axis-aligned rectangle that completely encloses the candidate combination figure.

5. The PCB panel optimization method according to claim 3, characterized in that, The step of obtaining the utilization rate of the outer convex hull corresponding to the candidate combined graph includes: The utilization rate of the circumscribed convex hull is calculated based on the formula for the utilization rate of the circumscribed convex hull. The formula for the utilization rate of the circumscribed convex hull is as follows: ; in, Indicates the utilization rate of the circumscribed convex hull. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph.

6. The PCB panel optimization method according to claim 3, characterized in that, The process of obtaining the orthogonal rectangle fit degree includes: The orthogonal rectangle fitness degree is calculated based on the orthogonal rectangle fitness degree formula, which is as follows: ; in, Indicates the fit of orthogonal rectangles. Represents candidate combination graphics. This represents the actual area of ​​the candidate combination of shapes. This represents the area of ​​the smallest rectangle that contains all vertices of the candidate composite graph and whose sides are parallel to the coordinate axes.

7. The PCB panel optimization method according to claim 3, characterized in that, The step of obtaining the proportion of the circumscribed convex hull to the orthogonal rectangle includes: The proportion of the circumscribed convex hull to the orthogonal rectangle is calculated based on the formula for the proportion of the circumscribed convex hull to the orthogonal rectangle. The formula for the proportion of the circumscribed convex hull to the orthogonal rectangle is as follows: ; in, This indicates the proportion of the circumscribed convex hull to the orthogonal rectangle. This represents the area of ​​the smallest convex polygon that contains all the vertices of the candidate composite graph. This represents the area of ​​the smallest rectangle containing its circumscribed convex hull and whose sides are parallel to the coordinate axes.

8. The PCB panel optimization method according to claim 1, characterized in that, The process of constructing the layer set corresponding to the motherboard based on the motherboard type and the set of graphics to be arranged includes: Obtain the geometric information of the mother plate corresponding to the mother plate type; Based on preset spacing constraints, the graphics in the set of graphics to be arranged are arranged sequentially along a preset direction to form a layered structure; Calculate the layer utilization rate corresponding to different layers in the layer structure; The target layer is determined based on the layer utilization rate. Based on the set of graphics to be arranged and the graphics corresponding to the target layer, a set of graphics is constructed, and the geometric information of the mother plate is used to construct the layer set corresponding to the mother plate.

9. The PCB panel optimization method according to claim 8, characterized in that, The preset spacing constraint condition is: in, The first one arranged in a preset direction The width of the graphic, This indicates the number of figures in the set of figures to be arranged. This indicates the minimum allowable spacing between adjacent graphics arranged in a preset direction. Indicates the available width of the motherboard.

10. The PCB panel optimization method according to claim 8, characterized in that, The formula for calculating the layer utilization rate is as follows: ; in, The layer utilization rate is represented by CS, which represents the candidate combined graphic, and Area (CS) represents the actual area of ​​the candidate combined graphic. This indicates the width of the layer corresponding to the motherboard. This indicates the height of the layer corresponding to the motherboard.

11. The PCB panel optimization processing method according to claim 8, characterized in that, The preset constraints include: one and only one of the motherboard types must be selected; And, the graphics in the expanded set of graphics to be arranged can only be placed on the selected master board; And, for each type of Cobon, there is one and only one rotated graphic placed; If two graphics in the expanded set of graphics to be arranged are placed on the same motherboard at the same time, their relative reference points belong to a feasible partition of the other party's buffered critical polygon. And, in the extended set of graphics to be arranged, all placed graphics have no overlap and satisfy the minimum spacing; And, the reference point of the graphic in the expanded set of graphics to be arranged must be located inside the buffered inner critical polygon of the mother plate; And, the Cobond satisfies its specific location binding, boundary / corner or association constraints.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an optimization processing program for a PCB panel. When the optimization processing program for the PCB panel is executed by a processor, the device on which the optimization processing program for the PCB panel is installed implements the optimization processing method for the PCB panel as described in any one of claims 1-9.

13. An optimization processing device for PCB panels, characterized in that, include: The acquisition module is used to acquire the first graphic of the PCB panel target, the discrete rotation angle set, and the geometric information of the motherboard; The first construction module is used to perform a rotation operation around the centroid on the first graphic based on the discrete rotation angle set to generate a second graphic of the puzzle target under different rotation angles, so as to construct a single graphic rotation set corresponding to the puzzle target; The second construction module is used to splice any two second graphics in the single graphic rotation set to form a candidate combined graphic, and to screen the candidate combined graphic based on a multi-index evaluation system to construct an optimized combined graphic set corresponding to the puzzle target. The third construction module is used to merge the single graphic rotation set with the optimized combination graphic set to construct the graphic set to be arranged corresponding to the puzzle target; The fourth construction module is used to construct the layer set corresponding to the mother plate based on the geometric information of the mother plate and the set of graphics to be arranged; The determining module is used to determine the extended set of graphics to be arranged corresponding to the panel target based on the set of graphics to be arranged and the set of layers; The optimization module is used to construct a mixed integer linear programming model for the layout optimization of the PCB panel, taking the extended set of graphics to be arranged as input and maximizing the utilization rate of the motherboard material as output, under the condition of satisfying preset constraints.

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