Sram device and method for implementing redundancy repair based on registers

Abstract

The present application relates to sram device and method based on register redundancy repair, by designing address comparison unit and register unit for sram memory without redundant row and column, when redundancy repair is needed, address comparison unit can be used to determine whether to access data in sram memory bank or data in register unit, to achieve the purpose of using register to realize sram redundancy repair mechanism. Compared with the traditional sram repair method, the above repair design realizes the automatic repair process of sram without redundant row and column, thereby reducing the sram design cost and design cycle, compared with sram with redundant row and column, the above repair design can flexibly allocate repair resources according to the failure of sram, and is compatible with the existing EDA tool automatic process.

Description

Technical Field

[0001] This invention belongs to the field of memory chip technology and relates to an SRAM device and method for redundancy repair based on registers. Background Technology

[0002] Most chips currently incorporate SRAM (Static Random Access Memory), and SRAM typically occupies a significant portion of the chip's area; for example, in some chips, SRAM can exceed 50% of the total chip area. Therefore, SRAM failure significantly impacts chip yield, necessitating SRAM repair measures to improve chip yield. Traditional SRAM repair methods involve adding redundant rows or columns during the SRAM design phase. This allows for the replacement of faulty locations with redundant rows or columns during testing. However, this method requires custom SRAM design, increasing design costs and time. Therefore, achieving SRAM repair without adding redundant rows or columns, thereby reducing SRAM design costs and time, has become a key technical challenge. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional methods, this invention proposes an SRAM device and a SRAM repair method based on registers for redundancy repair, which can achieve SRAM repair without adding redundant rows or columns, thereby reducing SRAM design cost and design cycle.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, an SRAM device for redundancy repair based on registers is provided, including a self-test repair module and an SRAM packaging module, wherein the self-test repair module and the SRAM packaging module are connected via an SRAM bus; The self-test repair module is used to obtain repair information from the programmable memory and perform self-tests and repairs on the SRAM memory of the SRAM package module. The SRAM package module includes repair logic and an SRAM memory bank. The SRAM memory bank includes multiple memory blocks with no redundant rows and columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory bank and the address comparison unit are connected to the SRAM bus. The register unit is connected to the address comparison unit. The address comparison unit is used to access the data register currently used to replace the faulty memory location when the repair signal is enabled and the address accessed by the SRAM matches the repair address, based on the received repair information and the SRAM access signal. Otherwise, it accesses the memory location in the SRAM memory bank where the address matches. The register unit includes at least one data register.

[0005] In one embodiment, the logic unit of the self-test repair module includes a built-in self-test controller, a built-in self-test repair controller, a built-in self-test repair analyzer, a built-in self-test repair register, and a built-in self-test interface. The built-in self-test repair register is connected to both the built-in self-test repair controller and the built-in self-test repair analyzer. The built-in self-test repair controller is used to obtain repair information from the programmable memory. The built-in self-test repair register is used to provide repair information to the SRAM package module. The built-in self-test interface is connected to both the built-in self-test controller and the built-in self-test repair analyzer. The built-in self-test interface is connected to the SRAM package module via the SRAM bus. The built-in self-test controller is connected to the built-in self-test repair analyzer.

[0006] In one embodiment, the storage location includes a data word, a byte, or a double data word.

[0007] On the other hand, a register-based redundancy repair method for SRAM is also provided, which is applied to an SRAM device that implements redundancy repair based on registers. The SRAM device includes a self-test repair module and an SRAM packaging module, and the self-test repair module and the SRAM packaging module are connected through an SRAM bus. The self-test repair module is used to obtain repair information from the programmable memory and perform self-tests and repairs on the SRAM memory of the SRAM package module. The SRAM package module includes repair logic and SRAM memory. The SRAM memory includes multiple memory blocks with no redundant rows and columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory and the address comparison unit are connected to the SRAM bus. The register unit is connected to the address comparison unit. The register unit includes at least one data register. The SRAM repair method based on registers for redundancy correction includes the following steps: Based on the DFT library of the SRAM package module, use EDA tools to complete the insertion of logic units and pattern generation of the self-test repair module; The address comparison unit accesses the data register currently used to replace the faulty storage location based on the received repair information and SRAM access signal. If the repair signal is enabled and the SRAM access address matches the repair address, the unit accesses the storage location in the SRAM memory where the address matches. Otherwise, it accesses the storage location in the SRAM memory where the address matches.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned SRAM device and method for redundancy repair based on registers, by designing address comparison units and register units for SRAM memories without redundant rows and columns, allows the address comparison units to determine whether to access data in the SRAM memory or the register unit when redundancy repair is required, thus achieving the goal of implementing an SRAM redundancy repair mechanism using registers. Compared to traditional SRAM repair methods, the above repair design implements an automatic repair process for SRAMs without redundant rows and columns, thereby reducing SRAM design costs and design cycle. Compared to SRAMs with redundant rows and columns, the above repair design can flexibly allocate repair resources according to the SRAM failure situation, is not limited by the SRAM row and column width, can repair as little as one byte, and is compatible with existing EDA tool automation processes. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a block diagram of an SRAM device that implements redundancy repair based on registers in one embodiment. Figure 2 This is a schematic diagram of the repair design process of an SRAM device that implements redundancy repair based on registers in one embodiment. Figure 3 This is a flowchart illustrating an SRAM repair method based on registers for redundancy repair in one embodiment. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0012] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0013] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0014] In one embodiment, such as Figure 1 As shown, a SRAM device for redundancy repair based on registers is provided, including a self-test repair module and an SRAM packaging module, which are connected via an SRAM bus. The self-test repair module is used to obtain repair information from the programmable memory and perform self-testing and repair on the SRAM memory of the SRAM packaging module. The SRAM packaging module includes repair logic and an SRAM memory bank, which includes multiple memory blocks with no redundant rows and columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory bank and the address comparison unit are connected to the SRAM bus, and the register unit is connected to the address comparison unit. The address comparison unit is used to access the data register currently used to replace the faulty memory location when the repair signal is enabled and the address accessed by the SRAM matches the repair address, based on the received repair information and the SRAM access signal; otherwise, it accesses the memory location in the SRAM memory where the address matches the repair address. The register unit includes at least one data register.

[0015] It is understood that the design of this embodiment utilizes data registers to implement the SRAM word repair mechanism (redundancy repair technology), which can achieve repair without adding redundant rows and columns to the SRAM, and is compatible with the existing EDA (Electronic Design Automation) tool automation process.

[0016] Specifically, SRAM word redundancy is simulated using data registers. Based on the structure of the SRAM package module, the SRAM DFT library information is described, a customized MBIST (Built-in Self-Test Logic) algorithm is developed, and the existing mature MBIST repair process is reused. DFT stands for Design for Test, and the SRAM DFT library information refers to the structural description information of the SRAM package module. Different EDA tools describe this information in different formats, using standardized data files for chip-level test integration. The Memory Built-in Self-Test (MBIST) is a Design for Test (DFT) technology that enables autonomous testing of embedded memories (such as SRAM) by embedding test logic circuits (including test vector generators, controllers, and comparators) inside the chip.

[0017] like Figure 1 As shown, the SRAM device for redundant repair based on registers includes two main parts: a self-test repair module and an SRAM packaging module. The programmable memory (efuse) is used to store repair information, such as whether each set of redundant data registers is enabled for repair and the destination address of the repair.

[0018] The self-test repair module (i.e., memory mbist & repair) is a control circuit for performing self-tests (BIST) and repairs on SRAM memory. Further, this module may include: BISC (BIST controller, i.e., built-in self-test controller, used to control the execution of mbist tests, generate test stimuli, and output test results); BISRC (BIST repair controller, used to collect repair information during mbist tests and write it to EFUSE; during normal operation, it loads the EFUSE repair information onto the BISR and allocates it to the corresponding SRAM to be repaired); BIRA (BIST repair analysis, used to determine whether repair is possible based on the mbist execution results; if repair is possible, the corresponding address record is reported to the BISRC via the BISR); and BISR (BIST repair analysis). The repair register, or built-in self-test repair register, is a set of shift registers that capture repair information after the MIST execution is completed and send it to the BISRC, and then program it into the efuse. During normal operation, the BISRC obtains repair information from the efuse and then shifts it to the SRAM that needs repair via the BISR. The BISI (BIST interface, built-in self-test interface, BISI is mainly used to switch between MIST access and normal function access, and to compare whether the data output by the SRAM is consistent with the expected data during the MIST test, and feed the comparison result back to the BISC and BIRA). These logical units are automatically inserted by existing EDA tools according to the structure of the SRAM.

[0019] The SRAM wrapper module (i.e., SRAM_wrapper) includes repair logic and SRAM memory. The SRAM memory can be combined from multiple memory banks to achieve a larger capacity, depending on different usage scenarios. The repair logic includes an address comparison unit and a register unit. The register unit can include at least one data register for replacing erroneous memory locations, such as, but not limited to, SRAM words. Specifically, multiple data registers can be configured to replace multiple erroneous memory locations, thereby achieving greater error tolerance.

[0020] The address comparison unit controls whether data in the SRAM memory is written to or read from the data register. Based on the received repair information and the SRAM access signal, the address comparison unit accesses the data register currently used to replace the faulty memory location when the repair signal is enabled (i.e., valid) and the SRAM access address matches the repair address; otherwise, it accesses the memory location in the SRAM memory where the address matches. The repair address refers to the address of the faulty memory location in the SRAM memory.

[0021] The entire repair process can be as follows Figure 2 As shown, the sram_wrapper is designed first. Based on the sram failure status and resource availability, the number of data registers and the composition of the sram memory are selected. Assuming a word repair design, the data register width is 32 bits. The number of registers selected can be determined based on the size of the sram memory and the failure status. For example, a 16KB sram memory is composed of four 4KB memory blocks. If the failure rate of the 4KB memory blocks is 1%, and 100% of the failures are within two words, there can be a maximum of eight word failures in four blocks. If eight sets of registers are selected, 100% sram repair can be achieved, but the resources consumed will be the most, and in 99% of cases, some of the repair registers will be unused. Since the failure rate of each block is low, two sets can be selected for repair. In this way, any two word failures within 16KB can be repaired, which is a better balance between repair and resource overhead.

[0022] Then, the DFT library for the sram_wrapper (i.e., the sram_wrapper DFT library) is written. This involves designing the DFT library based on the sram_wrapper and the selected EDA tool, describing the sram memory and repair information. EDA tools have specific format definitions for the DFT library they use, which may vary between different tools. The DFT library describes the following information: First, the sram structure, such as the number of sram banks, the sram bank address mapping, and the row and column address mappings for each sram bank; second, the MIST algorithm information, using options like Marchc or Checkboard; and third, the repair information, including the number of redundant word registers and their corresponding comparison addresses.

[0023] Finally, EDA tools are used to insert the relevant logic units for the MBIST and generate the patterns (test stimuli). These are mature processes in existing EDA tools. This step is consistent with SRAM operations with redundancy (i.e., redundant rows and columns) and can be automated by EDA tools. For example, for inserting the relevant logic units for the MBIST, the EDA tool reads the information from the DFT library, generates the relevant logic required by the external storage self-test repair module, and outputs a complete design connected to the designed SRAM storage module. For pattern generation, after generating the self-test repair module, the EDA tool outputs a complete design of the SRAM with test repair. The EDA tool can then generate stimulus signals (patterns) for subsequent testing and repair of the SRAM based on this complete design. These patterns are used to implement the entire process of SRAM MBIST testing, writing SRAM repair information to EFUSE, and EFUSE loading the repair information into the SRAM.

[0024] The aforementioned SRAM device for redundancy repair based on registers, by designing address comparison units and register units for SRAM memories without redundant rows and columns, allows the address comparison units to determine whether to access data in the SRAM memory or the register unit when redundancy repair is needed. This achieves the goal of implementing an SRAM redundancy repair mechanism using registers. Compared to traditional SRAM repair methods, the above repair design implements an automatic repair process for SRAMs without redundant rows and columns, thereby reducing SRAM design costs and design cycle. Compared to SRAMs with redundant rows and columns, the above repair design can flexibly allocate repair resources according to the SRAM failure status and is compatible with existing EDA tool automation processes.

[0025] In one embodiment, the storage location includes a data word, a byte, or a double data word.

[0026] It is understood that in this embodiment, the SRAM device that implements redundancy repair based on registers has flexible and adjustable granularity during redundancy repair. For example, by replacing the storage location word with byte or double word, repair at different granularities can be achieved, thereby further compatibility with different SRAM designs. Moreover, this repair information can be shared between different SRAM banks, achieving better design cost and design cycle reduction effects.

[0027] Each module component in the aforementioned SRAM device for redundancy repair based on registers can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of a device with data processing capabilities, or stored in software within the memory of the aforementioned device, so that the processor can invoke and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of verification computer devices already existing in the art.

[0028] In one embodiment, a register-based SRAM repair method for redundancy repair is also provided, applied to an SRAM device for register-based redundancy repair. The SRAM device includes a self-test repair module and an SRAM packaging module, which are connected via an SRAM bus. The self-test repair module obtains repair information from a programmable memory and performs self-testing and repair on the SRAM memory of the SRAM packaging module. The SRAM packaging module includes repair logic and an SRAM memory bank. The SRAM memory bank includes multiple memory blocks with no redundant rows or columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory bank and the address comparison unit are connected to the SRAM bus, and the register unit is connected to the address comparison unit. The register unit includes at least one data register.

[0029] like Figure 3 As shown, the SRAM repair method based on register redundancy repair may include the following steps S12 to S14: S12, based on the DFT library of the SRAM package module, use EDA tools to complete the insertion of logic units and pattern generation of the self-test repair module; S14, the address comparison unit accesses the data register currently used to replace the faulty storage location based on the received repair information and SRAM access signal. If the repair signal is enabled and the SRAM access address matches the repair address, the unit accesses the storage location in the SRAM memory where the address matches.

[0030] It is understandable that the specific limitations of the SRAM repair method based on register redundancy repair can be found in the corresponding limitations of the SRAM device based on register redundancy repair mentioned above, and will not be repeated here.

[0031] The aforementioned SRAM repair method based on register-based redundancy repair utilizes address comparison units and register units designed for SRAM memories without redundant rows and columns. When redundancy repair is required, the address comparison unit determines whether to access data in the SRAM memory or the register unit, thus achieving the goal of implementing an SRAM redundancy repair mechanism using registers. Compared to traditional SRAM repair methods, this repair design implements an automatic repair process for SRAMs without redundant rows and columns, thereby reducing SRAM design costs and cycle time. Compared to SRAMs with redundant rows and columns, this repair design can flexibly allocate repair resources based on SRAM failure conditions and is compatible with existing EDA tool automation processes.

[0032] In one embodiment, the logic unit of the self-test repair module includes a built-in self-test controller, a built-in self-test repair controller, a built-in self-test repair analyzer, a built-in self-test repair register, and a built-in self-test interface. The built-in self-test repair register is connected to both the built-in self-test repair controller and the built-in self-test repair analyzer. The built-in self-test repair controller is used to obtain repair information from the programmable memory. The built-in self-test repair register is used to provide repair information to the SRAM package module. The built-in self-test interface is connected to both the built-in self-test controller and the built-in self-test repair analyzer. The built-in self-test interface is connected to the SRAM package module via the SRAM bus. The built-in self-test controller is connected to the built-in self-test repair analyzer.

[0033] In one embodiment, the storage location includes a data word, a byte, or a double data word.

[0034] It should be understood that, although Figure 3 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 3 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. An SRAM device for redundancy repair based on registers, characterized in that, It includes a self-test repair module and an SRAM package module, with the self-test repair module and the SRAM package module connected via an SRAM bus; The self-test repair module is used to obtain repair information from the programmable memory and perform self-tests and repairs on the SRAM memory of the SRAM package module. The SRAM package module includes repair logic and an SRAM memory bank. The SRAM memory bank includes multiple memory blocks with no redundant rows and columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory bank and the address comparison unit are connected to the SRAM bus, and the register unit is connected to the address comparison unit. The address comparison unit is used to access the data register currently used to replace the faulty memory location when the repair signal is enabled and the address accessed by the SRAM matches the repair address, based on the received repair information and the SRAM access signal. Otherwise, it accesses the memory location in the SRAM memory bank where the address matches. The register unit includes at least one data register.

2. The SRAM device for redundancy repair based on registers according to claim 1, characterized in that, The logic unit of the self-test repair module includes a built-in self-test controller, a built-in self-test repair controller, a built-in self-test repair analyzer, a built-in self-test repair registry, and a built-in self-test interface. The built-in self-test repair registry is connected to both the built-in self-test repair controller and the built-in self-test repair analyzer. The built-in self-test repair controller is used to obtain repair information from the programmable memory. The built-in self-test repair registry is used to provide repair information to the SRAM package module. The built-in self-test interface is connected to both the built-in self-test controller and the built-in self-test repair analyzer. The built-in self-test interface is connected to the SRAM package module via the SRAM bus. The built-in self-test controller is connected to the built-in self-test repair analyzer.

3. The SRAM device for redundancy repair based on registers according to claim 1 or 2, characterized in that, Storage locations include data words, bytes, or double data words.

4. A SRAM repair method based on register-based redundancy repair, characterized in that, This is applied to an SRAM device that implements redundancy repair based on registers. The SRAM device includes a self-test repair module and an SRAM packaging module, which are connected via an SRAM bus. The self-test repair module is used to obtain repair information from the programmable memory and perform self-tests and repairs on the SRAM memory of the SRAM package module. The SRAM package module includes repair logic and SRAM memory. The SRAM memory includes multiple memory blocks with no redundant rows and columns. The repair logic includes an address comparison unit and a register unit. Both the SRAM memory and the address comparison unit are connected to the SRAM bus. The register unit is connected to the address comparison unit. The register unit includes at least one data register; The SRAM repair method based on registers for redundancy correction includes the following steps: Based on the DFT library of the SRAM package module, use EDA tools to complete the insertion of logic units and pattern generation of the self-test repair module; The address comparison unit accesses the data register currently used to replace the faulty storage location based on the received repair information and SRAM access signal. If the repair signal is enabled and the SRAM access address matches the repair address, the unit accesses the storage location in the SRAM memory where the address matches. Otherwise, it accesses the storage location in the SRAM memory where the address matches.

5. The SRAM repair method based on register-based redundancy repair according to claim 4, characterized in that, The logic unit of the self-test repair module includes a built-in self-test controller, a built-in self-test repair controller, a built-in self-test repair analyzer, a built-in self-test repair registry, and a built-in self-test interface. The built-in self-test repair registry is connected to both the built-in self-test repair controller and the built-in self-test repair analyzer. The built-in self-test repair controller is used to obtain repair information from the programmable memory. The built-in self-test repair registry is used to provide repair information to the SRAM package module. The built-in self-test interface is connected to both the built-in self-test controller and the built-in self-test repair analyzer. The built-in self-test interface is connected to the SRAM package module via the SRAM bus. The built-in self-test controller is connected to the built-in self-test repair analyzer.

6. The SRAM repair method based on register-based redundancy repair according to claim 4 or 5, characterized in that, Storage locations include data words, bytes, or double data words.

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