A method for reducing the probability of occurrence of unc errors in an ssd storage device
By implementing active and passive data inspection in SSD storage devices and dynamically updating the read reference voltage level, the problem of high UNC error incidence is solved, the performance and reliability of the device are improved in high-concurrency and variable-temperature environments, and hardware costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies in SSD storage devices suffer from problems such as a high probability of UNC errors, performance loss, high cost, and poor adaptability to different scenarios, especially affecting the reliability and stability of the device under high temperature variations and high concurrency scenarios.
By employing active and passive data inspection mechanisms, the optimal reference voltage level is dynamically updated. Combined with optimization for variable temperature scenarios, the probability of UNC errors is reduced. This is achieved using firmware algorithms without the need for additional hardware resources.
It improves the read success rate of SSDs in high-concurrency and high-real-time scenarios, reduces read latency and performance fluctuations, lowers hardware costs, and enhances the stability and lifespan of devices in variable temperature environments.
Smart Images
Figure CN122116996A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SSD storage technology, and in particular to a method for reducing the probability of UNC errors in SSD storage devices. Background Technology
[0002] SSD storage devices are widely used in consumer electronics, data centers, and industrial control due to their advantages such as high-speed read / write speeds, low power consumption, and shock resistance. They primarily use NAND flash memory as their storage medium. However, due to the physical characteristics of NAND flash memory, such as charge leakage, read disturbances, data retention degradation, and temperature sensitivity, uncorrectable errors (UNCs) are prone to occur under long-term use or specific scenarios. UNC errors lead to permanent data loss, severely impacting the reliability of storage devices. To address this issue, the industry currently mainly employs the following technical methods: 1. Hardware LDPC error correction technology: This technology enhances error correction capabilities by integrating low-density parity check (LDPC) encoding and decoding circuits into the main control chip. However, this method has significant limitations: supporting LDPC algorithms with stronger error correction capabilities requires more complex hardware circuits, which increases the size and cost of the main control chip. This is especially problematic for cost-sensitive consumer-grade SSDs, making it difficult to balance performance and cost-effectiveness.
[0003] 2. Read Retry Mechanism: When a UNC error occurs during the initial read operation, the SSD firmware automatically adjusts the read reference voltage to retry and recover the data. However, the read voltage retry process requires multiple accesses to the NAND flash memory, consuming I / O resources and significantly increasing read latency. In high-concurrency or real-time-critical applications (such as databases or virtualization environments), this performance fluctuation can severely impact system stability.
[0004] 3. RAID-based data redundancy scheme: This scheme distributes data across multiple NAND flash memory chips using mirroring or striping, and uses redundant information to correct errors. However, this method requires additional flash memory chips as redundancy space, increasing hardware costs. Furthermore, redundant data management introduces additional power consumption and latency, making it unsuitable for low-cost, high-density storage needs.
[0005] Furthermore, NAND flash memory is highly sensitive to temperature changes. In variable temperature scenarios (such as high-temperature write followed by low-temperature read, or low-temperature write followed by high-temperature read), the charge retention characteristics of flash cells change, leading to increased read voltage offset and a significant increase in the probability of UNC errors. Current technologies lack targeted temperature adaptation mechanisms, increasing the frequency of read voltage retries and further amplifying performance loss.
[0006] In summary, while existing technologies can partially mitigate UNC errors, they suffer from three major drawbacks: Performance loss: Mechanisms such as read voltage retry introduce additional latency, making it difficult to meet the demands of high-performance applications. High cost: Hardware error correction and redundancy schemes increase the cost of chips and flash memory. Poor scenario adaptability: Lack of optimization in complex environments such as varying temperatures leads to reliability fluctuations.
[0007] Therefore, there is an urgent need in this field for a low-cost, high-performance UNC error prevention solution that can adapt to environmental changes in order to enhance the overall competitiveness of SSDs. Summary of the Invention
[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method to reduce the probability of UNC errors in SSD storage devices.
[0009] The objective of this invention is achieved through the following technical solution: a method for reducing the probability of UNC errors in SSD storage devices, comprising the following steps: Active data inspection phase: The firmware periodically triggers read operation inspections of the data written to the NAND flash memory, updates the optimal read reference voltage level or rewrites data on the verge of error based on the inspection results, and prevents UNC errors from occurring. Passive data inspection phase: triggered by host IO operation, read operation inspection is performed on data where the number of LDPC ECC failure bits exceeds the warning value during read IO, and the optimal read reference voltage level is updated or the data on the verge of error is rewritten based on the inspection results; Read reference voltage optimization phase: Maintain and update the optimal read reference voltage range information of the written data, and prioritize the use of the optimal read reference voltage range during read operations to reduce the time overhead of read operations; In the variable temperature scenario, the optimal read reference voltage selection and optimization stage is as follows: based on the read and write scenarios during data writing and reading, the optimal read reference voltage level is matched and prioritized according to the classification and sorting.
[0010] Preferably, the triggering conditions for the active data inspection phase include at least one of the following: the SSD is powered on for the first time, the number of P / E cycles and the temperature reach a threshold, the data retention time reaches a threshold, or the number of read disturbances reaches a threshold; wherein, the higher the number of P / E cycles or the higher the temperature, the shorter the inspection cycle.
[0011] Preferably, the inspection data range during the active data inspection phase is dynamically adjusted based on the triggering conditions: For periodic inspections triggered by initial power-on, P / E cycles, and temperature, read operation inspections are performed on all blocks with written data. For periodic inspections triggered by Data Retention time and Read Disturb count, only the blocks containing data that have reached the threshold are inspected for read operations.
[0012] Preferably, the inspection method for read operation inspection in the active data inspection phase includes: For periodic inspections triggered by initial power-on, P / E cycles, temperature, and Data Retention time, a WL is selected for each physical layer of the block to be inspected, and all reference read voltage levels are checked by page. For inspections triggered by the number of Read Disturb reads, the inspection of the block to be inspected is performed by page for all WLs of each physical layer, covering all reference read voltage levels.
[0013] Preferably, the data active inspection phase and the data passive inspection phase, when processing the inspection results, include the following steps: Each page read operation returns the number of LDPC ECC failure bits to determine whether the data on that page is on the verge of error. If the number of bits is below the threshold, the optimal read reference voltage level for that data location is updated. If the number of bits is above the threshold, the data on the verge of error is rewritten to a block with a better state.
[0014] Preferably, the method for updating the optimal read reference voltage level information during the read reference voltage optimization phase includes at least one of the following: When the SSD is powered on, a read operation check is performed on all written data, and the optimal read reference voltage level for all data is constructed based on the number of LDPC ECC failure bits. The optimal reference voltage level for updating the corresponding data after periodic active or passive inspection; After the host reads an I / O and enters the Read Retry process, the optimal read reference voltage level of the page containing the data and other data in the same layer of the NAND flash physical block is used as the optimal read reference voltage level for a successful Read Retry.
[0015] Preferably, the step of optimizing the selection of the reference voltage for the variable temperature scenario further includes the following steps: The optimal read reference voltage levels are categorized and sorted according to usage scenarios, including high-temperature write and low-temperature read levels, low-temperature write and high-temperature read levels, and Data Retention levels. Record the writing temperature and writing time when writing data, and query the reading temperature and reading time when reading data, and match the priority level category according to the writing scenario and reading scenario.
[0016] The beneficial effects of this invention are: 1) Through proactive and passive data inspection mechanisms, this invention can proactively identify and repair data on the verge of error (such as data decay caused by charge leakage) before UNC errors occur, avoiding frequent triggering of traditional read voltage retries. This improves the first-read success rate by prioritizing the use of the optimal read reference voltage level during read operations, reducing the probability of entering the read voltage retrieval process and lowering read latency. This is particularly suitable for high-concurrency or high-real-time application scenarios (such as databases and cloud computing). It also reduces performance fluctuations: the inspection mechanism is implemented in firmware, without interrupting normal I / O operations, effectively avoiding precipitous performance drops caused by read retries and ensuring the performance consistency of the SSD during long-term operation.
[0017] 2) This invention is implemented entirely through firmware algorithms, without relying on additional hardware resources (such as high-performance LDPC chips or redundant flash memory). It enhances reliability without increasing hardware costs, offering a significant cost advantage: traditional solutions require enhanced LDPC error correction capabilities or RAID redundancy to address UNC errors, while this invention achieves reliability improvements based on existing controller chips and NAND flash memory through intelligent inspection and voltage optimization, making it suitable for consumer-grade or cost-sensitive SSD products. The solution is based on firmware logic, adaptable to NAND flash memory chips from different manufacturers, eliminating the need for customized modifications for specific hardware, thus lowering the barriers to technology portability and commercialization.
[0018] 3) Addressing the pain point of UNC errors in NAND flash memory under temperature variations, this invention effectively responds to temperature shocks through a dynamic read reference voltage classification and matching mechanism. This reduces performance loss caused by temperature fluctuations, automatically matching the optimal voltage level in scenarios such as high-temperature write / low-temperature read and low-temperature write / high-temperature read, reducing the probability of read retry and significantly improving the stability of industrial-grade SSDs in wide-temperature environments. Through preventative data migration (rewriting data on the verge of error), it reduces read interference and write wear on flash memory blocks, indirectly extending the lifespan of the SSD.
[0019] 4) The inspection and voltage optimization mechanism of this invention forms a dynamic feedback closed loop, possessing continuous evolution capabilities: Through periodic inspections and passive inspections triggered by host I / O, the system can learn the flash memory degradation pattern in real time, dynamically update the voltage level strategy, and adapt to the aging characteristics of different usage stages. The firmware implementation supports remote upgrades and parameter adjustments, and can flexibly integrate new inspection strategies (such as AI-based predictive models), reserving space for future technology iterations. Attached Figure Description
[0020] Figure 1 This is a flowchart illustrating the overall method of the present invention; Figure 2 Flowchart for the proactive data inspection phase; Figure 3 Flowchart for the passive data inspection phase; Figure 4 Optimization phase flowchart for reading reference voltage; Figure 5 Flowchart for the optimization phase of reading reference voltage in variable temperature scenarios. Detailed Implementation
[0021] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] First, the meanings of some English words or abbreviations appearing in this invention are explained: SSD: Solid State Drive, a storage device based on flash memory.
[0023] NAND flash memory: a non-volatile storage medium that stores charge through floating-gate transistors, is the core component of SSDs.
[0024] UNC: Uncorrectable Error, refers to data errors that are beyond the ability to be corrected, resulting in permanent data loss.
[0025] LDPC: Low-Density Parity-Check, a forward error correction coding technique used to detect and repair data errors.
[0026] Read Retry: The read voltage retry mechanism adjusts the read reference voltage to reread data in response to UNC errors.
[0027] RAID: Redundant Array of Independent Disks, which improves reliability through data distribution and redundancy.
[0028] IO: Input / Output operations refer to data transfer between the host and the SSD.
[0029] P / E cycles: Program / Erase cycles, reflecting the wear and tear of NAND flash memory.
[0030] Data Retention: This refers to the ability of a flash memory cell to retain its charge in the absence of power.
[0031] Read Disturb: The phenomenon of charge leakage between adjacent cells when frequently reading a certain area.
[0032] DMA: Direct Memory Access, allows peripherals to read and write memory directly without going through the CPU.
[0033] ECC: Error Correction Code, used to detect and correct data errors.
[0034] TLC: Triple-Level Cell, a type of NAND flash memory where each cell stores 3 bits of data.
[0035] WL: Word Line, a wire in NAND flash memory that connects memory cells in the same row.
[0036] Page: The smallest unit of reading and writing in NAND flash memory.
[0037] Block: A unit of flash memory erasure consisting of multiple pages.
[0038] Layer: Physical layer, refers to the vertically stacked storage layers in 3D NAND flash memory.
[0039] See Figures 1-5 This invention provides a technical solution: a method for reducing the probability of UNC errors in SSD storage devices, comprising the following steps: Active data inspection phase: The firmware periodically triggers read operation inspections of the data written to the NAND flash memory, updates the optimal read reference voltage level or rewrites data on the verge of error based on the inspection results, and prevents UNC errors from occurring. Passive data inspection phase: triggered by host IO operation, read operation inspection is performed on data where the number of LDPC ECC failure bits exceeds the warning value during read IO, and the optimal read reference voltage level is updated or the data on the verge of error is rewritten based on the inspection results; Read reference voltage optimization phase: Maintain and update the optimal read reference voltage range information of the written data, and prioritize the use of the optimal read reference voltage range during read operations to reduce the time overhead of read operations; In the variable temperature scenario, the optimal read reference voltage selection and optimization stage is as follows: based on the read and write scenarios during data writing and reading, the optimal read reference voltage level is matched and prioritized according to the classification and sorting.
[0040] In this embodiment, the present invention can improve SSD performance and reduce the probability of UNC (Unique Non-Common) without increasing costs. Furthermore, this solution is implemented based on SSD firmware, reducing the specific compatibility requirements with the chip and NAND flash memory, thus possessing greater commercial value for widespread adoption.
[0041] The key points of this invention can be divided into the following aspects: 1. Active Data Inspection: The system performs read operations on the data written to the NAND flash memory within a certain period of time. Based on the number of LDPC ECC failure bits, it actively detects and repairs data that is on the verge of error due to charge leakage (data retention capacity decay) and performs corresponding processing before UNC occurs.
[0042] 2. Passive data inspection: For host IO data, for each DMA operation, based on the number of LDPC ECC failure bits, proactively detect and repair data that is on the verge of error due to charge leakage (data retention capacity decay), and perform corresponding processing before UNC occurs.
[0043] 3. Optimized Read Reference Voltage: The optimal read reference voltage for the current NAND flash memory is established through power-on inspection and read retry, thereby reducing the time overhead of read operations.
[0044] 4. Optimization of read reference voltage selection in variable temperature scenarios: In scenarios such as writing at high temperature and reading at low temperature, or writing at low temperature and reading at high temperature, the corresponding read reference voltage index is selected first based on the index to reduce the time overhead of read operations.
[0045] In some embodiments, the triggering conditions for the active data inspection phase include at least one of the following: the SSD is powered on for the first time, the number of P / E cycles and the temperature reach a threshold, the data retention time reaches a threshold, or the number of read disturbances reaches a threshold; wherein, the higher the number of P / E cycles or the higher the temperature, the shorter the inspection cycle.
[0046] In some embodiments, the scope of the inspection data in the active data inspection phase is dynamically adjusted according to the triggering conditions: For periodic inspections triggered by initial power-on, P / E cycles, and temperature, read operation inspections are performed on all blocks with written data. For periodic inspections triggered by Data Retention time and Read Disturb count, only the blocks containing data that have reached the threshold are inspected for read operations.
[0047] In some embodiments, the inspection method for read operation inspection during the active data inspection phase includes: For periodic inspections triggered by initial power-on, P / E cycles, temperature, and Data Retention time, a WL is selected for each physical layer of the block to be inspected, and all reference read voltage levels are checked by page. For inspections triggered by the number of Read Disturb reads, the inspection of the block to be inspected is performed by page for all WLs of each physical layer, covering all reference read voltage levels.
[0048] In this embodiment, as Figure 2 As shown, during the active data inspection phase, the firmware periodically performs read operation inspections on the data written to the NAND flash memory. The firmware actively triggers read operation inspections of written data upon first power-on, during normal operation, or based on factors such as the P / E count, temperature, Data Retention time, and Read Disturb strategy of the flash memory. The P / E count and temperature follow a pattern: higher P / E counts result in shorter inspection cycles, and higher temperatures also result in shorter inspection cycles. The Data Retention time is a data storage duration threshold derived from manufacturer reference values and flash memory analysis experiments. The Read Disturb threshold is a maximum data read count threshold derived from manufacturer reference values and flash memory analysis experiments. Data inspection is triggered when any of these conditions reaches the threshold.
[0049] Inspection data range: For power-on inspections and periodic inspections triggered by P / E cycles and temperature, read operations will be performed on all blocks with written data. For inspections triggered by Data Retention and Read Disturbance, read operations will only be performed on the blocks containing data that have reached the threshold.
[0050] Read operation inspection method: For inspections triggered by power-on, P / E cycles, temperature, and Data Retention, to improve inspection efficiency, a read operation inspection of all reference read voltage levels will be performed on a page-by-page basis for each physical layer of the block to be inspected. For inspections triggered by Read Disturbance, a read operation inspection of all reference read voltage levels will be performed on a page-by-page basis for all read voltage levels of the block to be inspected, covering all read voltage levels for each physical layer.
[0051] Inspection result processing: Each page read operation returns the number of LDPC ECC failure bits, which is used to determine whether the data on that page is on the verge of error. If it does not exceed the threshold, it means that the data is still relatively robust, and only the optimal reference read voltage level information at that position needs to be updated; if it exceeds the threshold, it means that the data is on the verge of error and there is a risk of UNC. In this case, the data on the verge of error will be rewritten to a block with a better status.
[0052] In some embodiments, when processing the inspection results in the active data inspection phase and the passive data inspection phase, the following steps are included: Each page read operation returns the number of LDPC ECC failure bits to determine whether the data on that page is on the verge of error. If the number of bits is below the threshold, the optimal read reference voltage level for that data location is updated. If the number of bits is above the threshold, the data on the verge of error is rewritten to a block with a better state.
[0053] In this embodiment, as Figure 3 As shown, the passive inspection phase of the data passive inspection is triggered by host I / O.
[0054] Passive inspection trigger condition: Host read IO operation, although no UNC occurred, the number of LDPCECC failure bits exceeded the warning value.
[0055] Inspection data range: Passive inspection will only inspect the block containing data that exceeds the warning value during read IO.
[0056] Read operation inspection method: Passive inspection will perform read operation inspections on all reference read voltage levels for each physical layer and all WLs by page for the block to be inspected.
[0057] The processing of inspection results is the same as that of the proactive data inspection phase.
[0058] In some embodiments, the method for updating the optimal read reference voltage level information during the read reference voltage optimization phase includes at least one of the following: When the SSD is powered on, a read operation check is performed on all written data, and the optimal read reference voltage level for all data is constructed based on the number of LDPC ECC failure bits. The optimal reference voltage level for updating the corresponding data after periodic active or passive inspection; After the host reads an I / O and enters the Read Retry process, the optimal read reference voltage level of the page containing the data and other data in the same layer of the NAND flash physical block is used as the optimal read reference voltage level for a successful Read Retry.
[0059] In this embodiment, as Figure 4 As shown, the SSD firmware maintains the optimal read reference voltage level information for written data, and uses this optimal read reference voltage level first during each data read operation. The SSD firmware establishes the current optimal read reference voltage for the NAND flash memory through power-on checks and read retry mechanisms to reduce the time overhead of read operations.
[0060] Optimal read voltage level update: When the SSD is powered on, the firmware will perform read operation inspection on all written data. During the read inspection, the optimal read reference voltage level for all data will be constructed based on the number of LDPC ECC failure bits. Periodic active and passive inspections will also update the optimal read reference voltage level for the corresponding data. When the host read IO enters the ReadRetry process, the optimal voltage level of the page where the data is located and other data in the same layer of the NAND flash physical block will also be updated to the level of successful Read Retry.
[0061] Optimal read voltage level usage: When reading written data, the SSD firmware prioritizes using the optimal read reference voltage level at the data location to improve the success rate of the first read, reduce the chance of entering a read retry, and minimize time overhead. If a read retry process is entered while reading data, since NAND flash memory is divided into different layers, each layer has similar physical characteristics. After a successful read retry, the optimal voltage level for the same type of page within the same layer (e.g., low page, middle page, and up page for TLC chips) is updated to the level where the read retry was successful. This way, the next time data is read from other pages within the same layer, the optimal read voltage level will be used first, further improving the first read success rate.
[0062] In some embodiments, the step of selecting and optimizing the reference voltage for variable temperature scenarios further includes the following steps: The optimal read reference voltage levels are categorized and sorted according to usage scenarios, including high-temperature write and low-temperature read levels, low-temperature write and high-temperature read levels, and Data Retention levels. Record the writing temperature and writing time when writing data, and query the reading temperature and reading time when reading data, and match the priority level category according to the writing scenario and reading scenario.
[0063] In this embodiment, as Figure 5 As shown, in scenarios such as high-temperature write and low-temperature read, and low-temperature write and high-temperature, after entering ReadRetry, the corresponding read reference voltage index is selected first according to the index to reduce the time overhead of the read operation.
[0064] Optimal read voltage levels are categorized and sorted: The firmware categorizes and sorts the optimal read reference voltage levels obtained from NAND flash memory manufacturers and chip experiments according to different usage scenarios and types, such as high temperature write low temperature read levels, low temperature write high temperature levels, and Data Retention levels. Data read / write scenario matching: During data writing, the system records the writing scenario, such as writing temperature and writing time; during data reading, it queries the current reading scenario, such as reading temperature and reading time. The firmware determines which category of optimal read voltage to prioritize based on the writing and reading scenarios. For example, if the chip temperature is 90 degrees Celsius during writing and -20 degrees Celsius during reading, it can prioritize trying the high-temperature write and low-temperature read voltage category.
[0065] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for reducing the probability of UNC errors in SSD storage devices, characterized in that: Includes the following steps: Active data inspection phase: The firmware periodically triggers read operation inspections of the data written to the NAND flash memory, updates the optimal read reference voltage level or rewrites data on the verge of error based on the inspection results, and prevents UNC errors from occurring. Passive data inspection phase: triggered by host IO operation, read operation inspection is performed on data where the number of LDPC ECC failure bits exceeds the warning value during read IO, and the optimal read reference voltage level is updated or the data on the verge of error is rewritten based on the inspection results; Read reference voltage optimization phase: Maintain and update the optimal read reference voltage range information of the written data, and prioritize the use of the optimal read reference voltage range during read operations to reduce the time overhead of read operations; In the variable temperature scenario, the optimal read reference voltage selection and optimization stage is as follows: based on the read and write scenarios during data writing and reading, the optimal read reference voltage level is matched and prioritized according to the classification and sorting.
2. The method for reducing the probability of UNC errors in SSD storage devices according to claim 1, characterized in that: The triggering conditions for the active data inspection phase include at least one of the following: the SSD is powered on for the first time, the number of P / E cycles and the temperature reach a threshold, the data retention time reaches a threshold, or the number of read disturbances reaches a threshold; wherein, the higher the number of P / E cycles or the higher the temperature, the shorter the inspection cycle.
3. The method for reducing the probability of UNC errors in SSD storage devices according to claim 2, characterized in that: The scope of inspection data in the active data inspection phase is dynamically adjusted according to the triggering conditions: For periodic inspections triggered by initial power-on, P / E cycles, and temperature, read operation inspections are performed on all blocks with written data. For periodic inspections triggered by Data Retention time and Read Disturb count, only the blocks containing data that have reached the threshold are inspected for read operations.
4. The method for reducing the probability of UNC errors in SSD storage devices according to claim 1, characterized in that: The inspection methods for read operation inspection in the active data inspection phase include: For periodic inspections triggered by initial power-on, P / E cycles, temperature, and Data Retention time, a WL is selected for each physical layer of the block to be inspected, and all reference read voltage levels are checked by page. For inspections triggered by the number of Read Disturb reads, the inspection of the block to be inspected is performed by page for all WLs of each physical layer, covering all reference read voltage levels.
5. The method for reducing the probability of UNC errors in SSD storage devices according to claim 1, characterized in that: The data active inspection phase and the data passive inspection phase, when processing the inspection results, include the following steps: Each page read operation returns the number of LDPC ECC failure bits to determine whether the data on that page is on the verge of error. If the number of bits is below the threshold, the optimal read reference voltage level for that data location is updated. If the number of bits is above the threshold, the data on the verge of error is rewritten to a block with a better state.
6. The method for reducing the probability of UNC errors in SSD storage devices according to claim 1, characterized in that: The method for updating the optimal read reference voltage level information during the optimization phase includes at least one of the following: When the SSD is powered on, a read operation check is performed on all written data, and the optimal read reference voltage level for all data is constructed based on the number of LDPC ECC failure bits. The optimal reference voltage level for updating the corresponding data after periodic active or passive inspection; After the host reads an I / O and enters the Read Retry process, the optimal read reference voltage level of the page containing the data and other data in the same layer of the NAND flash physical block is used as the optimal read reference voltage level for a successful Read Retry.
7. The method for reducing the probability of UNC errors in SSD storage devices according to claim 1, characterized in that: The aforementioned optimization stage for selecting the reference voltage in variable temperature scenarios also includes the following steps: The optimal read reference voltage levels are categorized and sorted according to usage scenarios, including high-temperature write and low-temperature read levels, low-temperature write and high-temperature read levels, and Data Retention levels. Record the writing temperature and writing time when writing data, and query the reading temperature and reading time when reading data, and match the priority level category according to the writing scenario and reading scenario.