A method for manufacturing a high-speed DFB laser

Abstract

The application relates to the technical field of optoelectronic device manufacturing, in particular to a preparation method of a high-speed DFB laser, which comprises the following steps: S1, substrate cleaning and bottom layer epitaxial growth; S2, grating mask manufacturing; S3, first RIE shallow etching; S4, selective chemical etching and mask adjustment; S5, second RIE deep etching; S6, mask removal and secondary epitaxy; S7, ridge waveguide photoetching and dry etching; S8, third epitaxy; S9, P-type contact layer growth and window opening; S10, ohmic contact metallization; S11, passivation, anti-reflection coating and dicing. The application adopts step-by-step grating etching technology, divides grating preparation into three stages of shallow etching, selective etching and deep etching, and realizes accurate decoupling control of grating period, width, depth and duty cycle.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic device manufacturing technology, and in particular to a method for preparing a high-speed DFB laser. Background Technology

[0002] Due to their excellent single-mode characteristics, narrow linewidth, and good temperature stability, DFB lasers have become core light source devices in optical communication systems. DFB lasers achieve distributed feedback and single-mode oscillation of the optical field by introducing a periodic grating structure near the active region and utilizing the Bragg diffraction effect. Their core performance is closely related to the grating structure, waveguide structure, and the material properties of the active region.

[0003] Currently, DFB lasers are generally fabricated using a two-step epitaxial growth method. The core process is as follows: First, a first epitaxial growth is performed on an n-InP substrate to form the underlying structure, including a buffer layer and a grating substrate. Then, a grating mask is fabricated using holographic or electron beam lithography, and the grating structure is formed through a one-step reactive ion etching (RIE) process. Finally, a second epitaxial growth is performed to cover the active region, cladding, and other upper structures, completing the device fabrication. Traditional two-step epitaxial growth methods only use a one-step RIE etching process to form the grating in the fabrication of DFB lasers. Due to factors such as the anisotropy of ion bombardment, mask loss, and fluctuations in the etching gas composition during etching, it is difficult to precisely control the grating depth and sidewall perpendicularity. This results in problems such as sidewall roughness, uneven depth, and duty cycle deviation in the grating structure, thus affecting the stability of optical signal transmission. Therefore, a high-speed DFB laser fabrication method is needed. Summary of the Invention

[0004] The purpose of this invention is to solve the problem of insufficient control precision of grating structure in the traditional DFB laser fabrication process, and to propose a method for fabricating a high-speed DFB laser.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for fabricating a high-speed DFB laser, comprising the following steps: S1: Substrate cleaning and epitaxial growth of the underlying layer: n-InP was selected as the substrate. After cleaning, an n-type InP buffer layer and an InGaAsP grating substrate layer were grown sequentially by MOCVD technology. S2: Grating mask fabrication: Using electron beam lithography, a precisely periodic grating mask is fabricated on the surface of the InGaAsP grating substrate. S3: First RIE shallow etching: Shallow etching is performed using ICP-RIE process to lock the grating period and initial width; S4: Selective chemical etching and mask adjustment: Fine-tuning the grating duty cycle using a mixed etching solution to improve sidewall smoothness; S5: Second RIE deep etching: Deep etching is performed through ICP-RIE process to form a step-by-step etched grating with a high aspect ratio; S6: Mask Removal and Secondary Epitaxy: After removing the grating mask, InP spacer, strain-compensated multi-quantum-well active region and upper InP waveguide layer are grown sequentially by MOCVD technology. S7: Ridge waveguide photolithography and dry etching: A composite process combining photolithography with ICP-RIE dry etching and wet etching is used to etch a narrow ridge waveguide mesa on the secondary epitaxial layer. S8: Third epitaxy: Using MOCVD selective epitaxy technology, Fe-doped semi-insulating InP buried layers are grown on both sides of the ridge waveguide mesa, completely covering the sidewalls of the ridge waveguide mesa. S9: P-type contact layer growth and window opening: Grow a P-type InP cladding layer and a P+ contact layer, and open the electrode window by photolithography etching; S10: Ohmic contact metallization: P-type top electrode and N-type bottom electrode are prepared by electron beam evaporation technology and annealed to form ohmic contact; S11: Passivation, Anti-reflection Coating and Dicing: Passivation, anti-reflection coating and dicing are performed sequentially to complete device fabrication.

[0006] As a further description of the above technical solution: The substrate cleaning process in step S1 is as follows: Acetone and ethanol are used sequentially for ultrasonic cleaning for 10-15 minutes each to remove organic contaminants from the substrate surface; then, a mixed solution of H2SO4:H2O2:H2O (volume ratio 3:1:1) is used for chemical etching at a temperature of 25℃-30℃ for 2-3 minutes to remove the oxide and damaged layers from the substrate surface; finally, the substrate is rinsed thoroughly with deionized water and dried under a nitrogen atmosphere; the n-type InP buffer layer has a thickness of 200-500 nm and a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The bandgap of the InGaAsP grating substrate corresponds to a wavelength of 1.1-1.3 μm, a thickness of 300-600 nm, and a doping concentration of 5 × 10⁻⁶. 17 -1×10 18 cm -3 .

[0007] As a further description of the above technical solution: In step S2, the electron beam exposure technology uses a positive electron beam resist, the spin coating speed is 3000-5000 rpm, the spin coating time is 30-60s, and the pre-baking treatment is carried out at 180℃-200℃ for 2-3 minutes to form a resist film layer with a thickness of 200-300nm.

[0008] As a further description of the above technical solution: In step S3, the etching gas is a mixture of CH4 and H2 with a volume ratio of 1:3-5, the etching pressure is 10-20 mTorr, the RF power is 50-80 W, the etching time is 30-60 s, and the etching depth is 50-100 nm. In step S5, the etching gas is a mixture of CH4 and H2 with a volume ratio of 1:2-3, the etching pressure is 15-25 mTorr, the RF power is 80-120 W, the etching time is 180-300 s, and the etching depth is 200-400 nm.

[0009] As a further description of the above technical solution: In step S4, the mixed etching solution is composed of HBr, H2O2 and H2O, with a volume ratio of HBr:H2O2:H2O=1:1-2:5-8, an etching temperature of 20℃-25℃, and an etching rate of 5-10nm / s.

[0010] As a further description of the above technical solution: In step S8, the Fe doping concentration of the SI-InP buried layer is 5 × 10⁻⁶. 17 -2×10 18 cm -3 The growth temperature is 620℃-640℃, and the thickness is consistent with the height of the ridge waveguide platform.

[0011] As a further description of the above technical solution: In step S10, the P-type top electrode is a multilayer structure of Ti, Pt, and Au, with thicknesses of 20-30 nm, 50-80 nm, and 200-300 nm, respectively, and an annealing temperature of 400℃-450℃; the N-type bottom electrode is a multilayer structure of AuGe, Ni, and Au, with an annealing temperature of 350℃-400℃.

[0012] As a further description of the above technical solution: In step S11, after dicing, the die is flip-chip soldered onto the heat sink, and after gold wire bonding, the device is packaged using TO packaging.

[0013] The present invention has the following beneficial effects: 1. Compared with existing technologies, this invention employs a step-by-step grating etching technique, dividing grating fabrication into three stages: shallow etching, selective etching, and deep etching. This achieves precise decoupled control of the grating period, width, depth, and duty cycle. The shallow etching stage ensures high-precision shaping of the grating period and width; the selective etching stage optimizes the duty cycle and sidewall flatness; and the deep etching stage precisely controls the grating depth. The resulting step-by-step grating possesses excellent structural characteristics, including a high aspect ratio, high sidewall perpendicularity, and low sidewall roughness, thereby improving the stability of optical signal transmission.

[0014] 2. Compared with existing technologies, this invention innovatively adopts an Fe-doped semi-insulating InP buried layer structure to replace the traditional dielectric isolation layer or ion implantation isolation structure. The semi-insulating InP buried layer structure, through selective epitaxial growth, completely covers the sidewalls of the ridge waveguide, strictly limiting the current to a narrow ridge top region. This reduces the effective contact area of ​​the PN junction, effectively improving communication quality under high-speed modulation. Attached Figure Description

[0015] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0016] refer to Figure 1 The present invention provides a method for fabricating a high-speed DFB laser, comprising the following steps: S1: Substrate cleaning and epitaxial growth An n-type InP single-layer wafer was selected as the substrate. The substrate has a crystal orientation of (100) and is doped with S at a concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The substrate thickness is 350-500μm. First, the substrate undergoes a rigorous cleaning process: ultrasonic cleaning with acetone and ethanol for 10-15 minutes each to remove organic contaminants from the substrate surface; then chemical etching is performed using a 3:1:1 volume ratio H2SO4:H2O2:H2O mixed solution at 25℃-30℃ for 2-3 minutes to remove the oxide and damaged layers from the substrate surface; finally, it is rinsed thoroughly with deionized water and dried under a nitrogen atmosphere for later use.

[0017] After cleaning, metal-organic chemical vapor deposition (MOCVD) is used for epitaxial growth of the underlying layer, specifically including: (1) An n-type InP buffer layer with a thickness of 200-500 nm and a doping concentration of 1 × 10⁻⁶ nm is grown on an n-InP substrate. 18 -5×10 18 cm -3 Its function is to reduce the impact of substrate defects on the upper structure and optimize the crystal quality of the epitaxial layer. (2) An InGaAsP grating substrate is grown on the n-type InP buffer layer. Its composition satisfies the requirement that the wavelength corresponding to the bandgap is 1.1-1.3 μm (matching the optical field distribution of the subsequent active region), the thickness is 300-600 nm, and the doping concentration is 5 × 10⁻⁶. 17 -1×10 18 cm -3 This provides a high-quality substrate material for subsequent grating etching.

[0018] During epitaxial growth, the MOCVD process parameters are controlled as follows: growth temperature 620℃-650℃, growth pressure 50-100 mbar, V / III group element molar ratio 10-20, hydrogen as carrier gas, and flow rate 50-100 slm; the MBE process parameters are controlled as follows: growth temperature 500℃-530℃, and background vacuum better than 1×10⁻⁶. -10 Torr, with a beam equivalent pressure (BEP) ratio of In:Ga:As:P = 0.5:0.3:1.2:0.8. By precisely controlling the epitaxial process parameters, the surface roughness Ra of the underlying epitaxial layer is ensured to be ≤0.5nm, resulting in excellent crystal quality.

[0019] S2: Grating mask fabrication A periodically precise grating mask was fabricated on an InGaAsP grating substrate using high-precision electron beam lithography (EBL). The specific process is as follows: (1) A positive electron beam resist (such as ZEP520A) is spin-coated on the surface of the grating substrate. The spin-coating speed is 3000-5000 rpm and the spin-coating time is 30-60s. Then, a pre-baking treatment is performed at 180℃-200℃ for 2-3 minutes to form a resist film with a thickness of 200-300nm. (2) Exposure is performed using an electron beam exposure machine (accelerating voltage of 50-100kV, beam current of 10-50pA) according to a preset grating period (usually 240-260nm, determined according to Bragg diffraction conditions), with an exposure dose of 80-120μC / cm². (3) After exposure, a special developer (such as ZED-N50) is used for development. The development temperature is 20℃-25℃ and the development time is 60-90s. Then, it is rinsed with deionized water and dried with nitrogen to form a grating mask. The line width uniformity error of this mask is ≤±5nm and the period uniformity error is ≤±0.01μm, which provides a guarantee for subsequent high-precision grating etching.

[0020] S3: First RIE shallow etching Using the grating mask prepared in step 2 as the masking layer, a first shallow etching process was performed using reactive ion etching (RIE) to determine the grating period and width, and to perform preliminary calibration of the duty cycle. A mixture of CH4 and H2 was used as the etching gas, with a CH4 to H2 volume ratio of 1:3-5. The etching pressure was 10-20 mTorr, the RF power was 50-80 W, and the etching time was 30-60 s.

[0021] The depth of the first shallow etching is controlled at 50-100 nm. This depth ensures precise shaping of the grating period and width while allowing sufficient adjustment space for subsequent deep etching processes. During etching, optical emission spectroscopy (OES) is used to monitor the etching endpoint in real time, ensuring that the uniformity error of the etching depth is ≤ ±5 nm. After etching, the grating structure is observed using a scanning electron microscope (SEM), and the deviation of its line width from the preset value is ≤ ±10 nm, while the period uniformity remains within ±0.01 μm.

[0022] S4: Selective Chemical Etching and Mask Adjustment To further optimize the duty cycle of the grating and improve the flatness of its sidewalls, selective chemical etching and mask adjustment were performed on the grating after the first shallow etching. The specific process is as follows: (1) If there are residues or line width deviations in the grating mask, use oxygen plasma ashing process (power of 30-50W, time of 10-20s) to slightly remove part of the resist mask and adjust the mask line width. (2) Selective wet etching was performed using a mixed etching solution of HBr, H2O2, and H2O. The volume ratio of the etching solution was HBr:H2O2:H2O = 1:1-2:5-8. The etching temperature was controlled at 20℃-25℃, and the etching time was 30-60s. This etching solution showed high selectivity for InGaAsP grating materials, with an etching rate of 5-10nm / s. It also had a slight smoothing effect on the grating sidewalls, effectively reducing sidewall roughness. (3) After etching is completed, rinse thoroughly with deionized water and dry in a nitrogen atmosphere. Detect the duty cycle of the grating by SEM. If the target value is not reached, repeat the above etching process, shortening the etching time to 10-15s each time, until the duty cycle meets the requirements.

[0023] This step, through the synergistic effect of wet etching and mask adjustment, achieves precise control of the grating duty cycle and improves the morphology of the grating sidewalls, laying the foundation for subsequent deep etching to form a high aspect ratio grating.

[0024] S5: Second RIE Deep Erosion Based on the optimized grating structure from step 4, a second RIE deep etching is performed to form a step-etched grating with a high aspect ratio. The core objective of this etching is to precisely control the grating depth and optimize the coupling coefficient κ. The etching gas is still a mixture of CH4 and H2, but its volume ratio is adjusted to 1:2-3 to enhance the anisotropy of the etching and reduce lateral corrosion of the sidewalls. The etching pressure is 15-25 mTorr, the RF power is 80-120 W, the etching time is 180-300 s, and the etching depth is controlled at 200-400 nm.

[0025] To ensure precise control of the etching depth, a laser interferometer is used to monitor the grating depth change in real time during the etching process. Etching is immediately stopped when the preset depth is reached. After etching, the resulting step-by-step grating exhibits excellent structural characteristics: an aspect ratio of 3-5:1, sidewall perpendicularity ≥85°, sidewall roughness ≤3nm, and a stable duty cycle between 0.4 and 0.6. Through this step-by-step etching process, the effective coupling coefficient κ of the grating can be precisely controlled, ensuring that the κL value remains stable within the optimized range of 2.0-3.0, thus guaranteeing high single-mode stability of the device.

[0026] S6: Mask Removal and Secondary Epitaxy The grating mask was completely removed using an oxygen plasma ashing process (50-80W power, 30-60s), followed by secondary epitaxial growth to sequentially form an InP spacer layer, a strain-compensated multiple quantum well (SC-MQW) active region, and an upper InP waveguide layer. The secondary epitaxy also employed MOCVD technology, with the following process parameters: (1) InP separator growth: thickness 50-100nm, doping concentration 1×10 17 -5×10 17 cm -3 The growth temperature is 630℃-660℃. Its function is to isolate the grating from the active region and avoid the influence of the grating structure on the crystal quality of the active region. (2) SC-MQW Active Region Growth: Composed of 5-8 alternating cycles of compressive strain well layers and tensile strain barrier layers. The well layer material is InGaAsP, with a composition corresponding to a wavelength of 1.55 μm (communication window wavelength), a strain value of -0.8% to -1.2% (compressive strain), and a thickness of 6-10 nm; the barrier layer material is InGaAsP or InP, with a strain value of +0.3% to +0.7% (tensile strain), and a thickness of 10-15 nm. Through the synergistic design of the compressive strain well and tensile strain barrier, the valence bandgap splitting can be effectively improved, and the hole transport resistance can be reduced, thereby significantly improving the differential gain of the active region. (3) Growth of the upper InP waveguide layer: thickness is 150-250nm, doping concentration is 5×10⁻⁶ 16 -1×10 17 cm -3 The growth temperature is consistent with that of the InP separator. Its function is to confine the light field, reduce light field leakage, and improve the coupling efficiency between the light field and the active region.

[0027] During the secondary epitaxy process, by precisely controlling the growth temperature, V / III ratio and growth rate, the crystal quality of the active region of SC-MQW is ensured to be excellent, the strain distribution is uniform, and the thickness uniformity error of each layer is ≤±1nm.

[0028] S7: Ridge waveguide lithography and dry etching A composite process combining photolithography with ICP-RIE dry etching and wet etching is used to etch a narrow ridge waveguide mesa onto the secondary epitaxial layer. The specific process is as follows: (1) Spin-coat photoresist (such as AZ6130) on the surface of the lower InP waveguide layer at a spin speed of 4000-6000 rpm and a thickness of 1.0-1.5 μm. After pre-baking (110℃-120℃, 1-2 minutes), exposure, and development, a ridge waveguide photoresist mask is formed with a mask width of 1.2-1.8 μm. (2) ICP-RIE dry etching is used for main etching. The etching gas is a mixture of Cl2 and BCl3 with a volume ratio of 1:2-3. The etching pressure is 5-10 mTorr, the RF power is 100-150 W, the bias power is 20-40 W, and the etching depth is controlled at 40-60 nm above the active region (i.e., from the surface of the upper InP waveguide layer to a position 40-60 nm away from the upper interface of the SC-MQW active region). The etching rate is 100-150 nm / min. (3) In order to improve the verticality and flatness of the sidewall of the ridge waveguide, a mixed etching solution of H3PO4:H2O2:H2O (volume ratio of 1:1:10) was used for wet etching, and the etching time was 10-20s. The sidewall after dry etching was smoothed so that the verticality of the sidewall is ≥88° and the roughness of the sidewall is ≤2nm.

[0029] The width of the narrow ridge waveguide mesa is controlled at 1.2-1.8μm, which can effectively confine the current and optical field, improve the current injection efficiency and optical field confinement factor, and provide a suitable mesa structure for the subsequent growth of semi-insulating buried layers.

[0030] S8: Third Extension Using MOCVD selective epitaxy, Fe-doped semi-insulating InP (SI-InP) buried layers are grown on both sides of the ridge waveguide mesa. This step is the core process for achieving low parasitic capacitance. The specific process is as follows: (1) Place the etched sample into the MOCVD reaction chamber and perform surface pretreatment: anneal at 600℃-620℃ for 10-15 minutes in H2 atmosphere to remove surface oxide layer and contaminants. (2) Using Fe as the doping element, a Si-InP buried layer was grown with an Fe doping concentration of 5 × 10⁻⁶. 17 -2×10 18 cm -3 The buried layer thickness is consistent with the height of the ridge waveguide mesa, ensuring complete coverage of the sidewalls of the ridge waveguide mesa. The growth temperature is 620℃-640℃, the growth pressure is 50-80mbar, the V / III ratio is 15-25, and the growth rate is 50-80nm / min. (3) Due to the use of selective epitaxy, the SI-InP buried layer is grown only on the n-InP buffer layer surface on both sides of the ridge waveguide mesa, while the photoresist mask (not removed) on the top of the ridge waveguide mesa can prevent the buried layer material from growing on the top of the mesa, thus forming a buried waveguide structure.

[0031] The core advantage of the SI-BH structure lies in the fact that Fe-doped InP has extremely high resistivity, enabling excellent lateral current isolation and strictly limiting the current to a narrow ridge top region. At the same time, this structure limits the effective contact area of ​​the PN junction to the ridge top surface, significantly reducing the contact area between the PN junction sidewall and the isolation layer, thereby reducing the parasitic capacitance of the device to below 5fF, providing a key guarantee for high-speed modulation at 40GHz and above.

[0032] S9: P-type contact layer growth and window opening After completing the SI-BH buried layer growth, the photoresist mask on top of the ridge waveguide mesa is removed, and the epitaxial growth of the P-type contact layer and the window opening process continue: (1) P-InP cladding growth: A P-type InP cladding with a thickness of 800-1200 nm was grown on the top of the ridge waveguide mesa and on the surface of the SI-InP buried layer. The doping element was Zn with a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The growth temperature is 610℃-630℃; (2) P+ contact layer growth: A heavily P+ doped contact layer is grown on the P-InP cladding. The material used is InGaAs, with a thickness of 200-300 nm and a Zn doping concentration of 1×10⁻⁶. 19 -5×10 19 cm -3 Its function is to reduce ohmic contact resistance; (3) Window opening: The electrode window mask is fabricated on the P+ contact layer using photolithography. Then, the P+ contact layer in the non-contact area is removed by ICP-RIE dry etching (etching depth is 200-300nm) to form the electrode window. The window size matches the top electrode size.

[0033] S10: Ohmic contact metallization The metallization of the top and bottom electrodes is performed using electron beam evaporation technology. The specific process is as follows: (1) Top electrode fabrication: The top electrode is a P-type ohmic contact, employing a multilayer metal structure of Ti, Pt, and Au. First, a Ti layer (20-30 nm thick) is evaporated as an adhesion layer and ohmic contact layer. Then, a Pt layer (50-80 nm thick) is evaporated as a barrier layer to prevent Au from interdiffusion with the semiconductor material. Finally, an Au layer (200-300 nm thick) is evaporated as a conductive layer. After evaporation, rapid thermal annealing is performed at 400℃-450℃ for 30-60 s to form a good ohmic contact. (2) Bottom electrode fabrication: The sample was flipped over, and the back side of the n-InP substrate was thinned by grinding (thickness reduced from 350-500 μm to 100-150 μm). Then, the bottom electrode was evaporated, using a multilayer metal structure of AuGe, Ni, and Au. The AuGe layer (thickness 50-70 nm), Ni layer (thickness 20-30 nm), and Au layer (thickness 200-300 nm) were evaporated sequentially, and then subjected to RTA annealing at 350℃-400℃ (time 60-90 s) to form an N-type ohmic contact.

[0034] S11: Passivation, anti-reflective coating and die-cutting packaging (1) Passivation treatment: A silicon nitride passivation layer with a thickness of 100-200 nm is deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). The passivation layer can effectively protect the device surface, reduce the impact of environmental factors on device performance, and at the same time reduce surface recombination current and improve device reliability; (2) Anti-reflection coating: The output cavity surface (front end) of the laser is coated with an anti-reflection coating. The coating material is a multilayer film composed of SiO2 and TiO2. The coating thickness is optimized according to the wavelength of 1.55μm to reduce the cavity surface reflectivity to below 1% and reduce the impact of cavity surface reflection on single-mode characteristics. The rear end is coated with a high reflectivity (HR) coating with a reflectivity ≥95% to improve optical feedback efficiency. (3) Dicing and Packaging: A diamond dicing machine is used to dic the wafer along the preset dicing path to divide it into individual dies; then the dies are flip-chip bonded to the heat sink, gold wire bonding is performed, and finally packaged into TO package form to complete the fabrication of the high-speed DFB laser.

[0035] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a high-speed DFB laser, characterized in that, Includes the following steps: S1: Substrate cleaning and epitaxial growth of the underlying layer: n-InP was selected as the substrate. After cleaning, an n-type InP buffer layer and an InGaAsP grating substrate were grown sequentially by MOCVD technology. S2: Grating mask fabrication: Using electron beam lithography, a precisely periodic grating mask is fabricated on the surface of the InGaAsP grating substrate. S3: First RIE shallow etching: Shallow etching is performed using ICP-RIE process to lock the grating period and initial width; S4: Selective chemical etching and mask adjustment: Fine-tuning the grating duty cycle using a mixed etching solution to improve sidewall smoothness; S5: Second RIE deep etching: Deep etching is performed through ICP-RIE process to form a step-by-step etched grating with a high aspect ratio; S6: Mask Removal and Secondary Epitaxy: After removing the grating mask, InP spacer, strain-compensated multi-quantum-well active region and upper InP waveguide layer are grown sequentially by MOCVD technology. S7: Ridge waveguide photolithography and dry etching: A composite process combining photolithography with ICP-RIE dry etching and wet etching is used to etch a narrow ridge waveguide mesa on the secondary epitaxial layer. S8: Third epitaxy: Using MOCVD selective epitaxy technology, Fe-doped semi-insulating InP buried layers are grown on both sides of the ridge waveguide mesa to completely cover the sidewalls of the ridge waveguide mesa. S9: P-type contact layer growth and window opening: Grow a P-type InP cladding layer and a P+ contact layer, and open the electrode window by photolithography etching; S10: Ohmic contact metallization: P-type top electrode and N-type bottom electrode are prepared by electron beam evaporation technology and annealed to form ohmic contact; S11: Passivation, Anti-reflection Coating and Dicing: Passivation, anti-reflection coating and dicing are performed sequentially to complete device fabrication.

2. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: The substrate cleaning process in step S1 is as follows: Acetone and ethanol are used sequentially for ultrasonic cleaning for 10-15 minutes each to remove organic contaminants from the substrate surface; then, a mixed solution of H2SO4:H2O2:H2O (volume ratio 3:1:1) is used for chemical etching at a temperature of 25℃-30℃ for 2-3 minutes to remove the oxide and damaged layers from the substrate surface; finally, the substrate is rinsed thoroughly with deionized water and dried under a nitrogen atmosphere; the n-type InP buffer layer has a thickness of 200-500 nm and a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The bandgap of the InGaAsP grating substrate corresponds to a wavelength of 1.1-1.3 μm, a thickness of 300-600 nm, and a doping concentration of 5 × 10⁻⁶. 17 -1×10 18 cm -3 .

3. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S2, the electron beam exposure technology uses a positive electron beam resist, the spin coating speed is 3000-5000 rpm, the spin coating time is 30-60s, and the pre-baking treatment is carried out at 180℃-200℃ for 2-3 minutes to form a resist film layer with a thickness of 200-300nm.

4. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S3, the etching gas is a mixture of CH4 and H2 with a volume ratio of 1:3-5, the etching pressure is 10-20 mTorr, the RF power is 50-80 W, the etching time is 30-60 s, and the etching depth is 50-100 nm. In step S5, the etching gas is a mixture of CH4 and H2 with a volume ratio of 1:2-3, the etching pressure is 15-25 mTorr, the RF power is 80-120 W, the etching time is 180-300 s, and the etching depth is 200-400 nm.

5. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S4, the mixed etching solution is composed of HBr, H2O2 and H2O, with a volume ratio of HBr:H2O2:H2O=1:1-2:5-8, an etching temperature of 20℃-25℃, and an etching rate of 5-10nm / s.

6. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S8, the Fe doping concentration of the SI-InP buried layer is 5 × 10⁻⁶. 17 -2×10 18 cm -3 The growth temperature is 620℃-640℃, and the thickness is consistent with the height of the ridge waveguide platform.

7. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S10, the P-type top electrode is a multilayer structure of Ti, Pt, and Au, with thicknesses of 20-30 nm, 50-80 nm, and 200-300 nm, respectively, and an annealing temperature of 400℃-450℃; the N-type bottom electrode is a multilayer structure of AuGe, Ni, and Au, with an annealing temperature of 350℃-400℃.

8. The method for fabricating a high-speed DFB laser according to claim 1, characterized in that: In step S11, after dicing, the die is flip-chip soldered onto the heat sink, and after gold wire bonding, the device is packaged using TO packaging.

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