A clamp protection circuit for an LLC circuit

Abstract

The application relates to the field of power electronics, and discloses a sealing wave protection circuit of an LLC circuit, which realizes periodical sealing wave protection through the cooperation of a hardware detection and protection circuit and software protection: a comparison unit is used to monitor the maximum LLC current in real time, a latch unit is combined to lock the overcurrent state, the sealing wave is triggered when the current zero moment is identified through the PWM falling edge, high reverse pressure damage caused by the shutdown of the MOS tube at the current peak value is effectively avoided, a delay reset unit is automatically reset within less than 1 / 4 of a period, the system resumes normal work in the next period after the sealing wave, the hysteresis problem of pure software sealing wave is eliminated, large-specification MOS tubes are not needed, and the hardware cost is significantly reduced while the reliability is ensured.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a wave blocking protection circuit for LLC circuits. Background Technology

[0002] In UPS systems employing reverse LLC circuits for battery-mode voltage boosting, there are two main risk points for component damage. First, during the initial few cycles of switching from mains power to battery power, the LLC current increases significantly, easily damaging the MOSFET. Second, a bus short circuit in battery-powered mode can trigger overcurrent, similarly damaging the MOSFET.

[0003] Existing solutions typically fall into two categories. The first is to use a larger-sized MOSFET, relying on the hardware's inherent performance to withstand overcurrent surges. The second is to trigger a TZ signal using a hardware overcurrent comparator to shut down the MOSFET's waveform generation, or to rely on software to detect overcurrent and perform waveform blocking. However, these solutions have significant drawbacks. The system current sampling frequency is much lower than the LLC frequency, and pure software waveform blocking suffers from severe lag. The waveform blocking point is uncertain; if the waveform blocking action happens to occur at the current peak, it can lead to excessively high reverse voltage in the MOSFET, causing damage. In this case, even shutting down the waveform generation will not provide protection. Using a larger-sized MOSFET significantly increases hardware costs.

[0004] Therefore, improvements to existing technologies are necessary.

[0005] The above information is provided as background information only to aid in understanding the present invention, and does not constitute an assertion or admission that any of the above content can be used as prior art relative to the present invention. Summary of the Invention

[0006] This invention provides a wave blocking protection circuit for LLC circuits to solve the problems existing in the prior art.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A waveform blocking protection circuit for an LLC circuit includes a comparator unit, a latch unit, a logic control unit, a delay reset unit, and a microcontroller; wherein,

[0009] The comparison unit is connected to the microcontroller and the logic control unit respectively, and is used to compare the negative half-cycle LLC_PWM signal provided by the microcontroller with the reference voltage, and output the comparison signal to the logic control unit;

[0010] The latching unit is connected to the logic control unit and is used to latch the LLC_LMT signal in a timely manner when the LLC_LMT signal changes from a low level to a high level input, and continuously output a high level to the logic control unit.

[0011] The logic control unit is connected to the microcontroller and is used to change the level output to the microcontroller from high to low when the comparison signal enters the falling edge.

[0012] The microcontroller is used to initialize the state of the latch unit and the logic control unit, ensuring that the output state of the two flip-flops is known, i.e., to reset before the circuit runs; it is also used to control the LLC circuit to block the waveform when the output level of the logic control unit changes from high to low.

[0013] The logic control unit is also used to set the latch unit when the level output to the microcontroller changes from high to low and the level output to the latch unit changes from low to high.

[0014] The delay reset unit is connected to the logic control unit and is used to reset the logic control unit after the LLC circuit is turned off from emitting a wave, with a delay of less than 1 / 4 of the LLC cycle, so that the level output by the logic control unit to the microcontroller changes from low level to high level. The microcontroller then releases the LLC circuit from emitting a wave, and the next LLC cycle emits a wave normally, thereby realizing the LLC wave blocking cycle by cycle.

[0015] Furthermore, in the wave blocking protection circuit of the LLC circuit, the comparison unit includes a comparator CMP1;

[0016] The non-inverting input of the comparator CMP1 is connected to the PWM signal of the microcontroller, the inverting input of the comparator CMP1 receives the reference voltage, and the output of the comparator CMP1 is connected to the logic control unit.

[0017] Furthermore, in the wave blocking protection circuit of the LLC circuit, the comparison unit further includes a first resistor R1 and a second resistor R2;

[0018] The first resistor R1 is connected in series with the non-inverting input of the comparator CMP1;

[0019] The second resistor R2 is connected in series with the inverting input of the comparator CMP1.

[0020] Furthermore, in the wave blocking protection circuit of the LLC circuit, the latching unit includes a first D flip-flop U1;

[0021] The CP pin of the first D flip-flop U1 receives the LLC_LMT signal;

[0022] The Q pin of the first D flip-flop U1 is connected to the logic control unit;

[0023] The first D flip-flop U1 The pin is connected to the logic control unit;

[0024] The S pin of the first D flip-flop U1 is connected to ground;

[0025] The D pin of the first D flip-flop U1 is connected to the positive power supply voltage.

[0026] Furthermore, in the blocking protection circuit of the LLC circuit, the latching unit also includes a second capacitor C2, a third capacitor C3, a third resistor R3, and a sixth resistor R6;

[0027] One end of the third resistor R3 is connected to the Q pin of the first D flip-flop U1, and the other end is connected to the logic control unit;

[0028] One end of the sixth resistor R6 is connected to the first D flip-flop U1. One end is connected to the logic control unit;

[0029] One end of the third capacitor C3 is connected to the logic control unit, and the other end is connected to ground;

[0030] One end of the first capacitor C1 is connected to the logic control unit, and the other end is connected to ground.

[0031] Furthermore, in the wave blocking protection circuit of the LLC circuit, the logic control unit includes a second D flip-flop U2;

[0032] The S pin of the second D flip-flop U2 is connected to ground;

[0033] The D pin of the second D flip-flop U2 is connected to the Q pin of the first D flip-flop U1;

[0034] The CP pin of the second D flip-flop U2 is connected to the output terminal of the comparator CMP1 and is also connected to the positive power supply voltage.

[0035] The second D flip-flop U2 The foot is connected to the microcontroller;

[0036] The Q pin of the second D flip-flop U2 is connected to the positive power supply voltage and the R pin of the first D flip-flop U1, respectively.

[0037] Furthermore, in the wave blocking protection circuit of the LLC circuit, the logic control unit also includes a fourth resistor R4;

[0038] The fourth resistor R4 is connected in series between the Q pin of the second D flip-flop U2 and the positive power supply voltage.

[0039] Furthermore, in the wave blocking protection circuit of the LLC circuit, the delay reset unit includes a fifth resistor R5 and a second capacitor C2;

[0040] The fifth resistor R5 is connected in series between the Q pin of the second D flip-flop U2 and the R pin of the first D flip-flop U1;

[0041] One end of the second capacitor C2 is connected to the R pin of the first D flip-flop U1, and the other end is connected to ground.

[0042] Furthermore, in the wave blocking protection circuit of the LLC circuit, the microcontroller includes MCU U3;

[0043] The MCU U3 and the second D flip-flop U2 Foot connection.

[0044] Furthermore, in the blocking protection circuit of the LLC circuit, the microcontroller is also used to control the LLC circuit to continuously block the waveform when the LLC circuit is short-circuited.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] This invention provides a wave-blocking protection circuit for LLC circuits. Through the coordinated operation of hardware detection and protection circuits and software protection, cycle-by-cycle wave-blocking protection is achieved: the comparison unit monitors the maximum value of LLC current in real time, and the latching unit locks the overcurrent state, ensuring that wave-blocking is triggered by identifying the current zero-crossing moment through the falling edge of the PWM, effectively avoiding damage caused by high reverse voltage when the MOSFET is turned off at the current peak; the delayed reset unit automatically resets within less than 1 / 4 of the cycle, so that the system resumes normal operation in the next cycle after wave-blocking. This eliminates the hysteresis problem of pure software wave-blocking and eliminates the need to use large-size MOSFETs, significantly reducing hardware costs while ensuring reliability.

[0047] The present invention has other features and advantages, which will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a functional module diagram of a wave blocking protection circuit for an LLC circuit provided in an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the existing LLC circuit mentioned in this embodiment;

[0051] Figure 3 This is a schematic diagram of the circuit principle of a wave blocking protection circuit for an LLC circuit provided in an embodiment of the present invention.

[0052] Figure label:

[0053] Comparison unit 1, latch unit 2, logic control unit 3, delay reset unit 4, microcontroller 5. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] Please refer to Figure 1 This invention provides a wave blocking protection circuit for an LLC circuit, comprising a comparison unit 1, a latch unit 2, a logic control unit 3, a delay reset unit 4, and a microcontroller 5; wherein,

[0056] The comparison unit 1 is connected to both the microcontroller 5 and the logic control unit 3. Its core function is to compare the negative half-cycle LLC_PWM signal provided by the microcontroller 5 (this signal serves as the drive signal for the MOSFET in the LLC circuit and plays a crucial role in the normal operation of the LLC circuit) with a reference voltage. Through this comparison operation, it is possible to determine in real time whether the level of the LLC_PWM signal exceeds the normal range. After completing the comparison, the comparison unit 1 outputs the generated comparison signal to the logic control unit 3, providing basic data support for subsequent logic judgments and protection actions.

[0057] The latch unit 2 is connected to the logic control unit 3, and its main function is to latch specific signals. Specifically, when the LLC_LMT signal (i.e., the current limiting signal, which is converted into a voltage signal after sampling the current signal and input into the comparator to be compared with the reference voltage, and then output by the comparator) changes from a low level to a high level and is input, the latch unit 2 will promptly latch the signal. Once latching is successful, the latch unit 2 will continuously output a high-level signal to the logic control unit 3, ensuring that when a current limiting condition occurs, the logic control unit 3 can promptly obtain information and make a corresponding response, providing a stable signal basis for the overcurrent protection of the circuit.

[0058] The logic control unit 3 is connected to the microcontroller 5, as well as the aforementioned comparison unit 1 and latch unit 2. It performs complex logic judgments and signal processing tasks. When the logic control unit 3 receives a comparison signal from the comparison unit 1 and detects that the signal has reached a falling edge, the output level to the microcontroller 5 changes from high to low. This level change is an important signal sent to the microcontroller 5, indicating a possible abnormal situation requiring waveform blocking protection.

[0059] The microcontroller 5 is used to initialize the states of the latch unit and the logic control unit, ensuring that the output states of the two flip-flops are known, i.e., a reset is performed before the circuit operates; it also constantly monitors the output level of the logic control unit 3. Once a change from high to low level is detected, the microcontroller 5 reacts quickly, immediately controlling the LLC circuit to perform a blocking operation to prevent damage to the circuit due to overcurrent or other abnormal conditions, ensuring the safe and stable operation of the entire system. Existing LLC circuit structures are as follows... Figure 2 As shown.

[0060] In addition, the logic control unit 3 has another important function. When the level it outputs to the microcontroller 5 changes from high to low, and simultaneously the level it outputs to the latch unit 2 changes from low to high, the logic control unit 3 sets the latch unit 2. This operation further strengthens the circuit's locking and memory function for overcurrent states, ensuring that an effective protection signal can be continuously provided when an overcurrent condition persists.

[0061] The delayed reset unit 4 is connected to the logic control unit 3, and its main function is to reset the logic control unit 3 at a specific time point. Specifically, after the LLC circuit's waveform transmission is turned off, the delayed reset unit 4 controls the delay time to ensure that the delay time is less than 1 / 4 of the LLC cycle. When the preset delay time is reached, the delayed reset unit 4 resets the logic control unit 3. After the reset, the level state output by the logic control unit 3 to the microcontroller 5 changes from low to high. At this time, the microcontroller 5 releases the waveform blocking restriction on the LLC circuit, allowing the LLC circuit to resume normal waveform transmission in the next cycle. Through this delayed reset mechanism, the cycle-by-cycle waveform blocking protection function of the LLC circuit is realized, ensuring timely waveform blocking protection of the circuit under abnormal conditions and rapid recovery of normal operation after the abnormal conditions are eliminated, thus improving the circuit's operating efficiency and stability.

[0062] The LLC circuit blocking protection circuit proposed in this embodiment of the invention achieves cycle-by-cycle blocking protection for the LLC circuit through deep collaboration between hardware detection and protection circuits and software protection. At the hardware level, the comparison unit 1 monitors the maximum LLC current value in real time and accurately, enabling timely detection of abnormal current changes in the circuit. Combined with the reliable locking of the overcurrent state by the latch unit 2, the blocking operation is triggered by identifying the current zero-crossing moment through the falling edge of the PWM, effectively avoiding high reverse voltage damage caused by the MOSFET being turned off at the current peak, greatly improving the MOSFET's lifespan and the circuit's reliability. At the software level, in close cooperation with the hardware protection circuit, the microcontroller 5 monitors and responds quickly to the output signal of the logic control unit 3 in real time, achieving control over the blocking and deblocking of the LLC circuit. Meanwhile, the delayed reset unit 4 automatically completes the reset operation within less than 1 / 4 of the cycle, enabling the system to quickly return to normal operation in the next cycle after the wave blocking. This not only successfully eliminates the hysteresis problem existing in the pure software wave blocking scheme, but also eliminates the need to use large-size, high-cost MOSFETs. While ensuring the reliability of the circuit in all aspects, it significantly reduces the hardware cost and provides an efficient, economical and reliable protection solution for the application and development of LLC circuits.

[0063] Please refer to Figure 3 In one embodiment of this invention, the internal structure and connection relationships of the comparison unit 1 are designed in detail and clearly. The comparison unit 1 includes a comparator CMP1, which plays a core role in the signal monitoring stage of the entire wave blocking protection circuit.

[0064] From a connectivity perspective, comparator CMP1 has three important connection ports, which are connected to other key components in the circuit. Specifically, the non-inverting input of comparator CMP1 is connected to the PWM signal of the microcontroller 5. This connection method allows the microcontroller 5 to provide the comparator CMP1 with a negative half-cycle LLC_PWM signal. This signal serves as the drive signal for the MOSFET in the LLC circuit, and its level directly reflects the operating status of the MOSFET and the current change trend in the circuit, providing the comparator CMP1 with the basic signal source for comparison.

[0065] The inverting input of comparator CMP1 is used to receive a reference voltage. This reference voltage serves as a standard threshold for determining whether the LLC_PWM signal is abnormal. By comparing the LLC_PWM signal with the reference voltage, comparator CMP1 can accurately determine whether the current in the circuit exceeds the normal range, thus providing a reliable basis for subsequent protection actions.

[0066] The output of comparator CMP1 is connected to the logic control unit 3. When comparator CMP1 compares the LLC_PWM signal received at its non-inverting input with the reference voltage received at its inverting input, it generates a corresponding comparison signal based on the comparison result and transmits this signal to the logic control unit 3 through its output. This signal transmission process is a crucial step in the entire wave blocking protection circuit's logic judgment and protection action. It ensures that the logic control unit 3 can promptly acquire abnormal information from the circuit and react accordingly.

[0067] In summary, in this embodiment, the comparison unit 1 establishes a connection with the microcontroller 5, the logic control unit 3, and the reference voltage through the comparator CMP1, forming a complete and efficient signal monitoring and transmission link, which provides a solid foundation for the protection of the LLC circuit.

[0068] Please refer to this again. Figure 3 In one embodiment of this invention, to further optimize the performance of the comparison unit 1 and enhance its signal processing stability and accuracy, the comparison unit 1, in addition to the core component comparator CMP1, is also equipped with three key resistive components: a first resistor R1 and a second resistor R2.

[0069] The first resistor R1 is connected in series with the non-inverting input of comparator CMP1. In the circuit, the negative half-cycle LLC_PWM signal output by microcontroller 5 must pass through the first resistor R1 before it can be transmitted to the non-inverting input of comparator CMP1. The first resistor R1 mainly serves to limit current and divide voltage. On the one hand, it can limit the current flowing into the non-inverting input of the comparator, preventing damage to the comparator due to excessive current and ensuring that the comparator operates within a safe current range. On the other hand, by properly selecting the resistance value of the first resistor R1, it can cooperate with other components in the circuit to perform voltage division processing on the LLC_PWM signal, adjusting its voltage value to the appropriate range for comparator CMP1, thereby improving the comparator's signal detection accuracy and response speed.

[0070] The second resistor R2 is connected in series at the inverting input of comparator CMP1. The reference voltage must pass through the second resistor R2 before entering the inverting input of comparator CMP1. The second resistor R2 also functions as a current limiter and voltage divider. It limits the current flowing into the inverting input of the comparator, protecting it from excessive current surges. Simultaneously, by precisely setting the value of the second resistor R2, the reference voltage can be appropriately adjusted to ensure accurate comparison with the LLC_PWM signal. Furthermore, the second resistor R2 can also suppress noise interference in the circuit to a certain extent, improving the stability of the reference voltage, thereby ensuring the accuracy and reliability of the comparison result of comparator CMP1.

[0071] In summary, in this embodiment, the first resistor R1 and the second resistor R2 work closely with the comparator CMP1 to form a high-performance, stable, and reliable comparator unit 1. Through their synergistic effect, the comparator unit 1 ensures accurate and stable comparison of the LLC_PWM signal and the reference voltage, providing a reliable comparison signal for the subsequent logic control unit 3. This achieves precise waveform blocking protection for the LLC circuit, effectively improving the safety and reliability of the entire circuit system.

[0072] Please refer to this again. Figure 3 In one embodiment of this invention, the internal structure and layout of the latch unit 2 are designed. The core component of the latch unit 2 is a first D flip-flop U1, which plays a crucial role in latching and stabilizing the output of key signals in the circuit.

[0073] From a connectivity perspective, each pin of the first D flip-flop U1 is connected to other key components of the circuit. Specifically, the CP pin of the first D flip-flop U1 receives the LLC_LMT signal, which serves as a current-limiting signal. Changes in the LLC_LMT signal's level reflect whether the current in the circuit exceeds the limit. When the LLC_LMT signal transitions from low to high, it triggers the first D flip-flop U1 to update its state, providing the necessary conditions for subsequent latching operations.

[0074] The Q pin of the first D flip-flop U1 is connected to the logic control unit 3. The Q pin is connected to the logic control unit 3. After the first D flip-flop U1 completes the latching operation of the input signal, its Q pin will output a stable high or low level signal and transmit the signal to the logic control unit 3. This signal transmission process is a key link in the information interaction between the latching unit 2 and the logic control unit 3. It ensures that the logic control unit 3 can obtain the state information latched by the latching unit 2 in a timely manner, thereby providing an accurate basis for subsequent logic judgment and protection actions.

[0075] The S pin of the first D flip-flop U1 is connected to ground, which ensures that the S pin is always in a low-level state. Under normal operating conditions, the low-level S pin will not trigger the set operation of the first D flip-flop U1, thus ensuring that the first D flip-flop U1 can perform normal latching and output operations according to the preset logic rules, based on the LLC_LMT signal input from the CP pin and its internal state.

[0076] The D pin of the first D flip-flop U1 is connected to the positive power supply voltage (VCC). This connection ensures that the D pin remains at a high level, providing a stable data input source for the first D flip-flop U1. When the CP pin receives a valid trigger signal (the LLC_LMT signal changes from low to high), the first D flip-flop U1 latches the high-level signal from the D pin internally and outputs a corresponding high-level signal through the Q pin, thereby achieving reliable latching of the current-limiting state.

[0077] In addition, to further optimize the performance of latch unit 2 and enhance its anti-interference capability and signal stability, in one embodiment of this example, latch unit 2 is further configured with a first capacitor C1 and a third capacitor C3, a third resistor R3 and a sixth resistor R6.

[0078] One end of the third resistor R3 is connected to the Q pin of the first D flip-flop U1, and the other end is connected to the logic control unit;

[0079] One end of the sixth resistor R6 is connected to the first D flip-flop U1. One end is connected to the logic control unit;

[0080] One end of the first capacitor C1 is connected to the logic control unit (specifically, to the second D flip-flop U2), and the other end is connected to ground. The first capacitor C1 primarily functions to filter and stabilize the reset signal in the circuit. It can filter out high-frequency noise interference in the input signal at pin R, preventing the first D flip-flop U1 from erroneously resetting due to noise interference. Simultaneously, the first capacitor C1 can also provide a brief charge storage for pin R in abnormal situations such as power fluctuations or momentary power outages, ensuring that the first D flip-flop U1 can perform a reset operation in a stable state, thereby improving the reliability and stability of the latch unit 2.

[0081] One end of the third capacitor C3 is connected to the logic control unit (specifically, to the second D flip-flop U2), and the other end is connected to ground. The main function of the third capacitor C3 is to filter and stabilize the signal output from pin D. It can filter out high-frequency glitches and noise interference in the output signal from pin D, making the output signal smoother and more stable. This is crucial for the subsequent connection with the logic control unit 3, because a stable output signal ensures that the logic control unit 3 receives accurate and reliable information, thereby avoiding logical judgment errors caused by signal interference and further improving the performance and reliability of the entire wave blocking protection circuit.

[0082] In summary, in this embodiment, the latch unit 2, through the coordinated operation of the first D flip-flop U1, the first capacitor C1, and the third capacitor C3, forms a fully functional and stable signal latching and processing module. It can accurately and reliably latch and output the LLC_LMT signal, and provide stable and accurate status information for the subsequent logic control unit 3, thus providing a solid guarantee for achieving precise waveform blocking protection of the LLC circuit.

[0083] Please refer to this again. Figure 3 In one embodiment of this invention, the internal structure and connection relationships of the logic control unit 3 are designed to ensure stable and reliable circuit operation. The logic control unit 3 includes a key component, the second D flip-flop U2, which plays a crucial role in the logic control process.

[0084] Looking at the pin connections of the second D flip-flop U2, its S pin is connected to ground, ensuring that the S pin is always in a low-level state. Under normal operating conditions, the low-level S pin will not trigger the set operation of the second D flip-flop U2, thus guaranteeing that the second D flip-flop U2 can perform normal state updates and output operations according to preset logic rules and other input signals.

[0085] The D pin of the second D flip-flop U2 is connected to the third resistor R3 and the third capacitor C3, respectively. The R pin of the second D flip-flop U2 is connected to the sixth resistor R6 and the first capacitor C1, respectively. The signal output from the Q pin of the first D flip-flop U1 reflects the current limiting state information in the circuit. This signal serves as a data input source and is transmitted to the D pin of the second D flip-flop U2 via the third resistor R3. When the second D flip-flop U2 receives a valid clock signal, it latches the signal input from the D pin internally and performs corresponding processing according to internal logic, providing a data basis for subsequent logical judgments.

[0086] The CP pin of the second D flip-flop U2 is connected to the output of the comparator CMP1 and is connected to the positive power supply voltage (VCC) through the seventh resistor R7. The output signal of the comparator CMP1 is generated based on the comparison result of the LLC_PWM signal and the reference voltage. This signal is used as a clock signal input to the CP pin of the second D flip-flop U2. The seventh resistor R7 here serves as a current limiter and voltage divider. It limits the current flowing into the CP pin to prevent damage to the second D flip-flop U2 due to excessive current. At the same time, it also divides the positive power supply voltage to ensure that the clock signal voltage input to the CP pin is within an appropriate range, thereby improving the accuracy and response speed of the second D flip-flop U2 in recognizing the clock signal.

[0087] The second D flip-flop U2 The pin is connected to the microcontroller 5. Through this connection, the second D flip-flop U2 can transmit its internally processed state information to the microcontroller 5, enabling the microcontroller 5 to understand the circuit's logic state in real time and perform corresponding control and adjustments as needed. Simultaneously, the microcontroller 5 can also send control signals to the second D flip-flop U2 through this connection, enabling configuration of the second D flip-flop U2's operating mode and intervention in its state.

[0088] The Q pin of the second D flip-flop U2 has a dual connection. Firstly, it is connected to the R pin of the second D flip-flop U2 via the delayed reset unit 4. This connection forms a feedback loop; when the Q pin outputs a specific signal, after processing by the delayed reset unit 4, it acts on the R pin after a certain delay, thus resetting the second D flip-flop U2. The design of the delayed reset unit 4 ensures the accuracy and stability of the reset operation, avoiding unnecessary resets due to momentary interference or misoperation, thereby improving the reliability and anti-interference capability of the entire logic control unit 3. Secondly, the Q pin of the second D flip-flop U2 is also connected to the positive power supply voltage and the R pin of the first D flip-flop U1, but more accurately and in accordance with circuit design specifications, these connections are achieved through the fourth resistor R4 and the fifth resistor R5.

[0089] To further optimize the performance of the logic control unit 3 and ensure the stability and reliability of signal transmission, in one embodiment of this invention, the logic control unit 3 is additionally equipped with a fourth resistor R4.

[0090] The fourth resistor, R4, is connected in series between the Q pin of the second D flip-flop U2 and the positive power supply voltage. The fourth resistor R4 primarily functions as a current limiter and voltage divider. It limits the current flowing from the Q pin to the positive power supply voltage, preventing damage to the second D flip-flop U2 and other related components due to excessive current. Simultaneously, by appropriately selecting the value of the fourth resistor R4, the signal output from the Q pin can be voltage-divided, adjusting the signal voltage to a suitable range to meet the signal level requirements of subsequent circuits, thereby improving the stability and compatibility of signal transmission.

[0091] In summary, in this embodiment, the logic control unit 3, through the coordinated operation of the second D flip-flop U2, the fourth resistor R4, and the delay reset unit 4, forms a fully functional and stable logic control module. It can accurately and reliably perform logical judgments and processing of input signals, and through a reasonable feedback mechanism and signal adjustment, achieve precise control over itself and other related components, providing strong support for the stable operation and precise protection of the LLC circuit.

[0092] Please refer to this again. Figure 3 In one embodiment of this invention, the internal structure and connection method of the delayed reset unit 4 are designed, which plays a crucial role in ensuring the stable operation and reliable reset of the entire circuit system.

[0093] Specifically, the delayed reset unit 4 mainly consists of two core components: a fifth resistor R5 and a second capacitor C2. In terms of component connections, the fifth resistor R5 is connected in series between the Q pin of the second D flip-flop U2 and the R pin of the first D flip-flop U1. The fifth resistor R5 plays a crucial role in current limiting and voltage division in the circuit. On one hand, it limits the current flowing from the Q pin of the second D flip-flop U2 to the R pin of the first D flip-flop U1, preventing damage to the R pin of the first D flip-flop U1 and subsequent related circuit components due to excessive current, thus ensuring circuit safety. On the other hand, the fifth resistor R5 and the second capacitor C2 work together to determine the timing characteristics of the delayed reset. By appropriately selecting the resistance value of the fifth resistor R5, its effect on current and voltage distribution can be adjusted, thereby precisely controlling the length of the delayed reset to meet the reset delay requirements in different application scenarios.

[0094] One end of the second capacitor C2 is connected to the R pin of the first D flip-flop U1, and the other end is connected to ground. The second capacitor C2 plays a crucial role in energy storage and filtering within the delay reset unit 4. When the Q pin of the second D flip-flop U2 outputs a high-level signal, this signal charges the second capacitor C2 through the fifth resistor R5. During charging, the voltage across the second capacitor C2 gradually increases. Due to the charging characteristics of a capacitor, the voltage rise is not instantaneous but follows a certain time pattern, providing a time basis for the delay reset. When the voltage across the second capacitor C2 reaches a certain threshold, it will cause the R pin of the first D flip-flop U1 to receive a valid reset signal, thereby triggering the second D flip-flop U2 to perform a reset operation. After the second D flip-flop U2 is reset, its Q pin outputs a low-level signal. At this time, the second capacitor C2 will discharge through the fifth resistor R5, preparing for the next charging and reset operation.

[0095] Furthermore, the second capacitor C2 also has a filtering function. It can filter out high-frequency noise interference in the signal input to the R pin of the first D flip-flop U1, making the reset signal purer and more stable. During actual circuit operation, it is inevitable to be affected by various external factors, generating high-frequency noise signals. If these noise signals directly act on the R pin of the first D flip-flop U1, they may cause erroneous reset operations, affecting the normal operation of the circuit. The presence of the second capacitor C2 can effectively suppress these high-frequency noises, ensuring the accuracy and reliability of the reset signal, thereby improving the performance and stability of the entire delayed reset unit 4.

[0096] In summary, in this embodiment, the delay reset unit 4 achieves precise delay reset of the second D flip-flop U2 through the ingenious cooperation of the fifth resistor R5 and the second capacitor C2. The current limiting and voltage dividing functions of the fifth resistor R5 and the energy storage and filtering functions of the second capacitor C2 complement each other, jointly ensuring the stability and reliability of the delay reset process and providing a strong guarantee for the stable operation of the entire circuit system.

[0097] Please refer to this again. Figure 3 In one embodiment of this invention, the internal structure and external connection design of the microcontroller 5 are crucial for realizing intelligent control of the circuit.

[0098] Specifically, the microcontroller 5 includes the key core component MCU U3. MCU U3 is an integrated circuit chip that integrates multiple functional modules such as a processor core, memory, and input / output interfaces. It has powerful data processing capabilities and flexible control functions, and can analyze and process input signals according to a preset program, and output corresponding control signals, thereby achieving precise control of the entire circuit system.

[0099] From the perspective of connection, the MCU U3 and the second D flip-flop U2 Pin connection. This connection method establishes an information exchange channel between MCU U3 and the second D flip-flop U2. The second D flip-flop U2 is responsible for latching and logically processing the input signals in the logic control unit 3, and its output signal reflects the information of a specific logic state in the circuit. Through the connection with MCU U3, the second D flip-flop U2 can transmit the processed state information to MCU U3 in real time.

[0100] After receiving the signal from the second D flip-flop U2, MCU U3 utilizes its powerful internal data processing capabilities to perform in-depth analysis of these signals. For example, MCU U3 can determine whether the circuit is in an abnormal state such as overcurrent or overvoltage, or whether a specific logic operation has been completed, based on the received signal. Based on these analysis results, MCU U3 can make corresponding decisions in a timely manner and send control signals to other components in the circuit through its output interface to achieve operations such as adjusting the circuit's operating mode and triggering protection functions.

[0101] Simultaneously, MCU U3 can also send control commands to the second D flip-flop U2 through this connection to configure and adjust its operating state. For example, MCU U3 can change parameters such as the clock frequency and data input method of the second D flip-flop U2 according to actual needs, making it better adaptable to different working scenarios and task requirements. This two-way information interaction and control mechanism enables MCU U3 and the second D flip-flop U2 to work closely together to achieve intelligent control and efficient operation of the circuit system.

[0102] In addition, MCU U3 typically has abundant external interfaces and communication functions, enabling data transmission and communication with other devices or systems. Through these interfaces, MCU U3 can upload the operating status information of the circuit system to a host computer or other monitoring equipment, realizing remote monitoring and control; at the same time, it can also receive control commands from external sources, further expanding the functionality and application scope of the circuit system.

[0103] In summary, in this embodiment, the microcontroller 5, through the connection between the MCU U3 and the second D flip-flop U2, constructs a highly efficient information interaction and control platform. The MCU U3, with its powerful data processing capabilities and flexible control functions, works in conjunction with the second D flip-flop U2 to achieve real-time monitoring, intelligent analysis, and precise control of the circuit system, providing strong support for the stable operation and reliable performance of the entire circuit system.

[0104] In one embodiment of this example, the microcontroller 5 is further configured to control the LLC circuit to continuously block the waveform when the LLC circuit is short-circuited.

[0105] It should be noted that, to ensure the LLC circuit remains in a blocked state until the short-circuit fault is cleared, preventing recurrence and secondary damage, microcontroller 5 continuously outputs a blocked state control signal. It constantly monitors whether the short-circuit fault still exists, determining whether the short-circuit state has been resolved by continuously collecting and analyzing parameters such as current and voltage in the circuit. As long as the short-circuit fault is detected, microcontroller 5 will keep the power switch in the off state, maintaining the blocked state of the LLC circuit. Only when the short-circuit fault is cleared and the current, voltage, and other parameters in the circuit return to normal will microcontroller 5 restart the normal drive control of the power switch according to a preset program, allowing the LLC circuit to resume normal operation.

[0106] The microcontroller 5's function of controlling continuous waveform blocking during LLC circuit short circuits brings significant advantages to the entire circuit system. On one hand, it greatly improves the reliability and safety of the circuit system. By quickly responding to short-circuit faults and taking effective waveform blocking measures, it can avoid large-scale component damage and circuit failures caused by short circuits, reducing maintenance costs and downtime. On the other hand, this intelligent control method reflects the automation and intelligence level of the circuit system. The microcontroller 5 can automatically make decisions and adjustments based on real-time monitored circuit states without manual intervention, improving the operating efficiency and stability of the circuit system.

[0107] In summary, in this embodiment, the microcontroller 5, through real-time monitoring and intelligent control of the LLC circuit, can quickly and effectively control the LLC circuit to continuously block the waveform when a short-circuit fault occurs, providing a solid guarantee for the safe and stable operation of the LLC circuit.

[0108] Although this invention frequently uses terms such as comparison unit, latch unit, and logic control unit, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this invention; interpreting them as any additional limitation would contradict the spirit of this invention.

[0109] Finally, it should be noted that although the above embodiments have been described in the description and drawings of this invention, this should not limit the scope of patent protection of this invention. Any technical solutions that are based on the essential concept of this invention, utilize the content described in the description and drawings of this invention to make equivalent structural or procedural substitutions or modifications, as well as the direct or indirect application of the technical solutions of the above embodiments to other related technical fields, are all included within the scope of patent protection of this invention.

Claims

1. A wave-blocking protection circuit for an LLC circuit, characterized in that, It includes a comparison unit, a latch unit, a logic control unit, a delay-reset unit, and a microcontroller; among which, The comparison unit is connected to the microcontroller and the logic control unit respectively, and is used to compare the negative half-cycle LLC_PWM signal provided by the microcontroller with the reference voltage, and output the comparison signal to the logic control unit; The latching unit is connected to the logic control unit and is used to latch the LLC_LMT signal in a timely manner when the LLC_LMT signal changes from a low level to a high level input, and continuously output a high level to the logic control unit. The logic control unit is connected to the microcontroller and is used to change the level output to the microcontroller from high to low when the comparison signal enters the falling edge. The microcontroller is used to control the LLC circuit to block the waveform when it detects that the output level of the logic control unit changes from high to low. The logic control unit is also used to set the latch unit when the level output to the microcontroller changes from high to low and the level output to the latch unit changes from low to high. The delay reset unit is connected to the logic control unit and is used to reset the logic control unit after the LLC circuit is turned off from emitting a wave, with a delay of less than 1 / 4 of the LLC cycle, so that the level output by the logic control unit to the microcontroller changes from low level to high level. The microcontroller then releases the LLC circuit from emitting a wave, and the next LLC cycle emits a wave normally, thereby realizing the LLC wave blocking cycle by cycle.

2. The wave blocking protection circuit for the LLC circuit according to claim 1, characterized in that, The comparison unit includes a comparator CMP1; The non-inverting input of the comparator CMP1 is connected to the PWM signal of the microcontroller, the inverting input of the comparator CMP1 receives the reference voltage, and the output of the comparator CMP1 is connected to the logic control unit.

3. The wave blocking protection circuit for the LLC circuit according to claim 2, characterized in that, The comparison unit further includes a first resistor R1 and a second resistor R2; The first resistor R1 is connected in series with the non-inverting input of the comparator CMP1; The second resistor R2 is connected in series with the inverting input of the comparator CMP1.

4. The wave blocking protection circuit for the LLC circuit according to claim 2, characterized in that, The latch unit includes a first D flip-flop U1; The CP pin of the first D flip-flop U1 receives the LLC_LMT signal; The Q pin of the first D flip-flop U1 is connected to the logic control unit; The first D flip-flop U1 The pin is connected to the logic control unit; The S pin of the first D flip-flop U1 is connected to ground; The D pin of the first D flip-flop U1 is connected to the positive power supply voltage.

5. The wave blocking protection circuit for the LLC circuit according to claim 4, characterized in that, The latching unit also includes a first capacitor C1, a third capacitor C3, a third resistor R3, and a sixth resistor R6; One end of the third resistor R3 is connected to the Q pin of the first D flip-flop U1, and the other end is connected to the logic control unit; One end of the sixth resistor R6 is connected to the first D flip-flop U1. One end is connected to the logic control unit; One end of the third capacitor C3 is connected to the logic control unit, and the other end is connected to ground; One end of the first capacitor C1 is connected to the logic control unit, and the other end is connected to ground.

6. The wave blocking protection circuit for the LLC circuit according to claim 5, characterized in that, The logic control unit includes a second D flip-flop U2; The S pin of the second D flip-flop U2 is connected to ground; The D pin of the second D flip-flop U2 is connected to the third resistor R3 and the third capacitor C3 respectively; The R pin of the second D flip-flop U2 is connected to the sixth resistor R6 and the first capacitor C1, respectively; The CP pin of the second D flip-flop U2 is connected to the output terminal of the comparator CMP1 and is also connected to the positive power supply voltage. The second D flip-flop U2 The foot is connected to the microcontroller; The Q pin of the second D flip-flop U2 is connected to the positive power supply voltage and the R pin of the first D flip-flop U1, respectively.

7. The wave blocking protection circuit for the LLC circuit according to claim 6, characterized in that, The logic control unit also includes a fourth resistor R4; The fourth resistor R4 is connected in series between the Q pin of the second D flip-flop U2 and the positive power supply voltage.

8. The wave blocking protection circuit for the LLC circuit according to claim 6, characterized in that, The delayed reset unit includes a fifth resistor R5 and a second capacitor C2; The fifth resistor R5 is connected in series between the Q pin of the second D flip-flop U2 and the R pin of the first D flip-flop U1; One end of the second capacitor C2 is connected to the R pin of the first D flip-flop U1, and the other end is connected to ground.

9. The wave blocking protection circuit for the LLC circuit according to claim 8, characterized in that, The microcontroller includes MCUU3; The MCU U3 and the second D flip-flop U2 Foot connection.

10. The wave blocking protection circuit for the LLC circuit according to claim 1, characterized in that, The microcontroller is also used to control the LLC circuit to continuously block the waveform when the LLC circuit is short-circuited.

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